1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
266 /* is_specific_opcode implies no_transform. */
267 unsigned is_no_transform
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
278 unsigned is_no_reorder
: 1;
280 /* Uses absolute literal addressing for l32r. */
281 unsigned is_abslit
: 1;
283 unsigned is_align
: 1;
284 unsigned alignment
: 5;
288 /* Structure for saving information about a block of property data
289 for frags that have the same flags. */
290 struct xtensa_block_info_struct
296 struct xtensa_block_info_struct
*next
;
300 /* Structure for saving the current state before emitting literals. */
301 typedef struct emit_state_struct
306 int generating_literals
;
310 /* Opcode placement information */
312 typedef unsigned long long bitfield
;
313 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
314 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
315 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317 #define MAX_FORMATS 32
319 typedef struct op_placement_info_struct
322 /* A number describing how restrictive the issue is for this
323 opcode. For example, an opcode that fits lots of different
324 formats has a high freedom, as does an opcode that fits
325 only one format but many slots in that format. The most
326 restrictive is the opcode that fits only one slot in one
329 xtensa_format narrowest
;
333 /* formats is a bitfield with the Nth bit set
334 if the opcode fits in the Nth xtensa_format. */
337 /* slots[N]'s Mth bit is set if the op fits in the
338 Mth slot of the Nth xtensa_format. */
339 bitfield slots
[MAX_FORMATS
];
341 /* A count of the number of slots in a given format
342 an op can fit (i.e., the bitcount of the slot field above). */
343 char slots_in_format
[MAX_FORMATS
];
345 } op_placement_info
, *op_placement_info_table
;
347 op_placement_info_table op_placement_table
;
350 /* Extra expression types. */
352 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
353 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
354 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 #define O_pcrel O_md4 /* value is a PC-relative offset */
356 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
357 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
358 #define O_tlscall O_md7 /* TLS_CALL relocation */
359 #define O_tpoff O_md8 /* TPOFF relocation */
360 #define O_dtpoff O_md9 /* DTPOFF relocation */
362 struct suffix_reloc_map
366 bfd_reloc_code_real_type reloc
;
367 unsigned char operator;
370 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
372 static struct suffix_reloc_map suffix_relocs
[] =
374 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
375 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
376 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
377 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
378 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
379 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
380 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
381 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
382 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
383 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
397 directive_literal_prefix
,
399 directive_absolute_literals
,
400 directive_last_directive
406 bfd_boolean can_be_negated
;
409 const directive_infoS directive_info
[] =
412 { "literal", FALSE
},
414 { "transform", TRUE
},
415 { "freeregs", FALSE
},
416 { "longcalls", TRUE
},
417 { "literal_prefix", FALSE
},
418 { "schedule", TRUE
},
419 { "absolute-literals", TRUE
}
422 bfd_boolean directive_state
[] =
426 #if !XCHAL_HAVE_DENSITY
431 TRUE
, /* transform */
432 FALSE
, /* freeregs */
433 FALSE
, /* longcalls */
434 FALSE
, /* literal_prefix */
435 FALSE
, /* schedule */
436 #if XSHAL_USE_ABSOLUTE_LITERALS
437 TRUE
/* absolute_literals */
439 FALSE
/* absolute_literals */
444 /* Directive functions. */
446 static void xtensa_begin_directive (int);
447 static void xtensa_end_directive (int);
448 static void xtensa_literal_prefix (void);
449 static void xtensa_literal_position (int);
450 static void xtensa_literal_pseudo (int);
451 static void xtensa_frequency_pseudo (int);
452 static void xtensa_elf_cons (int);
453 static void xtensa_leb128 (int);
455 /* Parsing and Idiom Translation. */
457 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
459 /* Various Other Internal Functions. */
461 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
462 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
463 static void xtensa_mark_literal_pool_location (void);
464 static addressT
get_expanded_loop_offset (xtensa_opcode
);
465 static fragS
*get_literal_pool_location (segT
);
466 static void set_literal_pool_location (segT
, fragS
*);
467 static void xtensa_set_frag_assembly_state (fragS
*);
468 static void finish_vinsn (vliw_insn
*);
469 static bfd_boolean
emit_single_op (TInsn
*);
470 static int total_frag_text_expansion (fragS
*);
471 static bfd_boolean use_trampolines
= TRUE
;
472 static void xtensa_check_frag_count (void);
473 static void xtensa_create_trampoline_frag (bfd_boolean
);
474 static void xtensa_maybe_create_trampoline_frag (void);
475 struct trampoline_frag
;
476 static int init_trampoline_frag (struct trampoline_frag
*);
478 /* Alignment Functions. */
480 static int get_text_align_power (unsigned);
481 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
482 static int branch_align_power (segT
);
484 /* Helpers for xtensa_relax_frag(). */
486 static long relax_frag_add_nop (fragS
*);
488 /* Accessors for additional per-subsegment information. */
490 static unsigned get_last_insn_flags (segT
, subsegT
);
491 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
492 static float get_subseg_total_freq (segT
, subsegT
);
493 static float get_subseg_target_freq (segT
, subsegT
);
494 static void set_subseg_freq (segT
, subsegT
, float, float);
496 /* Segment list functions. */
498 static void xtensa_move_literals (void);
499 static void xtensa_reorder_segments (void);
500 static void xtensa_switch_to_literal_fragment (emit_state
*);
501 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
502 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
503 static void xtensa_restore_emit_state (emit_state
*);
504 static segT
cache_literal_section (bfd_boolean
);
506 /* Import from elf32-xtensa.c in BFD library. */
508 extern asection
*xtensa_make_property_section (asection
*, const char *);
510 /* op_placement_info functions. */
512 static void init_op_placement_info_table (void);
513 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
514 static int xg_get_single_size (xtensa_opcode
);
515 static xtensa_format
xg_get_single_format (xtensa_opcode
);
516 static int xg_get_single_slot (xtensa_opcode
);
518 /* TInsn and IStack functions. */
520 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
521 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
522 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
523 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
524 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
525 static void tinsn_from_chars (TInsn
*, char *, int);
526 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
527 static int get_num_stack_text_bytes (IStack
*);
528 static int get_num_stack_literal_bytes (IStack
*);
529 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
531 /* vliw_insn functions. */
533 static void xg_init_vinsn (vliw_insn
*);
534 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
535 static void xg_clear_vinsn (vliw_insn
*);
536 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
537 static void xg_free_vinsn (vliw_insn
*);
538 static bfd_boolean vinsn_to_insnbuf
539 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
540 static void vinsn_from_chars (vliw_insn
*, char *);
542 /* Expression Utilities. */
544 bfd_boolean
expr_is_const (const expressionS
*);
545 offsetT
get_expr_const (const expressionS
*);
546 void set_expr_const (expressionS
*, offsetT
);
547 bfd_boolean
expr_is_register (const expressionS
*);
548 offsetT
get_expr_register (const expressionS
*);
549 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
550 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
551 static void copy_expr (expressionS
*, const expressionS
*);
553 /* Section renaming. */
555 static void build_section_rename (const char *);
558 /* ISA imported from bfd. */
559 extern xtensa_isa xtensa_default_isa
;
561 extern int target_big_endian
;
563 static xtensa_opcode xtensa_addi_opcode
;
564 static xtensa_opcode xtensa_addmi_opcode
;
565 static xtensa_opcode xtensa_call0_opcode
;
566 static xtensa_opcode xtensa_call4_opcode
;
567 static xtensa_opcode xtensa_call8_opcode
;
568 static xtensa_opcode xtensa_call12_opcode
;
569 static xtensa_opcode xtensa_callx0_opcode
;
570 static xtensa_opcode xtensa_callx4_opcode
;
571 static xtensa_opcode xtensa_callx8_opcode
;
572 static xtensa_opcode xtensa_callx12_opcode
;
573 static xtensa_opcode xtensa_const16_opcode
;
574 static xtensa_opcode xtensa_entry_opcode
;
575 static xtensa_opcode xtensa_extui_opcode
;
576 static xtensa_opcode xtensa_movi_opcode
;
577 static xtensa_opcode xtensa_movi_n_opcode
;
578 static xtensa_opcode xtensa_isync_opcode
;
579 static xtensa_opcode xtensa_j_opcode
;
580 static xtensa_opcode xtensa_jx_opcode
;
581 static xtensa_opcode xtensa_l32r_opcode
;
582 static xtensa_opcode xtensa_loop_opcode
;
583 static xtensa_opcode xtensa_loopnez_opcode
;
584 static xtensa_opcode xtensa_loopgtz_opcode
;
585 static xtensa_opcode xtensa_nop_opcode
;
586 static xtensa_opcode xtensa_nop_n_opcode
;
587 static xtensa_opcode xtensa_or_opcode
;
588 static xtensa_opcode xtensa_ret_opcode
;
589 static xtensa_opcode xtensa_ret_n_opcode
;
590 static xtensa_opcode xtensa_retw_opcode
;
591 static xtensa_opcode xtensa_retw_n_opcode
;
592 static xtensa_opcode xtensa_rsr_lcount_opcode
;
593 static xtensa_opcode xtensa_waiti_opcode
;
594 static int config_max_slots
= 0;
597 /* Command-line Options. */
599 bfd_boolean use_literal_section
= TRUE
;
600 enum flix_level produce_flix
= FLIX_ALL
;
601 static bfd_boolean align_targets
= TRUE
;
602 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
603 static bfd_boolean has_a0_b_retw
= FALSE
;
604 static bfd_boolean workaround_a0_b_retw
= FALSE
;
605 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
606 static bfd_boolean workaround_short_loop
= FALSE
;
607 static bfd_boolean maybe_has_short_loop
= FALSE
;
608 static bfd_boolean workaround_close_loop_end
= FALSE
;
609 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
610 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
612 /* When workaround_short_loops is TRUE, all loops with early exits must
613 have at least 3 instructions. workaround_all_short_loops is a modifier
614 to the workaround_short_loop flag. In addition to the
615 workaround_short_loop actions, all straightline loopgtz and loopnez
616 must have at least 3 instructions. */
618 static bfd_boolean workaround_all_short_loops
= FALSE
;
622 xtensa_setup_hw_workarounds (int earliest
, int latest
)
624 if (earliest
> latest
)
625 as_fatal (_("illegal range of target hardware versions"));
627 /* Enable all workarounds for pre-T1050.0 hardware. */
628 if (earliest
< 105000 || latest
< 105000)
630 workaround_a0_b_retw
|= TRUE
;
631 workaround_b_j_loop_end
|= TRUE
;
632 workaround_short_loop
|= TRUE
;
633 workaround_close_loop_end
|= TRUE
;
634 workaround_all_short_loops
|= TRUE
;
635 enforce_three_byte_loop_align
= TRUE
;
642 option_density
= OPTION_MD_BASE
,
646 option_no_generate_flix
,
653 option_no_link_relax
,
661 option_text_section_literals
,
662 option_no_text_section_literals
,
664 option_absolute_literals
,
665 option_no_absolute_literals
,
667 option_align_targets
,
668 option_no_align_targets
,
670 option_warn_unaligned_targets
,
675 option_workaround_a0_b_retw
,
676 option_no_workaround_a0_b_retw
,
678 option_workaround_b_j_loop_end
,
679 option_no_workaround_b_j_loop_end
,
681 option_workaround_short_loop
,
682 option_no_workaround_short_loop
,
684 option_workaround_all_short_loops
,
685 option_no_workaround_all_short_loops
,
687 option_workaround_close_loop_end
,
688 option_no_workaround_close_loop_end
,
690 option_no_workarounds
,
692 option_rename_section_name
,
695 option_prefer_const16
,
697 option_target_hardware
,
700 option_no_trampolines
,
703 const char *md_shortopts
= "";
705 struct option md_longopts
[] =
707 { "density", no_argument
, NULL
, option_density
},
708 { "no-density", no_argument
, NULL
, option_no_density
},
710 { "flix", no_argument
, NULL
, option_flix
},
711 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
712 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
714 /* Both "relax" and "generics" are deprecated and treated as equivalent
715 to the "transform" option. */
716 { "relax", no_argument
, NULL
, option_relax
},
717 { "no-relax", no_argument
, NULL
, option_no_relax
},
718 { "generics", no_argument
, NULL
, option_generics
},
719 { "no-generics", no_argument
, NULL
, option_no_generics
},
721 { "transform", no_argument
, NULL
, option_transform
},
722 { "no-transform", no_argument
, NULL
, option_no_transform
},
723 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
724 { "no-text-section-literals", no_argument
, NULL
,
725 option_no_text_section_literals
},
726 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
727 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
728 /* This option was changed from -align-target to -target-align
729 because it conflicted with the "-al" option. */
730 { "target-align", no_argument
, NULL
, option_align_targets
},
731 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
732 { "warn-unaligned-targets", no_argument
, NULL
,
733 option_warn_unaligned_targets
},
734 { "longcalls", no_argument
, NULL
, option_longcalls
},
735 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
737 { "no-workaround-a0-b-retw", no_argument
, NULL
,
738 option_no_workaround_a0_b_retw
},
739 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
741 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
742 option_no_workaround_b_j_loop_end
},
743 { "workaround-b-j-loop-end", no_argument
, NULL
,
744 option_workaround_b_j_loop_end
},
746 { "no-workaround-short-loops", no_argument
, NULL
,
747 option_no_workaround_short_loop
},
748 { "workaround-short-loops", no_argument
, NULL
,
749 option_workaround_short_loop
},
751 { "no-workaround-all-short-loops", no_argument
, NULL
,
752 option_no_workaround_all_short_loops
},
753 { "workaround-all-short-loop", no_argument
, NULL
,
754 option_workaround_all_short_loops
},
756 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
757 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
759 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
761 { "no-workaround-close-loop-end", no_argument
, NULL
,
762 option_no_workaround_close_loop_end
},
763 { "workaround-close-loop-end", no_argument
, NULL
,
764 option_workaround_close_loop_end
},
766 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
768 { "link-relax", no_argument
, NULL
, option_link_relax
},
769 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
771 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
773 { "trampolines", no_argument
, NULL
, option_trampolines
},
774 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
776 { NULL
, no_argument
, NULL
, 0 }
779 size_t md_longopts_size
= sizeof md_longopts
;
783 md_parse_option (int c
, char *arg
)
788 as_warn (_("--density option is ignored"));
790 case option_no_density
:
791 as_warn (_("--no-density option is ignored"));
793 case option_link_relax
:
796 case option_no_link_relax
:
800 produce_flix
= FLIX_ALL
;
802 case option_no_generate_flix
:
803 produce_flix
= FLIX_NO_GENERATE
;
806 produce_flix
= FLIX_NONE
;
808 case option_generics
:
809 as_warn (_("--generics is deprecated; use --transform instead"));
810 return md_parse_option (option_transform
, arg
);
811 case option_no_generics
:
812 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
813 return md_parse_option (option_no_transform
, arg
);
815 as_warn (_("--relax is deprecated; use --transform instead"));
816 return md_parse_option (option_transform
, arg
);
817 case option_no_relax
:
818 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
819 return md_parse_option (option_no_transform
, arg
);
820 case option_longcalls
:
821 directive_state
[directive_longcalls
] = TRUE
;
823 case option_no_longcalls
:
824 directive_state
[directive_longcalls
] = FALSE
;
826 case option_text_section_literals
:
827 use_literal_section
= FALSE
;
829 case option_no_text_section_literals
:
830 use_literal_section
= TRUE
;
832 case option_absolute_literals
:
833 if (!absolute_literals_supported
)
835 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
838 directive_state
[directive_absolute_literals
] = TRUE
;
840 case option_no_absolute_literals
:
841 directive_state
[directive_absolute_literals
] = FALSE
;
844 case option_workaround_a0_b_retw
:
845 workaround_a0_b_retw
= TRUE
;
847 case option_no_workaround_a0_b_retw
:
848 workaround_a0_b_retw
= FALSE
;
850 case option_workaround_b_j_loop_end
:
851 workaround_b_j_loop_end
= TRUE
;
853 case option_no_workaround_b_j_loop_end
:
854 workaround_b_j_loop_end
= FALSE
;
857 case option_workaround_short_loop
:
858 workaround_short_loop
= TRUE
;
860 case option_no_workaround_short_loop
:
861 workaround_short_loop
= FALSE
;
864 case option_workaround_all_short_loops
:
865 workaround_all_short_loops
= TRUE
;
867 case option_no_workaround_all_short_loops
:
868 workaround_all_short_loops
= FALSE
;
871 case option_workaround_close_loop_end
:
872 workaround_close_loop_end
= TRUE
;
874 case option_no_workaround_close_loop_end
:
875 workaround_close_loop_end
= FALSE
;
878 case option_no_workarounds
:
879 workaround_a0_b_retw
= FALSE
;
880 workaround_b_j_loop_end
= FALSE
;
881 workaround_short_loop
= FALSE
;
882 workaround_all_short_loops
= FALSE
;
883 workaround_close_loop_end
= FALSE
;
886 case option_align_targets
:
887 align_targets
= TRUE
;
889 case option_no_align_targets
:
890 align_targets
= FALSE
;
893 case option_warn_unaligned_targets
:
894 warn_unaligned_branch_targets
= TRUE
;
897 case option_rename_section_name
:
898 build_section_rename (arg
);
902 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
903 should be emitted or not. FIXME: Not implemented. */
906 case option_prefer_l32r
:
908 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
912 case option_prefer_const16
:
914 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
918 case option_target_hardware
:
920 int earliest
, latest
= 0;
921 if (*arg
== 0 || *arg
== '-')
922 as_fatal (_("invalid target hardware version"));
924 earliest
= strtol (arg
, &arg
, 0);
928 else if (*arg
== '-')
931 as_fatal (_("invalid target hardware version"));
932 latest
= strtol (arg
, &arg
, 0);
935 as_fatal (_("invalid target hardware version"));
937 xtensa_setup_hw_workarounds (earliest
, latest
);
941 case option_transform
:
942 /* This option has no affect other than to use the defaults,
943 which are already set. */
946 case option_no_transform
:
947 /* This option turns off all transformations of any kind.
948 However, because we want to preserve the state of other
949 directives, we only change its own field. Thus, before
950 you perform any transformation, always check if transform
951 is available. If you use the functions we provide for this
952 purpose, you will be ok. */
953 directive_state
[directive_transform
] = FALSE
;
956 case option_trampolines
:
957 use_trampolines
= TRUE
;
960 case option_no_trampolines
:
961 use_trampolines
= FALSE
;
971 md_show_usage (FILE *stream
)
975 --[no-]text-section-literals\n\
976 [Do not] put literals in the text section\n\
977 --[no-]absolute-literals\n\
978 [Do not] default to use non-PC-relative literals\n\
979 --[no-]target-align [Do not] try to align branch targets\n\
980 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
981 --[no-]transform [Do not] transform instructions\n\
982 --flix both allow hand-written and generate flix bundles\n\
983 --no-generate-flix allow hand-written but do not generate\n\
985 --no-allow-flix neither allow hand-written nor generate\n\
987 --rename-section old=new Rename section 'old' to 'new'\n\
988 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
989 when jumps do not reach their targets\n", stream
);
993 /* Functions related to the list of current label symbols. */
996 xtensa_add_insn_label (symbolS
*sym
)
1000 if (!free_insn_labels
)
1001 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
1004 l
= free_insn_labels
;
1005 free_insn_labels
= l
->next
;
1009 l
->next
= insn_labels
;
1015 xtensa_clear_insn_labels (void)
1019 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1027 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1031 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1033 symbolS
*lit_sym
= lit
->sym
;
1034 S_SET_VALUE (lit_sym
, new_offset
);
1035 symbol_set_frag (lit_sym
, new_frag
);
1040 /* Directive data and functions. */
1042 typedef struct state_stackS_struct
1044 directiveE directive
;
1045 bfd_boolean negated
;
1046 bfd_boolean old_state
;
1050 struct state_stackS_struct
*prev
;
1053 state_stackS
*directive_state_stack
;
1055 const pseudo_typeS md_pseudo_table
[] =
1057 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1058 { "literal_position", xtensa_literal_position
, 0 },
1059 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1060 { "long", xtensa_elf_cons
, 4 },
1061 { "word", xtensa_elf_cons
, 4 },
1062 { "4byte", xtensa_elf_cons
, 4 },
1063 { "short", xtensa_elf_cons
, 2 },
1064 { "2byte", xtensa_elf_cons
, 2 },
1065 { "sleb128", xtensa_leb128
, 1},
1066 { "uleb128", xtensa_leb128
, 0},
1067 { "begin", xtensa_begin_directive
, 0 },
1068 { "end", xtensa_end_directive
, 0 },
1069 { "literal", xtensa_literal_pseudo
, 0 },
1070 { "frequency", xtensa_frequency_pseudo
, 0 },
1076 use_transform (void)
1078 /* After md_end, you should be checking frag by frag, rather
1079 than state directives. */
1080 gas_assert (!past_xtensa_end
);
1081 return directive_state
[directive_transform
];
1086 do_align_targets (void)
1088 /* Do not use this function after md_end; just look at align_targets
1089 instead. There is no target-align directive, so alignment is either
1090 enabled for all frags or not done at all. */
1091 gas_assert (!past_xtensa_end
);
1092 return align_targets
&& use_transform ();
1097 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1101 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1103 as_where (&file
, &line
);
1105 stack
->directive
= directive
;
1106 stack
->negated
= negated
;
1107 stack
->old_state
= directive_state
[directive
];
1110 stack
->datum
= datum
;
1111 stack
->prev
= directive_state_stack
;
1112 directive_state_stack
= stack
;
1114 directive_state
[directive
] = !negated
;
1119 directive_pop (directiveE
*directive
,
1120 bfd_boolean
*negated
,
1125 state_stackS
*top
= directive_state_stack
;
1127 if (!directive_state_stack
)
1129 as_bad (_("unmatched end directive"));
1130 *directive
= directive_none
;
1134 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1135 *directive
= top
->directive
;
1136 *negated
= top
->negated
;
1139 *datum
= top
->datum
;
1140 directive_state_stack
= top
->prev
;
1146 directive_balance (void)
1148 while (directive_state_stack
)
1150 directiveE directive
;
1151 bfd_boolean negated
;
1156 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1157 as_warn_where ((char *) file
, line
,
1158 _(".begin directive with no matching .end directive"));
1164 inside_directive (directiveE dir
)
1166 state_stackS
*top
= directive_state_stack
;
1168 while (top
&& top
->directive
!= dir
)
1171 return (top
!= NULL
);
1176 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1180 char *directive_string
;
1182 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1187 input_line_pointer
+= 3;
1190 len
= strspn (input_line_pointer
,
1191 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1193 /* This code is a hack to make .begin [no-][generics|relax] exactly
1194 equivalent to .begin [no-]transform. We should remove it when
1195 we stop accepting those options. */
1197 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1199 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1200 directive_string
= "transform";
1202 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1204 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1205 directive_string
= "transform";
1208 directive_string
= input_line_pointer
;
1210 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1212 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1214 input_line_pointer
+= len
;
1215 *directive
= (directiveE
) i
;
1216 if (*negated
&& !directive_info
[i
].can_be_negated
)
1217 as_bad (_("directive %s cannot be negated"),
1218 directive_info
[i
].name
);
1223 as_bad (_("unknown directive"));
1224 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1229 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1231 directiveE directive
;
1232 bfd_boolean negated
;
1236 get_directive (&directive
, &negated
);
1237 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1239 discard_rest_of_line ();
1243 if (cur_vinsn
.inside_bundle
)
1244 as_bad (_("directives are not valid inside bundles"));
1248 case directive_literal
:
1249 if (!inside_directive (directive_literal
))
1251 /* Previous labels go with whatever follows this directive, not with
1252 the literal, so save them now. */
1253 saved_insn_labels
= insn_labels
;
1256 as_warn (_(".begin literal is deprecated; use .literal instead"));
1257 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1258 xtensa_switch_to_literal_fragment (state
);
1259 directive_push (directive_literal
, negated
, state
);
1262 case directive_literal_prefix
:
1263 /* Have to flush pending output because a movi relaxed to an l32r
1264 might produce a literal. */
1265 md_flush_pending_output ();
1266 /* Check to see if the current fragment is a literal
1267 fragment. If it is, then this operation is not allowed. */
1268 if (generating_literals
)
1270 as_bad (_("cannot set literal_prefix inside literal fragment"));
1274 /* Allocate the literal state for this section and push
1275 onto the directive stack. */
1276 ls
= xmalloc (sizeof (lit_state
));
1279 *ls
= default_lit_sections
;
1280 directive_push (directive_literal_prefix
, negated
, ls
);
1282 /* Process the new prefix. */
1283 xtensa_literal_prefix ();
1286 case directive_freeregs
:
1287 /* This information is currently unused, but we'll accept the statement
1288 and just discard the rest of the line. This won't check the syntax,
1289 but it will accept every correct freeregs directive. */
1290 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1291 directive_push (directive_freeregs
, negated
, 0);
1294 case directive_schedule
:
1295 md_flush_pending_output ();
1296 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1297 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1298 directive_push (directive_schedule
, negated
, 0);
1299 xtensa_set_frag_assembly_state (frag_now
);
1302 case directive_density
:
1303 as_warn (_(".begin [no-]density is ignored"));
1306 case directive_absolute_literals
:
1307 md_flush_pending_output ();
1308 if (!absolute_literals_supported
&& !negated
)
1310 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1313 xtensa_set_frag_assembly_state (frag_now
);
1314 directive_push (directive
, negated
, 0);
1318 md_flush_pending_output ();
1319 xtensa_set_frag_assembly_state (frag_now
);
1320 directive_push (directive
, negated
, 0);
1324 demand_empty_rest_of_line ();
1329 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1331 directiveE begin_directive
, end_directive
;
1332 bfd_boolean begin_negated
, end_negated
;
1336 emit_state
**state_ptr
;
1339 if (cur_vinsn
.inside_bundle
)
1340 as_bad (_("directives are not valid inside bundles"));
1342 get_directive (&end_directive
, &end_negated
);
1344 md_flush_pending_output ();
1346 switch ((int) end_directive
)
1348 case XTENSA_UNDEFINED
:
1349 discard_rest_of_line ();
1352 case (int) directive_density
:
1353 as_warn (_(".end [no-]density is ignored"));
1354 demand_empty_rest_of_line ();
1357 case (int) directive_absolute_literals
:
1358 if (!absolute_literals_supported
&& !end_negated
)
1360 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1361 demand_empty_rest_of_line ();
1370 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1371 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1372 (const void **) state_ptr
);
1374 if (begin_directive
!= directive_none
)
1376 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1378 as_bad (_("does not match begin %s%s at %s:%d"),
1379 begin_negated
? "no-" : "",
1380 directive_info
[begin_directive
].name
, file
, line
);
1384 switch (end_directive
)
1386 case directive_literal
:
1387 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1388 xtensa_restore_emit_state (state
);
1389 xtensa_set_frag_assembly_state (frag_now
);
1391 if (!inside_directive (directive_literal
))
1393 /* Restore the list of current labels. */
1394 xtensa_clear_insn_labels ();
1395 insn_labels
= saved_insn_labels
;
1399 case directive_literal_prefix
:
1400 /* Restore the default collection sections from saved state. */
1401 s
= (lit_state
*) state
;
1403 default_lit_sections
= *s
;
1405 /* Free the state storage. */
1406 free (s
->lit_prefix
);
1410 case directive_schedule
:
1411 case directive_freeregs
:
1415 xtensa_set_frag_assembly_state (frag_now
);
1421 demand_empty_rest_of_line ();
1425 /* Place an aligned literal fragment at the current location. */
1428 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1430 md_flush_pending_output ();
1432 if (inside_directive (directive_literal
))
1433 as_warn (_(".literal_position inside literal directive; ignoring"));
1434 xtensa_mark_literal_pool_location ();
1436 demand_empty_rest_of_line ();
1437 xtensa_clear_insn_labels ();
1441 /* Support .literal label, expr, ... */
1444 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1447 char *p
, *base_name
;
1451 if (inside_directive (directive_literal
))
1453 as_bad (_(".literal not allowed inside .begin literal region"));
1454 ignore_rest_of_line ();
1458 md_flush_pending_output ();
1460 /* Previous labels go with whatever follows this directive, not with
1461 the literal, so save them now. */
1462 saved_insn_labels
= insn_labels
;
1465 /* If we are using text-section literals, then this is the right value... */
1468 base_name
= input_line_pointer
;
1470 xtensa_switch_to_literal_fragment (&state
);
1472 /* ...but if we aren't using text-section-literals, then we
1473 need to put them in the section we just switched to. */
1474 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1477 /* FIXME, despite the previous comments, dest_seg is unused... */
1480 /* All literals are aligned to four-byte boundaries. */
1481 frag_align (2, 0, 0);
1482 record_alignment (now_seg
, 2);
1484 c
= get_symbol_end ();
1485 /* Just after name is now '\0'. */
1486 p
= input_line_pointer
;
1490 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1492 as_bad (_("expected comma or colon after symbol name; "
1493 "rest of line ignored"));
1494 ignore_rest_of_line ();
1495 xtensa_restore_emit_state (&state
);
1503 input_line_pointer
++; /* skip ',' or ':' */
1505 xtensa_elf_cons (4);
1507 xtensa_restore_emit_state (&state
);
1509 /* Restore the list of current labels. */
1510 xtensa_clear_insn_labels ();
1511 insn_labels
= saved_insn_labels
;
1516 xtensa_literal_prefix (void)
1521 /* Parse the new prefix from the input_line_pointer. */
1523 len
= strspn (input_line_pointer
,
1524 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1525 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1527 /* Get a null-terminated copy of the name. */
1528 name
= xmalloc (len
+ 1);
1530 strncpy (name
, input_line_pointer
, len
);
1533 /* Skip the name in the input line. */
1534 input_line_pointer
+= len
;
1536 default_lit_sections
.lit_prefix
= name
;
1538 /* Clear cached literal sections, since the prefix has changed. */
1539 default_lit_sections
.lit_seg
= NULL
;
1540 default_lit_sections
.lit4_seg
= NULL
;
1544 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1547 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1549 float fall_through_f
, target_f
;
1551 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1552 if (fall_through_f
< 0)
1554 as_bad (_("fall through frequency must be greater than 0"));
1555 ignore_rest_of_line ();
1559 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1562 as_bad (_("branch target frequency must be greater than 0"));
1563 ignore_rest_of_line ();
1567 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1569 demand_empty_rest_of_line ();
1573 /* Like normal .long/.short/.word, except support @plt, etc.
1574 Clobbers input_line_pointer, checks end-of-line. */
1577 xtensa_elf_cons (int nbytes
)
1580 bfd_reloc_code_real_type reloc
;
1582 md_flush_pending_output ();
1584 if (cur_vinsn
.inside_bundle
)
1585 as_bad (_("directives are not valid inside bundles"));
1587 if (is_it_end_of_statement ())
1589 demand_empty_rest_of_line ();
1596 if (exp
.X_op
== O_symbol
1597 && *input_line_pointer
== '@'
1598 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1601 reloc_howto_type
*reloc_howto
=
1602 bfd_reloc_type_lookup (stdoutput
, reloc
);
1604 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1605 as_bad (_("unsupported relocation"));
1606 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1607 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1608 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1609 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1610 as_bad (_("opcode-specific %s relocation used outside "
1611 "an instruction"), reloc_howto
->name
);
1612 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1613 as_bad (_("%s relocations do not fit in %d bytes"),
1614 reloc_howto
->name
, nbytes
);
1615 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1616 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1617 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1618 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1621 char *p
= frag_more ((int) nbytes
);
1622 xtensa_set_frag_assembly_state (frag_now
);
1623 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1624 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1629 xtensa_set_frag_assembly_state (frag_now
);
1630 emit_expr (&exp
, (unsigned int) nbytes
);
1633 while (*input_line_pointer
++ == ',');
1635 input_line_pointer
--; /* Put terminator back into stream. */
1636 demand_empty_rest_of_line ();
1639 static bfd_boolean is_leb128_expr
;
1642 xtensa_leb128 (int sign
)
1644 is_leb128_expr
= TRUE
;
1646 is_leb128_expr
= FALSE
;
1650 /* Parsing and Idiom Translation. */
1652 /* Parse @plt, etc. and return the desired relocation. */
1653 static bfd_reloc_code_real_type
1654 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1661 struct suffix_reloc_map
*ptr
;
1664 return BFD_RELOC_NONE
;
1666 for (ch
= *str
, str2
= ident
;
1667 (str2
< ident
+ sizeof (ident
) - 1
1668 && (ISALNUM (ch
) || ch
== '@'));
1671 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1678 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1679 if (ch
== ptr
->suffix
[0]
1680 && len
== ptr
->length
1681 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1683 /* Now check for "identifier@suffix+constant". */
1684 if (*str
== '-' || *str
== '+')
1686 char *orig_line
= input_line_pointer
;
1687 expressionS new_exp
;
1689 input_line_pointer
= str
;
1690 expression (&new_exp
);
1691 if (new_exp
.X_op
== O_constant
)
1693 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1694 str
= input_line_pointer
;
1697 if (&input_line_pointer
!= str_p
)
1698 input_line_pointer
= orig_line
;
1705 return BFD_RELOC_UNUSED
;
1709 /* Find the matching operator type. */
1710 static unsigned char
1711 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1713 struct suffix_reloc_map
*sfx
;
1714 unsigned char operator = (unsigned char) -1;
1716 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1718 if (sfx
->reloc
== reloc
)
1720 operator = sfx
->operator;
1724 gas_assert (operator != (unsigned char) -1);
1729 /* Find the matching reloc type. */
1730 static bfd_reloc_code_real_type
1731 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1733 struct suffix_reloc_map
*sfx
;
1734 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1736 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1738 if (sfx
->operator == operator)
1747 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1748 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1749 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1750 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1753 if (reloc
== BFD_RELOC_UNUSED
)
1754 return BFD_RELOC_32
;
1761 expression_end (const char *name
)
1784 #define ERROR_REG_NUM ((unsigned) -1)
1787 tc_get_register (const char *prefix
)
1790 const char *next_expr
;
1791 const char *old_line_pointer
;
1794 old_line_pointer
= input_line_pointer
;
1796 if (*input_line_pointer
== '$')
1797 ++input_line_pointer
;
1799 /* Accept "sp" as a synonym for "a1". */
1800 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1801 && expression_end (input_line_pointer
+ 2))
1803 input_line_pointer
+= 2;
1804 return 1; /* AR[1] */
1807 while (*input_line_pointer
++ == *prefix
++)
1809 --input_line_pointer
;
1814 as_bad (_("bad register name: %s"), old_line_pointer
);
1815 return ERROR_REG_NUM
;
1818 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1820 as_bad (_("bad register number: %s"), input_line_pointer
);
1821 return ERROR_REG_NUM
;
1826 while (ISDIGIT ((int) *input_line_pointer
))
1827 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1829 if (!(next_expr
= expression_end (input_line_pointer
)))
1831 as_bad (_("bad register name: %s"), old_line_pointer
);
1832 return ERROR_REG_NUM
;
1835 input_line_pointer
= (char *) next_expr
;
1842 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1844 xtensa_isa isa
= xtensa_default_isa
;
1846 /* Check if this is an immediate operand. */
1847 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1849 bfd_reloc_code_real_type reloc
;
1850 segT t
= expression (tok
);
1852 if (t
== absolute_section
1853 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1855 gas_assert (tok
->X_op
== O_constant
);
1856 tok
->X_op
= O_symbol
;
1857 tok
->X_add_symbol
= &abs_symbol
;
1860 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1861 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1866 case BFD_RELOC_LO16
:
1867 if (tok
->X_op
== O_constant
)
1869 tok
->X_add_number
&= 0xffff;
1873 case BFD_RELOC_HI16
:
1874 if (tok
->X_op
== O_constant
)
1876 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1880 case BFD_RELOC_UNUSED
:
1881 as_bad (_("unsupported relocation"));
1883 case BFD_RELOC_32_PCREL
:
1884 as_bad (_("pcrel relocation not allowed in an instruction"));
1889 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1894 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1895 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1897 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1900 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1901 as_bad (_("register number out of range"));
1904 tok
->X_op
= O_register
;
1905 tok
->X_add_symbol
= 0;
1906 tok
->X_add_number
= reg
;
1911 /* Split up the arguments for an opcode or pseudo-op. */
1914 tokenize_arguments (char **args
, char *str
)
1916 char *old_input_line_pointer
;
1917 bfd_boolean saw_comma
= FALSE
;
1918 bfd_boolean saw_arg
= FALSE
;
1919 bfd_boolean saw_colon
= FALSE
;
1921 char *arg_end
, *arg
;
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1926 input_line_pointer
= str
;
1928 while (*input_line_pointer
)
1931 switch (*input_line_pointer
)
1938 input_line_pointer
++;
1939 if (saw_comma
|| saw_colon
|| !saw_arg
)
1945 input_line_pointer
++;
1946 if (saw_comma
|| saw_colon
|| !saw_arg
)
1952 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1955 arg_end
= input_line_pointer
+ 1;
1956 while (!expression_end (arg_end
))
1959 arg_len
= arg_end
- input_line_pointer
;
1960 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1961 args
[num_args
] = arg
;
1965 strncpy (arg
, input_line_pointer
, arg_len
);
1966 arg
[arg_len
] = '\0';
1968 input_line_pointer
= arg_end
;
1978 if (saw_comma
|| saw_colon
)
1980 input_line_pointer
= old_input_line_pointer
;
1985 as_bad (_("extra comma"));
1987 as_bad (_("extra colon"));
1989 as_bad (_("missing argument"));
1991 as_bad (_("missing comma or colon"));
1992 input_line_pointer
= old_input_line_pointer
;
1997 /* Parse the arguments to an opcode. Return TRUE on error. */
2000 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2002 expressionS
*tok
, *last_tok
;
2003 xtensa_opcode opcode
= insn
->opcode
;
2004 bfd_boolean had_error
= TRUE
;
2005 xtensa_isa isa
= xtensa_default_isa
;
2006 int n
, num_regs
= 0;
2007 int opcode_operand_count
;
2008 int opnd_cnt
, last_opnd_cnt
;
2009 unsigned int next_reg
= 0;
2010 char *old_input_line_pointer
;
2012 if (insn
->insn_type
== ITYPE_LITERAL
)
2013 opcode_operand_count
= 1;
2015 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2018 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2020 /* Save and restore input_line_pointer around this function. */
2021 old_input_line_pointer
= input_line_pointer
;
2027 /* Skip invisible operands. */
2028 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2034 for (n
= 0; n
< num_args
; n
++)
2036 input_line_pointer
= arg_strings
[n
];
2037 if (*input_line_pointer
== ':')
2039 xtensa_regfile opnd_rf
;
2040 input_line_pointer
++;
2043 gas_assert (opnd_cnt
> 0);
2045 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2047 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2048 as_warn (_("incorrect register number, ignoring"));
2053 if (opnd_cnt
>= opcode_operand_count
)
2055 as_warn (_("too many arguments"));
2058 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2060 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2061 next_reg
= tok
->X_add_number
+ 1;
2063 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2065 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2067 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2068 /* minus 1 because we are seeing one right now */
2074 last_opnd_cnt
= opnd_cnt
;
2075 demand_empty_rest_of_line ();
2082 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2086 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2089 insn
->ntok
= tok
- insn
->tok
;
2093 input_line_pointer
= old_input_line_pointer
;
2099 get_invisible_operands (TInsn
*insn
)
2101 xtensa_isa isa
= xtensa_default_isa
;
2102 static xtensa_insnbuf slotbuf
= NULL
;
2104 xtensa_opcode opc
= insn
->opcode
;
2105 int slot
, opnd
, fmt_found
;
2109 slotbuf
= xtensa_insnbuf_alloc (isa
);
2111 /* Find format/slot where this can be encoded. */
2114 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2116 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2118 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2124 if (fmt_found
) break;
2129 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2133 /* First encode all the visible operands
2134 (to deal with shared field operands). */
2135 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2137 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2138 && (insn
->tok
[opnd
].X_op
== O_register
2139 || insn
->tok
[opnd
].X_op
== O_constant
))
2141 val
= insn
->tok
[opnd
].X_add_number
;
2142 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2143 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2147 /* Then pull out the values for the invisible ones. */
2148 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2150 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2152 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2153 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2154 insn
->tok
[opnd
].X_add_number
= val
;
2155 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2156 insn
->tok
[opnd
].X_op
= O_register
;
2158 insn
->tok
[opnd
].X_op
= O_constant
;
2167 xg_reverse_shift_count (char **cnt_argp
)
2169 char *cnt_arg
, *new_arg
;
2170 cnt_arg
= *cnt_argp
;
2172 /* replace the argument with "31-(argument)" */
2173 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2174 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2177 *cnt_argp
= new_arg
;
2181 /* If "arg" is a constant expression, return non-zero with the value
2185 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2188 char *save_ptr
= input_line_pointer
;
2190 input_line_pointer
= arg
;
2192 input_line_pointer
= save_ptr
;
2194 if (exp
.X_op
== O_constant
)
2196 *valp
= exp
.X_add_number
;
2205 xg_replace_opname (char **popname
, char *newop
)
2208 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2209 strcpy (*popname
, newop
);
2214 xg_check_num_args (int *pnum_args
,
2219 int num_args
= *pnum_args
;
2221 if (num_args
< expected_num
)
2223 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2224 num_args
, opname
, expected_num
);
2228 if (num_args
> expected_num
)
2230 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2231 num_args
, opname
, expected_num
);
2232 while (num_args
-- > expected_num
)
2234 free (arg_strings
[num_args
]);
2235 arg_strings
[num_args
] = 0;
2237 *pnum_args
= expected_num
;
2245 /* If the register is not specified as part of the opcode,
2246 then get it from the operand and move it to the opcode. */
2249 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2251 xtensa_isa isa
= xtensa_default_isa
;
2253 char *opname
, *new_opname
;
2254 const char *sr_name
;
2255 int is_user
, is_write
;
2260 is_user
= (opname
[1] == 'u');
2261 is_write
= (opname
[0] == 'w');
2263 /* Opname == [rw]ur or [rwx]sr... */
2265 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2268 /* Check if the argument is a symbolic register name. */
2269 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2270 /* Handle WSR to "INTSET" as a special case. */
2271 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2272 && !strcasecmp (arg_strings
[1], "intset"))
2273 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2274 if (sr
== XTENSA_UNDEFINED
2275 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2277 /* Maybe it's a register number.... */
2279 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2281 as_bad (_("invalid register '%s' for '%s' instruction"),
2282 arg_strings
[1], opname
);
2285 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2286 if (sr
== XTENSA_UNDEFINED
)
2288 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2289 (long) val
, opname
);
2294 /* Remove the last argument, which is now part of the opcode. */
2295 free (arg_strings
[1]);
2299 /* Translate the opcode. */
2300 sr_name
= xtensa_sysreg_name (isa
, sr
);
2301 /* Another special case for "WSR.INTSET".... */
2302 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2304 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2305 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2307 *popname
= new_opname
;
2314 xtensa_translate_old_userreg_ops (char **popname
)
2316 xtensa_isa isa
= xtensa_default_isa
;
2318 char *opname
, *new_opname
;
2319 const char *sr_name
;
2320 bfd_boolean has_underbar
= FALSE
;
2323 if (opname
[0] == '_')
2325 has_underbar
= TRUE
;
2329 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2330 if (sr
!= XTENSA_UNDEFINED
)
2332 /* The new default name ("nnn") is different from the old default
2333 name ("URnnn"). The old default is handled below, and we don't
2334 want to recognize [RW]nnn, so do nothing if the name is the (new)
2336 static char namebuf
[10];
2337 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2338 if (strcmp (namebuf
, opname
+ 1) == 0)
2346 /* Only continue if the reg name is "URnnn". */
2347 if (opname
[1] != 'u' || opname
[2] != 'r')
2349 val
= strtoul (opname
+ 3, &end
, 10);
2353 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2354 if (sr
== XTENSA_UNDEFINED
)
2356 as_bad (_("invalid register number (%ld) for '%s'"),
2357 (long) val
, opname
);
2362 /* Translate the opcode. */
2363 sr_name
= xtensa_sysreg_name (isa
, sr
);
2364 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2365 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2366 opname
[0], sr_name
);
2368 *popname
= new_opname
;
2375 xtensa_translate_zero_immed (char *old_op
,
2385 gas_assert (opname
[0] != '_');
2387 if (strcmp (opname
, old_op
) != 0)
2390 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2392 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2394 xg_replace_opname (popname
, new_op
);
2395 free (arg_strings
[1]);
2396 arg_strings
[1] = arg_strings
[2];
2405 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2406 Returns non-zero if an error was found. */
2409 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2411 char *opname
= *popname
;
2412 bfd_boolean has_underbar
= FALSE
;
2416 has_underbar
= TRUE
;
2420 if (strcmp (opname
, "mov") == 0)
2422 if (use_transform () && !has_underbar
&& density_supported
)
2423 xg_replace_opname (popname
, "mov.n");
2426 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2428 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2429 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2430 strcpy (arg_strings
[2], arg_strings
[1]);
2436 if (strcmp (opname
, "bbsi.l") == 0)
2438 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2440 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2441 if (target_big_endian
)
2442 xg_reverse_shift_count (&arg_strings
[1]);
2446 if (strcmp (opname
, "bbci.l") == 0)
2448 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2450 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2451 if (target_big_endian
)
2452 xg_reverse_shift_count (&arg_strings
[1]);
2456 /* Don't do anything special with NOPs inside FLIX instructions. They
2457 are handled elsewhere. Real NOP instructions are always available
2458 in configurations with FLIX, so this should never be an issue but
2459 check for it anyway. */
2460 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2461 && strcmp (opname
, "nop") == 0)
2463 if (use_transform () && !has_underbar
&& density_supported
)
2464 xg_replace_opname (popname
, "nop.n");
2467 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2469 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2470 arg_strings
[0] = (char *) xmalloc (3);
2471 arg_strings
[1] = (char *) xmalloc (3);
2472 arg_strings
[2] = (char *) xmalloc (3);
2473 strcpy (arg_strings
[0], "a1");
2474 strcpy (arg_strings
[1], "a1");
2475 strcpy (arg_strings
[2], "a1");
2481 /* Recognize [RW]UR and [RWX]SR. */
2482 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2483 && (opname
[1] == 'u' || opname
[1] == 's'))
2484 || (opname
[0] == 'x' && opname
[1] == 's'))
2486 && opname
[3] == '\0')
2487 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2489 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2490 [RW]<name> if <name> is the non-default name of a user register. */
2491 if ((opname
[0] == 'r' || opname
[0] == 'w')
2492 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2493 return xtensa_translate_old_userreg_ops (popname
);
2495 /* Relax branches that don't allow comparisons against an immediate value
2496 of zero to the corresponding branches with implicit zero immediates. */
2497 if (!has_underbar
&& use_transform ())
2499 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2500 pnum_args
, arg_strings
))
2503 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2504 pnum_args
, arg_strings
))
2507 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2508 pnum_args
, arg_strings
))
2511 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2512 pnum_args
, arg_strings
))
2520 /* Functions for dealing with the Xtensa ISA. */
2522 /* Currently the assembler only allows us to use a single target per
2523 fragment. Because of this, only one operand for a given
2524 instruction may be symbolic. If there is a PC-relative operand,
2525 the last one is chosen. Otherwise, the result is the number of the
2526 last immediate operand, and if there are none of those, we fail and
2530 get_relaxable_immed (xtensa_opcode opcode
)
2532 int last_immed
= -1;
2535 if (opcode
== XTENSA_UNDEFINED
)
2538 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2539 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2541 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2543 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2545 if (last_immed
== -1
2546 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2553 static xtensa_opcode
2554 get_opcode_from_buf (const char *buf
, int slot
)
2556 static xtensa_insnbuf insnbuf
= NULL
;
2557 static xtensa_insnbuf slotbuf
= NULL
;
2558 xtensa_isa isa
= xtensa_default_isa
;
2563 insnbuf
= xtensa_insnbuf_alloc (isa
);
2564 slotbuf
= xtensa_insnbuf_alloc (isa
);
2567 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2568 fmt
= xtensa_format_decode (isa
, insnbuf
);
2569 if (fmt
== XTENSA_UNDEFINED
)
2570 return XTENSA_UNDEFINED
;
2572 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2573 return XTENSA_UNDEFINED
;
2575 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2576 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2580 #ifdef TENSILICA_DEBUG
2582 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2585 xtensa_print_insn_table (void)
2587 int num_opcodes
, num_operands
;
2588 xtensa_opcode opcode
;
2589 xtensa_isa isa
= xtensa_default_isa
;
2591 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2592 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2595 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2596 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2597 for (opn
= 0; opn
< num_operands
; opn
++)
2599 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2601 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2603 xtensa_regfile opnd_rf
=
2604 xtensa_operand_regfile (isa
, opcode
, opn
);
2605 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2607 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2608 fputs ("[lLr] ", stderr
);
2610 fputs ("i ", stderr
);
2612 fprintf (stderr
, "\n");
2618 print_vliw_insn (xtensa_insnbuf vbuf
)
2620 xtensa_isa isa
= xtensa_default_isa
;
2621 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2622 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2625 fprintf (stderr
, "format = %d\n", f
);
2627 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2629 xtensa_opcode opcode
;
2633 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2634 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2635 opname
= xtensa_opcode_name (isa
, opcode
);
2637 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2638 fprintf (stderr
, " operands = ");
2640 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2644 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2646 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2647 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2648 fprintf (stderr
, "%d ", val
);
2650 fprintf (stderr
, "\n");
2652 xtensa_insnbuf_free (isa
, sbuf
);
2655 #endif /* TENSILICA_DEBUG */
2659 is_direct_call_opcode (xtensa_opcode opcode
)
2661 xtensa_isa isa
= xtensa_default_isa
;
2662 int n
, num_operands
;
2664 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2667 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2668 for (n
= 0; n
< num_operands
; n
++)
2670 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2671 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2678 /* Convert from BFD relocation type code to slot and operand number.
2679 Returns non-zero on failure. */
2682 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2684 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2685 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2687 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2690 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2691 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2693 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2703 /* Convert from slot number to BFD relocation type code for the
2704 standard PC-relative relocations. Return BFD_RELOC_NONE on
2707 static bfd_reloc_code_real_type
2708 encode_reloc (int slot
)
2710 if (slot
< 0 || slot
> 14)
2711 return BFD_RELOC_NONE
;
2713 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2717 /* Convert from slot numbers to BFD relocation type code for the
2718 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2720 static bfd_reloc_code_real_type
2721 encode_alt_reloc (int slot
)
2723 if (slot
< 0 || slot
> 14)
2724 return BFD_RELOC_NONE
;
2726 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2731 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2734 xtensa_opcode opcode
,
2740 uint32 valbuf
= value
;
2742 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2744 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2746 as_bad_where ((char *) file
, line
,
2747 _("operand %d of '%s' has out of range value '%u'"),
2749 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2752 as_bad_where ((char *) file
, line
,
2753 _("operand %d of '%s' has invalid value '%u'"),
2755 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2760 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2766 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2769 xtensa_opcode opcode
,
2773 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2774 fmt
, slot
, slotbuf
, &val
);
2775 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2780 /* Checks for rules from xtensa-relax tables. */
2782 /* The routine xg_instruction_matches_option_term must return TRUE
2783 when a given option term is true. The meaning of all of the option
2784 terms is given interpretation by this function. */
2787 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2789 if (strcmp (option
->option_name
, "realnop") == 0
2790 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2792 /* These conditions were evaluated statically when building the
2793 relaxation table. There's no need to reevaluate them now. */
2796 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2797 return insn
->extra_arg
.X_op
== O_register
;
2800 as_fatal (_("internal error: unknown option name '%s'"),
2801 option
->option_name
);
2807 xg_instruction_matches_or_options (TInsn
*insn
,
2808 const ReqOrOptionList
*or_option
)
2810 const ReqOrOption
*option
;
2811 /* Must match each of the AND terms. */
2812 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2814 if (xg_instruction_matches_option_term (insn
, option
))
2822 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2824 const ReqOption
*req_options
;
2825 /* Must match each of the AND terms. */
2826 for (req_options
= options
;
2827 req_options
!= NULL
;
2828 req_options
= req_options
->next
)
2830 /* Must match one of the OR clauses. */
2831 if (!xg_instruction_matches_or_options (insn
,
2832 req_options
->or_option_terms
))
2839 /* Return the transition rule that matches or NULL if none matches. */
2842 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2844 PreconditionList
*condition_l
;
2846 if (rule
->opcode
!= insn
->opcode
)
2849 for (condition_l
= rule
->conditions
;
2850 condition_l
!= NULL
;
2851 condition_l
= condition_l
->next
)
2855 Precondition
*cond
= condition_l
->precond
;
2860 /* The expression must be the constant. */
2861 gas_assert (cond
->op_num
< insn
->ntok
);
2862 exp1
= &insn
->tok
[cond
->op_num
];
2863 if (expr_is_const (exp1
))
2868 if (get_expr_const (exp1
) != cond
->op_data
)
2872 if (get_expr_const (exp1
) == cond
->op_data
)
2879 else if (expr_is_register (exp1
))
2884 if (get_expr_register (exp1
) != cond
->op_data
)
2888 if (get_expr_register (exp1
) == cond
->op_data
)
2900 gas_assert (cond
->op_num
< insn
->ntok
);
2901 gas_assert (cond
->op_data
< insn
->ntok
);
2902 exp1
= &insn
->tok
[cond
->op_num
];
2903 exp2
= &insn
->tok
[cond
->op_data
];
2908 if (!expr_is_equal (exp1
, exp2
))
2912 if (expr_is_equal (exp1
, exp2
))
2924 if (!xg_instruction_matches_options (insn
, rule
->options
))
2932 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2934 bfd_boolean a_greater
= FALSE
;
2935 bfd_boolean b_greater
= FALSE
;
2937 ReqOptionList
*l_a
= a
->options
;
2938 ReqOptionList
*l_b
= b
->options
;
2940 /* We only care if they both are the same except for
2941 a const16 vs. an l32r. */
2943 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2945 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2946 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2947 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2949 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2951 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2953 /* This is the case we care about. */
2954 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2955 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2962 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2963 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2973 l_or_a
= l_or_a
->next
;
2974 l_or_b
= l_or_b
->next
;
2976 if (l_or_a
|| l_or_b
)
2985 /* Incomparable if the substitution was used differently in two cases. */
2986 if (a_greater
&& b_greater
)
2998 static TransitionRule
*
2999 xg_instruction_match (TInsn
*insn
)
3001 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3003 gas_assert (insn
->opcode
< table
->num_opcodes
);
3005 /* Walk through all of the possible transitions. */
3006 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3008 TransitionRule
*rule
= l
->rule
;
3009 if (xg_instruction_matches_rule (insn
, rule
))
3016 /* Various Other Internal Functions. */
3019 is_unique_insn_expansion (TransitionRule
*r
)
3021 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3023 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3029 /* Check if there is exactly one relaxation for INSN that converts it to
3030 another instruction of equal or larger size. If so, and if TARG is
3031 non-null, go ahead and generate the relaxed instruction into TARG. If
3032 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3033 instruction, i.e., ignore relaxations that convert to an instruction of
3034 equal size. In some contexts where this function is used, only
3035 a single widening is allowed and the NARROW_ONLY argument is used to
3036 exclude cases like ADDI being "widened" to an ADDMI, which may
3037 later be relaxed to an ADDMI/ADDI pair. */
3040 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3042 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3044 TransitionRule
*match
= 0;
3046 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3047 gas_assert (insn
->opcode
< table
->num_opcodes
);
3049 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3051 TransitionRule
*rule
= l
->rule
;
3053 if (xg_instruction_matches_rule (insn
, rule
)
3054 && is_unique_insn_expansion (rule
)
3055 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3056 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3067 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3072 /* Return the maximum number of bytes this opcode can expand to. */
3075 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3077 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3079 int max_size
= xg_get_single_size (opcode
);
3081 gas_assert (opcode
< table
->num_opcodes
);
3083 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3085 TransitionRule
*rule
= l
->rule
;
3086 BuildInstr
*build_list
;
3091 build_list
= rule
->to_instr
;
3092 if (is_unique_insn_expansion (rule
))
3094 gas_assert (build_list
->typ
== INSTR_INSTR
);
3095 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3098 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3100 switch (build_list
->typ
)
3103 this_size
+= xg_get_single_size (build_list
->opcode
);
3105 case INSTR_LITERAL_DEF
:
3106 case INSTR_LABEL_DEF
:
3111 if (this_size
> max_size
)
3112 max_size
= this_size
;
3118 /* Return the maximum number of literal bytes this opcode can generate. */
3121 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3123 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3127 gas_assert (opcode
< table
->num_opcodes
);
3129 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3131 TransitionRule
*rule
= l
->rule
;
3132 BuildInstr
*build_list
;
3137 build_list
= rule
->to_instr
;
3138 if (is_unique_insn_expansion (rule
))
3140 gas_assert (build_list
->typ
== INSTR_INSTR
);
3141 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3144 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3146 switch (build_list
->typ
)
3148 case INSTR_LITERAL_DEF
:
3149 /* Hard-coded 4-byte literal. */
3153 case INSTR_LABEL_DEF
:
3158 if (this_size
> max_size
)
3159 max_size
= this_size
;
3166 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3168 int steps_taken
= 0;
3169 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3172 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3173 gas_assert (insn
->opcode
< table
->num_opcodes
);
3175 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3177 TransitionRule
*rule
= l
->rule
;
3179 if (xg_instruction_matches_rule (insn
, rule
))
3181 if (steps_taken
== lateral_steps
)
3191 get_special_literal_symbol (void)
3193 static symbolS
*sym
= NULL
;
3196 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3202 get_special_label_symbol (void)
3204 static symbolS
*sym
= NULL
;
3207 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3213 xg_valid_literal_expression (const expressionS
*exp
)
3235 /* This will check to see if the value can be converted into the
3236 operand type. It will return TRUE if it does not fit. */
3239 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3241 uint32 valbuf
= value
;
3242 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3248 /* Assumes: All immeds are constants. Check that all constants fit
3249 into their immeds; return FALSE if not. */
3252 xg_immeds_fit (const TInsn
*insn
)
3254 xtensa_isa isa
= xtensa_default_isa
;
3258 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3259 for (i
= 0; i
< n
; ++i
)
3261 const expressionS
*exp
= &insn
->tok
[i
];
3263 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3270 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3275 /* The symbol should have a fixup associated with it. */
3284 /* This should only be called after we have an initial
3285 estimate of the addresses. */
3288 xg_symbolic_immeds_fit (const TInsn
*insn
,
3294 xtensa_isa isa
= xtensa_default_isa
;
3302 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3304 for (i
= 0; i
< n
; ++i
)
3306 const expressionS
*exp
= &insn
->tok
[i
];
3308 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3315 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3321 /* Check for the worst case. */
3322 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3327 /* We only allow symbols for PC-relative references.
3328 If pc_frag == 0, then we don't have frag locations yet. */
3330 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3333 /* If it is a weak symbol or a symbol in a different section,
3334 it cannot be known to fit at assembly time. */
3335 if (S_IS_WEAK (exp
->X_add_symbol
)
3336 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3338 /* For a direct call with --no-longcalls, be optimistic and
3339 assume it will be in range. If the symbol is weak and
3340 undefined, it may remain undefined at link-time, in which
3341 case it will have a zero value and almost certainly be out
3342 of range for a direct call; thus, relax for undefined weak
3343 symbols even if longcalls is not enabled. */
3344 if (is_direct_call_opcode (insn
->opcode
)
3345 && ! pc_frag
->tc_frag_data
.use_longcalls
3346 && (! S_IS_WEAK (exp
->X_add_symbol
)
3347 || S_IS_DEFINED (exp
->X_add_symbol
)))
3353 symbolP
= exp
->X_add_symbol
;
3354 sym_frag
= symbol_get_frag (symbolP
);
3355 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3356 pc
= pc_frag
->fr_address
+ pc_offset
;
3358 /* If frag has yet to be reached on this pass, assume it
3359 will move by STRETCH just as we did. If this is not so,
3360 it will be because some frag between grows, and that will
3361 force another pass. Beware zero-length frags. There
3362 should be a faster way to do this. */
3365 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3366 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3371 new_offset
= target
;
3372 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3373 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3378 /* The symbol should have a fixup associated with it. */
3387 /* Return TRUE on success. */
3390 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3396 targ
->debug_line
= insn
->debug_line
;
3397 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3402 targ
->opcode
= bi
->opcode
;
3403 targ
->insn_type
= ITYPE_INSN
;
3404 targ
->is_specific_opcode
= FALSE
;
3406 for (; op
!= NULL
; op
= op
->next
)
3408 int op_num
= op
->op_num
;
3409 int op_data
= op
->op_data
;
3411 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3413 if (targ
->ntok
<= op_num
)
3414 targ
->ntok
= op_num
+ 1;
3419 set_expr_const (&targ
->tok
[op_num
], op_data
);
3422 gas_assert (op_data
< insn
->ntok
);
3423 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3426 if (insn
->extra_arg
.X_op
!= O_register
)
3428 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3431 sym
= get_special_literal_symbol ();
3432 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3433 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3434 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3435 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3438 sym
= get_special_label_symbol ();
3439 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3441 case OP_OPERAND_HI16U
:
3442 case OP_OPERAND_LOW16U
:
3443 gas_assert (op_data
< insn
->ntok
);
3444 if (expr_is_const (&insn
->tok
[op_data
]))
3447 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3448 val
= xg_apply_userdef_op_fn (op
->typ
,
3451 targ
->tok
[op_num
].X_add_number
= val
;
3455 /* For const16 we can create relocations for these. */
3456 if (targ
->opcode
== XTENSA_UNDEFINED
3457 || (targ
->opcode
!= xtensa_const16_opcode
))
3459 gas_assert (op_data
< insn
->ntok
);
3460 /* Need to build a O_lo16 or O_hi16. */
3461 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3462 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3464 if (op
->typ
== OP_OPERAND_HI16U
)
3465 targ
->tok
[op_num
].X_op
= O_hi16
;
3466 else if (op
->typ
== OP_OPERAND_LOW16U
)
3467 targ
->tok
[op_num
].X_op
= O_lo16
;
3474 /* currently handles:
3477 OP_OPERAND_F32MINUS */
3478 if (xg_has_userdef_op_fn (op
->typ
))
3480 gas_assert (op_data
< insn
->ntok
);
3481 if (expr_is_const (&insn
->tok
[op_data
]))
3484 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3485 val
= xg_apply_userdef_op_fn (op
->typ
,
3488 targ
->tok
[op_num
].X_add_number
= val
;
3491 return FALSE
; /* We cannot use a relocation for this. */
3500 case INSTR_LITERAL_DEF
:
3502 targ
->opcode
= XTENSA_UNDEFINED
;
3503 targ
->insn_type
= ITYPE_LITERAL
;
3504 targ
->is_specific_opcode
= FALSE
;
3505 for (; op
!= NULL
; op
= op
->next
)
3507 int op_num
= op
->op_num
;
3508 int op_data
= op
->op_data
;
3509 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3511 if (targ
->ntok
<= op_num
)
3512 targ
->ntok
= op_num
+ 1;
3517 gas_assert (op_data
< insn
->ntok
);
3518 /* We can only pass resolvable literals through. */
3519 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3521 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3533 case INSTR_LABEL_DEF
:
3535 targ
->opcode
= XTENSA_UNDEFINED
;
3536 targ
->insn_type
= ITYPE_LABEL
;
3537 targ
->is_specific_opcode
= FALSE
;
3538 /* Literal with no ops is a label? */
3539 gas_assert (op
== NULL
);
3550 /* Return TRUE on success. */
3553 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3555 for (; bi
!= NULL
; bi
= bi
->next
)
3557 TInsn
*next_insn
= istack_push_space (istack
);
3559 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3566 /* Return TRUE on valid expansion. */
3569 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3571 int stack_size
= istack
->ninsn
;
3572 int steps_taken
= 0;
3573 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3576 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3577 gas_assert (insn
->opcode
< table
->num_opcodes
);
3579 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3581 TransitionRule
*rule
= l
->rule
;
3583 if (xg_instruction_matches_rule (insn
, rule
))
3585 if (lateral_steps
== steps_taken
)
3589 /* This is it. Expand the rule to the stack. */
3590 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3593 /* Check to see if it fits. */
3594 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3596 TInsn
*tinsn
= &istack
->insn
[i
];
3598 if (tinsn
->insn_type
== ITYPE_INSN
3599 && !tinsn_has_symbolic_operands (tinsn
)
3600 && !xg_immeds_fit (tinsn
))
3602 istack
->ninsn
= stack_size
;
3615 /* Relax the assembly instruction at least "min_steps".
3616 Return the number of steps taken.
3618 For relaxation to correctly terminate, every relaxation chain must
3619 terminate in one of two ways:
3621 1. If the chain from one instruction to the next consists entirely of
3622 single instructions, then the chain *must* handle all possible
3623 immediates without failing. It must not ever fail because an
3624 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3625 chain is one example. L32R loads 32 bits, and there cannot be an
3626 immediate larger than 32 bits, so it satisfies this condition.
3627 Single instruction relaxation chains are as defined by
3628 xg_is_single_relaxable_instruction.
3630 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3631 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3633 Strictly speaking, in most cases you can violate condition 1 and be OK
3634 -- in particular when the last two instructions have the same single
3635 size. But nevertheless, you should guarantee the above two conditions.
3637 We could fix this so that single-instruction expansions correctly
3638 terminate when they can't handle the range, but the error messages are
3639 worse, and it actually turns out that in every case but one (18-bit wide
3640 branches), you need a multi-instruction expansion to get the full range
3641 anyway. And because 18-bit branches are handled identically to 15-bit
3642 branches, there isn't any point in changing it. */
3645 xg_assembly_relax (IStack
*istack
,
3648 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3649 offsetT pc_offset
, /* offset in fragment */
3650 int min_steps
, /* minimum conversion steps */
3651 long stretch
) /* number of bytes stretched so far */
3653 int steps_taken
= 0;
3655 /* Some of its immeds don't fit. Try to build a relaxed version.
3656 This may go through a couple of stages of single instruction
3657 transformations before we get there. */
3659 TInsn single_target
;
3661 int lateral_steps
= 0;
3662 int istack_size
= istack
->ninsn
;
3664 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3665 && steps_taken
>= min_steps
)
3667 istack_push (istack
, insn
);
3670 current_insn
= *insn
;
3672 /* Walk through all of the single instruction expansions. */
3673 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3676 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3679 if (steps_taken
>= min_steps
)
3681 istack_push (istack
, &single_target
);
3685 current_insn
= single_target
;
3688 /* Now check for a multi-instruction expansion. */
3689 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3691 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3694 if (steps_taken
>= min_steps
)
3696 istack_push (istack
, ¤t_insn
);
3701 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3703 if (steps_taken
>= min_steps
)
3707 istack
->ninsn
= istack_size
;
3710 /* It's not going to work -- use the original. */
3711 istack_push (istack
, insn
);
3717 xg_finish_frag (char *last_insn
,
3718 enum xtensa_relax_statesE frag_state
,
3719 enum xtensa_relax_statesE slot0_state
,
3721 bfd_boolean is_insn
)
3723 /* Finish off this fragment so that it has at LEAST the desired
3724 max_growth. If it doesn't fit in this fragment, close this one
3725 and start a new one. In either case, return a pointer to the
3726 beginning of the growth area. */
3730 frag_grow (max_growth
);
3731 old_frag
= frag_now
;
3733 frag_now
->fr_opcode
= last_insn
;
3735 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3737 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3738 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3740 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3741 xtensa_set_frag_assembly_state (frag_now
);
3743 /* Just to make sure that we did not split it up. */
3744 gas_assert (old_frag
->fr_next
== frag_now
);
3748 /* Return TRUE if the target frag is one of the next non-empty frags. */
3751 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3756 for (; fragP
; fragP
= fragP
->fr_next
)
3758 if (fragP
== target
)
3760 if (fragP
->fr_fix
!= 0)
3762 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3764 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3765 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3767 if (fragP
->fr_type
== rs_space
)
3775 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3777 xtensa_isa isa
= xtensa_default_isa
;
3779 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3784 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3785 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3788 for (i
= 0; i
< num_ops
; i
++)
3790 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3796 if (target_op
== -1)
3799 if (insn
->ntok
<= target_op
)
3802 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3805 sym
= insn
->tok
[target_op
].X_add_symbol
;
3809 if (insn
->tok
[target_op
].X_add_number
!= 0)
3812 target_frag
= symbol_get_frag (sym
);
3813 if (target_frag
== NULL
)
3816 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3817 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3825 xg_add_branch_and_loop_targets (TInsn
*insn
)
3827 xtensa_isa isa
= xtensa_default_isa
;
3828 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3830 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3833 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3834 && insn
->tok
[i
].X_op
== O_symbol
)
3835 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3839 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3840 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3844 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3846 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3847 && insn
->tok
[i
].X_op
== O_symbol
)
3849 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3850 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3851 if (S_IS_DEFINED (sym
))
3852 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3859 /* Return FALSE if no error. */
3862 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3867 switch (instr_spec
->typ
)
3870 new_insn
->insn_type
= ITYPE_INSN
;
3871 new_insn
->opcode
= instr_spec
->opcode
;
3873 case INSTR_LITERAL_DEF
:
3874 new_insn
->insn_type
= ITYPE_LITERAL
;
3875 new_insn
->opcode
= XTENSA_UNDEFINED
;
3877 case INSTR_LABEL_DEF
:
3880 new_insn
->is_specific_opcode
= FALSE
;
3881 new_insn
->debug_line
= old_insn
->debug_line
;
3882 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3884 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3887 const expressionS
*src_exp
;
3893 /* The expression must be the constant. */
3894 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3895 exp
= &new_insn
->tok
[b_op
->op_num
];
3896 set_expr_const (exp
, b_op
->op_data
);
3900 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3901 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3902 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3903 exp
= &new_insn
->tok
[b_op
->op_num
];
3904 copy_expr (exp
, src_exp
);
3909 as_bad (_("can't handle generation of literal/labels yet"));
3913 as_bad (_("can't handle undefined OP TYPE"));
3918 new_insn
->ntok
= num_ops
;
3923 /* Return TRUE if it was simplified. */
3926 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3928 TransitionRule
*rule
;
3929 BuildInstr
*insn_spec
;
3931 if (old_insn
->is_specific_opcode
|| !density_supported
)
3934 rule
= xg_instruction_match (old_insn
);
3938 insn_spec
= rule
->to_instr
;
3939 /* There should only be one. */
3940 gas_assert (insn_spec
!= NULL
);
3941 gas_assert (insn_spec
->next
== NULL
);
3942 if (insn_spec
->next
!= NULL
)
3945 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3951 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3952 l32i.n. (2) Check the number of operands. (3) Place the instruction
3953 tokens into the stack or relax it and place multiple
3954 instructions/literals onto the stack. Return FALSE if no error. */
3957 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3961 bfd_boolean do_expand
;
3963 tinsn_init (&new_insn
);
3965 /* Narrow it if we can. xg_simplify_insn now does all the
3966 appropriate checking (e.g., for the density option). */
3967 if (xg_simplify_insn (orig_insn
, &new_insn
))
3968 orig_insn
= &new_insn
;
3970 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3972 if (orig_insn
->ntok
< noperands
)
3974 as_bad (_("found %d operands for '%s': Expected %d"),
3976 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3980 if (orig_insn
->ntok
> noperands
)
3981 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3983 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3986 /* If there are not enough operands, we will assert above. If there
3987 are too many, just cut out the extras here. */
3988 orig_insn
->ntok
= noperands
;
3990 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3993 /* Special case for extui opcode which has constraints not handled
3994 by the ordinary operand encoding checks. The number of operands
3995 and related syntax issues have already been checked. */
3996 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3998 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3999 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4000 if (shiftimm
+ maskimm
> 32)
4002 as_bad (_("immediate operands sum to greater than 32"));
4007 /* If the instruction will definitely need to be relaxed, it is better
4008 to expand it now for better scheduling. Decide whether to expand
4010 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4012 /* Calls should be expanded to longcalls only in the backend relaxation
4013 so that the assembly scheduler will keep the L32R/CALLX instructions
4015 if (is_direct_call_opcode (orig_insn
->opcode
))
4018 if (tinsn_has_symbolic_operands (orig_insn
))
4020 /* The values of symbolic operands are not known yet, so only expand
4021 now if an operand is "complex" (e.g., difference of symbols) and
4022 will have to be stored as a literal regardless of the value. */
4023 if (!tinsn_has_complex_operands (orig_insn
))
4026 else if (xg_immeds_fit (orig_insn
))
4030 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4032 istack_push (istack
, orig_insn
);
4038 /* Return TRUE if the section flags are marked linkonce
4039 or the name is .gnu.linkonce.*. */
4041 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4044 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4046 flagword flags
, link_once_flags
;
4048 flags
= bfd_get_section_flags (abfd
, sec
);
4049 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4051 /* Flags might not be set yet. */
4052 if (!link_once_flags
4053 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4054 link_once_flags
= SEC_LINK_ONCE
;
4056 return (link_once_flags
!= 0);
4061 xtensa_add_literal_sym (symbolS
*sym
)
4065 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4067 l
->next
= literal_syms
;
4073 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4075 static int lit_num
= 0;
4076 static char name
[256];
4079 sprintf (name
, ".L_lit_sym%d", lit_num
);
4081 /* Create a local symbol. If it is in a linkonce section, we have to
4082 be careful to make sure that if it is used in a relocation that the
4083 symbol will be in the output file. */
4084 if (get_is_linkonce_section (stdoutput
, sec
))
4086 symbolP
= symbol_new (name
, sec
, 0, frag
);
4087 S_CLEAR_EXTERNAL (symbolP
);
4088 /* symbolP->local = 1; */
4091 symbolP
= symbol_new (name
, sec
, 0, frag
);
4093 xtensa_add_literal_sym (symbolP
);
4100 /* Currently all literals that are generated here are 32-bit L32R targets. */
4103 xg_assemble_literal (/* const */ TInsn
*insn
)
4106 symbolS
*lit_sym
= NULL
;
4107 bfd_reloc_code_real_type reloc
;
4108 bfd_boolean pcrel
= FALSE
;
4111 /* size = 4 for L32R. It could easily be larger when we move to
4112 larger constants. Add a parameter later. */
4113 offsetT litsize
= 4;
4114 offsetT litalign
= 2; /* 2^2 = 4 */
4115 expressionS saved_loc
;
4116 expressionS
* emit_val
;
4118 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4120 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4121 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4123 xtensa_switch_to_literal_fragment (&state
);
4125 emit_val
= &insn
->tok
[0];
4126 if (emit_val
->X_op
== O_big
)
4128 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4131 /* This happens when someone writes a "movi a2, big_number". */
4132 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4133 _("invalid immediate"));
4134 xtensa_restore_emit_state (&state
);
4139 /* Force a 4-byte align here. Note that this opens a new frag, so all
4140 literals done with this function have a frag to themselves. That's
4141 important for the way text section literals work. */
4142 frag_align (litalign
, 0, 0);
4143 record_alignment (now_seg
, litalign
);
4145 switch (emit_val
->X_op
)
4155 p
= frag_more (litsize
);
4156 xtensa_set_frag_assembly_state (frag_now
);
4157 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4158 if (emit_val
->X_add_symbol
)
4159 emit_val
->X_op
= O_symbol
;
4161 emit_val
->X_op
= O_constant
;
4162 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4163 litsize
, emit_val
, pcrel
, reloc
);
4167 emit_expr (emit_val
, litsize
);
4171 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4172 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4173 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4174 lit_sym
= frag_now
->fr_symbol
;
4177 xtensa_restore_emit_state (&state
);
4183 xg_assemble_literal_space (/* const */ int size
, int slot
)
4186 /* We might have to do something about this alignment. It only
4187 takes effect if something is placed here. */
4188 offsetT litalign
= 2; /* 2^2 = 4 */
4189 fragS
*lit_saved_frag
;
4191 gas_assert (size
% 4 == 0);
4193 xtensa_switch_to_literal_fragment (&state
);
4195 /* Force a 4-byte align here. */
4196 frag_align (litalign
, 0, 0);
4197 record_alignment (now_seg
, litalign
);
4201 lit_saved_frag
= frag_now
;
4202 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4203 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4204 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4207 xtensa_restore_emit_state (&state
);
4208 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4212 /* Put in a fixup record based on the opcode.
4213 Return TRUE on success. */
4216 xg_add_opcode_fix (TInsn
*tinsn
,
4224 xtensa_opcode opcode
= tinsn
->opcode
;
4225 bfd_reloc_code_real_type reloc
;
4226 reloc_howto_type
*howto
;
4230 reloc
= BFD_RELOC_NONE
;
4232 /* First try the special cases for "alternate" relocs. */
4233 if (opcode
== xtensa_l32r_opcode
)
4235 if (fragP
->tc_frag_data
.use_absolute_literals
)
4236 reloc
= encode_alt_reloc (slot
);
4238 else if (opcode
== xtensa_const16_opcode
)
4240 if (exp
->X_op
== O_lo16
)
4242 reloc
= encode_reloc (slot
);
4243 exp
->X_op
= O_symbol
;
4245 else if (exp
->X_op
== O_hi16
)
4247 reloc
= encode_alt_reloc (slot
);
4248 exp
->X_op
= O_symbol
;
4252 if (opnum
!= get_relaxable_immed (opcode
))
4254 as_bad (_("invalid relocation for operand %i of '%s'"),
4255 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4259 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4260 into the symbol table where the generic portions of the assembler
4261 won't know what to do with them. */
4262 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4264 as_bad (_("invalid expression for operand %i of '%s'"),
4265 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4269 /* Next try the generic relocs. */
4270 if (reloc
== BFD_RELOC_NONE
)
4271 reloc
= encode_reloc (slot
);
4272 if (reloc
== BFD_RELOC_NONE
)
4274 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4278 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4281 as_bad (_("undefined symbol for opcode \"%s\""),
4282 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4286 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4287 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4288 howto
->pc_relative
, reloc
);
4289 the_fix
->fx_no_overflow
= 1;
4290 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4291 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4292 the_fix
->tc_fix_data
.slot
= slot
;
4299 xg_emit_insn_to_buf (TInsn
*tinsn
,
4303 bfd_boolean build_fix
)
4305 static xtensa_insnbuf insnbuf
= NULL
;
4306 bfd_boolean has_symbolic_immed
= FALSE
;
4307 bfd_boolean ok
= TRUE
;
4310 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4312 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4313 if (has_symbolic_immed
&& build_fix
)
4316 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4317 int slot
= xg_get_single_slot (tinsn
->opcode
);
4318 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4319 expressionS
*exp
= &tinsn
->tok
[opnum
];
4321 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4324 fragP
->tc_frag_data
.is_insn
= TRUE
;
4325 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4326 (unsigned char *) buf
, 0);
4332 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4334 symbolS
*sym
= get_special_literal_symbol ();
4338 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4339 for (i
= 0; i
< insn
->ntok
; i
++)
4340 if (insn
->tok
[i
].X_add_symbol
== sym
)
4341 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4347 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4349 symbolS
*sym
= get_special_label_symbol ();
4351 for (i
= 0; i
< insn
->ntok
; i
++)
4352 if (insn
->tok
[i
].X_add_symbol
== sym
)
4353 insn
->tok
[i
].X_add_symbol
= label_sym
;
4358 /* Return TRUE if the instruction can write to the specified
4359 integer register. */
4362 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4366 xtensa_isa isa
= xtensa_default_isa
;
4368 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4370 for (i
= 0; i
< num_ops
; i
++)
4373 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4374 if ((inout
== 'o' || inout
== 'm')
4375 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4377 xtensa_regfile opnd_rf
=
4378 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4379 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4381 if ((insn
->tok
[i
].X_op
== O_register
)
4382 && (insn
->tok
[i
].X_add_number
== regnum
))
4392 is_bad_loopend_opcode (const TInsn
*tinsn
)
4394 xtensa_opcode opcode
= tinsn
->opcode
;
4396 if (opcode
== XTENSA_UNDEFINED
)
4399 if (opcode
== xtensa_call0_opcode
4400 || opcode
== xtensa_callx0_opcode
4401 || opcode
== xtensa_call4_opcode
4402 || opcode
== xtensa_callx4_opcode
4403 || opcode
== xtensa_call8_opcode
4404 || opcode
== xtensa_callx8_opcode
4405 || opcode
== xtensa_call12_opcode
4406 || opcode
== xtensa_callx12_opcode
4407 || opcode
== xtensa_isync_opcode
4408 || opcode
== xtensa_ret_opcode
4409 || opcode
== xtensa_ret_n_opcode
4410 || opcode
== xtensa_retw_opcode
4411 || opcode
== xtensa_retw_n_opcode
4412 || opcode
== xtensa_waiti_opcode
4413 || opcode
== xtensa_rsr_lcount_opcode
)
4420 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4421 This allows the debugger to add unaligned labels.
4422 Also, the assembler generates stabs labels that need
4423 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4426 is_unaligned_label (symbolS
*sym
)
4428 const char *name
= S_GET_NAME (sym
);
4429 static size_t fake_size
= 0;
4433 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4436 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4438 fake_size
= strlen (FAKE_LABEL_NAME
);
4441 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4442 && (name
[fake_size
] == 'F'
4443 || name
[fake_size
] == 'L'
4444 || (name
[fake_size
] == 'e'
4445 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4453 next_non_empty_frag (const fragS
*fragP
)
4455 fragS
*next_fragP
= fragP
->fr_next
;
4457 /* Sometimes an empty will end up here due storage allocation issues.
4458 So we have to skip until we find something legit. */
4459 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4460 next_fragP
= next_fragP
->fr_next
;
4462 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4470 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4472 xtensa_opcode out_opcode
;
4473 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4475 if (next_fragP
== NULL
)
4478 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4479 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4481 *opcode
= out_opcode
;
4489 frag_format_size (const fragS
*fragP
)
4491 static xtensa_insnbuf insnbuf
= NULL
;
4492 xtensa_isa isa
= xtensa_default_isa
;
4497 insnbuf
= xtensa_insnbuf_alloc (isa
);
4500 return XTENSA_UNDEFINED
;
4502 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4503 (unsigned char *) fragP
->fr_literal
, 0);
4505 fmt
= xtensa_format_decode (isa
, insnbuf
);
4506 if (fmt
== XTENSA_UNDEFINED
)
4507 return XTENSA_UNDEFINED
;
4508 fmt_size
= xtensa_format_length (isa
, fmt
);
4510 /* If the next format won't be changing due to relaxation, just
4511 return the length of the first format. */
4512 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4515 /* If during relaxation we have to pull an instruction out of a
4516 multi-slot instruction, we will return the more conservative
4517 number. This works because alignment on bigger instructions
4518 is more restrictive than alignment on smaller instructions.
4519 This is more conservative than we would like, but it happens
4522 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4525 /* If we aren't doing one of our own relaxations or it isn't
4526 slot-based, then the insn size won't change. */
4527 if (fragP
->fr_type
!= rs_machine_dependent
)
4529 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4532 /* If an instruction is about to grow, return the longer size. */
4533 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4534 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4535 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4537 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4538 instruction in the relaxed version is of length 3. (The case
4539 where we have to pull the instruction out of a FLIX bundle
4540 is handled conservatively above.) However, frags with opcodes
4541 that are expanding to wide branches end up having formats that
4542 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4543 we can't tell directly what format the relaxer picked. This
4544 is a wart in the design of the relaxer that should someday be
4545 fixed, but would require major changes, or at least should
4546 be accompanied by major changes to make use of that data.
4548 In any event, we can tell that we are expanding from a single-slot
4549 format to a wider one with the logic below. */
4552 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4554 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4556 if (relaxed_size
== xtensa_format_length (isa
, i
))
4557 return relaxed_size
;
4563 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4564 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4571 next_frag_format_size (const fragS
*fragP
)
4573 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4574 return frag_format_size (next_fragP
);
4578 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4579 required two-byte instructions to be treated as three-byte instructions
4580 for loop instruction alignment. This restriction was removed beginning
4581 with Xtensa LX. Now the only requirement on loop instruction alignment
4582 is that the first instruction of the loop must appear at an address that
4583 does not cross a fetch boundary. */
4586 get_loop_align_size (int insn_size
)
4588 if (insn_size
== XTENSA_UNDEFINED
)
4589 return xtensa_fetch_width
;
4591 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4598 /* If the next legit fragment is an end-of-loop marker,
4599 switch its state so it will instantiate a NOP. */
4602 update_next_frag_state (fragS
*fragP
)
4604 fragS
*next_fragP
= fragP
->fr_next
;
4605 fragS
*new_target
= NULL
;
4609 /* We are guaranteed there will be one of these... */
4610 while (!(next_fragP
->fr_type
== rs_machine_dependent
4611 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4612 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4613 next_fragP
= next_fragP
->fr_next
;
4615 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4616 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4617 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4619 /* ...and one of these. */
4620 new_target
= next_fragP
->fr_next
;
4621 while (!(new_target
->fr_type
== rs_machine_dependent
4622 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4623 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4624 new_target
= new_target
->fr_next
;
4626 gas_assert (new_target
->fr_type
== rs_machine_dependent
4627 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4628 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4631 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4633 if (next_fragP
->fr_type
== rs_machine_dependent
4634 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4636 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4640 next_fragP
= next_fragP
->fr_next
;
4646 next_frag_is_branch_target (const fragS
*fragP
)
4648 /* Sometimes an empty will end up here due to storage allocation issues,
4649 so we have to skip until we find something legit. */
4650 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4652 if (fragP
->tc_frag_data
.is_branch_target
)
4654 if (fragP
->fr_fix
!= 0)
4662 next_frag_is_loop_target (const fragS
*fragP
)
4664 /* Sometimes an empty will end up here due storage allocation issues.
4665 So we have to skip until we find something legit. */
4666 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4668 if (fragP
->tc_frag_data
.is_loop_target
)
4670 if (fragP
->fr_fix
!= 0)
4677 /* As specified in the relaxation table, when a loop instruction is
4678 relaxed, there are 24 bytes between the loop instruction itself and
4679 the first instruction in the loop. */
4681 #define RELAXED_LOOP_INSN_BYTES 24
4684 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4686 const fragS
*next_fragp
= fragp
->fr_next
;
4687 xtensa_opcode next_opcode
;
4689 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4692 /* Sometimes an empty will end up here due to storage allocation issues,
4693 so we have to skip until we find something legit. */
4694 while (next_fragp
->fr_fix
== 0)
4695 next_fragp
= next_fragp
->fr_next
;
4697 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4700 /* There is some implicit knowledge encoded in here.
4701 The LOOP instructions that are NOT RELAX_IMMED have
4702 been relaxed. Note that we can assume that the LOOP
4703 instruction is in slot 0 because loops aren't bundleable. */
4704 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4705 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4711 /* Mark a location where we can later insert literal frags. Update
4712 the section's literal_pool_loc, so subsequent literals can be
4713 placed nearest to their use. */
4716 xtensa_mark_literal_pool_location (void)
4718 /* Any labels pointing to the current location need
4719 to be adjusted to after the literal pool. */
4721 fragS
*pool_location
;
4723 if (use_literal_section
)
4726 /* We stash info in these frags so we can later move the literal's
4727 fixes into this frchain's fix list. */
4728 pool_location
= frag_now
;
4729 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4730 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4731 frag_variant (rs_machine_dependent
, 0, 0,
4732 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4733 xtensa_set_frag_assembly_state (frag_now
);
4734 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4735 frag_variant (rs_machine_dependent
, 0, 0,
4736 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4737 xtensa_set_frag_assembly_state (frag_now
);
4739 /* Now put a frag into the literal pool that points to this location. */
4740 set_literal_pool_location (now_seg
, pool_location
);
4741 xtensa_switch_to_non_abs_literal_fragment (&s
);
4742 frag_align (2, 0, 0);
4743 record_alignment (now_seg
, 2);
4745 /* Close whatever frag is there. */
4746 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4747 xtensa_set_frag_assembly_state (frag_now
);
4748 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4749 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4750 xtensa_restore_emit_state (&s
);
4751 xtensa_set_frag_assembly_state (frag_now
);
4755 /* Build a nop of the correct size into tinsn. */
4758 build_nop (TInsn
*tinsn
, int size
)
4764 tinsn
->opcode
= xtensa_nop_n_opcode
;
4766 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4767 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4771 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4773 tinsn
->opcode
= xtensa_or_opcode
;
4774 set_expr_const (&tinsn
->tok
[0], 1);
4775 set_expr_const (&tinsn
->tok
[1], 1);
4776 set_expr_const (&tinsn
->tok
[2], 1);
4780 tinsn
->opcode
= xtensa_nop_opcode
;
4782 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4787 /* Assemble a NOP of the requested size in the buffer. User must have
4788 allocated "buf" with at least "size" bytes. */
4791 assemble_nop (int size
, char *buf
)
4793 static xtensa_insnbuf insnbuf
= NULL
;
4796 build_nop (&tinsn
, size
);
4799 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4801 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4802 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4803 (unsigned char *) buf
, 0);
4807 /* Return the number of bytes for the offset of the expanded loop
4808 instruction. This should be incorporated into the relaxation
4809 specification but is hard-coded here. This is used to auto-align
4810 the loop instruction. It is invalid to call this function if the
4811 configuration does not have loops or if the opcode is not a loop
4815 get_expanded_loop_offset (xtensa_opcode opcode
)
4817 /* This is the OFFSET of the loop instruction in the expanded loop.
4818 This MUST correspond directly to the specification of the loop
4819 expansion. It will be validated on fragment conversion. */
4820 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4821 if (opcode
== xtensa_loop_opcode
)
4823 if (opcode
== xtensa_loopnez_opcode
)
4825 if (opcode
== xtensa_loopgtz_opcode
)
4827 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4833 get_literal_pool_location (segT seg
)
4835 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4840 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4842 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4846 /* Set frag assembly state should be called when a new frag is
4847 opened and after a frag has been closed. */
4850 xtensa_set_frag_assembly_state (fragS
*fragP
)
4852 if (!density_supported
)
4853 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4855 /* This function is called from subsegs_finish, which is called
4856 after xtensa_end, so we can't use "use_transform" or
4857 "use_schedule" here. */
4858 if (!directive_state
[directive_transform
])
4859 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4860 if (directive_state
[directive_longcalls
])
4861 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4862 fragP
->tc_frag_data
.use_absolute_literals
=
4863 directive_state
[directive_absolute_literals
];
4864 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4869 relaxable_section (asection
*sec
)
4871 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4872 && strcmp (sec
->name
, ".eh_frame") != 0);
4877 xtensa_mark_frags_for_org (void)
4881 /* Walk over each fragment of all of the current segments. If we find
4882 a .org frag in any of the segments, mark all frags prior to it as
4883 "no transform", which will prevent linker optimizations from messing
4884 up the .org distance. This should be done after
4885 xtensa_find_unmarked_state_frags, because we don't want to worry here
4886 about that function trashing the data we save here. */
4888 for (seclist
= &stdoutput
->sections
;
4889 seclist
&& *seclist
;
4890 seclist
= &(*seclist
)->next
)
4892 segT sec
= *seclist
;
4893 segment_info_type
*seginfo
;
4896 flags
= bfd_get_section_flags (stdoutput
, sec
);
4897 if (flags
& SEC_DEBUGGING
)
4899 if (!(flags
& SEC_ALLOC
))
4902 seginfo
= seg_info (sec
);
4903 if (seginfo
&& seginfo
->frchainP
)
4905 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4906 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4907 fragP
= fragP
->fr_next
)
4909 /* cvt_frag_to_fill has changed the fr_type of org frags to
4910 rs_fill, so use the value as cached in rs_subtype here. */
4911 if (fragP
->fr_subtype
== RELAX_ORG
)
4913 while (last_fragP
!= fragP
->fr_next
)
4915 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4916 last_fragP
= last_fragP
->fr_next
;
4926 xtensa_find_unmarked_state_frags (void)
4930 /* Walk over each fragment of all of the current segments. For each
4931 unmarked fragment, mark it with the same info as the previous
4933 for (seclist
= &stdoutput
->sections
;
4934 seclist
&& *seclist
;
4935 seclist
= &(*seclist
)->next
)
4937 segT sec
= *seclist
;
4938 segment_info_type
*seginfo
;
4941 flags
= bfd_get_section_flags (stdoutput
, sec
);
4942 if (flags
& SEC_DEBUGGING
)
4944 if (!(flags
& SEC_ALLOC
))
4947 seginfo
= seg_info (sec
);
4948 if (seginfo
&& seginfo
->frchainP
)
4950 fragS
*last_fragP
= 0;
4951 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4952 fragP
= fragP
->fr_next
)
4954 if (fragP
->fr_fix
!= 0
4955 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4957 if (last_fragP
== 0)
4959 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4960 _("assembly state not set for first frag in section %s"),
4965 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4966 fragP
->tc_frag_data
.is_no_density
=
4967 last_fragP
->tc_frag_data
.is_no_density
;
4968 fragP
->tc_frag_data
.is_no_transform
=
4969 last_fragP
->tc_frag_data
.is_no_transform
;
4970 fragP
->tc_frag_data
.use_longcalls
=
4971 last_fragP
->tc_frag_data
.use_longcalls
;
4972 fragP
->tc_frag_data
.use_absolute_literals
=
4973 last_fragP
->tc_frag_data
.use_absolute_literals
;
4976 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4985 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4987 void *unused ATTRIBUTE_UNUSED
)
4989 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4990 segment_info_type
*seginfo
= seg_info (sec
);
4991 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4993 if (flags
& SEC_CODE
)
4995 xtensa_isa isa
= xtensa_default_isa
;
4996 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4997 while (frag
!= NULL
)
4999 if (frag
->tc_frag_data
.is_branch_target
)
5002 addressT branch_align
, frag_addr
;
5005 xtensa_insnbuf_from_chars
5006 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5007 fmt
= xtensa_format_decode (isa
, insnbuf
);
5008 op_size
= xtensa_format_length (isa
, fmt
);
5009 branch_align
= 1 << branch_align_power (sec
);
5010 frag_addr
= frag
->fr_address
% branch_align
;
5011 if (frag_addr
+ op_size
> branch_align
)
5012 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5013 _("unaligned branch target: %d bytes at 0x%lx"),
5014 op_size
, (long) frag
->fr_address
);
5016 frag
= frag
->fr_next
;
5018 xtensa_insnbuf_free (isa
, insnbuf
);
5024 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5026 void *unused ATTRIBUTE_UNUSED
)
5028 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5029 segment_info_type
*seginfo
= seg_info (sec
);
5030 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5031 xtensa_isa isa
= xtensa_default_isa
;
5033 if (flags
& SEC_CODE
)
5035 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5036 while (frag
!= NULL
)
5038 if (frag
->tc_frag_data
.is_first_loop_insn
)
5044 if (frag
->fr_fix
== 0)
5045 frag
= next_non_empty_frag (frag
);
5049 xtensa_insnbuf_from_chars
5050 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5051 fmt
= xtensa_format_decode (isa
, insnbuf
);
5052 op_size
= xtensa_format_length (isa
, fmt
);
5053 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5055 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5056 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5057 _("unaligned loop: %d bytes at 0x%lx"),
5058 op_size
, (long) frag
->fr_address
);
5061 frag
= frag
->fr_next
;
5063 xtensa_insnbuf_free (isa
, insnbuf
);
5069 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5071 xtensa_isa isa
= xtensa_default_isa
;
5072 static xtensa_insnbuf insnbuf
= NULL
;
5073 static xtensa_insnbuf slotbuf
= NULL
;
5076 bfd_boolean alt_reloc
;
5077 xtensa_opcode opcode
;
5078 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5080 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5082 as_fatal (_("unexpected fix"));
5086 insnbuf
= xtensa_insnbuf_alloc (isa
);
5087 slotbuf
= xtensa_insnbuf_alloc (isa
);
5090 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5091 fmt
= xtensa_format_decode (isa
, insnbuf
);
5092 if (fmt
== XTENSA_UNDEFINED
)
5093 as_fatal (_("undecodable fix"));
5094 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5095 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5096 if (opcode
== XTENSA_UNDEFINED
)
5097 as_fatal (_("undecodable fix"));
5099 /* CONST16 immediates are not PC-relative, despite the fact that we
5100 reuse the normal PC-relative operand relocations for the low part
5101 of a CONST16 operand. */
5102 if (opcode
== xtensa_const16_opcode
)
5105 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5106 get_relaxable_immed (opcode
), val
,
5107 fixP
->fx_file
, fixP
->fx_line
);
5109 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5110 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5116 /* External Functions and Other GAS Hooks. */
5119 xtensa_target_format (void)
5121 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5126 xtensa_file_arch_init (bfd
*abfd
)
5128 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5133 md_number_to_chars (char *buf
, valueT val
, int n
)
5135 if (target_big_endian
)
5136 number_to_chars_bigendian (buf
, val
, n
);
5138 number_to_chars_littleendian (buf
, val
, n
);
5142 /* This function is called once, at assembler startup time. It should
5143 set up all the tables, etc. that the MD part of the assembler will
5149 segT current_section
= now_seg
;
5150 int current_subsec
= now_subseg
;
5154 xtensa_default_isa
= xtensa_isa_init (0, 0);
5155 isa
= xtensa_default_isa
;
5159 /* Set up the literal sections. */
5160 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5162 subseg_set (current_section
, current_subsec
);
5164 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5165 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5166 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5167 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5168 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5169 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5170 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5171 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5172 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5173 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5174 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5175 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5176 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5177 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5178 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5179 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5180 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5181 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5182 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5183 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5184 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5185 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5186 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5187 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5188 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5189 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5190 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5191 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5192 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5193 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5194 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5196 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5198 int format_slots
= xtensa_format_num_slots (isa
, i
);
5199 if (format_slots
> config_max_slots
)
5200 config_max_slots
= format_slots
;
5203 xg_init_vinsn (&cur_vinsn
);
5205 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5207 init_op_placement_info_table ();
5209 /* Set up the assembly state. */
5210 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5211 xtensa_set_frag_assembly_state (frag_now
);
5215 /* TC_INIT_FIX_DATA hook */
5218 xtensa_init_fix_data (fixS
*x
)
5220 x
->tc_fix_data
.slot
= 0;
5221 x
->tc_fix_data
.X_add_symbol
= NULL
;
5222 x
->tc_fix_data
.X_add_number
= 0;
5226 /* tc_frob_label hook */
5229 xtensa_frob_label (symbolS
*sym
)
5233 if (cur_vinsn
.inside_bundle
)
5235 as_bad (_("labels are not valid inside bundles"));
5239 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5241 /* Since the label was already attached to a frag associated with the
5242 previous basic block, it now needs to be reset to the current frag. */
5243 symbol_set_frag (sym
, frag_now
);
5244 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5246 if (generating_literals
)
5247 xtensa_add_literal_sym (sym
);
5249 xtensa_add_insn_label (sym
);
5251 if (symbol_get_tc (sym
)->is_loop_target
)
5253 if ((get_last_insn_flags (now_seg
, now_subseg
)
5254 & FLAG_IS_BAD_LOOPEND
) != 0)
5255 as_bad (_("invalid last instruction for a zero-overhead loop"));
5257 xtensa_set_frag_assembly_state (frag_now
);
5258 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5259 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5261 xtensa_set_frag_assembly_state (frag_now
);
5262 xtensa_move_labels (frag_now
, 0);
5265 /* No target aligning in the absolute section. */
5266 if (now_seg
!= absolute_section
5267 && !is_unaligned_label (sym
)
5268 && !generating_literals
)
5270 xtensa_set_frag_assembly_state (frag_now
);
5272 if (do_align_targets ())
5273 frag_var (rs_machine_dependent
, 0, (int) freq
,
5274 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5275 frag_now
->fr_offset
, NULL
);
5277 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5278 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5279 xtensa_set_frag_assembly_state (frag_now
);
5280 xtensa_move_labels (frag_now
, 0);
5283 /* We need to mark the following properties even if we aren't aligning. */
5285 /* If the label is already known to be a branch target, i.e., a
5286 forward branch, mark the frag accordingly. Backward branches
5287 are handled by xg_add_branch_and_loop_targets. */
5288 if (symbol_get_tc (sym
)->is_branch_target
)
5289 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5291 /* Loops only go forward, so they can be identified here. */
5292 if (symbol_get_tc (sym
)->is_loop_target
)
5293 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5295 dwarf2_emit_label (sym
);
5299 /* tc_unrecognized_line hook */
5302 xtensa_unrecognized_line (int ch
)
5307 if (cur_vinsn
.inside_bundle
== 0)
5309 /* PR8110: Cannot emit line number info inside a FLIX bundle
5310 when using --gstabs. Temporarily disable debug info. */
5311 generate_lineno_debug ();
5312 if (debug_type
== DEBUG_STABS
)
5314 xt_saved_debug_type
= debug_type
;
5315 debug_type
= DEBUG_NONE
;
5318 cur_vinsn
.inside_bundle
= 1;
5322 as_bad (_("extra opening brace"));
5328 if (cur_vinsn
.inside_bundle
)
5329 finish_vinsn (&cur_vinsn
);
5332 as_bad (_("extra closing brace"));
5337 as_bad (_("syntax error"));
5344 /* md_flush_pending_output hook */
5347 xtensa_flush_pending_output (void)
5349 /* This line fixes a bug where automatically generated gstabs info
5350 separates a function label from its entry instruction, ending up
5351 with the literal position between the function label and the entry
5352 instruction and crashing code. It only happens with --gstabs and
5353 --text-section-literals, and when several other obscure relaxation
5354 conditions are met. */
5355 if (outputting_stabs_line_debug
)
5358 if (cur_vinsn
.inside_bundle
)
5359 as_bad (_("missing closing brace"));
5361 /* If there is a non-zero instruction fragment, close it. */
5362 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5364 frag_wane (frag_now
);
5366 xtensa_set_frag_assembly_state (frag_now
);
5368 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5370 xtensa_clear_insn_labels ();
5374 /* We had an error while parsing an instruction. The string might look
5375 like this: "insn arg1, arg2 }". If so, we need to see the closing
5376 brace and reset some fields. Otherwise, the vinsn never gets closed
5377 and the num_slots field will grow past the end of the array of slots,
5378 and bad things happen. */
5381 error_reset_cur_vinsn (void)
5383 if (cur_vinsn
.inside_bundle
)
5385 if (*input_line_pointer
== '}'
5386 || *(input_line_pointer
- 1) == '}'
5387 || *(input_line_pointer
- 2) == '}')
5388 xg_clear_vinsn (&cur_vinsn
);
5394 md_assemble (char *str
)
5396 xtensa_isa isa
= xtensa_default_isa
;
5399 bfd_boolean has_underbar
= FALSE
;
5400 char *arg_strings
[MAX_INSN_ARGS
];
5402 TInsn orig_insn
; /* Original instruction from the input. */
5404 tinsn_init (&orig_insn
);
5406 /* Split off the opcode. */
5407 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5408 opname
= xmalloc (opnamelen
+ 1);
5409 memcpy (opname
, str
, opnamelen
);
5410 opname
[opnamelen
] = '\0';
5412 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5415 as_bad (_("syntax error"));
5419 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5422 /* Check for an underbar prefix. */
5425 has_underbar
= TRUE
;
5429 orig_insn
.insn_type
= ITYPE_INSN
;
5431 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5432 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5434 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5435 extra argument and set the opcode to "CALLXn". */
5436 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5437 && strncasecmp (opname
, "callx", 5) == 0)
5439 unsigned long window_size
;
5442 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5443 if (suffix
!= opname
+ 5
5444 && (window_size
== 0
5447 || window_size
== 12)
5448 && strcasecmp (suffix
, ".tls") == 0)
5450 switch (window_size
)
5452 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5453 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5454 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5455 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5459 as_bad (_("wrong number of operands for '%s'"), opname
);
5462 bfd_reloc_code_real_type reloc
;
5463 char *old_input_line_pointer
;
5464 expressionS
*tok
= &orig_insn
.extra_arg
;
5466 old_input_line_pointer
= input_line_pointer
;
5467 input_line_pointer
= arg_strings
[num_args
- 1];
5470 if (tok
->X_op
== O_symbol
5471 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5472 == BFD_RELOC_XTENSA_TLS_CALL
))
5473 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5475 as_bad (_("bad relocation expression for '%s'"), opname
);
5477 input_line_pointer
= old_input_line_pointer
;
5483 /* Special case: Check for "j.l" psuedo op. */
5484 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5485 && strncasecmp (opname
, "j.l", 3) == 0)
5488 as_bad (_("wrong number of operands for '%s'"), opname
);
5491 char *old_input_line_pointer
;
5492 expressionS
*tok
= &orig_insn
.extra_arg
;
5494 old_input_line_pointer
= input_line_pointer
;
5495 input_line_pointer
= arg_strings
[num_args
- 1];
5497 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5498 input_line_pointer
= old_input_line_pointer
;
5501 orig_insn
.opcode
= xtensa_j_opcode
;
5505 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5507 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5508 if (fmt
== XTENSA_UNDEFINED
)
5510 as_bad (_("unknown opcode or format name '%s'"), opname
);
5511 error_reset_cur_vinsn ();
5514 if (!cur_vinsn
.inside_bundle
)
5516 as_bad (_("format names only valid inside bundles"));
5517 error_reset_cur_vinsn ();
5520 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5521 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5523 cur_vinsn
.format
= fmt
;
5524 free (has_underbar
? opname
- 1 : opname
);
5525 error_reset_cur_vinsn ();
5529 /* Parse the arguments. */
5530 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5532 as_bad (_("syntax error"));
5533 error_reset_cur_vinsn ();
5537 /* Free the opcode and argument strings, now that they've been parsed. */
5538 free (has_underbar
? opname
- 1 : opname
);
5540 while (num_args
-- > 0)
5541 free (arg_strings
[num_args
]);
5543 /* Get expressions for invisible operands. */
5544 if (get_invisible_operands (&orig_insn
))
5546 error_reset_cur_vinsn ();
5550 /* Check for the right number and type of arguments. */
5551 if (tinsn_check_arguments (&orig_insn
))
5553 error_reset_cur_vinsn ();
5557 /* Record the line number for each TInsn, because a FLIX bundle may be
5558 spread across multiple input lines and individual instructions may be
5559 moved around in some cases. */
5560 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5561 dwarf2_where (&orig_insn
.debug_line
);
5562 dwarf2_consume_line_info ();
5564 xg_add_branch_and_loop_targets (&orig_insn
);
5566 /* Check that immediate value for ENTRY is >= 16. */
5567 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5569 expressionS
*exp
= &orig_insn
.tok
[2];
5570 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5571 as_warn (_("entry instruction with stack decrement < 16"));
5575 assemble_tokens (opcode, tok, ntok);
5576 expand the tokens from the orig_insn into the
5577 stack of instructions that will not expand
5578 unless required at relaxation time. */
5580 if (!cur_vinsn
.inside_bundle
)
5581 emit_single_op (&orig_insn
);
5582 else /* We are inside a bundle. */
5584 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5585 cur_vinsn
.num_slots
++;
5586 if (*input_line_pointer
== '}'
5587 || *(input_line_pointer
- 1) == '}'
5588 || *(input_line_pointer
- 2) == '}')
5589 finish_vinsn (&cur_vinsn
);
5592 /* We've just emitted a new instruction so clear the list of labels. */
5593 xtensa_clear_insn_labels ();
5595 xtensa_check_frag_count ();
5599 /* HANDLE_ALIGN hook */
5601 /* For a .align directive, we mark the previous block with the alignment
5602 information. This will be placed in the object file in the
5603 property section corresponding to this section. */
5606 xtensa_handle_align (fragS
*fragP
)
5609 && ! fragP
->tc_frag_data
.is_literal
5610 && (fragP
->fr_type
== rs_align
5611 || fragP
->fr_type
== rs_align_code
)
5612 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5613 && fragP
->fr_offset
> 0
5614 && now_seg
!= bss_section
)
5616 fragP
->tc_frag_data
.is_align
= TRUE
;
5617 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5620 if (fragP
->fr_type
== rs_align_test
)
5623 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5625 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5626 _("unaligned entry instruction"));
5629 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5630 fragP
->fr_subtype
= RELAX_ORG
;
5634 /* TC_FRAG_INIT hook */
5637 xtensa_frag_init (fragS
*frag
)
5639 xtensa_set_frag_assembly_state (frag
);
5644 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5650 /* Round up a section size to the appropriate boundary. */
5653 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5655 return size
; /* Byte alignment is fine. */
5660 md_pcrel_from (fixS
*fixP
)
5663 static xtensa_insnbuf insnbuf
= NULL
;
5664 static xtensa_insnbuf slotbuf
= NULL
;
5667 xtensa_opcode opcode
;
5670 xtensa_isa isa
= xtensa_default_isa
;
5671 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5672 bfd_boolean alt_reloc
;
5674 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5677 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5682 insnbuf
= xtensa_insnbuf_alloc (isa
);
5683 slotbuf
= xtensa_insnbuf_alloc (isa
);
5686 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5687 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5688 fmt
= xtensa_format_decode (isa
, insnbuf
);
5690 if (fmt
== XTENSA_UNDEFINED
)
5691 as_fatal (_("bad instruction format"));
5693 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5694 as_fatal (_("invalid relocation"));
5696 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5697 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5699 /* Check for "alternate" relocations (operand not specified). None
5700 of the current uses for these are really PC-relative. */
5701 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5703 if (opcode
!= xtensa_l32r_opcode
5704 && opcode
!= xtensa_const16_opcode
)
5705 as_fatal (_("invalid relocation for '%s' instruction"),
5706 xtensa_opcode_name (isa
, opcode
));
5710 opnum
= get_relaxable_immed (opcode
);
5712 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5713 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5715 as_bad_where (fixP
->fx_file
,
5717 _("invalid relocation for operand %d of '%s'"),
5718 opnum
, xtensa_opcode_name (isa
, opcode
));
5721 return 0 - opnd_value
;
5725 /* TC_FORCE_RELOCATION hook */
5728 xtensa_force_relocation (fixS
*fix
)
5730 switch (fix
->fx_r_type
)
5732 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5733 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5734 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5735 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5736 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5737 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5738 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5739 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5740 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5741 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5742 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5743 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5744 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5745 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5746 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5747 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5753 if (linkrelax
&& fix
->fx_addsy
5754 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5757 return generic_force_reloc (fix
);
5761 /* TC_VALIDATE_FIX_SUB hook */
5764 xtensa_validate_fix_sub (fixS
*fix
)
5766 segT add_symbol_segment
, sub_symbol_segment
;
5768 /* The difference of two symbols should be resolved by the assembler when
5769 linkrelax is not set. If the linker may relax the section containing
5770 the symbols, then an Xtensa DIFF relocation must be generated so that
5771 the linker knows to adjust the difference value. */
5772 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5775 /* Make sure both symbols are in the same segment, and that segment is
5776 "normal" and relaxable. If the segment is not "normal", then the
5777 fix is not valid. If the segment is not "relaxable", then the fix
5778 should have been handled earlier. */
5779 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5780 if (! SEG_NORMAL (add_symbol_segment
) ||
5781 ! relaxable_section (add_symbol_segment
))
5783 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5784 return (sub_symbol_segment
== add_symbol_segment
);
5788 /* NO_PSEUDO_DOT hook */
5790 /* This function has nothing to do with pseudo dots, but this is the
5791 nearest macro to where the check needs to take place. FIXME: This
5795 xtensa_check_inside_bundle (void)
5797 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5798 as_bad (_("directives are not valid inside bundles"));
5800 /* This function must always return FALSE because it is called via a
5801 macro that has nothing to do with bundling. */
5806 /* md_elf_section_change_hook */
5809 xtensa_elf_section_change_hook (void)
5811 /* Set up the assembly state. */
5812 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5813 xtensa_set_frag_assembly_state (frag_now
);
5817 /* tc_fix_adjustable hook */
5820 xtensa_fix_adjustable (fixS
*fixP
)
5822 /* We need the symbol name for the VTABLE entries. */
5823 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5824 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5831 /* tc_symbol_new_hook */
5833 symbolS
*expr_symbols
= NULL
;
5836 xtensa_symbol_new_hook (symbolS
*sym
)
5838 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5840 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5847 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5849 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5852 /* Subtracted symbols are only allowed for a few relocation types, and
5853 unless linkrelax is enabled, they should not make it to this point. */
5854 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5855 || fixP
->fx_r_type
== BFD_RELOC_16
5856 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5859 switch (fixP
->fx_r_type
)
5861 case BFD_RELOC_32_PCREL
:
5867 switch (fixP
->fx_r_type
)
5870 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5873 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5876 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5882 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5883 - S_GET_VALUE (fixP
->fx_subsy
));
5885 /* The difference value gets written out, and the DIFF reloc
5886 identifies the address of the subtracted symbol (i.e., the one
5887 with the lowest address). */
5889 fixP
->fx_offset
-= val
;
5890 fixP
->fx_subsy
= NULL
;
5892 else if (! fixP
->fx_addsy
)
5899 case BFD_RELOC_XTENSA_PLT
:
5900 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5901 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5904 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5905 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5906 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5907 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5908 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5909 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5910 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5913 case BFD_RELOC_XTENSA_SLOT0_OP
:
5914 case BFD_RELOC_XTENSA_SLOT1_OP
:
5915 case BFD_RELOC_XTENSA_SLOT2_OP
:
5916 case BFD_RELOC_XTENSA_SLOT3_OP
:
5917 case BFD_RELOC_XTENSA_SLOT4_OP
:
5918 case BFD_RELOC_XTENSA_SLOT5_OP
:
5919 case BFD_RELOC_XTENSA_SLOT6_OP
:
5920 case BFD_RELOC_XTENSA_SLOT7_OP
:
5921 case BFD_RELOC_XTENSA_SLOT8_OP
:
5922 case BFD_RELOC_XTENSA_SLOT9_OP
:
5923 case BFD_RELOC_XTENSA_SLOT10_OP
:
5924 case BFD_RELOC_XTENSA_SLOT11_OP
:
5925 case BFD_RELOC_XTENSA_SLOT12_OP
:
5926 case BFD_RELOC_XTENSA_SLOT13_OP
:
5927 case BFD_RELOC_XTENSA_SLOT14_OP
:
5930 /* Write the tentative value of a PC-relative relocation to a
5931 local symbol into the instruction. The value will be ignored
5932 by the linker, and it makes the object file disassembly
5933 readable when all branch targets are encoded in relocations. */
5935 gas_assert (fixP
->fx_addsy
);
5936 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5937 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5939 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5940 - md_pcrel_from (fixP
));
5941 (void) xg_apply_fix_value (fixP
, val
);
5944 else if (! fixP
->fx_addsy
)
5947 if (xg_apply_fix_value (fixP
, val
))
5952 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5953 case BFD_RELOC_XTENSA_TLS_FUNC
:
5954 case BFD_RELOC_XTENSA_TLS_ARG
:
5955 case BFD_RELOC_XTENSA_TLS_CALL
:
5956 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5957 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5958 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5959 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5960 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5961 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5962 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5963 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5964 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5965 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5966 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5967 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5968 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5969 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5970 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5971 /* These all need to be resolved at link-time. Do nothing now. */
5974 case BFD_RELOC_VTABLE_INHERIT
:
5975 case BFD_RELOC_VTABLE_ENTRY
:
5980 as_bad (_("unhandled local relocation fix %s"),
5981 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5987 md_atof (int type
, char *litP
, int *sizeP
)
5989 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5994 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5996 return total_frag_text_expansion (fragP
);
6000 /* Translate internal representation of relocation info to BFD target
6004 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6008 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
6009 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6010 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6011 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6013 /* Make sure none of our internal relocations make it this far.
6014 They'd better have been fully resolved by this point. */
6015 gas_assert ((int) fixp
->fx_r_type
> 0);
6017 reloc
->addend
= fixp
->fx_offset
;
6019 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6020 if (reloc
->howto
== NULL
)
6022 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6023 _("cannot represent `%s' relocation in object file"),
6024 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6025 free (reloc
->sym_ptr_ptr
);
6030 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6031 as_fatal (_("internal error; cannot generate `%s' relocation"),
6032 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6038 /* Checks for resource conflicts between instructions. */
6040 /* The func unit stuff could be implemented as bit-vectors rather
6041 than the iterative approach here. If it ends up being too
6042 slow, we will switch it. */
6045 new_resource_table (void *data
,
6048 unit_num_copies_func uncf
,
6049 opcode_num_units_func onuf
,
6050 opcode_funcUnit_use_unit_func ouuf
,
6051 opcode_funcUnit_use_stage_func ousf
)
6054 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6056 rt
->cycles
= cycles
;
6057 rt
->allocated_cycles
= cycles
;
6059 rt
->unit_num_copies
= uncf
;
6060 rt
->opcode_num_units
= onuf
;
6061 rt
->opcode_unit_use
= ouuf
;
6062 rt
->opcode_unit_stage
= ousf
;
6064 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6065 for (i
= 0; i
< cycles
; i
++)
6066 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6073 clear_resource_table (resource_table
*rt
)
6076 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6077 for (j
= 0; j
< rt
->num_units
; j
++)
6078 rt
->units
[i
][j
] = 0;
6082 /* We never shrink it, just fake it into thinking so. */
6085 resize_resource_table (resource_table
*rt
, int cycles
)
6089 rt
->cycles
= cycles
;
6090 if (cycles
<= rt
->allocated_cycles
)
6093 old_cycles
= rt
->allocated_cycles
;
6094 rt
->allocated_cycles
= cycles
;
6096 rt
->units
= xrealloc (rt
->units
,
6097 rt
->allocated_cycles
* sizeof (unsigned char *));
6098 for (i
= 0; i
< old_cycles
; i
++)
6099 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6100 rt
->num_units
* sizeof (unsigned char));
6101 for (i
= old_cycles
; i
< cycles
; i
++)
6102 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6107 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6110 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6112 for (i
= 0; i
< uses
; i
++)
6114 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6115 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6116 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6117 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6118 if (copies_in_use
>= copies
)
6126 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6129 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6131 for (i
= 0; i
< uses
; i
++)
6133 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6134 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6135 /* Note that this allows resources to be oversubscribed. That's
6136 essential to the way the optional scheduler works.
6137 resources_available reports when a resource is over-subscribed,
6138 so it's easy to tell. */
6139 rt
->units
[stage
+ cycle
][unit
]++;
6145 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6148 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6150 for (i
= 0; i
< uses
; i
++)
6152 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6153 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6154 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6155 rt
->units
[stage
+ cycle
][unit
]--;
6160 /* Wrapper functions make parameterized resource reservation
6164 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6166 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6172 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6174 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6179 /* Note that this function does not check issue constraints, but
6180 solely whether the hardware is available to execute the given
6181 instructions together. It also doesn't check if the tinsns
6182 write the same state, or access the same tieports. That is
6183 checked by check_t1_t2_reads_and_writes. */
6186 resources_conflict (vliw_insn
*vinsn
)
6189 static resource_table
*rt
= NULL
;
6191 /* This is the most common case by far. Optimize it. */
6192 if (vinsn
->num_slots
== 1)
6197 xtensa_isa isa
= xtensa_default_isa
;
6198 rt
= new_resource_table
6199 (isa
, xtensa_num_pipe_stages
,
6200 xtensa_isa_num_funcUnits (isa
),
6201 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6202 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6203 opcode_funcUnit_use_unit
,
6204 opcode_funcUnit_use_stage
);
6207 clear_resource_table (rt
);
6209 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6211 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6213 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6220 /* finish_vinsn, emit_single_op and helper functions. */
6222 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6223 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6224 static void xg_assemble_vliw_tokens (vliw_insn
*);
6227 /* We have reached the end of a bundle; emit into the frag. */
6230 finish_vinsn (vliw_insn
*vinsn
)
6237 if (find_vinsn_conflicts (vinsn
))
6239 xg_clear_vinsn (vinsn
);
6243 /* First, find a format that works. */
6244 if (vinsn
->format
== XTENSA_UNDEFINED
)
6245 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6247 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6248 && produce_flix
== FLIX_NONE
)
6250 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6251 xg_clear_vinsn (vinsn
);
6255 if (vinsn
->format
== XTENSA_UNDEFINED
)
6257 as_where (&file_name
, &line
);
6258 as_bad_where (file_name
, line
,
6259 _("couldn't find a valid instruction format"));
6260 fprintf (stderr
, _(" ops were: "));
6261 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6262 fprintf (stderr
, _(" %s;"),
6263 xtensa_opcode_name (xtensa_default_isa
,
6264 vinsn
->slots
[i
].opcode
));
6265 fprintf (stderr
, _("\n"));
6266 xg_clear_vinsn (vinsn
);
6270 if (vinsn
->num_slots
6271 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6273 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6274 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6275 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6277 xg_clear_vinsn (vinsn
);
6281 if (resources_conflict (vinsn
))
6283 as_where (&file_name
, &line
);
6284 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6285 fprintf (stderr
, " ops were: ");
6286 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6287 fprintf (stderr
, " %s;",
6288 xtensa_opcode_name (xtensa_default_isa
,
6289 vinsn
->slots
[i
].opcode
));
6290 fprintf (stderr
, "\n");
6291 xg_clear_vinsn (vinsn
);
6295 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6297 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6299 symbolS
*lit_sym
= NULL
;
6301 bfd_boolean e
= FALSE
;
6302 bfd_boolean saved_density
= density_supported
;
6304 /* We don't want to narrow ops inside multi-slot bundles. */
6305 if (vinsn
->num_slots
> 1)
6306 density_supported
= FALSE
;
6308 istack_init (&slotstack
);
6309 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6311 vinsn
->slots
[i
].opcode
=
6312 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6314 vinsn
->slots
[i
].ntok
= 0;
6317 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6323 density_supported
= saved_density
;
6327 xg_clear_vinsn (vinsn
);
6331 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6333 TInsn
*insn
= &slotstack
.insn
[j
];
6334 if (insn
->insn_type
== ITYPE_LITERAL
)
6336 gas_assert (lit_sym
== NULL
);
6337 lit_sym
= xg_assemble_literal (insn
);
6341 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6343 xg_resolve_literals (insn
, lit_sym
);
6344 if (j
!= slotstack
.ninsn
- 1)
6345 emit_single_op (insn
);
6349 if (vinsn
->num_slots
> 1)
6351 if (opcode_fits_format_slot
6352 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6355 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6359 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6360 if (vinsn
->format
== XTENSA_UNDEFINED
)
6361 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6363 vinsn
->slots
[i
].opcode
6364 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6367 vinsn
->slots
[i
].ntok
= 0;
6372 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6373 vinsn
->format
= XTENSA_UNDEFINED
;
6378 /* Now check resource conflicts on the modified bundle. */
6379 if (resources_conflict (vinsn
))
6381 as_where (&file_name
, &line
);
6382 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6383 fprintf (stderr
, " ops were: ");
6384 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6385 fprintf (stderr
, " %s;",
6386 xtensa_opcode_name (xtensa_default_isa
,
6387 vinsn
->slots
[i
].opcode
));
6388 fprintf (stderr
, "\n");
6389 xg_clear_vinsn (vinsn
);
6393 /* First, find a format that works. */
6394 if (vinsn
->format
== XTENSA_UNDEFINED
)
6395 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6397 xg_assemble_vliw_tokens (vinsn
);
6399 xg_clear_vinsn (vinsn
);
6401 xtensa_check_frag_count ();
6405 /* Given an vliw instruction, what conflicts are there in register
6406 usage and in writes to states and queues?
6408 This function does two things:
6409 1. Reports an error when a vinsn contains illegal combinations
6410 of writes to registers states or queues.
6411 2. Marks individual tinsns as not relaxable if the combination
6412 contains antidependencies.
6414 Job 2 handles things like swap semantics in instructions that need
6415 to be relaxed. For example,
6419 normally would be relaxed to
6424 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6426 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6428 then we can't relax it into
6431 { add a0, a1, a0 ; add a2, a0, a4 ; }
6433 because the value of a0 is trashed before the second add can read it. */
6435 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6438 find_vinsn_conflicts (vliw_insn
*vinsn
)
6442 xtensa_isa isa
= xtensa_default_isa
;
6444 gas_assert (!past_xtensa_end
);
6446 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6448 TInsn
*op1
= &vinsn
->slots
[i
];
6449 if (op1
->is_specific_opcode
)
6450 op1
->keep_wide
= TRUE
;
6452 op1
->keep_wide
= FALSE
;
6455 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6457 TInsn
*op1
= &vinsn
->slots
[i
];
6459 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6462 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6466 TInsn
*op2
= &vinsn
->slots
[j
];
6467 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6468 switch (conflict_type
)
6471 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6472 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6473 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6476 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6477 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6478 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6481 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6482 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6483 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6486 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6487 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6488 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6491 /* Everything is OK. */
6494 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6495 || conflict_type
== 'a');
6502 as_bad (_("multiple branches or jumps in the same bundle"));
6510 /* Check how the state used by t1 and t2 relate.
6513 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6514 case B: no relationship between what is read and written (both could
6515 read the same reg though)
6516 case C: t1 writes a register t2 writes (a register conflict within a
6518 case D: t1 writes a state that t2 also writes
6519 case E: t1 writes a tie queue that t2 also writes
6520 case F: two volatile queue accesses
6524 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6526 xtensa_isa isa
= xtensa_default_isa
;
6527 xtensa_regfile t1_regfile
, t2_regfile
;
6529 int t1_base_reg
, t1_last_reg
;
6530 int t2_base_reg
, t2_last_reg
;
6531 char t1_inout
, t2_inout
;
6533 char conflict
= 'b';
6538 bfd_boolean t1_volatile
= FALSE
;
6539 bfd_boolean t2_volatile
= FALSE
;
6541 /* Check registers. */
6542 for (j
= 0; j
< t2
->ntok
; j
++)
6544 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6547 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6548 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6549 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6551 for (i
= 0; i
< t1
->ntok
; i
++)
6553 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6556 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6558 if (t1_regfile
!= t2_regfile
)
6561 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6562 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6564 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6565 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6567 if (t1_inout
== 'm' || t1_inout
== 'o'
6568 || t2_inout
== 'm' || t2_inout
== 'o')
6575 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6576 t1_last_reg
= (t1_base_reg
6577 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6579 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6581 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6583 if (t1_reg
!= t2_reg
)
6586 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6592 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6598 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6606 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6607 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6608 for (j
= 0; j
< t2_states
; j
++)
6610 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6611 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6612 for (i
= 0; i
< t1_states
; i
++)
6614 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6615 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6616 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6619 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6625 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6631 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6636 /* Check tieports. */
6637 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6638 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6639 for (j
= 0; j
< t2_interfaces
; j
++)
6641 xtensa_interface t2_int
6642 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6643 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6645 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6646 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6649 for (i
= 0; i
< t1_interfaces
; i
++)
6651 xtensa_interface t1_int
6652 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6653 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6655 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6656 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6659 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6662 if (t1_int
!= t2_int
)
6665 if (t2_inout
== 'i' && t1_inout
== 'o')
6671 if (t1_inout
== 'i' && t2_inout
== 'o')
6677 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6686 static xtensa_format
6687 xg_find_narrowest_format (vliw_insn
*vinsn
)
6689 /* Right now we assume that the ops within the vinsn are properly
6690 ordered for the slots that the programmer wanted them in. In
6691 other words, we don't rearrange the ops in hopes of finding a
6692 better format. The scheduler handles that. */
6694 xtensa_isa isa
= xtensa_default_isa
;
6695 xtensa_format format
;
6696 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6698 if (vinsn
->num_slots
== 1)
6699 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6701 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6704 xg_copy_vinsn (&v_copy
, vinsn
);
6705 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6709 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6711 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6713 v_copy
.slots
[slot
].opcode
=
6714 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6715 v_copy
.slots
[slot
].ntok
= 0;
6718 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6721 else if (v_copy
.num_slots
> 1)
6724 /* Try the widened version. */
6725 if (!v_copy
.slots
[slot
].keep_wide
6726 && !v_copy
.slots
[slot
].is_specific_opcode
6727 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6729 && opcode_fits_format_slot (widened
.opcode
,
6732 v_copy
.slots
[slot
] = widened
;
6737 if (fit
== v_copy
.num_slots
)
6739 xg_copy_vinsn (vinsn
, &v_copy
);
6740 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6741 vinsn
->format
= format
;
6747 if (format
== xtensa_isa_num_formats (isa
))
6748 return XTENSA_UNDEFINED
;
6754 /* Return the additional space needed in a frag
6755 for possible relaxations of any ops in a VLIW insn.
6756 Also fill out the relaxations that might be required of
6757 each tinsn in the vinsn. */
6760 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6762 bfd_boolean finish_frag
= FALSE
;
6763 int extra_space
= 0;
6766 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6768 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6769 if (!tinsn_has_symbolic_operands (tinsn
))
6771 /* A narrow instruction could be widened later to help
6772 alignment issues. */
6773 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6774 && !tinsn
->is_specific_opcode
6775 && vinsn
->num_slots
== 1)
6777 /* Difference in bytes between narrow and wide insns... */
6779 tinsn
->subtype
= RELAX_NARROW
;
6784 if (workaround_b_j_loop_end
6785 && tinsn
->opcode
== xtensa_jx_opcode
6786 && use_transform ())
6788 /* Add 2 of these. */
6789 extra_space
+= 3; /* for the nop size */
6790 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6793 /* Need to assemble it with space for the relocation. */
6794 if (xg_is_relaxable_insn (tinsn
, 0)
6795 && !tinsn
->is_specific_opcode
)
6797 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6798 int max_literal_size
=
6799 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6801 tinsn
->literal_space
= max_literal_size
;
6803 tinsn
->subtype
= RELAX_IMMED
;
6804 extra_space
+= max_size
;
6808 /* A fix record will be added for this instruction prior
6809 to relaxation, so make it end the frag. */
6814 *pfinish_frag
= finish_frag
;
6820 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6822 xtensa_isa isa
= xtensa_default_isa
;
6823 int slot
, chosen_slot
;
6825 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6826 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6827 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6829 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6830 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6832 if (slot
== chosen_slot
)
6833 vinsn
->slots
[slot
] = *tinsn
;
6836 vinsn
->slots
[slot
].opcode
=
6837 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6838 vinsn
->slots
[slot
].ntok
= 0;
6839 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6846 emit_single_op (TInsn
*orig_insn
)
6849 IStack istack
; /* put instructions into here */
6850 symbolS
*lit_sym
= NULL
;
6851 symbolS
*label_sym
= NULL
;
6853 istack_init (&istack
);
6855 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6856 Because the scheduling and bundling characteristics of movi and
6857 l32r or const16 are so different, we can do much better if we relax
6858 it prior to scheduling and bundling, rather than after. */
6859 if ((orig_insn
->opcode
== xtensa_movi_opcode
6860 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6861 && !cur_vinsn
.inside_bundle
6862 && (orig_insn
->tok
[1].X_op
== O_symbol
6863 || orig_insn
->tok
[1].X_op
== O_pltrel
6864 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6865 || orig_insn
->tok
[1].X_op
== O_tlsarg
6866 || orig_insn
->tok
[1].X_op
== O_tpoff
6867 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6868 && !orig_insn
->is_specific_opcode
&& use_transform ())
6869 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6871 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6874 for (i
= 0; i
< istack
.ninsn
; i
++)
6876 TInsn
*insn
= &istack
.insn
[i
];
6877 switch (insn
->insn_type
)
6880 gas_assert (lit_sym
== NULL
);
6881 lit_sym
= xg_assemble_literal (insn
);
6885 static int relaxed_sym_idx
= 0;
6886 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6887 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6889 gas_assert (label_sym
== NULL
);
6890 label_sym
= symbol_find_or_make (label
);
6891 gas_assert (label_sym
);
6899 xg_resolve_literals (insn
, lit_sym
);
6901 xg_resolve_labels (insn
, label_sym
);
6903 bundle_tinsn (insn
, &v
);
6918 total_frag_text_expansion (fragS
*fragP
)
6921 int total_expansion
= 0;
6923 for (slot
= 0; slot
< config_max_slots
; slot
++)
6924 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6926 return total_expansion
;
6930 /* Emit a vliw instruction to the current fragment. */
6933 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6935 bfd_boolean finish_frag
;
6936 bfd_boolean is_jump
= FALSE
;
6937 bfd_boolean is_branch
= FALSE
;
6938 xtensa_isa isa
= xtensa_default_isa
;
6943 struct dwarf2_line_info debug_line
;
6944 bfd_boolean loc_directive_seen
= FALSE
;
6947 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6949 if (generating_literals
)
6951 static int reported
= 0;
6953 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6954 _("cannot assemble into a literal fragment"));
6961 if (frag_now_fix () != 0
6962 && (! frag_now
->tc_frag_data
.is_insn
6963 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6964 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6965 || (directive_state
[directive_longcalls
]
6966 != frag_now
->tc_frag_data
.use_longcalls
)
6967 || (directive_state
[directive_absolute_literals
]
6968 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6970 frag_wane (frag_now
);
6972 xtensa_set_frag_assembly_state (frag_now
);
6975 if (workaround_a0_b_retw
6976 && vinsn
->num_slots
== 1
6977 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6978 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6979 && use_transform ())
6981 has_a0_b_retw
= TRUE
;
6983 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6984 After the first assembly pass we will check all of them and
6985 add a nop if needed. */
6986 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6987 frag_var (rs_machine_dependent
, 4, 4,
6988 RELAX_ADD_NOP_IF_A0_B_RETW
,
6989 frag_now
->fr_symbol
,
6990 frag_now
->fr_offset
,
6992 xtensa_set_frag_assembly_state (frag_now
);
6993 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6994 frag_var (rs_machine_dependent
, 4, 4,
6995 RELAX_ADD_NOP_IF_A0_B_RETW
,
6996 frag_now
->fr_symbol
,
6997 frag_now
->fr_offset
,
6999 xtensa_set_frag_assembly_state (frag_now
);
7002 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7004 tinsn
= &vinsn
->slots
[slot
];
7006 /* See if the instruction implies an aligned section. */
7007 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7008 record_alignment (now_seg
, 2);
7010 /* Determine the best line number for debug info. */
7011 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7012 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7013 || tinsn
->debug_line
.line
< debug_line
.line
7014 || tinsn
->debug_line
.column
< debug_line
.column
))
7015 debug_line
= tinsn
->debug_line
;
7016 if (tinsn
->loc_directive_seen
)
7017 loc_directive_seen
= TRUE
;
7020 /* Special cases for instructions that force an alignment... */
7021 /* None of these opcodes are bundle-able. */
7022 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7026 /* Remember the symbol that marks the end of the loop in the frag
7027 that marks the start of the loop. This way we can easily find
7028 the end of the loop at the beginning, without adding special code
7029 to mark the loop instructions themselves. */
7030 symbolS
*target_sym
= NULL
;
7031 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7032 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7034 xtensa_set_frag_assembly_state (frag_now
);
7035 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7037 max_fill
= get_text_align_max_fill_size
7038 (get_text_align_power (xtensa_fetch_width
),
7039 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7041 if (use_transform ())
7042 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7043 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7045 frag_var (rs_machine_dependent
, 0, 0,
7046 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7047 xtensa_set_frag_assembly_state (frag_now
);
7050 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7051 && !vinsn
->slots
[0].is_specific_opcode
)
7053 xtensa_mark_literal_pool_location ();
7054 xtensa_move_labels (frag_now
, 0);
7055 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7058 if (vinsn
->num_slots
== 1)
7060 if (workaround_a0_b_retw
&& use_transform ())
7061 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7062 is_register_writer (&vinsn
->slots
[0], "a", 0));
7064 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7065 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7068 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7070 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7072 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7074 /* vinsn_to_insnbuf will produce the error. */
7075 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7077 f
= frag_more (insn_size
+ extra_space
);
7078 xtensa_set_frag_assembly_state (frag_now
);
7079 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7082 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7083 if (vinsn
->format
== XTENSA_UNDEFINED
)
7086 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7088 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7089 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7092 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7094 tinsn
= &vinsn
->slots
[slot
];
7095 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7096 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7097 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7098 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7099 if (tinsn
->literal_space
!= 0)
7100 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7101 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7103 if (tinsn
->subtype
== RELAX_NARROW
)
7104 gas_assert (vinsn
->num_slots
== 1);
7105 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7107 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7110 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7111 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7115 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7116 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7120 frag_variant (rs_machine_dependent
,
7121 extra_space
, extra_space
, RELAX_SLOTS
,
7122 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7123 xtensa_set_frag_assembly_state (frag_now
);
7126 /* Special cases for loops:
7127 close_loop_end should be inserted AFTER short_loop.
7128 Make sure that CLOSE loops are processed BEFORE short_loops
7129 when converting them. */
7131 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7132 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7133 && !vinsn
->slots
[0].is_specific_opcode
)
7135 if (workaround_short_loop
&& use_transform ())
7137 maybe_has_short_loop
= TRUE
;
7138 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7139 frag_var (rs_machine_dependent
, 4, 4,
7140 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7141 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7142 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7143 frag_var (rs_machine_dependent
, 4, 4,
7144 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7145 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7148 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7149 loop at least 12 bytes away from another loop's end. */
7150 if (workaround_close_loop_end
&& use_transform ())
7152 maybe_has_close_loop_end
= TRUE
;
7153 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7154 frag_var (rs_machine_dependent
, 12, 12,
7155 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7156 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7160 if (use_transform ())
7164 gas_assert (finish_frag
);
7165 frag_var (rs_machine_dependent
,
7166 xtensa_fetch_width
, xtensa_fetch_width
,
7168 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7169 xtensa_set_frag_assembly_state (frag_now
);
7170 xtensa_maybe_create_trampoline_frag ();
7172 else if (is_branch
&& do_align_targets ())
7174 gas_assert (finish_frag
);
7175 frag_var (rs_machine_dependent
,
7176 xtensa_fetch_width
, xtensa_fetch_width
,
7177 RELAX_MAYBE_UNREACHABLE
,
7178 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7179 xtensa_set_frag_assembly_state (frag_now
);
7180 frag_var (rs_machine_dependent
,
7182 RELAX_MAYBE_DESIRE_ALIGN
,
7183 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7184 xtensa_set_frag_assembly_state (frag_now
);
7188 /* Now, if the original opcode was a call... */
7189 if (do_align_targets ()
7190 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7192 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7193 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7194 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7195 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7196 xtensa_set_frag_assembly_state (frag_now
);
7199 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7201 frag_wane (frag_now
);
7203 xtensa_set_frag_assembly_state (frag_now
);
7208 /* xtensa_end and helper functions. */
7210 static void xtensa_cleanup_align_frags (void);
7211 static void xtensa_fix_target_frags (void);
7212 static void xtensa_mark_narrow_branches (void);
7213 static void xtensa_mark_zcl_first_insns (void);
7214 static void xtensa_mark_difference_of_two_symbols (void);
7215 static void xtensa_fix_a0_b_retw_frags (void);
7216 static void xtensa_fix_b_j_loop_end_frags (void);
7217 static void xtensa_fix_close_loop_end_frags (void);
7218 static void xtensa_fix_short_loop_frags (void);
7219 static void xtensa_sanity_check (void);
7220 static void xtensa_add_config_info (void);
7225 directive_balance ();
7226 xtensa_flush_pending_output ();
7228 past_xtensa_end
= TRUE
;
7230 xtensa_move_literals ();
7232 xtensa_reorder_segments ();
7233 xtensa_cleanup_align_frags ();
7234 xtensa_fix_target_frags ();
7235 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7236 xtensa_fix_a0_b_retw_frags ();
7237 if (workaround_b_j_loop_end
)
7238 xtensa_fix_b_j_loop_end_frags ();
7240 /* "close_loop_end" should be processed BEFORE "short_loop". */
7241 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7242 xtensa_fix_close_loop_end_frags ();
7244 if (workaround_short_loop
&& maybe_has_short_loop
)
7245 xtensa_fix_short_loop_frags ();
7247 xtensa_mark_narrow_branches ();
7248 xtensa_mark_zcl_first_insns ();
7250 xtensa_sanity_check ();
7252 xtensa_add_config_info ();
7254 xtensa_check_frag_count ();
7258 struct trampoline_frag
7260 struct trampoline_frag
*next
;
7261 bfd_boolean needs_jump_around
;
7266 struct trampoline_seg
7268 struct trampoline_seg
*next
;
7270 struct trampoline_frag trampoline_list
;
7273 static struct trampoline_seg trampoline_seg_list
;
7274 #define J_RANGE (128 * 1024)
7276 static int unreachable_count
= 0;
7280 xtensa_maybe_create_trampoline_frag (void)
7282 if (!use_trampolines
)
7285 /* We create an area for possible trampolines every 10 unreachable frags.
7286 These are preferred over the ones not preceded by an unreachable frag,
7287 because we don't have to jump around them. This function is called after
7288 each RELAX_UNREACHABLE frag is created. */
7290 if (++unreachable_count
> 10)
7292 xtensa_create_trampoline_frag (FALSE
);
7293 clear_frag_count ();
7294 unreachable_count
= 0;
7299 xtensa_check_frag_count (void)
7301 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7304 /* We create an area for possible trampolines every 8000 frags or so. This
7305 is an estimate based on the max range of a "j" insn (+/-128K) divided
7306 by a typical frag byte count (16), minus a few for safety. This function
7307 is called after each source line is processed. */
7309 if (get_frag_count () > 8000)
7311 xtensa_create_trampoline_frag (TRUE
);
7312 clear_frag_count ();
7313 unreachable_count
= 0;
7317 static xtensa_insnbuf trampoline_buf
= NULL
;
7318 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7320 #define TRAMPOLINE_FRAG_SIZE 3000
7323 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7325 /* Emit a frag where we can place intermediate jump instructions,
7326 in case we need to jump farther than 128K bytes.
7327 Each jump instruction takes three bytes.
7328 We allocate enough for 1000 trampolines in each frag.
7329 If that's not enough, oh well. */
7331 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7332 struct trampoline_frag
*tf
;
7335 int size
= TRAMPOLINE_FRAG_SIZE
;
7337 for ( ; ts
; ts
= ts
->next
)
7339 if (ts
->seg
== now_seg
)
7345 ts
= (struct trampoline_seg
*)xcalloc(sizeof (struct trampoline_seg
), 1);
7346 ts
->next
= trampoline_seg_list
.next
;
7347 trampoline_seg_list
.next
= ts
;
7351 frag_wane (frag_now
);
7353 xtensa_set_frag_assembly_state (frag_now
);
7354 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7355 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7356 if (trampoline_buf
== NULL
)
7358 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7359 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7361 tf
= (struct trampoline_frag
*)xmalloc(sizeof (struct trampoline_frag
));
7362 tf
->next
= ts
->trampoline_list
.next
;
7363 ts
->trampoline_list
.next
= tf
;
7364 tf
->needs_jump_around
= needs_jump_around
;
7370 static struct trampoline_seg
*
7371 find_trampoline_seg (asection
*seg
)
7373 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7375 for ( ; ts
; ts
= ts
->next
)
7385 void dump_trampolines (void);
7388 dump_trampolines (void)
7390 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7392 for ( ; ts
; ts
= ts
->next
)
7394 asection
*seg
= ts
->seg
;
7398 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7399 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7400 for ( ; tf
; tf
= tf
->next
)
7402 if (tf
->fragP
== NULL
)
7404 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7405 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7406 tf
->needs_jump_around
? "T" : "F");
7412 xtensa_cleanup_align_frags (void)
7417 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7418 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7421 /* Walk over all of the fragments in a subsection. */
7422 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7424 if ((fragP
->fr_type
== rs_align
7425 || fragP
->fr_type
== rs_align_code
7426 || (fragP
->fr_type
== rs_machine_dependent
7427 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7428 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7429 && fragP
->fr_fix
== 0)
7431 fragS
*next
= fragP
->fr_next
;
7434 && next
->fr_fix
== 0
7435 && next
->fr_type
== rs_machine_dependent
7436 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7439 next
= next
->fr_next
;
7442 /* If we don't widen branch targets, then they
7443 will be easier to align. */
7444 if (fragP
->tc_frag_data
.is_branch_target
7445 && fragP
->fr_opcode
== fragP
->fr_literal
7446 && fragP
->fr_type
== rs_machine_dependent
7447 && fragP
->fr_subtype
== RELAX_SLOTS
7448 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7450 if (fragP
->fr_type
== rs_machine_dependent
7451 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7452 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7458 /* Re-process all of the fragments looking to convert all of the
7459 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7460 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7461 Otherwise, convert to a .fill 0. */
7464 xtensa_fix_target_frags (void)
7469 /* When this routine is called, all of the subsections are still intact
7470 so we walk over subsections instead of sections. */
7471 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7472 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7476 /* Walk over all of the fragments in a subsection. */
7477 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7479 if (fragP
->fr_type
== rs_machine_dependent
7480 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7482 if (next_frag_is_branch_target (fragP
))
7483 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7492 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7495 xtensa_mark_narrow_branches (void)
7500 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7501 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7504 /* Walk over all of the fragments in a subsection. */
7505 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7507 if (fragP
->fr_type
== rs_machine_dependent
7508 && fragP
->fr_subtype
== RELAX_SLOTS
7509 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7513 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7514 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7516 if (vinsn
.num_slots
== 1
7517 && xtensa_opcode_is_branch (xtensa_default_isa
,
7518 vinsn
.slots
[0].opcode
) == 1
7519 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7520 && is_narrow_branch_guaranteed_in_range (fragP
,
7523 fragP
->fr_subtype
= RELAX_SLOTS
;
7524 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7525 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7533 /* A branch is typically widened only when its target is out of
7534 range. However, we would like to widen them to align a subsequent
7535 branch target when possible.
7537 Because the branch relaxation code is so convoluted, the optimal solution
7538 (combining the two cases) is difficult to get right in all circumstances.
7539 We therefore go with an "almost as good" solution, where we only
7540 use for alignment narrow branches that definitely will not expand to a
7541 jump and a branch. These functions find and mark these cases. */
7543 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7544 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7545 We start counting beginning with the frag after the 2-byte branch, so the
7546 maximum offset is (4 - 2) + 63 = 65. */
7547 #define MAX_IMMED6 65
7549 static offsetT
unrelaxed_frag_max_size (fragS
*);
7552 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7554 const expressionS
*exp
= &tinsn
->tok
[1];
7555 symbolS
*symbolP
= exp
->X_add_symbol
;
7556 offsetT max_distance
= exp
->X_add_number
;
7559 if (exp
->X_op
!= O_symbol
)
7562 target_frag
= symbol_get_frag (symbolP
);
7564 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7565 if (is_branch_jmp_to_next (tinsn
, fragP
))
7568 /* The branch doesn't branch over it's own frag,
7569 but over the subsequent ones. */
7570 fragP
= fragP
->fr_next
;
7571 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7573 max_distance
+= unrelaxed_frag_max_size (fragP
);
7574 fragP
= fragP
->fr_next
;
7576 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7583 xtensa_mark_zcl_first_insns (void)
7588 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7589 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7592 /* Walk over all of the fragments in a subsection. */
7593 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7595 if (fragP
->fr_type
== rs_machine_dependent
7596 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7597 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7599 /* Find the loop frag. */
7600 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7601 /* Find the first insn frag. */
7602 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7604 /* Handle a corner case that comes up in hardware
7605 diagnostics. The original assembly looks like this:
7608 <empty_frag>--not found by next_non_empty_frag
7611 Depending on the start address, the assembler may or
7612 may not change it to look something like this:
7615 nop--frag isn't empty anymore
7618 So set up to check the alignment of the nop if it
7620 while (loop_frag
!= targ_frag
)
7622 if (loop_frag
->fr_type
== rs_machine_dependent
7623 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7624 || loop_frag
->fr_subtype
7625 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7626 targ_frag
= loop_frag
;
7628 loop_frag
= loop_frag
->fr_next
;
7631 /* Of course, sometimes (mostly for toy test cases) a
7632 zero-cost loop instruction is the last in a section. */
7635 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7636 /* Do not widen a frag that is the first instruction of a
7637 zero-cost loop. It makes that loop harder to align. */
7638 if (targ_frag
->fr_type
== rs_machine_dependent
7639 && targ_frag
->fr_subtype
== RELAX_SLOTS
7640 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7643 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7644 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7647 frag_wane (targ_frag
);
7648 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7652 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7660 /* When a difference-of-symbols expression is encoded as a uleb128 or
7661 sleb128 value, the linker is unable to adjust that value to account for
7662 link-time relaxation. Mark all the code between such symbols so that
7663 its size cannot be changed by linker relaxation. */
7666 xtensa_mark_difference_of_two_symbols (void)
7670 for (expr_sym
= expr_symbols
; expr_sym
;
7671 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7673 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7675 if (exp
->X_op
== O_subtract
)
7677 symbolS
*left
= exp
->X_add_symbol
;
7678 symbolS
*right
= exp
->X_op_symbol
;
7680 /* Difference of two symbols not in the same section
7681 are handled with relocations in the linker. */
7682 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7688 if (symbol_get_frag (left
)->fr_address
7689 <= symbol_get_frag (right
)->fr_address
)
7691 start
= symbol_get_frag (left
);
7692 end
= symbol_get_frag (right
);
7696 start
= symbol_get_frag (right
);
7697 end
= symbol_get_frag (left
);
7700 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7701 walk
= start
->tc_frag_data
.no_transform_end
;
7706 walk
->tc_frag_data
.is_no_transform
= 1;
7707 walk
= walk
->fr_next
;
7709 while (walk
&& walk
->fr_address
< end
->fr_address
);
7711 start
->tc_frag_data
.no_transform_end
= walk
;
7718 /* Re-process all of the fragments looking to convert all of the
7719 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7720 conditional branch or a retw/retw.n, convert this frag to one that
7721 will generate a NOP. In any case close it off with a .fill 0. */
7723 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7726 xtensa_fix_a0_b_retw_frags (void)
7731 /* When this routine is called, all of the subsections are still intact
7732 so we walk over subsections instead of sections. */
7733 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7734 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7738 /* Walk over all of the fragments in a subsection. */
7739 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7741 if (fragP
->fr_type
== rs_machine_dependent
7742 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7744 if (next_instrs_are_b_retw (fragP
))
7746 if (fragP
->tc_frag_data
.is_no_transform
)
7747 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7749 relax_frag_add_nop (fragP
);
7759 next_instrs_are_b_retw (fragS
*fragP
)
7761 xtensa_opcode opcode
;
7763 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7764 static xtensa_insnbuf insnbuf
= NULL
;
7765 static xtensa_insnbuf slotbuf
= NULL
;
7766 xtensa_isa isa
= xtensa_default_isa
;
7769 bfd_boolean branch_seen
= FALSE
;
7773 insnbuf
= xtensa_insnbuf_alloc (isa
);
7774 slotbuf
= xtensa_insnbuf_alloc (isa
);
7777 if (next_fragP
== NULL
)
7780 /* Check for the conditional branch. */
7781 xtensa_insnbuf_from_chars
7782 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7783 fmt
= xtensa_format_decode (isa
, insnbuf
);
7784 if (fmt
== XTENSA_UNDEFINED
)
7787 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7789 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7790 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7792 branch_seen
= (branch_seen
7793 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7799 offset
+= xtensa_format_length (isa
, fmt
);
7800 if (offset
== next_fragP
->fr_fix
)
7802 next_fragP
= next_non_empty_frag (next_fragP
);
7806 if (next_fragP
== NULL
)
7809 /* Check for the retw/retw.n. */
7810 xtensa_insnbuf_from_chars
7811 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7812 fmt
= xtensa_format_decode (isa
, insnbuf
);
7814 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7815 have no problems. */
7816 if (fmt
== XTENSA_UNDEFINED
7817 || xtensa_format_num_slots (isa
, fmt
) != 1)
7820 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7821 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7823 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7830 /* Re-process all of the fragments looking to convert all of the
7831 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7832 loop end label, convert this frag to one that will generate a NOP.
7833 In any case close it off with a .fill 0. */
7835 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7838 xtensa_fix_b_j_loop_end_frags (void)
7843 /* When this routine is called, all of the subsections are still intact
7844 so we walk over subsections instead of sections. */
7845 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7846 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7850 /* Walk over all of the fragments in a subsection. */
7851 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7853 if (fragP
->fr_type
== rs_machine_dependent
7854 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7856 if (next_instr_is_loop_end (fragP
))
7858 if (fragP
->tc_frag_data
.is_no_transform
)
7859 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7861 relax_frag_add_nop (fragP
);
7871 next_instr_is_loop_end (fragS
*fragP
)
7873 const fragS
*next_fragP
;
7875 if (next_frag_is_loop_target (fragP
))
7878 next_fragP
= next_non_empty_frag (fragP
);
7879 if (next_fragP
== NULL
)
7882 if (!next_frag_is_loop_target (next_fragP
))
7885 /* If the size is >= 3 then there is more than one instruction here.
7886 The hardware bug will not fire. */
7887 if (next_fragP
->fr_fix
> 3)
7894 /* Re-process all of the fragments looking to convert all of the
7895 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7896 not MY loop's loop end within 12 bytes, add enough nops here to
7897 make it at least 12 bytes away. In any case close it off with a
7900 static offsetT min_bytes_to_other_loop_end
7901 (fragS
*, fragS
*, offsetT
);
7904 xtensa_fix_close_loop_end_frags (void)
7909 /* When this routine is called, all of the subsections are still intact
7910 so we walk over subsections instead of sections. */
7911 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7912 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7916 fragS
*current_target
= NULL
;
7918 /* Walk over all of the fragments in a subsection. */
7919 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7921 if (fragP
->fr_type
== rs_machine_dependent
7922 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7923 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7924 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7927 && fragP
->fr_type
== rs_machine_dependent
7928 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7931 int bytes_added
= 0;
7933 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7934 /* Max out at 12. */
7935 min_bytes
= min_bytes_to_other_loop_end
7936 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7938 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7940 if (fragP
->tc_frag_data
.is_no_transform
)
7941 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7944 while (min_bytes
+ bytes_added
7945 < REQUIRED_LOOP_DIVIDING_BYTES
)
7949 if (fragP
->fr_var
< length
)
7950 as_fatal (_("fr_var %lu < length %d"),
7951 (long) fragP
->fr_var
, length
);
7954 assemble_nop (length
,
7955 fragP
->fr_literal
+ fragP
->fr_fix
);
7956 fragP
->fr_fix
+= length
;
7957 fragP
->fr_var
-= length
;
7959 bytes_added
+= length
;
7965 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7966 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7972 static offsetT
unrelaxed_frag_min_size (fragS
*);
7975 min_bytes_to_other_loop_end (fragS
*fragP
,
7976 fragS
*current_target
,
7980 fragS
*current_fragP
;
7982 for (current_fragP
= fragP
;
7984 current_fragP
= current_fragP
->fr_next
)
7986 if (current_fragP
->tc_frag_data
.is_loop_target
7987 && current_fragP
!= current_target
)
7990 offset
+= unrelaxed_frag_min_size (current_fragP
);
7992 if (offset
>= max_size
)
8000 unrelaxed_frag_min_size (fragS
*fragP
)
8002 offsetT size
= fragP
->fr_fix
;
8004 /* Add fill size. */
8005 if (fragP
->fr_type
== rs_fill
)
8006 size
+= fragP
->fr_offset
;
8013 unrelaxed_frag_max_size (fragS
*fragP
)
8015 offsetT size
= fragP
->fr_fix
;
8016 switch (fragP
->fr_type
)
8019 /* Empty frags created by the obstack allocation scheme
8020 end up with type 0. */
8025 size
+= fragP
->fr_offset
;
8033 /* No further adjustments needed. */
8035 case rs_machine_dependent
:
8036 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8037 size
+= fragP
->fr_var
;
8040 /* We had darn well better know how big it is. */
8049 /* Re-process all of the fragments looking to convert all
8050 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8053 1) the instruction size count to the loop end label
8054 is too short (<= 2 instructions),
8055 2) loop has a jump or branch in it
8058 1) workaround_all_short_loops is TRUE
8059 2) The generating loop was a 'loopgtz' or 'loopnez'
8060 3) the instruction size count to the loop end label is too short
8062 then convert this frag (and maybe the next one) to generate a NOP.
8063 In any case close it off with a .fill 0. */
8065 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8066 static bfd_boolean
branch_before_loop_end (fragS
*);
8069 xtensa_fix_short_loop_frags (void)
8074 /* When this routine is called, all of the subsections are still intact
8075 so we walk over subsections instead of sections. */
8076 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8077 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8080 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8082 /* Walk over all of the fragments in a subsection. */
8083 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8085 if (fragP
->fr_type
== rs_machine_dependent
8086 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8087 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8090 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8091 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8092 current_opcode
= t_insn
.opcode
;
8093 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8094 current_opcode
) == 1);
8097 if (fragP
->fr_type
== rs_machine_dependent
8098 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8100 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8101 && (branch_before_loop_end (fragP
->fr_next
)
8102 || (workaround_all_short_loops
8103 && current_opcode
!= XTENSA_UNDEFINED
8104 && current_opcode
!= xtensa_loop_opcode
)))
8106 if (fragP
->tc_frag_data
.is_no_transform
)
8107 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8109 relax_frag_add_nop (fragP
);
8118 static int unrelaxed_frag_min_insn_count (fragS
*);
8121 count_insns_to_loop_end (fragS
*base_fragP
,
8122 bfd_boolean count_relax_add
,
8125 fragS
*fragP
= NULL
;
8130 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8132 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8133 if (insn_count
>= max_count
)
8136 if (count_relax_add
)
8138 if (fragP
->fr_type
== rs_machine_dependent
8139 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8141 /* In order to add the appropriate number of
8142 NOPs, we count an instruction for downstream
8145 if (insn_count
>= max_count
)
8155 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8157 xtensa_isa isa
= xtensa_default_isa
;
8158 static xtensa_insnbuf insnbuf
= NULL
;
8162 if (!fragP
->tc_frag_data
.is_insn
)
8166 insnbuf
= xtensa_insnbuf_alloc (isa
);
8168 /* Decode the fixed instructions. */
8169 while (offset
< fragP
->fr_fix
)
8173 xtensa_insnbuf_from_chars
8174 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8175 fmt
= xtensa_format_decode (isa
, insnbuf
);
8177 if (fmt
== XTENSA_UNDEFINED
)
8179 as_fatal (_("undecodable instruction in instruction frag"));
8182 offset
+= xtensa_format_length (isa
, fmt
);
8190 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8193 branch_before_loop_end (fragS
*base_fragP
)
8197 for (fragP
= base_fragP
;
8198 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8199 fragP
= fragP
->fr_next
)
8201 if (unrelaxed_frag_has_b_j (fragP
))
8209 unrelaxed_frag_has_b_j (fragS
*fragP
)
8211 static xtensa_insnbuf insnbuf
= NULL
;
8212 xtensa_isa isa
= xtensa_default_isa
;
8215 if (!fragP
->tc_frag_data
.is_insn
)
8219 insnbuf
= xtensa_insnbuf_alloc (isa
);
8221 /* Decode the fixed instructions. */
8222 while (offset
< fragP
->fr_fix
)
8227 xtensa_insnbuf_from_chars
8228 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8229 fmt
= xtensa_format_decode (isa
, insnbuf
);
8230 if (fmt
== XTENSA_UNDEFINED
)
8233 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8235 xtensa_opcode opcode
=
8236 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8237 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8238 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8241 offset
+= xtensa_format_length (isa
, fmt
);
8247 /* Checks to be made after initial assembly but before relaxation. */
8249 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8250 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8253 xtensa_sanity_check (void)
8260 as_where (&file_name
, &line
);
8261 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8262 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8266 /* Walk over all of the fragments in a subsection. */
8267 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8269 if (fragP
->fr_type
== rs_machine_dependent
8270 && fragP
->fr_subtype
== RELAX_SLOTS
8271 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8273 static xtensa_insnbuf insnbuf
= NULL
;
8276 if (fragP
->fr_opcode
!= NULL
)
8279 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8280 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8281 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8283 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8284 t_insn
.opcode
) == 1)
8286 if (is_empty_loop (&t_insn
, fragP
))
8288 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8289 as_bad (_("invalid empty loop"));
8291 if (!is_local_forward_loop (&t_insn
, fragP
))
8293 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8294 as_bad (_("loop target does not follow "
8295 "loop instruction in section"));
8302 new_logical_line (file_name
, line
);
8306 #define LOOP_IMMED_OPN 1
8308 /* Return TRUE if the loop target is the next non-zero fragment. */
8311 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8313 const expressionS
*exp
;
8317 if (insn
->insn_type
!= ITYPE_INSN
)
8320 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8323 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8326 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8328 if (exp
->X_op
!= O_symbol
)
8331 symbolP
= exp
->X_add_symbol
;
8335 if (symbol_get_frag (symbolP
) == NULL
)
8338 if (S_GET_VALUE (symbolP
) != 0)
8341 /* Walk through the zero-size fragments from this one. If we find
8342 the target fragment, then this is a zero-size loop. */
8344 for (next_fragP
= fragP
->fr_next
;
8346 next_fragP
= next_fragP
->fr_next
)
8348 if (next_fragP
== symbol_get_frag (symbolP
))
8350 if (next_fragP
->fr_fix
!= 0)
8358 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8360 const expressionS
*exp
;
8364 if (insn
->insn_type
!= ITYPE_INSN
)
8367 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8370 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8373 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8375 if (exp
->X_op
!= O_symbol
)
8378 symbolP
= exp
->X_add_symbol
;
8382 if (symbol_get_frag (symbolP
) == NULL
)
8385 /* Walk through fragments until we find the target.
8386 If we do not find the target, then this is an invalid loop. */
8388 for (next_fragP
= fragP
->fr_next
;
8390 next_fragP
= next_fragP
->fr_next
)
8392 if (next_fragP
== symbol_get_frag (symbolP
))
8400 #define XTINFO_NAME "Xtensa_Info"
8401 #define XTINFO_NAMESZ 12
8402 #define XTINFO_TYPE 1
8405 xtensa_add_config_info (void)
8411 info_sec
= subseg_new (".xtensa.info", 0);
8412 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8414 data
= xmalloc (100);
8415 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8416 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8417 sz
= strlen (data
) + 1;
8419 /* Add enough null terminators to pad to a word boundary. */
8422 while ((sz
& 3) != 0);
8424 /* Follow the standard note section layout:
8425 First write the length of the name string. */
8427 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8429 /* Next comes the length of the "descriptor", i.e., the actual data. */
8431 md_number_to_chars (p
, (valueT
) sz
, 4);
8433 /* Write the note type. */
8435 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8437 /* Write the name field. */
8438 p
= frag_more (XTINFO_NAMESZ
);
8439 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8441 /* Finally, write the descriptor. */
8443 memcpy (p
, data
, sz
);
8449 /* Alignment Functions. */
8452 get_text_align_power (unsigned target_size
)
8454 if (target_size
<= 4)
8457 if (target_size
<= 8)
8460 if (target_size
<= 16)
8463 if (target_size
<= 32)
8466 if (target_size
<= 64)
8469 if (target_size
<= 128)
8472 if (target_size
<= 256)
8475 if (target_size
<= 512)
8478 if (target_size
<= 1024)
8487 get_text_align_max_fill_size (int align_pow
,
8488 bfd_boolean use_nops
,
8489 bfd_boolean use_no_density
)
8492 return (1 << align_pow
);
8494 return 3 * (1 << align_pow
);
8496 return 1 + (1 << align_pow
);
8500 /* Calculate the minimum bytes of fill needed at "address" to align a
8501 target instruction of size "target_size" so that it does not cross a
8502 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8503 the fill can be an arbitrary number of bytes. Otherwise, the space must
8504 be filled by NOP instructions. */
8507 get_text_align_fill_size (addressT address
,
8510 bfd_boolean use_nops
,
8511 bfd_boolean use_no_density
)
8513 addressT alignment
, fill
, fill_limit
, fill_step
;
8514 bfd_boolean skip_one
= FALSE
;
8516 alignment
= (1 << align_pow
);
8517 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8521 fill_limit
= alignment
;
8524 else if (!use_no_density
)
8526 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8527 fill_limit
= alignment
* 2;
8533 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8534 fill_limit
= alignment
* 3;
8538 /* Try all fill sizes until finding one that works. */
8539 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8541 if (skip_one
&& fill
== 1)
8543 if ((address
+ fill
) >> align_pow
8544 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8553 branch_align_power (segT sec
)
8555 /* If the Xtensa processor has a fetch width of X, and
8556 the section is aligned to at least that boundary, then a branch
8557 target need only fit within that aligned block of memory to avoid
8558 a stall. Otherwise, try to fit branch targets within 4-byte
8559 aligned blocks (which may be insufficient, e.g., if the section
8560 has no alignment, but it's good enough). */
8561 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8562 int sec_align
= get_recorded_alignment (sec
);
8564 if (sec_align
>= fetch_align
)
8571 /* This will assert if it is not possible. */
8574 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8580 gas_assert (fill_size
% 3 == 0);
8581 return (fill_size
/ 3);
8584 gas_assert (fill_size
!= 1); /* Bad argument. */
8586 while (fill_size
> 1)
8589 if (fill_size
== 2 || fill_size
== 4)
8591 fill_size
-= insn_size
;
8594 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8600 get_text_align_nth_nop_size (offsetT fill_size
,
8602 bfd_boolean use_no_density
)
8609 gas_assert (fill_size
!= 1); /* Bad argument. */
8611 while (fill_size
> 1)
8614 if (fill_size
== 2 || fill_size
== 4)
8616 fill_size
-= insn_size
;
8626 /* For the given fragment, find the appropriate address
8627 for it to begin at if we are using NOPs to align it. */
8630 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8632 /* The rule is: get next fragment's FIRST instruction. Find
8633 the smallest number of bytes that need to be added to
8634 ensure that the next fragment's FIRST instruction will fit
8637 E.G., 2 bytes : 0, 1, 2 mod 4
8640 If the FIRST instruction MIGHT be relaxed,
8641 assume that it will become a 3-byte instruction.
8643 Note again here that LOOP instructions are not bundleable,
8644 and this relaxation only applies to LOOP opcodes. */
8647 int first_insn_size
;
8649 addressT pre_opcode_bytes
;
8652 xtensa_opcode opcode
;
8653 bfd_boolean is_loop
;
8655 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8656 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8658 /* Find the loop frag. */
8659 first_insn
= next_non_empty_frag (fragP
);
8660 /* Now find the first insn frag. */
8661 first_insn
= next_non_empty_frag (first_insn
);
8663 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8664 gas_assert (is_loop
);
8665 loop_insn_size
= xg_get_single_size (opcode
);
8667 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8668 pre_opcode_bytes
+= loop_insn_size
;
8670 /* For loops, the alignment depends on the size of the
8671 instruction following the loop, not the LOOP instruction. */
8673 if (first_insn
== NULL
)
8674 first_insn_size
= xtensa_fetch_width
;
8676 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8678 /* If it was 8, then we'll need a larger alignment for the section. */
8679 align_power
= get_text_align_power (first_insn_size
);
8680 record_alignment (now_seg
, align_power
);
8682 fill_size
= get_text_align_fill_size
8683 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8684 fragP
->tc_frag_data
.is_no_density
);
8686 return address
+ fill_size
;
8690 /* 3 mechanisms for relaxing an alignment:
8692 Align to a power of 2.
8693 Align so the next fragment's instruction does not cross a word boundary.
8694 Align the current instruction so that if the next instruction
8695 were 3 bytes, it would not cross a word boundary.
8699 zeros - This is easy; always insert zeros.
8700 nops - 3-byte and 2-byte instructions
8704 >=5 : 3-byte instruction + fn (n-3)
8705 widening - widen previous instructions. */
8708 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8710 addressT target_address
, loop_insn_offset
;
8712 xtensa_opcode loop_opcode
;
8713 bfd_boolean is_loop
;
8716 offsetT branch_align
;
8719 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8720 switch (fragP
->fr_subtype
)
8722 case RELAX_DESIRE_ALIGN
:
8723 target_size
= next_frag_format_size (fragP
);
8724 if (target_size
== XTENSA_UNDEFINED
)
8726 align_power
= branch_align_power (now_seg
);
8727 branch_align
= 1 << align_power
;
8728 /* Don't count on the section alignment being as large as the target. */
8729 if (target_size
> branch_align
)
8730 target_size
= branch_align
;
8731 opt_diff
= get_text_align_fill_size (address
, align_power
,
8732 target_size
, FALSE
, FALSE
);
8734 *max_diff
= (opt_diff
+ branch_align
8735 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8736 gas_assert (*max_diff
>= opt_diff
);
8739 case RELAX_ALIGN_NEXT_OPCODE
:
8740 /* The next non-empty frag after this one holds the LOOP instruction
8741 that needs to be aligned. The required alignment depends on the
8742 size of the next non-empty frag after the loop frag, i.e., the
8743 first instruction in the loop. */
8744 loop_frag
= next_non_empty_frag (fragP
);
8745 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8746 loop_insn_offset
= 0;
8747 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8748 gas_assert (is_loop
);
8750 /* If the loop has been expanded then the LOOP instruction
8751 could be at an offset from this fragment. */
8752 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8753 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8755 /* In an ideal world, which is what we are shooting for here,
8756 we wouldn't need to use any NOPs immediately prior to the
8757 LOOP instruction. If this approach fails, relax_frag_loop_align
8758 will call get_noop_aligned_address. */
8760 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8761 align_power
= get_text_align_power (target_size
);
8762 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8763 target_size
, FALSE
, FALSE
);
8765 *max_diff
= xtensa_fetch_width
8766 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8767 - target_size
+ opt_diff
;
8768 gas_assert (*max_diff
>= opt_diff
);
8779 /* md_relax_frag Hook and Helper Functions. */
8781 static long relax_frag_loop_align (fragS
*, long);
8782 static long relax_frag_for_align (fragS
*, long);
8783 static long relax_frag_immed
8784 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8787 /* Return the number of bytes added to this fragment, given that the
8788 input has been stretched already by "stretch". */
8791 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8793 xtensa_isa isa
= xtensa_default_isa
;
8794 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8795 long new_stretch
= 0;
8799 static xtensa_insnbuf vbuf
= NULL
;
8800 int slot
, num_slots
;
8803 as_where (&file_name
, &line
);
8804 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8806 fragP
->tc_frag_data
.unreported_expansion
= 0;
8808 switch (fragP
->fr_subtype
)
8810 case RELAX_ALIGN_NEXT_OPCODE
:
8811 /* Always convert. */
8812 if (fragP
->tc_frag_data
.relax_seen
)
8813 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8816 case RELAX_LOOP_END
:
8820 case RELAX_LOOP_END_ADD_NOP
:
8821 /* Add a NOP and switch to .fill 0. */
8822 new_stretch
= relax_frag_add_nop (fragP
);
8826 case RELAX_DESIRE_ALIGN
:
8827 /* Do nothing. The narrowing before this frag will either align
8832 case RELAX_LITERAL_FINAL
:
8835 case RELAX_LITERAL_NR
:
8837 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8838 gas_assert (unreported
== lit_size
);
8839 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8840 fragP
->fr_var
-= lit_size
;
8841 fragP
->fr_fix
+= lit_size
;
8847 vbuf
= xtensa_insnbuf_alloc (isa
);
8849 xtensa_insnbuf_from_chars
8850 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8851 fmt
= xtensa_format_decode (isa
, vbuf
);
8852 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8854 for (slot
= 0; slot
< num_slots
; slot
++)
8856 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8859 if (fragP
->tc_frag_data
.relax_seen
)
8860 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8864 case RELAX_IMMED_STEP1
:
8865 case RELAX_IMMED_STEP2
:
8866 case RELAX_IMMED_STEP3
:
8867 /* Place the immediate. */
8868 new_stretch
+= relax_frag_immed
8869 (now_seg
, fragP
, stretch
,
8870 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8871 fmt
, slot
, stretched_p
, FALSE
);
8875 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8881 case RELAX_LITERAL_POOL_BEGIN
:
8882 case RELAX_LITERAL_POOL_END
:
8883 case RELAX_MAYBE_UNREACHABLE
:
8884 case RELAX_MAYBE_DESIRE_ALIGN
:
8885 /* No relaxation required. */
8888 case RELAX_FILL_NOP
:
8889 case RELAX_UNREACHABLE
:
8890 if (fragP
->tc_frag_data
.relax_seen
)
8891 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8894 case RELAX_TRAMPOLINE
:
8895 if (fragP
->tc_frag_data
.relax_seen
)
8897 segment_info_type
*seginfo
= seg_info (now_seg
);
8898 fragS
*fP
; /* The out-of-range jump. */
8901 /* Scan for jumps that will not reach. */
8902 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
8904 symbolS
*s
= fixP
->fx_addsy
;
8905 xtensa_opcode opcode
;
8910 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
8911 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
8913 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
8914 (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8916 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
8917 gas_assert (fmt
!= XTENSA_UNDEFINED
);
8918 slot
= fixP
->tc_fix_data
.slot
;
8919 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
8920 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
8921 if (opcode
!= xtensa_j_opcode
)
8923 target
= S_GET_VALUE (s
);
8924 addr
= fixP
->fx_frag
->fr_address
;
8925 delta
= target
- addr
+ stretch
;
8926 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
8927 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
8928 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
8929 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
8930 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
8931 int lower
= (target
< addr
) ? target
: addr
;
8932 int upper
= (target
> addr
) ? target
: addr
;
8933 int midpoint
= lower
+ (upper
- lower
) / 2;
8935 if ((upper
- lower
) > 2 * J_RANGE
)
8937 /* One trampoline won't suffice; we need multiple jumps.
8938 Jump to the trampoline that's farthest, but still in
8939 range relative to the original "j" instruction. */
8940 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
8942 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
8943 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
8948 if (this_addr
- addr
< J_RANGE
)
8953 /* Backward jump. */
8954 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
8961 struct trampoline_frag
*best_tf
= NULL
;
8964 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
8966 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
8967 int this_delta
= abs (this_addr
- midpoint
);
8969 if (!best_tf
|| this_delta
< best_delta
)
8972 best_delta
= this_delta
;
8977 if (tf
->fragP
== fragP
)
8979 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
8981 if (abs (addr
- trampaddr
) < J_RANGE
)
8982 { /* The trampoline is in range of original; fix it! */
8988 new_stretch
+= init_trampoline_frag (tf
);
8989 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
8990 lsym
= fragP
->fr_symbol
;
8992 /* Assemble a jump to the target label here. */
8994 insn
.insn_type
= ITYPE_INSN
;
8995 insn
.opcode
= xtensa_j_opcode
;
8997 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
8998 fmt
= xg_get_single_format (xtensa_j_opcode
);
8999 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9000 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9001 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9004 /* Add a fix-up for the original j insn. */
9005 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9006 newfixP
->fx_no_overflow
= 1;
9007 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9008 newfixP
->tc_fix_data
.X_add_number
= offset
;
9009 newfixP
->tc_fix_data
.slot
= slot
;
9010 /* Move the fix-up from the original j insn to this one. */
9011 fixP
->fx_frag
= fragP
;
9012 fixP
->fx_where
= fragP
->fr_fix
- 3;
9013 fixP
->tc_fix_data
.slot
= 0;
9014 /* Adjust the jump around this trampoline (if present). */
9015 if (tf
->fixP
!= NULL
)
9017 tf
->fixP
->fx_offset
+= 3;
9020 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9021 /* Do we have room for more? */
9022 if (fragP
->fr_var
< 3)
9023 { /* No, convert to fill. */
9025 fragP
->fr_subtype
= 0;
9026 /* Remove from the trampoline_list. */
9027 prev
->next
= tf
->next
;
9038 as_bad (_("bad relaxation state"));
9041 /* Tell gas we need another relaxation pass. */
9042 if (! fragP
->tc_frag_data
.relax_seen
)
9044 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9048 new_logical_line (file_name
, line
);
9054 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9056 addressT old_address
, old_next_address
, old_size
;
9057 addressT new_address
, new_next_address
, new_size
;
9060 /* All the frags with relax_frag_for_alignment prior to this one in the
9061 section have been done, hopefully eliminating the need for a NOP here.
9062 But, this will put it in if necessary. */
9064 /* Calculate the old address of this fragment and the next fragment. */
9065 old_address
= fragP
->fr_address
- stretch
;
9066 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9067 fragP
->tc_frag_data
.text_expansion
[0]);
9068 old_size
= old_next_address
- old_address
;
9070 /* Calculate the new address of this fragment and the next fragment. */
9071 new_address
= fragP
->fr_address
;
9073 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9074 new_size
= new_next_address
- new_address
;
9076 growth
= new_size
- old_size
;
9078 /* Fix up the text_expansion field and return the new growth. */
9079 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9084 /* Add a NOP instruction. */
9087 relax_frag_add_nop (fragS
*fragP
)
9089 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9090 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9091 assemble_nop (length
, nop_buf
);
9092 fragP
->tc_frag_data
.is_insn
= TRUE
;
9094 if (fragP
->fr_var
< length
)
9096 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9100 fragP
->fr_fix
+= length
;
9101 fragP
->fr_var
-= length
;
9106 static long future_alignment_required (fragS
*, long);
9109 relax_frag_for_align (fragS
*fragP
, long stretch
)
9111 /* Overview of the relaxation procedure for alignment:
9112 We can widen with NOPs or by widening instructions or by filling
9113 bytes after jump instructions. Find the opportune places and widen
9114 them if necessary. */
9119 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9120 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9121 || (fragP
->fr_subtype
== RELAX_SLOTS
9122 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9124 stretch_me
= future_alignment_required (fragP
, stretch
);
9125 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9131 /* We expanded on a previous pass. Can we shrink now? */
9132 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9133 if (shrink
<= stretch
&& stretch
> 0)
9135 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9141 /* Below here, diff > 0. */
9142 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9148 /* Return the address of the next frag that should be aligned.
9150 By "address" we mean the address it _would_ be at if there
9151 is no action taken to align it between here and the target frag.
9152 In other words, if no narrows and no fill nops are used between
9153 here and the frag to align, _even_if_ some of the frags we use
9154 to align targets have already expanded on a previous relaxation
9157 Also, count each frag that may be used to help align the target.
9159 Return 0 if there are no frags left in the chain that need to be
9163 find_address_of_next_align_frag (fragS
**fragPP
,
9167 bfd_boolean
*paddable
)
9169 fragS
*fragP
= *fragPP
;
9170 addressT address
= fragP
->fr_address
;
9172 /* Do not reset the counts to 0. */
9176 /* Limit this to a small search. */
9177 if (*widens
>= (int) xtensa_fetch_width
)
9182 address
+= fragP
->fr_fix
;
9184 if (fragP
->fr_type
== rs_fill
)
9185 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9186 else if (fragP
->fr_type
== rs_machine_dependent
)
9188 switch (fragP
->fr_subtype
)
9190 case RELAX_UNREACHABLE
:
9194 case RELAX_FILL_NOP
:
9196 if (!fragP
->tc_frag_data
.is_no_density
)
9201 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9206 address
+= total_frag_text_expansion (fragP
);
9210 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9213 case RELAX_ALIGN_NEXT_OPCODE
:
9214 case RELAX_DESIRE_ALIGN
:
9218 case RELAX_MAYBE_UNREACHABLE
:
9219 case RELAX_MAYBE_DESIRE_ALIGN
:
9224 /* Just punt if we don't know the type. */
9231 /* Just punt if we don't know the type. */
9235 fragP
= fragP
->fr_next
;
9243 static long bytes_to_stretch (fragS
*, int, int, int, int);
9246 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9248 fragS
*this_frag
= fragP
;
9252 int narrow_nops
= 0;
9253 bfd_boolean paddable
= FALSE
;
9254 offsetT local_opt_diff
;
9257 int stretch_amount
= 0;
9258 int local_stretch_amount
;
9259 int global_stretch_amount
;
9261 address
= find_address_of_next_align_frag
9262 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9266 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9267 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9269 frag_wane (this_frag
);
9273 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9274 opt_diff
= local_opt_diff
;
9275 gas_assert (opt_diff
>= 0);
9276 gas_assert (max_diff
>= opt_diff
);
9281 fragP
= fragP
->fr_next
;
9283 while (fragP
&& opt_diff
< max_diff
&& address
)
9285 /* We only use these to determine if we can exit early
9286 because there will be plenty of ways to align future
9288 int glob_widens
= 0;
9291 bfd_boolean glob_pad
= 0;
9292 address
= find_address_of_next_align_frag
9293 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9294 /* If there is a padable portion, then skip. */
9295 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9300 offsetT next_m_diff
;
9301 offsetT next_o_diff
;
9303 /* Downrange frags haven't had stretch added to them yet. */
9306 /* The address also includes any text expansion from this
9307 frag in a previous pass, but we don't want that. */
9308 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9310 /* Assume we are going to move at least opt_diff. In
9311 reality, we might not be able to, but assuming that
9312 we will helps catch cases where moving opt_diff pushes
9313 the next target from aligned to unaligned. */
9314 address
+= opt_diff
;
9316 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9318 /* Now cleanup for the adjustments to address. */
9319 next_o_diff
+= opt_diff
;
9320 next_m_diff
+= opt_diff
;
9321 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9322 opt_diff
= next_o_diff
;
9323 if (next_m_diff
< max_diff
)
9324 max_diff
= next_m_diff
;
9325 fragP
= fragP
->fr_next
;
9329 /* If there are enough wideners in between, do it. */
9332 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9334 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9339 local_stretch_amount
9340 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9341 num_widens
, local_opt_diff
);
9342 global_stretch_amount
9343 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9344 num_widens
, opt_diff
);
9345 /* If the condition below is true, then the frag couldn't
9346 stretch the correct amount for the global case, so we just
9347 optimize locally. We'll rely on the subsequent frags to get
9348 the correct alignment in the global case. */
9349 if (global_stretch_amount
< local_stretch_amount
)
9350 stretch_amount
= local_stretch_amount
;
9352 stretch_amount
= global_stretch_amount
;
9354 if (this_frag
->fr_subtype
== RELAX_SLOTS
9355 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9356 gas_assert (stretch_amount
<= 1);
9357 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9359 if (this_frag
->tc_frag_data
.is_no_density
)
9360 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9362 gas_assert (stretch_amount
<= 3);
9365 return stretch_amount
;
9369 /* The idea: widen everything you can to get a target or loop aligned,
9370 then start using NOPs.
9372 wide_nops = the number of wide NOPs available for aligning
9373 narrow_nops = the number of narrow NOPs available for aligning
9374 (a subset of wide_nops)
9375 widens = the number of narrow instructions that should be widened
9380 bytes_to_stretch (fragS
*this_frag
,
9389 int bytes_short
= desired_diff
- num_widens
;
9391 gas_assert (desired_diff
>= 0
9392 && desired_diff
< (signed) xtensa_fetch_width
);
9393 if (desired_diff
== 0)
9396 gas_assert (wide_nops
> 0 || num_widens
> 0);
9398 /* Always prefer widening to NOP-filling. */
9399 if (bytes_short
< 0)
9401 /* There are enough RELAX_NARROW frags after this one
9402 to align the target without widening this frag in any way. */
9406 if (bytes_short
== 0)
9408 /* Widen every narrow between here and the align target
9409 and the align target will be properly aligned. */
9410 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9416 /* From here we will need at least one NOP to get an alignment.
9417 However, we may not be able to align at all, in which case,
9419 nops_needed
= desired_diff
/ 3;
9421 /* If there aren't enough nops, don't widen. */
9422 if (nops_needed
> wide_nops
)
9425 /* First try it with all wide nops. */
9426 nop_bytes
= nops_needed
* 3;
9427 extra_bytes
= desired_diff
- nop_bytes
;
9429 if (nop_bytes
+ num_widens
>= desired_diff
)
9431 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9433 else if (num_widens
== extra_bytes
)
9438 /* Add a narrow nop. */
9442 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9445 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9447 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9448 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9449 else if (num_widens
== extra_bytes
)
9454 /* Replace a wide nop with a narrow nop--we can get here if
9455 extra_bytes was negative in the previous conditional. */
9456 if (narrow_nops
== 1)
9460 if (nop_bytes
+ num_widens
>= desired_diff
)
9462 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9463 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9464 else if (num_widens
== extra_bytes
)
9469 /* If we can't satisfy any of the above cases, then we can't align
9470 using padding or fill nops. */
9475 static struct trampoline_frag
*
9476 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9478 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9479 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9480 struct trampoline_frag
*best_tf
= NULL
;
9483 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9484 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9485 offsetT addr
= fragP
->fr_address
;
9486 offsetT lower
= (addr
< target
) ? addr
: target
;
9487 offsetT upper
= (addr
> target
) ? addr
: target
;
9488 int delta
= upper
- lower
;
9489 offsetT midpoint
= lower
+ delta
/ 2;
9490 int this_delta
= -1;
9493 if (delta
> 2 * J_RANGE
)
9495 /* One trampoline won't do; we need multiple.
9496 Choose the farthest trampoline that's still in range of the original
9497 and let a later pass finish the job. */
9498 for ( ; tf
; tf
= tf
->next
)
9500 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9502 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9506 if (this_addr
- addr
< J_RANGE
)
9511 /* Backward jump. */
9512 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9515 if (abs (addr
- this_addr
) < J_RANGE
)
9521 for ( ; tf
; tf
= tf
->next
)
9523 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9524 this_delta
= abs (this_addr
- midpoint
);
9525 if (unreachable_only
&& tf
->needs_jump_around
)
9527 if (!best_tf
|| this_delta
< best_delta
)
9530 best_delta
= this_delta
;
9531 best_addr
= this_addr
;
9536 best_delta
< J_RANGE
&&
9537 abs(best_addr
- lower
) < J_RANGE
&&
9538 abs(best_addr
- upper
) < J_RANGE
)
9541 return NULL
; /* No suitable trampoline found. */
9545 static struct trampoline_frag
*
9546 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9548 struct trampoline_frag
*tf
= NULL
;
9550 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9553 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9560 check_and_update_trampolines (void)
9562 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9563 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9564 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9566 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9568 if (tf
->fragP
->fr_var
< 3)
9570 frag_wane (tf
->fragP
);
9571 prev
->next
= tf
->next
;
9579 init_trampoline_frag (struct trampoline_frag
*trampP
)
9581 fragS
*fp
= trampP
->fragP
;
9584 if (fp
->fr_fix
== 0)
9587 char label
[10 + 2 * sizeof(fp
)];
9588 sprintf (label
, ".L0_TR_%p", fp
);
9590 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
9591 fp
->fr_symbol
= lsym
;
9592 if (trampP
->needs_jump_around
)
9594 /* Add a jump around this block of jumps, in case
9595 control flows into this block. */
9599 xtensa_isa isa
= xtensa_default_isa
;
9601 fp
->tc_frag_data
.is_insn
= 1;
9602 /* Assemble a jump insn. */
9604 insn
.insn_type
= ITYPE_INSN
;
9605 insn
.opcode
= xtensa_j_opcode
;
9607 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
9608 fmt
= xg_get_single_format (xtensa_j_opcode
);
9609 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9610 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9611 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
9615 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
9616 trampP
->fixP
= fixP
;
9624 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
9626 fragS
*tramp
= trampP
->fragP
;
9628 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
9634 xtensa_isa isa
= xtensa_default_isa
;
9637 lsym
= tramp
->fr_symbol
;
9638 /* Assemble a jump to the target label in the trampoline frag. */
9639 tsym
= origfrag
->tc_frag_data
.slot_symbols
[0];
9640 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[0];
9642 insn
.insn_type
= ITYPE_INSN
;
9643 insn
.opcode
= xtensa_j_opcode
;
9645 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
9646 fmt
= xg_get_single_format (xtensa_j_opcode
);
9647 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9648 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9649 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
9653 /* add a fix-up for the trampoline jump. */
9654 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
9655 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
9656 fixP
= trampP
->fixP
;
9658 fixP
->fx_offset
+= 3;
9659 /* Modify the original j to point here. */
9660 origfrag
->tc_frag_data
.slot_symbols
[0] = lsym
;
9661 origfrag
->tc_frag_data
.slot_offsets
[0] = tramp
->fr_fix
- 3;
9662 /* If trampoline is full, remove it from the list. */
9663 check_and_update_trampolines ();
9670 relax_frag_immed (segT segP
,
9677 bfd_boolean estimate_only
)
9681 bfd_boolean negatable_branch
= FALSE
;
9682 bfd_boolean branch_jmp_to_next
= FALSE
;
9683 bfd_boolean from_wide_insn
= FALSE
;
9684 xtensa_isa isa
= xtensa_default_isa
;
9686 offsetT frag_offset
;
9688 int num_text_bytes
, num_literal_bytes
;
9689 int literal_diff
, total_text_diff
, this_text_diff
;
9691 gas_assert (fragP
->fr_opcode
!= NULL
);
9693 xg_clear_vinsn (&cur_vinsn
);
9694 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9695 if (cur_vinsn
.num_slots
> 1)
9696 from_wide_insn
= TRUE
;
9698 tinsn
= cur_vinsn
.slots
[slot
];
9699 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9701 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9704 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9705 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9707 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9709 old_size
= xtensa_format_length (isa
, fmt
);
9711 /* Special case: replace a branch to the next instruction with a NOP.
9712 This is required to work around a hardware bug in T1040.0 and also
9713 serves as an optimization. */
9715 if (branch_jmp_to_next
9716 && ((old_size
== 2) || (old_size
== 3))
9717 && !next_frag_is_loop_target (fragP
))
9720 /* Here is the fun stuff: Get the immediate field from this
9721 instruction. If it fits, we are done. If not, find the next
9722 instruction sequence that fits. */
9724 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9725 istack_init (&istack
);
9726 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9727 min_steps
, stretch
);
9728 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9730 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9732 /* Figure out the number of bytes needed. */
9733 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9735 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9736 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9741 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9744 num_text_bytes
+= old_size
;
9745 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9746 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9749 /* The first instruction in the relaxed sequence will go after
9750 the current wide instruction, and thus its symbolic immediates
9753 istack_init (&istack
);
9754 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9755 frag_offset
+ old_size
,
9756 min_steps
, stretch
+ old_size
);
9757 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9759 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9760 = (int) RELAX_IMMED
+ num_steps
;
9762 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9764 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9766 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9770 total_text_diff
= num_text_bytes
- old_size
;
9771 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9773 /* It MUST get larger. If not, we could get an infinite loop. */
9774 gas_assert (num_text_bytes
>= 0);
9775 gas_assert (literal_diff
>= 0);
9776 gas_assert (total_text_diff
>= 0);
9778 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9779 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9780 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9781 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9783 /* Find the associated expandable literal for this. */
9784 if (literal_diff
!= 0)
9786 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9789 gas_assert (literal_diff
== 4);
9790 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9792 /* We expect that the literal section state has NOT been
9794 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9795 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9796 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9798 /* We need to mark this section for another iteration
9804 if (negatable_branch
&& istack
.ninsn
> 1)
9805 update_next_frag_state (fragP
);
9807 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
9808 if (istack
.ninsn
> 2 &&
9809 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
9810 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
9811 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
9813 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
9815 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
9817 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
9821 this_text_diff
+= init_trampoline_frag (tf
);
9822 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
9826 /* If target symbol is undefined, assume it will reach once linked. */
9827 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
9829 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
9831 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9832 _("jump target out of range; no usable trampoline found"));
9838 return this_text_diff
;
9842 /* md_convert_frag Hook and Helper Functions. */
9844 static void convert_frag_align_next_opcode (fragS
*);
9845 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9846 static void convert_frag_fill_nop (fragS
*);
9847 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9850 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9852 static xtensa_insnbuf vbuf
= NULL
;
9853 xtensa_isa isa
= xtensa_default_isa
;
9860 as_where (&file_name
, &line
);
9861 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9863 switch (fragp
->fr_subtype
)
9865 case RELAX_ALIGN_NEXT_OPCODE
:
9866 /* Always convert. */
9867 convert_frag_align_next_opcode (fragp
);
9870 case RELAX_DESIRE_ALIGN
:
9871 /* Do nothing. If not aligned already, too bad. */
9875 case RELAX_LITERAL_FINAL
:
9880 vbuf
= xtensa_insnbuf_alloc (isa
);
9882 xtensa_insnbuf_from_chars
9883 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9884 fmt
= xtensa_format_decode (isa
, vbuf
);
9885 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9887 for (slot
= 0; slot
< num_slots
; slot
++)
9889 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9892 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9896 case RELAX_IMMED_STEP1
:
9897 case RELAX_IMMED_STEP2
:
9898 case RELAX_IMMED_STEP3
:
9899 /* Place the immediate. */
9902 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9907 /* This is OK because some slots could have
9908 relaxations and others have none. */
9914 case RELAX_UNREACHABLE
:
9915 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9916 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9917 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9921 case RELAX_MAYBE_UNREACHABLE
:
9922 case RELAX_MAYBE_DESIRE_ALIGN
:
9926 case RELAX_FILL_NOP
:
9927 convert_frag_fill_nop (fragp
);
9930 case RELAX_LITERAL_NR
:
9931 if (use_literal_section
)
9933 /* This should have been handled during relaxation. When
9934 relaxing a code segment, literals sometimes need to be
9935 added to the corresponding literal segment. If that
9936 literal segment has already been relaxed, then we end up
9937 in this situation. Marking the literal segments as data
9938 would make this happen less often (since GAS always relaxes
9939 code before data), but we could still get into trouble if
9940 there are instructions in a segment that is not marked as
9941 containing code. Until we can implement a better solution,
9942 cheat and adjust the addresses of all the following frags.
9943 This could break subsequent alignments, but the linker's
9944 literal coalescing will do that anyway. */
9947 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9948 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9949 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9952 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9956 as_bad (_("invalid relaxation fragment result"));
9959 case RELAX_TRAMPOLINE
:
9964 new_logical_line (file_name
, line
);
9969 convert_frag_align_next_opcode (fragS
*fragp
)
9971 char *nop_buf
; /* Location for Writing. */
9972 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9973 addressT aligned_address
;
9977 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9979 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9980 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9981 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9983 for (nop
= 0; nop
< nop_count
; nop
++)
9986 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9988 assemble_nop (nop_size
, nop_buf
);
9989 nop_buf
+= nop_size
;
9992 fragp
->fr_fix
+= fill_size
;
9993 fragp
->fr_var
-= fill_size
;
9998 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10000 TInsn tinsn
, single_target
;
10001 int size
, old_size
, diff
;
10002 offsetT frag_offset
;
10004 gas_assert (slot
== 0);
10005 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10007 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10009 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10010 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10011 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10016 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10018 /* No conversion. */
10023 gas_assert (fragP
->fr_opcode
!= NULL
);
10025 /* Frags in this relaxation state should only contain
10026 single instruction bundles. */
10027 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10029 /* Just convert it to a wide form.... */
10031 old_size
= xg_get_single_size (tinsn
.opcode
);
10033 tinsn_init (&single_target
);
10034 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10036 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10038 as_bad (_("unable to widen instruction"));
10042 size
= xg_get_single_size (single_target
.opcode
);
10043 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10044 frag_offset
, TRUE
);
10046 diff
= size
- old_size
;
10047 gas_assert (diff
>= 0);
10048 gas_assert (diff
<= fragP
->fr_var
);
10049 fragP
->fr_var
-= diff
;
10050 fragP
->fr_fix
+= diff
;
10058 convert_frag_fill_nop (fragS
*fragP
)
10060 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10061 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10062 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10063 - fragP
->fr_address
- fragP
->fr_fix
));
10066 /* No conversion. */
10070 assemble_nop (size
, loc
);
10071 fragP
->tc_frag_data
.is_insn
= TRUE
;
10072 fragP
->fr_var
-= size
;
10073 fragP
->fr_fix
+= size
;
10078 static fixS
*fix_new_exp_in_seg
10079 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10080 bfd_reloc_code_real_type
);
10081 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10084 convert_frag_immed (segT segP
,
10090 char *immed_instr
= fragP
->fr_opcode
;
10092 bfd_boolean expanded
= FALSE
;
10093 bfd_boolean branch_jmp_to_next
= FALSE
;
10094 char *fr_opcode
= fragP
->fr_opcode
;
10095 xtensa_isa isa
= xtensa_default_isa
;
10096 bfd_boolean from_wide_insn
= FALSE
;
10098 bfd_boolean is_loop
;
10100 gas_assert (fr_opcode
!= NULL
);
10102 xg_clear_vinsn (&cur_vinsn
);
10104 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10105 if (cur_vinsn
.num_slots
> 1)
10106 from_wide_insn
= TRUE
;
10108 orig_tinsn
= cur_vinsn
.slots
[slot
];
10109 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10111 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10113 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10114 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10116 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10118 /* Conversion just inserts a NOP and marks the fix as completed. */
10119 bytes
= xtensa_format_length (isa
, fmt
);
10122 cur_vinsn
.slots
[slot
].opcode
=
10123 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10124 cur_vinsn
.slots
[slot
].ntok
= 0;
10128 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10129 gas_assert (bytes
== 2 || bytes
== 3);
10130 build_nop (&cur_vinsn
.slots
[0], bytes
);
10131 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10133 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10134 xtensa_insnbuf_to_chars
10135 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10140 /* Here is the fun stuff: Get the immediate field from this
10141 instruction. If it fits, we're done. If not, find the next
10142 instruction sequence that fits. */
10146 symbolS
*lit_sym
= NULL
;
10147 int total_size
= 0;
10148 int target_offset
= 0;
10151 symbolS
*gen_label
= NULL
;
10152 offsetT frag_offset
;
10153 bfd_boolean first
= TRUE
;
10155 /* It does not fit. Find something that does and
10156 convert immediately. */
10157 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10158 istack_init (&istack
);
10159 xg_assembly_relax (&istack
, &orig_tinsn
,
10160 segP
, fragP
, frag_offset
, min_steps
, 0);
10162 old_size
= xtensa_format_length (isa
, fmt
);
10164 /* Assemble this right inline. */
10166 /* First, create the mapping from a label name to the REAL label. */
10168 for (i
= 0; i
< istack
.ninsn
; i
++)
10170 TInsn
*tinsn
= &istack
.insn
[i
];
10173 switch (tinsn
->insn_type
)
10175 case ITYPE_LITERAL
:
10176 if (lit_sym
!= NULL
)
10177 as_bad (_("multiple literals in expansion"));
10178 /* First find the appropriate space in the literal pool. */
10179 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10180 if (lit_frag
== NULL
)
10181 as_bad (_("no registered fragment for literal"));
10182 if (tinsn
->ntok
!= 1)
10183 as_bad (_("number of literal tokens != 1"));
10185 /* Set the literal symbol and add a fixup. */
10186 lit_sym
= lit_frag
->fr_symbol
;
10190 if (align_targets
&& !is_loop
)
10192 fragS
*unreach
= fragP
->fr_next
;
10193 while (!(unreach
->fr_type
== rs_machine_dependent
10194 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10195 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10197 unreach
= unreach
->fr_next
;
10200 gas_assert (unreach
->fr_type
== rs_machine_dependent
10201 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10202 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10204 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10206 gas_assert (gen_label
== NULL
);
10207 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10208 fr_opcode
- fragP
->fr_literal
10209 + target_offset
, fragP
);
10213 if (first
&& from_wide_insn
)
10215 target_offset
+= xtensa_format_length (isa
, fmt
);
10217 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10218 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10221 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10228 for (i
= 0; i
< istack
.ninsn
; i
++)
10230 TInsn
*tinsn
= &istack
.insn
[i
];
10234 bfd_reloc_code_real_type reloc_type
;
10236 switch (tinsn
->insn_type
)
10238 case ITYPE_LITERAL
:
10239 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10240 /* Already checked. */
10241 gas_assert (lit_frag
!= NULL
);
10242 gas_assert (lit_sym
!= NULL
);
10243 gas_assert (tinsn
->ntok
== 1);
10245 target_seg
= S_GET_SEGMENT (lit_sym
);
10246 gas_assert (target_seg
);
10247 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10248 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10249 &tinsn
->tok
[0], FALSE
, reloc_type
);
10256 xg_resolve_labels (tinsn
, gen_label
);
10257 xg_resolve_literals (tinsn
, lit_sym
);
10258 if (from_wide_insn
&& first
)
10261 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10263 cur_vinsn
.slots
[slot
] = *tinsn
;
10267 cur_vinsn
.slots
[slot
].opcode
=
10268 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10269 cur_vinsn
.slots
[slot
].ntok
= 0;
10271 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10272 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10273 (unsigned char *) immed_instr
, 0);
10274 fragP
->tc_frag_data
.is_insn
= TRUE
;
10275 size
= xtensa_format_length (isa
, fmt
);
10276 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10278 xg_emit_insn_to_buf
10279 (tinsn
, immed_instr
+ size
, fragP
,
10280 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10281 size
+= xg_get_single_size (tinsn
->opcode
);
10286 size
= xg_get_single_size (tinsn
->opcode
);
10287 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10288 immed_instr
- fragP
->fr_literal
, TRUE
);
10290 immed_instr
+= size
;
10291 total_size
+= size
;
10296 diff
= total_size
- old_size
;
10297 gas_assert (diff
>= 0);
10300 gas_assert (diff
<= fragP
->fr_var
);
10301 fragP
->fr_var
-= diff
;
10302 fragP
->fr_fix
+= diff
;
10305 /* Check for undefined immediates in LOOP instructions. */
10309 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10310 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10312 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10315 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10316 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10318 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10323 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10324 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10326 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10328 /* Add an expansion note on the expanded instruction. */
10329 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10330 &orig_tinsn
.tok
[0], TRUE
,
10331 BFD_RELOC_XTENSA_ASM_EXPAND
);
10336 /* Add a new fix expression into the desired segment. We have to
10337 switch to that segment to do this. */
10340 fix_new_exp_in_seg (segT new_seg
,
10341 subsegT new_subseg
,
10347 bfd_reloc_code_real_type r_type
)
10350 segT seg
= now_seg
;
10351 subsegT subseg
= now_subseg
;
10353 gas_assert (new_seg
!= 0);
10354 subseg_set (new_seg
, new_subseg
);
10356 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10357 subseg_set (seg
, subseg
);
10362 /* Relax a loop instruction so that it can span loop >256 bytes.
10368 addi as, as, lo8 (label-.L1)
10369 addmi as, as, mid8 (label-.L1)
10380 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10385 unsigned long target
;
10386 static xtensa_insnbuf insnbuf
= NULL
;
10387 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10388 xtensa_isa isa
= xtensa_default_isa
;
10389 addressT loop_offset
;
10390 addressT addi_offset
= 9;
10391 addressT addmi_offset
= 12;
10396 insnbuf
= xtensa_insnbuf_alloc (isa
);
10398 /* Get the loop offset. */
10399 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10401 /* Validate that there really is a LOOP at the loop_offset. Because
10402 loops are not bundleable, we can assume that the instruction will be
10404 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10405 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10407 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10408 addi_offset
+= loop_offset
;
10409 addmi_offset
+= loop_offset
;
10411 gas_assert (tinsn
->ntok
== 2);
10412 if (tinsn
->tok
[1].X_op
== O_constant
)
10413 target
= tinsn
->tok
[1].X_add_number
;
10414 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10416 /* Find the fragment. */
10417 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10418 gas_assert (S_GET_SEGMENT (sym
) == segP
10419 || S_GET_SEGMENT (sym
) == absolute_section
);
10420 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10424 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10428 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10429 loop_length_hi
= loop_length
& ~0x0ff;
10430 loop_length_lo
= loop_length
& 0x0ff;
10431 if (loop_length_lo
>= 128)
10433 loop_length_lo
-= 256;
10434 loop_length_hi
+= 256;
10437 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10438 32512. If the loop is larger than that, then we just fail. */
10439 if (loop_length_hi
> 32512)
10440 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10441 _("loop too long for LOOP instruction"));
10443 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10444 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10446 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10447 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10449 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10450 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10452 fragP
->tc_frag_data
.is_insn
= TRUE
;
10453 xtensa_insnbuf_to_chars
10454 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10456 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10457 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10458 xtensa_insnbuf_to_chars
10459 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10461 /* Walk through all of the frags from here to the loop end
10462 and mark them as no_transform to keep them from being modified
10463 by the linker. If we ever have a relocation for the
10464 addi/addmi of the difference of two symbols we can remove this. */
10467 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10468 next_fragP
= next_fragP
->fr_next
)
10470 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10471 if (next_fragP
->tc_frag_data
.is_loop_target
)
10473 if (target_count
== 2)
10479 /* A map that keeps information on a per-subsegment basis. This is
10480 maintained during initial assembly, but is invalid once the
10481 subsegments are smashed together. I.E., it cannot be used during
10484 typedef struct subseg_map_struct
10492 float total_freq
; /* fall-through + branch target frequency */
10493 float target_freq
; /* branch target frequency alone */
10495 struct subseg_map_struct
*next
;
10499 static subseg_map
*sseg_map
= NULL
;
10501 static subseg_map
*
10502 get_subseg_info (segT seg
, subsegT subseg
)
10504 subseg_map
*subseg_e
;
10506 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10508 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10515 static subseg_map
*
10516 add_subseg_info (segT seg
, subsegT subseg
)
10518 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
10519 memset (subseg_e
, 0, sizeof (subseg_map
));
10520 subseg_e
->seg
= seg
;
10521 subseg_e
->subseg
= subseg
;
10522 subseg_e
->flags
= 0;
10523 /* Start off considering every branch target very important. */
10524 subseg_e
->target_freq
= 1.0;
10525 subseg_e
->total_freq
= 1.0;
10526 subseg_e
->next
= sseg_map
;
10527 sseg_map
= subseg_e
;
10533 get_last_insn_flags (segT seg
, subsegT subseg
)
10535 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10537 return subseg_e
->flags
;
10543 set_last_insn_flags (segT seg
,
10548 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10550 subseg_e
= add_subseg_info (seg
, subseg
);
10552 subseg_e
->flags
|= fl
;
10554 subseg_e
->flags
&= ~fl
;
10559 get_subseg_total_freq (segT seg
, subsegT subseg
)
10561 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10563 return subseg_e
->total_freq
;
10569 get_subseg_target_freq (segT seg
, subsegT subseg
)
10571 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10573 return subseg_e
->target_freq
;
10579 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10581 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10583 subseg_e
= add_subseg_info (seg
, subseg
);
10584 subseg_e
->total_freq
= total_f
;
10585 subseg_e
->target_freq
= target_f
;
10589 /* Segment Lists and emit_state Stuff. */
10592 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10597 segT literal_section
= head
->seg
;
10599 /* Move the literal section to the front of the section list. */
10600 gas_assert (literal_section
);
10601 if (literal_section
!= stdoutput
->sections
)
10603 bfd_section_list_remove (stdoutput
, literal_section
);
10604 bfd_section_list_prepend (stdoutput
, literal_section
);
10611 static void mark_literal_frags (seg_list
*);
10614 xtensa_move_literals (void)
10617 frchainS
*frchain_from
, *frchain_to
;
10618 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
10619 fragS
**frag_splice
;
10622 fixS
*fix
, *next_fix
, **fix_splice
;
10625 mark_literal_frags (literal_head
->next
);
10627 if (use_literal_section
)
10630 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10632 /* Keep the literals for .init and .fini in separate sections. */
10633 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10634 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10637 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10638 search_frag
= frchain_from
->frch_root
;
10639 literal_pool
= NULL
;
10641 frag_splice
= &(frchain_from
->frch_root
);
10643 while (!search_frag
->tc_frag_data
.literal_frag
)
10645 gas_assert (search_frag
->fr_fix
== 0
10646 || search_frag
->fr_type
== rs_align
);
10647 search_frag
= search_frag
->fr_next
;
10650 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10651 == RELAX_LITERAL_POOL_BEGIN
);
10652 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10654 /* Make sure that all the frags in this series are closed, and
10655 that there is at least one left over of zero-size. This
10656 prevents us from making a segment with an frchain without any
10658 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10659 xtensa_set_frag_assembly_state (frag_now
);
10660 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10661 xtensa_set_frag_assembly_state (frag_now
);
10663 while (search_frag
!= frag_now
)
10665 next_frag
= search_frag
->fr_next
;
10667 /* First, move the frag out of the literal section and
10668 to the appropriate place. */
10669 if (search_frag
->tc_frag_data
.literal_frag
)
10671 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10672 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10673 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10674 gas_assert (frchain_to
);
10676 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10677 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10679 *frag_splice
= next_frag
;
10680 search_frag
->fr_next
= insert_after
->fr_next
;
10681 insert_after
->fr_next
= search_frag
;
10682 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10683 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10685 /* Now move any fixups associated with this frag to the
10687 fix
= frchain_from
->fix_root
;
10688 fix_splice
= &(frchain_from
->fix_root
);
10691 next_fix
= fix
->fx_next
;
10692 if (fix
->fx_frag
== search_frag
)
10694 *fix_splice
= next_fix
;
10695 fix
->fx_next
= frchain_to
->fix_root
;
10696 frchain_to
->fix_root
= fix
;
10697 if (frchain_to
->fix_tail
== NULL
)
10698 frchain_to
->fix_tail
= fix
;
10701 fix_splice
= &(fix
->fx_next
);
10704 search_frag
= next_frag
;
10707 if (frchain_from
->fix_root
!= NULL
)
10709 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10710 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10712 gas_assert (frchain_from
->fix_root
== NULL
);
10714 frchain_from
->fix_tail
= NULL
;
10715 xtensa_restore_emit_state (&state
);
10718 /* Now fix up the SEGMENT value for all the literal symbols. */
10719 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10721 symbolS
*lit_sym
= lit
->sym
;
10722 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10724 S_SET_SEGMENT (lit_sym
, dseg
);
10729 /* Walk over all the frags for segments in a list and mark them as
10730 containing literals. As clunky as this is, we can't rely on frag_var
10731 and frag_variant to get called in all situations. */
10734 mark_literal_frags (seg_list
*segment
)
10736 frchainS
*frchain_from
;
10737 fragS
*search_frag
;
10741 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10742 search_frag
= frchain_from
->frch_root
;
10743 while (search_frag
)
10745 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10746 search_frag
= search_frag
->fr_next
;
10748 segment
= segment
->next
;
10754 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10756 /* Move all of the sections in the section list to come
10757 after "after" in the gnu segment list. */
10762 segT literal_section
= head
->seg
;
10764 /* Move the literal section after "after". */
10765 gas_assert (literal_section
);
10766 if (literal_section
!= after
)
10768 bfd_section_list_remove (stdoutput
, literal_section
);
10769 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10777 /* Push all the literal segments to the end of the gnu list. */
10780 xtensa_reorder_segments (void)
10787 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10793 /* Now that we have the last section, push all the literal
10794 sections to the end. */
10795 xtensa_reorder_seg_list (literal_head
, last_sec
);
10797 /* Now perform the final error check. */
10798 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10800 gas_assert (new_count
== old_count
);
10804 /* Change the emit state (seg, subseg, and frag related stuff) to the
10805 correct location. Return a emit_state which can be passed to
10806 xtensa_restore_emit_state to return to current fragment. */
10809 xtensa_switch_to_literal_fragment (emit_state
*result
)
10811 if (directive_state
[directive_absolute_literals
])
10813 segT lit4_seg
= cache_literal_section (TRUE
);
10814 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10817 xtensa_switch_to_non_abs_literal_fragment (result
);
10819 /* Do a 4-byte align here. */
10820 frag_align (2, 0, 0);
10821 record_alignment (now_seg
, 2);
10826 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10828 static bfd_boolean recursive
= FALSE
;
10829 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10831 bfd_boolean is_init
=
10832 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10833 bfd_boolean is_fini
=
10834 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10836 if (pool_location
== NULL
10837 && !use_literal_section
10839 && !is_init
&& ! is_fini
)
10841 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10843 /* When we mark a literal pool location, we want to put a frag in
10844 the literal pool that points to it. But to do that, we want to
10845 switch_to_literal_fragment. But literal sections don't have
10846 literal pools, so their location is always null, so we would
10847 recurse forever. This is kind of hacky, but it works. */
10850 xtensa_mark_literal_pool_location ();
10854 lit_seg
= cache_literal_section (FALSE
);
10855 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10857 if (!use_literal_section
10858 && !is_init
&& !is_fini
10859 && get_literal_pool_location (now_seg
) != pool_location
)
10861 /* Close whatever frag is there. */
10862 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10863 xtensa_set_frag_assembly_state (frag_now
);
10864 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10865 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10866 xtensa_set_frag_assembly_state (frag_now
);
10871 /* Call this function before emitting data into the literal section.
10872 This is a helper function for xtensa_switch_to_literal_fragment.
10873 This is similar to a .section new_now_seg subseg. */
10876 xtensa_switch_section_emit_state (emit_state
*state
,
10878 subsegT new_now_subseg
)
10880 state
->name
= now_seg
->name
;
10881 state
->now_seg
= now_seg
;
10882 state
->now_subseg
= now_subseg
;
10883 state
->generating_literals
= generating_literals
;
10884 generating_literals
++;
10885 subseg_set (new_now_seg
, new_now_subseg
);
10889 /* Use to restore the emitting into the normal place. */
10892 xtensa_restore_emit_state (emit_state
*state
)
10894 generating_literals
= state
->generating_literals
;
10895 subseg_set (state
->now_seg
, state
->now_subseg
);
10899 /* Predicate function used to look up a section in a particular group. */
10902 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10904 const char *gname
= inf
;
10905 const char *group_name
= elf_group_name (sec
);
10907 return (group_name
== gname
10908 || (group_name
!= NULL
10910 && strcmp (group_name
, gname
) == 0));
10914 /* Get the literal section to be used for the current text section.
10915 The result may be cached in the default_lit_sections structure. */
10918 cache_literal_section (bfd_boolean use_abs_literals
)
10920 const char *text_name
, *group_name
= 0;
10921 char *base_name
, *name
, *suffix
;
10923 segT seg
, current_section
;
10924 int current_subsec
;
10925 bfd_boolean linkonce
= FALSE
;
10927 /* Save the current section/subsection. */
10928 current_section
= now_seg
;
10929 current_subsec
= now_subseg
;
10931 /* Clear the cached values if they are no longer valid. */
10932 if (now_seg
!= default_lit_sections
.current_text_seg
)
10934 default_lit_sections
.current_text_seg
= now_seg
;
10935 default_lit_sections
.lit_seg
= NULL
;
10936 default_lit_sections
.lit4_seg
= NULL
;
10939 /* Check if the literal section is already cached. */
10940 if (use_abs_literals
)
10941 pcached
= &default_lit_sections
.lit4_seg
;
10943 pcached
= &default_lit_sections
.lit_seg
;
10948 text_name
= default_lit_sections
.lit_prefix
;
10949 if (! text_name
|| ! *text_name
)
10951 text_name
= segment_name (current_section
);
10952 group_name
= elf_group_name (current_section
);
10953 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10956 base_name
= use_abs_literals
? ".lit4" : ".literal";
10959 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10960 sprintf (name
, "%s.%s", base_name
, group_name
);
10962 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10964 suffix
= strchr (text_name
+ linkonce_len
, '.');
10966 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10967 + (suffix
? strlen (suffix
) : 0));
10968 strcpy (name
, ".gnu.linkonce");
10969 strcat (name
, base_name
);
10971 strcat (name
, suffix
);
10976 /* If the section name begins or ends with ".text", then replace
10977 that portion instead of appending an additional suffix. */
10978 size_t len
= strlen (text_name
);
10980 && (strcmp (text_name
+ len
- 5, ".text") == 0
10981 || strncmp (text_name
, ".text", 5) == 0))
10984 name
= xmalloc (len
+ strlen (base_name
) + 1);
10985 if (strncmp (text_name
, ".text", 5) == 0)
10987 strcpy (name
, base_name
);
10988 strcat (name
, text_name
+ 5);
10992 strcpy (name
, text_name
);
10993 strcpy (name
+ len
, base_name
);
10997 /* Canonicalize section names to allow renaming literal sections.
10998 The group name, if any, came from the current text section and
10999 has already been canonicalized. */
11000 name
= tc_canonicalize_symbol_name (name
);
11002 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11003 (void *) group_name
);
11008 seg
= subseg_force_new (name
, 0);
11010 if (! use_abs_literals
)
11012 /* Add the newly created literal segment to the list. */
11013 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
11015 n
->next
= literal_head
->next
;
11016 literal_head
->next
= n
;
11019 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11020 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11021 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11023 elf_group_name (seg
) = group_name
;
11025 bfd_set_section_flags (stdoutput
, seg
, flags
);
11026 bfd_set_section_alignment (stdoutput
, seg
, 2);
11030 subseg_set (current_section
, current_subsec
);
11035 /* Property Tables Stuff. */
11037 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11038 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11039 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11041 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11042 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11044 static bfd_boolean
get_frag_is_literal (const fragS
*);
11045 static void xtensa_create_property_segments
11046 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11047 static void xtensa_create_xproperty_segments
11048 (frag_flags_fn
, const char *, xt_section_type
);
11049 static bfd_boolean
exclude_section_from_property_tables (segT
);
11050 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11051 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11052 static void add_xt_block_frags
11053 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11054 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11055 static void xtensa_frag_flags_init (frag_flags
*);
11056 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11057 static flagword
frag_flags_to_number (const frag_flags
*);
11058 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11060 /* Set up property tables after relaxation. */
11063 xtensa_post_relax_hook (void)
11065 xtensa_move_seg_list_to_beginning (literal_head
);
11067 xtensa_find_unmarked_state_frags ();
11068 xtensa_mark_frags_for_org ();
11069 xtensa_mark_difference_of_two_symbols ();
11071 xtensa_create_property_segments (get_frag_is_literal
,
11073 XTENSA_LIT_SEC_NAME
,
11075 xtensa_create_xproperty_segments (get_frag_property_flags
,
11076 XTENSA_PROP_SEC_NAME
,
11079 if (warn_unaligned_branch_targets
)
11080 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11081 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11085 /* This function is only meaningful after xtensa_move_literals. */
11088 get_frag_is_literal (const fragS
*fragP
)
11090 gas_assert (fragP
!= NULL
);
11091 return fragP
->tc_frag_data
.is_literal
;
11096 xtensa_create_property_segments (frag_predicate property_function
,
11097 frag_predicate end_property_function
,
11098 const char *section_name_base
,
11099 xt_section_type sec_type
)
11103 /* Walk over all of the current segments.
11104 Walk over each fragment
11105 For each non-empty fragment,
11106 Build a property record (append where possible). */
11108 for (seclist
= &stdoutput
->sections
;
11109 seclist
&& *seclist
;
11110 seclist
= &(*seclist
)->next
)
11112 segT sec
= *seclist
;
11114 if (exclude_section_from_property_tables (sec
))
11117 if (section_has_property (sec
, property_function
))
11119 segment_info_type
*xt_seg_info
;
11120 xtensa_block_info
**xt_blocks
;
11121 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11123 prop_sec
->output_section
= prop_sec
;
11124 subseg_set (prop_sec
, 0);
11125 xt_seg_info
= seg_info (prop_sec
);
11126 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11128 /* Walk over all of the frchains here and add new sections. */
11129 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11130 end_property_function
);
11134 /* Now we fill them out.... */
11136 for (seclist
= &stdoutput
->sections
;
11137 seclist
&& *seclist
;
11138 seclist
= &(*seclist
)->next
)
11140 segment_info_type
*seginfo
;
11141 xtensa_block_info
*block
;
11142 segT sec
= *seclist
;
11144 seginfo
= seg_info (sec
);
11145 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11149 xtensa_block_info
*cur_block
;
11151 bfd_size_type rec_size
;
11153 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11156 rec_size
= num_recs
* 8;
11157 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11164 subseg_set (sec
, 0);
11165 frag_data
= frag_more (rec_size
);
11167 for (i
= 0; i
< num_recs
; i
++)
11171 /* Write the fixup. */
11172 gas_assert (cur_block
);
11173 fix
= fix_new (frag_now
, i
* 8, 4,
11174 section_symbol (cur_block
->sec
),
11176 FALSE
, BFD_RELOC_32
);
11177 fix
->fx_file
= "<internal>";
11180 /* Write the length. */
11181 md_number_to_chars (&frag_data
[4 + i
* 8],
11182 cur_block
->size
, 4);
11183 cur_block
= cur_block
->next
;
11185 frag_wane (frag_now
);
11187 frag_wane (frag_now
);
11195 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11196 const char *section_name_base
,
11197 xt_section_type sec_type
)
11201 /* Walk over all of the current segments.
11202 Walk over each fragment.
11203 For each fragment that has instructions,
11204 build an instruction record (append where possible). */
11206 for (seclist
= &stdoutput
->sections
;
11207 seclist
&& *seclist
;
11208 seclist
= &(*seclist
)->next
)
11210 segT sec
= *seclist
;
11212 if (exclude_section_from_property_tables (sec
))
11215 if (section_has_xproperty (sec
, flag_fn
))
11217 segment_info_type
*xt_seg_info
;
11218 xtensa_block_info
**xt_blocks
;
11219 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11221 prop_sec
->output_section
= prop_sec
;
11222 subseg_set (prop_sec
, 0);
11223 xt_seg_info
= seg_info (prop_sec
);
11224 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11226 /* Walk over all of the frchains here and add new sections. */
11227 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11231 /* Now we fill them out.... */
11233 for (seclist
= &stdoutput
->sections
;
11234 seclist
&& *seclist
;
11235 seclist
= &(*seclist
)->next
)
11237 segment_info_type
*seginfo
;
11238 xtensa_block_info
*block
;
11239 segT sec
= *seclist
;
11241 seginfo
= seg_info (sec
);
11242 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11246 xtensa_block_info
*cur_block
;
11248 bfd_size_type rec_size
;
11250 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11253 rec_size
= num_recs
* (8 + 4);
11254 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11255 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11262 subseg_set (sec
, 0);
11263 frag_data
= frag_more (rec_size
);
11265 for (i
= 0; i
< num_recs
; i
++)
11269 /* Write the fixup. */
11270 gas_assert (cur_block
);
11271 fix
= fix_new (frag_now
, i
* 12, 4,
11272 section_symbol (cur_block
->sec
),
11274 FALSE
, BFD_RELOC_32
);
11275 fix
->fx_file
= "<internal>";
11278 /* Write the length. */
11279 md_number_to_chars (&frag_data
[4 + i
* 12],
11280 cur_block
->size
, 4);
11281 md_number_to_chars (&frag_data
[8 + i
* 12],
11282 frag_flags_to_number (&cur_block
->flags
),
11283 sizeof (flagword
));
11284 cur_block
= cur_block
->next
;
11286 frag_wane (frag_now
);
11288 frag_wane (frag_now
);
11296 exclude_section_from_property_tables (segT sec
)
11298 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11300 /* Sections that don't contribute to the memory footprint are excluded. */
11301 if ((flags
& SEC_DEBUGGING
)
11302 || !(flags
& SEC_ALLOC
)
11303 || (flags
& SEC_MERGE
))
11306 /* Linker cie and fde optimizations mess up property entries for
11307 eh_frame sections, but there is nothing inside them relevant to
11308 property tables anyway. */
11309 if (strcmp (sec
->name
, ".eh_frame") == 0)
11317 section_has_property (segT sec
, frag_predicate property_function
)
11319 segment_info_type
*seginfo
= seg_info (sec
);
11322 if (seginfo
&& seginfo
->frchainP
)
11324 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11326 if (property_function (fragP
)
11327 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11336 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11338 segment_info_type
*seginfo
= seg_info (sec
);
11341 if (seginfo
&& seginfo
->frchainP
)
11343 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11345 frag_flags prop_flags
;
11346 property_function (fragP
, &prop_flags
);
11347 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11355 /* Two types of block sections exist right now: literal and insns. */
11358 add_xt_block_frags (segT sec
,
11359 xtensa_block_info
**xt_block
,
11360 frag_predicate property_function
,
11361 frag_predicate end_property_function
)
11365 /* Build it if needed. */
11366 while (*xt_block
!= NULL
)
11367 xt_block
= &(*xt_block
)->next
;
11368 /* We are either at NULL at the beginning or at the end. */
11370 /* Walk through the frags. */
11371 if (seg_info (sec
)->frchainP
)
11373 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11375 fragP
= fragP
->fr_next
)
11377 if (property_function (fragP
)
11378 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11380 if (*xt_block
!= NULL
)
11382 if ((*xt_block
)->offset
+ (*xt_block
)->size
11383 == fragP
->fr_address
)
11384 (*xt_block
)->size
+= fragP
->fr_fix
;
11386 xt_block
= &((*xt_block
)->next
);
11388 if (*xt_block
== NULL
)
11390 xtensa_block_info
*new_block
= (xtensa_block_info
*)
11391 xmalloc (sizeof (xtensa_block_info
));
11392 new_block
->sec
= sec
;
11393 new_block
->offset
= fragP
->fr_address
;
11394 new_block
->size
= fragP
->fr_fix
;
11395 new_block
->next
= NULL
;
11396 xtensa_frag_flags_init (&new_block
->flags
);
11397 *xt_block
= new_block
;
11399 if (end_property_function
11400 && end_property_function (fragP
))
11402 xt_block
= &((*xt_block
)->next
);
11410 /* Break the encapsulation of add_xt_prop_frags here. */
11413 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
11415 if (prop_flags
->is_literal
11416 || prop_flags
->is_insn
11417 || prop_flags
->is_data
11418 || prop_flags
->is_unreachable
)
11425 xtensa_frag_flags_init (frag_flags
*prop_flags
)
11427 memset (prop_flags
, 0, sizeof (frag_flags
));
11432 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
11434 xtensa_frag_flags_init (prop_flags
);
11435 if (fragP
->tc_frag_data
.is_literal
)
11436 prop_flags
->is_literal
= TRUE
;
11437 if (fragP
->tc_frag_data
.is_specific_opcode
11438 || fragP
->tc_frag_data
.is_no_transform
)
11440 prop_flags
->is_no_transform
= TRUE
;
11441 if (xtensa_frag_flags_is_empty (prop_flags
))
11442 prop_flags
->is_data
= TRUE
;
11444 if (fragP
->tc_frag_data
.is_unreachable
)
11445 prop_flags
->is_unreachable
= TRUE
;
11446 else if (fragP
->tc_frag_data
.is_insn
)
11448 prop_flags
->is_insn
= TRUE
;
11449 if (fragP
->tc_frag_data
.is_loop_target
)
11450 prop_flags
->insn
.is_loop_target
= TRUE
;
11451 if (fragP
->tc_frag_data
.is_branch_target
)
11452 prop_flags
->insn
.is_branch_target
= TRUE
;
11453 if (fragP
->tc_frag_data
.is_no_density
)
11454 prop_flags
->insn
.is_no_density
= TRUE
;
11455 if (fragP
->tc_frag_data
.use_absolute_literals
)
11456 prop_flags
->insn
.is_abslit
= TRUE
;
11458 if (fragP
->tc_frag_data
.is_align
)
11460 prop_flags
->is_align
= TRUE
;
11461 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
11462 if (xtensa_frag_flags_is_empty (prop_flags
))
11463 prop_flags
->is_data
= TRUE
;
11469 frag_flags_to_number (const frag_flags
*prop_flags
)
11472 if (prop_flags
->is_literal
)
11473 num
|= XTENSA_PROP_LITERAL
;
11474 if (prop_flags
->is_insn
)
11475 num
|= XTENSA_PROP_INSN
;
11476 if (prop_flags
->is_data
)
11477 num
|= XTENSA_PROP_DATA
;
11478 if (prop_flags
->is_unreachable
)
11479 num
|= XTENSA_PROP_UNREACHABLE
;
11480 if (prop_flags
->insn
.is_loop_target
)
11481 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
11482 if (prop_flags
->insn
.is_branch_target
)
11484 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
11485 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
11488 if (prop_flags
->insn
.is_no_density
)
11489 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
11490 if (prop_flags
->is_no_transform
)
11491 num
|= XTENSA_PROP_NO_TRANSFORM
;
11492 if (prop_flags
->insn
.is_no_reorder
)
11493 num
|= XTENSA_PROP_INSN_NO_REORDER
;
11494 if (prop_flags
->insn
.is_abslit
)
11495 num
|= XTENSA_PROP_INSN_ABSLIT
;
11497 if (prop_flags
->is_align
)
11499 num
|= XTENSA_PROP_ALIGN
;
11500 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
11508 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
11509 const frag_flags
*prop_flags_2
)
11511 /* Cannot combine with an end marker. */
11513 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
11515 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
11517 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
11520 if (prop_flags_1
->is_insn
)
11522 /* Properties of the beginning of the frag. */
11523 if (prop_flags_2
->insn
.is_loop_target
)
11525 if (prop_flags_2
->insn
.is_branch_target
)
11527 if (prop_flags_1
->insn
.is_no_density
!=
11528 prop_flags_2
->insn
.is_no_density
)
11530 if (prop_flags_1
->is_no_transform
!=
11531 prop_flags_2
->is_no_transform
)
11533 if (prop_flags_1
->insn
.is_no_reorder
!=
11534 prop_flags_2
->insn
.is_no_reorder
)
11536 if (prop_flags_1
->insn
.is_abslit
!=
11537 prop_flags_2
->insn
.is_abslit
)
11541 if (prop_flags_1
->is_align
)
11549 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
11552 unsigned align_bits
;
11554 if (!xt_block
->flags
.is_align
)
11555 return xt_block
->size
;
11557 end_addr
= xt_block
->offset
+ xt_block
->size
;
11558 align_bits
= xt_block
->flags
.alignment
;
11559 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
11560 return end_addr
- xt_block
->offset
;
11565 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11566 const xtensa_block_info
*xt_block_2
)
11568 if (xt_block
->sec
!= xt_block_2
->sec
)
11570 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11571 != xt_block_2
->offset
)
11574 if (xt_block_2
->size
== 0
11575 && (!xt_block_2
->flags
.is_unreachable
11576 || xt_block
->flags
.is_unreachable
))
11578 if (xt_block_2
->flags
.is_align
11579 && xt_block
->flags
.is_align
)
11581 /* Nothing needed. */
11582 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11587 if (xt_block_2
->flags
.is_align
)
11589 /* Push alignment to previous entry. */
11590 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11591 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11596 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11597 &xt_block_2
->flags
))
11600 xt_block
->size
+= xt_block_2
->size
;
11602 if (xt_block_2
->flags
.is_align
)
11604 xt_block
->flags
.is_align
= TRUE
;
11605 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11613 add_xt_prop_frags (segT sec
,
11614 xtensa_block_info
**xt_block
,
11615 frag_flags_fn property_function
)
11619 /* Build it if needed. */
11620 while (*xt_block
!= NULL
)
11622 xt_block
= &(*xt_block
)->next
;
11624 /* We are either at NULL at the beginning or at the end. */
11626 /* Walk through the frags. */
11627 if (seg_info (sec
)->frchainP
)
11629 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11630 fragP
= fragP
->fr_next
)
11632 xtensa_block_info tmp_block
;
11633 tmp_block
.sec
= sec
;
11634 tmp_block
.offset
= fragP
->fr_address
;
11635 tmp_block
.size
= fragP
->fr_fix
;
11636 tmp_block
.next
= NULL
;
11637 property_function (fragP
, &tmp_block
.flags
);
11639 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11640 /* && fragP->fr_fix != 0) */
11642 if ((*xt_block
) == NULL
11643 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11645 xtensa_block_info
*new_block
;
11646 if ((*xt_block
) != NULL
)
11647 xt_block
= &(*xt_block
)->next
;
11648 new_block
= (xtensa_block_info
*)
11649 xmalloc (sizeof (xtensa_block_info
));
11650 *new_block
= tmp_block
;
11651 *xt_block
= new_block
;
11659 /* op_placement_info_table */
11661 /* op_placement_info makes it easier to determine which
11662 ops can go in which slots. */
11665 init_op_placement_info_table (void)
11667 xtensa_isa isa
= xtensa_default_isa
;
11668 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11669 xtensa_opcode opcode
;
11672 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11674 op_placement_table
= (op_placement_info_table
)
11675 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11676 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11678 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11680 op_placement_info
*opi
= &op_placement_table
[opcode
];
11681 /* FIXME: Make tinsn allocation dynamic. */
11682 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11683 as_fatal (_("too many operands in instruction"));
11684 opi
->narrowest
= XTENSA_UNDEFINED
;
11685 opi
->narrowest_size
= 0x7F;
11686 opi
->narrowest_slot
= 0;
11688 opi
->num_formats
= 0;
11690 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11692 opi
->slots
[fmt
] = 0;
11693 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11695 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11697 int fmt_length
= xtensa_format_length (isa
, fmt
);
11699 set_bit (fmt
, opi
->formats
);
11700 set_bit (slot
, opi
->slots
[fmt
]);
11701 if (fmt_length
< opi
->narrowest_size
11702 || (fmt_length
== opi
->narrowest_size
11703 && (xtensa_format_num_slots (isa
, fmt
)
11704 < xtensa_format_num_slots (isa
,
11707 opi
->narrowest
= fmt
;
11708 opi
->narrowest_size
= fmt_length
;
11709 opi
->narrowest_slot
= slot
;
11714 opi
->num_formats
++;
11717 xtensa_insnbuf_free (isa
, ibuf
);
11722 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11724 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11728 /* If the opcode is available in a single slot format, return its size. */
11731 xg_get_single_size (xtensa_opcode opcode
)
11733 return op_placement_table
[opcode
].narrowest_size
;
11737 static xtensa_format
11738 xg_get_single_format (xtensa_opcode opcode
)
11740 return op_placement_table
[opcode
].narrowest
;
11745 xg_get_single_slot (xtensa_opcode opcode
)
11747 return op_placement_table
[opcode
].narrowest_slot
;
11751 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11754 istack_init (IStack
*stack
)
11761 istack_empty (IStack
*stack
)
11763 return (stack
->ninsn
== 0);
11768 istack_full (IStack
*stack
)
11770 return (stack
->ninsn
== MAX_ISTACK
);
11774 /* Return a pointer to the top IStack entry.
11775 It is an error to call this if istack_empty () is TRUE. */
11778 istack_top (IStack
*stack
)
11780 int rec
= stack
->ninsn
- 1;
11781 gas_assert (!istack_empty (stack
));
11782 return &stack
->insn
[rec
];
11786 /* Add a new TInsn to an IStack.
11787 It is an error to call this if istack_full () is TRUE. */
11790 istack_push (IStack
*stack
, TInsn
*insn
)
11792 int rec
= stack
->ninsn
;
11793 gas_assert (!istack_full (stack
));
11794 stack
->insn
[rec
] = *insn
;
11799 /* Clear space for the next TInsn on the IStack and return a pointer
11800 to it. It is an error to call this if istack_full () is TRUE. */
11803 istack_push_space (IStack
*stack
)
11805 int rec
= stack
->ninsn
;
11807 gas_assert (!istack_full (stack
));
11808 insn
= &stack
->insn
[rec
];
11815 /* Remove the last pushed instruction. It is an error to call this if
11816 istack_empty () returns TRUE. */
11819 istack_pop (IStack
*stack
)
11821 int rec
= stack
->ninsn
- 1;
11822 gas_assert (!istack_empty (stack
));
11824 tinsn_init (&stack
->insn
[rec
]);
11828 /* TInsn functions. */
11831 tinsn_init (TInsn
*dst
)
11833 memset (dst
, 0, sizeof (TInsn
));
11837 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11840 tinsn_has_symbolic_operands (const TInsn
*insn
)
11843 int n
= insn
->ntok
;
11845 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11847 for (i
= 0; i
< n
; ++i
)
11849 switch (insn
->tok
[i
].X_op
)
11863 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11865 xtensa_isa isa
= xtensa_default_isa
;
11867 int n
= insn
->ntok
;
11869 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11871 for (i
= 0; i
< n
; ++i
)
11873 switch (insn
->tok
[i
].X_op
)
11881 /* Errors for these types are caught later. */
11886 /* Symbolic immediates are only allowed on the last immediate
11887 operand. At this time, CONST16 is the only opcode where we
11888 support non-PC-relative relocations. */
11889 if (i
!= get_relaxable_immed (insn
->opcode
)
11890 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11891 && insn
->opcode
!= xtensa_const16_opcode
))
11893 as_bad (_("invalid symbolic operand"));
11902 /* For assembly code with complex expressions (e.g. subtraction),
11903 we have to build them in the literal pool so that
11904 their results are calculated correctly after relaxation.
11905 The relaxation only handles expressions that
11906 boil down to SYMBOL + OFFSET. */
11909 tinsn_has_complex_operands (const TInsn
*insn
)
11912 int n
= insn
->ntok
;
11913 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11914 for (i
= 0; i
< n
; ++i
)
11916 switch (insn
->tok
[i
].X_op
)
11932 /* Encode a TInsn opcode and its constant operands into slotbuf.
11933 Return TRUE if there is a symbol in the immediate field. This
11934 function assumes that:
11935 1) The number of operands are correct.
11936 2) The insn_type is ITYPE_INSN.
11937 3) The opcode can be encoded in the specified format and slot.
11938 4) Operands are either O_constant or O_symbol, and all constants fit. */
11941 tinsn_to_slotbuf (xtensa_format fmt
,
11944 xtensa_insnbuf slotbuf
)
11946 xtensa_isa isa
= xtensa_default_isa
;
11947 xtensa_opcode opcode
= tinsn
->opcode
;
11948 bfd_boolean has_fixup
= FALSE
;
11949 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11952 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11953 if (noperands
!= tinsn
->ntok
)
11954 as_fatal (_("operand number mismatch"));
11956 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11958 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11959 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11963 for (i
= 0; i
< noperands
; i
++)
11965 expressionS
*exp
= &tinsn
->tok
[i
];
11974 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11976 /* The register number has already been checked in
11977 expression_maybe_register, so we don't need to check here. */
11978 opnd_value
= exp
->X_add_number
;
11979 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11980 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11983 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11987 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11989 as_where (&file_name
, &line
);
11990 /* It is a constant and we called this function
11991 then we have to try to fit it. */
11992 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11993 exp
->X_add_number
, file_name
, line
);
12006 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12007 into a multi-slot instruction, fill the other slots with NOPs.
12008 Return TRUE if there is a symbol in the immediate field. See also the
12009 assumptions listed for tinsn_to_slotbuf. */
12012 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12014 static xtensa_insnbuf slotbuf
= 0;
12015 static vliw_insn vinsn
;
12016 xtensa_isa isa
= xtensa_default_isa
;
12017 bfd_boolean has_fixup
= FALSE
;
12022 slotbuf
= xtensa_insnbuf_alloc (isa
);
12023 xg_init_vinsn (&vinsn
);
12026 xg_clear_vinsn (&vinsn
);
12028 bundle_tinsn (tinsn
, &vinsn
);
12030 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12032 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12034 /* Only one slot may have a fix-up because the rest contains NOPs. */
12036 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12037 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12044 /* Check the instruction arguments. Return TRUE on failure. */
12047 tinsn_check_arguments (const TInsn
*insn
)
12049 xtensa_isa isa
= xtensa_default_isa
;
12050 xtensa_opcode opcode
= insn
->opcode
;
12051 xtensa_regfile t1_regfile
, t2_regfile
;
12052 int t1_reg
, t2_reg
;
12053 int t1_base_reg
, t1_last_reg
;
12054 int t2_base_reg
, t2_last_reg
;
12055 char t1_inout
, t2_inout
;
12058 if (opcode
== XTENSA_UNDEFINED
)
12060 as_bad (_("invalid opcode"));
12064 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12066 as_bad (_("too few operands"));
12070 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12072 as_bad (_("too many operands"));
12076 /* Check registers. */
12077 for (j
= 0; j
< insn
->ntok
; j
++)
12079 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12082 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12083 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12085 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12087 for (i
= 0; i
< insn
->ntok
; i
++)
12092 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12095 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12097 if (t1_regfile
!= t2_regfile
)
12100 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12101 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12103 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12104 t1_last_reg
= (t1_base_reg
12105 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12107 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12109 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12111 if (t1_reg
!= t2_reg
)
12114 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12116 as_bad (_("multiple writes to the same register"));
12127 /* Load an instruction from its encoded form. */
12130 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12134 xg_init_vinsn (&vinsn
);
12135 vinsn_from_chars (&vinsn
, f
);
12137 *tinsn
= vinsn
.slots
[slot
];
12138 xg_free_vinsn (&vinsn
);
12143 tinsn_from_insnbuf (TInsn
*tinsn
,
12144 xtensa_insnbuf slotbuf
,
12149 xtensa_isa isa
= xtensa_default_isa
;
12151 /* Find the immed. */
12152 tinsn_init (tinsn
);
12153 tinsn
->insn_type
= ITYPE_INSN
;
12154 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12155 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12156 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12157 for (i
= 0; i
< tinsn
->ntok
; i
++)
12159 set_expr_const (&tinsn
->tok
[i
],
12160 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12161 tinsn
->opcode
, i
));
12166 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12169 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12171 xtensa_opcode opcode
= tinsn
->opcode
;
12174 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12176 opnum
= get_relaxable_immed (opcode
);
12177 gas_assert (opnum
>= 0);
12178 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12179 fragP
->tc_frag_data
.slot_symbols
[slot
],
12180 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12182 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12187 get_num_stack_text_bytes (IStack
*istack
)
12190 int text_bytes
= 0;
12192 for (i
= 0; i
< istack
->ninsn
; i
++)
12194 TInsn
*tinsn
= &istack
->insn
[i
];
12195 if (tinsn
->insn_type
== ITYPE_INSN
)
12196 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12203 get_num_stack_literal_bytes (IStack
*istack
)
12208 for (i
= 0; i
< istack
->ninsn
; i
++)
12210 TInsn
*tinsn
= &istack
->insn
[i
];
12211 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12218 /* vliw_insn functions. */
12221 xg_init_vinsn (vliw_insn
*v
)
12224 xtensa_isa isa
= xtensa_default_isa
;
12226 xg_clear_vinsn (v
);
12228 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12229 if (v
->insnbuf
== NULL
)
12230 as_fatal (_("out of memory"));
12232 for (i
= 0; i
< config_max_slots
; i
++)
12234 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12235 if (v
->slotbuf
[i
] == NULL
)
12236 as_fatal (_("out of memory"));
12242 xg_clear_vinsn (vliw_insn
*v
)
12246 memset (v
, 0, offsetof (vliw_insn
, slots
)
12247 + sizeof(TInsn
) * config_max_slots
);
12249 v
->format
= XTENSA_UNDEFINED
;
12251 v
->inside_bundle
= FALSE
;
12253 if (xt_saved_debug_type
!= DEBUG_NONE
)
12254 debug_type
= xt_saved_debug_type
;
12256 for (i
= 0; i
< config_max_slots
; i
++)
12257 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12262 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12265 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12266 dst
->insnbuf
= src
->insnbuf
;
12267 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12272 vinsn_has_specific_opcodes (vliw_insn
*v
)
12276 for (i
= 0; i
< v
->num_slots
; i
++)
12278 if (v
->slots
[i
].is_specific_opcode
)
12286 xg_free_vinsn (vliw_insn
*v
)
12289 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12290 for (i
= 0; i
< config_max_slots
; i
++)
12291 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12295 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12296 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12299 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12302 bfd_boolean record_fixup
)
12304 xtensa_isa isa
= xtensa_default_isa
;
12305 xtensa_format fmt
= vinsn
->format
;
12306 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12308 bfd_boolean has_fixup
= FALSE
;
12310 xtensa_format_encode (isa
, fmt
, insnbuf
);
12312 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12314 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12315 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12316 bfd_boolean tinsn_has_fixup
=
12317 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12318 vinsn
->slotbuf
[slot
]);
12320 xtensa_format_set_slot (isa
, fmt
, slot
,
12321 insnbuf
, vinsn
->slotbuf
[slot
]);
12322 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12324 if (vinsn
->num_slots
!= 1)
12325 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12326 else if (record_fixup
)
12327 /* Instructions that generate TLS relocations should always be
12328 relaxed in the front-end. If "record_fixup" is set, then this
12329 function is being called during back-end relaxation, so flag
12330 the unexpected behavior as an error. */
12331 as_bad (_("unexpected TLS relocation"));
12333 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12334 xtensa_format_length (isa
, fmt
),
12335 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12336 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12338 if (tinsn_has_fixup
)
12341 xtensa_opcode opcode
= tinsn
->opcode
;
12342 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12345 for (i
= 0; i
< noperands
; i
++)
12347 expressionS
* exp
= &tinsn
->tok
[i
];
12353 if (get_relaxable_immed (opcode
) == i
)
12355 /* Add a fix record for the instruction, except if this
12356 function is being called prior to relaxation, i.e.,
12357 if record_fixup is false, and the instruction might
12358 be relaxed later. */
12360 || tinsn
->is_specific_opcode
12361 || !xg_is_relaxable_insn (tinsn
, 0))
12363 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12364 frag_offset
- fragP
->fr_literal
);
12368 if (exp
->X_op
!= O_symbol
)
12369 as_bad (_("invalid operand"));
12370 tinsn
->symbol
= exp
->X_add_symbol
;
12371 tinsn
->offset
= exp
->X_add_number
;
12375 as_bad (_("symbolic operand not allowed"));
12383 as_bad (_("expression too complex"));
12395 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12397 static xtensa_insnbuf insnbuf
= NULL
;
12398 static xtensa_insnbuf slotbuf
= NULL
;
12401 xtensa_isa isa
= xtensa_default_isa
;
12405 insnbuf
= xtensa_insnbuf_alloc (isa
);
12406 slotbuf
= xtensa_insnbuf_alloc (isa
);
12409 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
12410 fmt
= xtensa_format_decode (isa
, insnbuf
);
12411 if (fmt
== XTENSA_UNDEFINED
)
12412 as_fatal (_("cannot decode instruction format"));
12413 vinsn
->format
= fmt
;
12414 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
12416 for (i
= 0; i
< vinsn
->num_slots
; i
++)
12418 TInsn
*tinsn
= &vinsn
->slots
[i
];
12419 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
12420 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
12425 /* Expression utilities. */
12427 /* Return TRUE if the expression is an integer constant. */
12430 expr_is_const (const expressionS
*s
)
12432 return (s
->X_op
== O_constant
);
12436 /* Get the expression constant.
12437 Calling this is illegal if expr_is_const () returns TRUE. */
12440 get_expr_const (const expressionS
*s
)
12442 gas_assert (expr_is_const (s
));
12443 return s
->X_add_number
;
12447 /* Set the expression to a constant value. */
12450 set_expr_const (expressionS
*s
, offsetT val
)
12452 s
->X_op
= O_constant
;
12453 s
->X_add_number
= val
;
12454 s
->X_add_symbol
= NULL
;
12455 s
->X_op_symbol
= NULL
;
12460 expr_is_register (const expressionS
*s
)
12462 return (s
->X_op
== O_register
);
12466 /* Get the expression constant.
12467 Calling this is illegal if expr_is_const () returns TRUE. */
12470 get_expr_register (const expressionS
*s
)
12472 gas_assert (expr_is_register (s
));
12473 return s
->X_add_number
;
12477 /* Set the expression to a symbol + constant offset. */
12480 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
12482 s
->X_op
= O_symbol
;
12483 s
->X_add_symbol
= sym
;
12484 s
->X_op_symbol
= NULL
; /* unused */
12485 s
->X_add_number
= offset
;
12489 /* Return TRUE if the two expressions are equal. */
12492 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
12494 if (s1
->X_op
!= s2
->X_op
)
12496 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
12498 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
12500 if (s1
->X_add_number
!= s2
->X_add_number
)
12507 copy_expr (expressionS
*dst
, const expressionS
*src
)
12509 memcpy (dst
, src
, sizeof (expressionS
));
12513 /* Support for the "--rename-section" option. */
12515 struct rename_section_struct
12519 struct rename_section_struct
*next
;
12522 static struct rename_section_struct
*section_rename
;
12525 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
12526 entries to the section_rename list. Note: Specifying multiple
12527 renamings separated by colons is not documented and is retained only
12528 for backward compatibility. */
12531 build_section_rename (const char *arg
)
12533 struct rename_section_struct
*r
;
12534 char *this_arg
= NULL
;
12535 char *next_arg
= NULL
;
12537 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12539 char *old_name
, *new_name
;
12543 next_arg
= strchr (this_arg
, ':');
12551 old_name
= this_arg
;
12552 new_name
= strchr (this_arg
, '=');
12554 if (*old_name
== '\0')
12556 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12559 if (!new_name
|| new_name
[1] == '\0')
12561 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12568 /* Check for invalid section renaming. */
12569 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12571 if (strcmp (r
->old_name
, old_name
) == 0)
12572 as_bad (_("section %s renamed multiple times"), old_name
);
12573 if (strcmp (r
->new_name
, new_name
) == 0)
12574 as_bad (_("multiple sections remapped to output section %s"),
12579 r
= (struct rename_section_struct
*)
12580 xmalloc (sizeof (struct rename_section_struct
));
12581 r
->old_name
= xstrdup (old_name
);
12582 r
->new_name
= xstrdup (new_name
);
12583 r
->next
= section_rename
;
12584 section_rename
= r
;
12590 xtensa_section_rename (char *name
)
12592 struct rename_section_struct
*r
= section_rename
;
12594 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12596 if (strcmp (r
->old_name
, name
) == 0)
12597 return r
->new_name
;