1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 size_t xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
446 /* Alignment Functions. */
448 static size_t get_text_align_power (int);
449 static addressT
get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
451 /* Helpers for xtensa_relax_frag(). */
453 static long relax_frag_add_nop (fragS
*);
455 /* Accessors for additional per-subsegment information. */
457 static unsigned get_last_insn_flags (segT
, subsegT
);
458 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
459 static float get_subseg_total_freq (segT
, subsegT
);
460 static float get_subseg_target_freq (segT
, subsegT
);
461 static void set_subseg_freq (segT
, subsegT
, float, float);
463 /* Segment list functions. */
465 static void xtensa_move_literals (void);
466 static void xtensa_reorder_segments (void);
467 static void xtensa_switch_to_literal_fragment (emit_state
*);
468 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
469 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
470 static void xtensa_restore_emit_state (emit_state
*);
471 static void cache_literal_section
472 (seg_list
*, const char *, segT
*, bfd_boolean
);
474 /* Import from elf32-xtensa.c in BFD library. */
476 extern char *xtensa_get_property_section_name (asection
*, const char *);
478 /* op_placement_info functions. */
480 static void init_op_placement_info_table (void);
481 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
482 static int xg_get_single_size (xtensa_opcode
);
483 static xtensa_format
xg_get_single_format (xtensa_opcode
);
485 /* TInsn and IStack functions. */
487 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
488 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
489 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
490 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
491 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
492 static void tinsn_from_chars (TInsn
*, char *, int);
493 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
494 static int get_num_stack_text_bytes (IStack
*);
495 static int get_num_stack_literal_bytes (IStack
*);
497 /* vliw_insn functions. */
499 static void xg_init_vinsn (vliw_insn
*);
500 static void xg_clear_vinsn (vliw_insn
*);
501 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
502 static void xg_free_vinsn (vliw_insn
*);
503 static bfd_boolean vinsn_to_insnbuf
504 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
505 static void vinsn_from_chars (vliw_insn
*, char *);
507 /* Expression Utilities. */
509 bfd_boolean
expr_is_const (const expressionS
*);
510 offsetT
get_expr_const (const expressionS
*);
511 void set_expr_const (expressionS
*, offsetT
);
512 bfd_boolean
expr_is_register (const expressionS
*);
513 offsetT
get_expr_register (const expressionS
*);
514 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
515 static void set_expr_symbol_offset_diff
516 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
517 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
518 static void copy_expr (expressionS
*, const expressionS
*);
520 #ifdef XTENSA_SECTION_RENAME
521 static void build_section_rename (const char *);
522 static void add_section_rename (char *, char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa
;
529 extern int target_big_endian
;
531 static xtensa_opcode xtensa_addi_opcode
;
532 static xtensa_opcode xtensa_addmi_opcode
;
533 static xtensa_opcode xtensa_call0_opcode
;
534 static xtensa_opcode xtensa_call4_opcode
;
535 static xtensa_opcode xtensa_call8_opcode
;
536 static xtensa_opcode xtensa_call12_opcode
;
537 static xtensa_opcode xtensa_callx0_opcode
;
538 static xtensa_opcode xtensa_callx4_opcode
;
539 static xtensa_opcode xtensa_callx8_opcode
;
540 static xtensa_opcode xtensa_callx12_opcode
;
541 static xtensa_opcode xtensa_const16_opcode
;
542 static xtensa_opcode xtensa_entry_opcode
;
543 static xtensa_opcode xtensa_movi_opcode
;
544 static xtensa_opcode xtensa_movi_n_opcode
;
545 static xtensa_opcode xtensa_isync_opcode
;
546 static xtensa_opcode xtensa_jx_opcode
;
547 static xtensa_opcode xtensa_l32r_opcode
;
548 static xtensa_opcode xtensa_loop_opcode
;
549 static xtensa_opcode xtensa_loopnez_opcode
;
550 static xtensa_opcode xtensa_loopgtz_opcode
;
551 static xtensa_opcode xtensa_nop_opcode
;
552 static xtensa_opcode xtensa_nop_n_opcode
;
553 static xtensa_opcode xtensa_or_opcode
;
554 static xtensa_opcode xtensa_ret_opcode
;
555 static xtensa_opcode xtensa_ret_n_opcode
;
556 static xtensa_opcode xtensa_retw_opcode
;
557 static xtensa_opcode xtensa_retw_n_opcode
;
558 static xtensa_opcode xtensa_rsr_lcount_opcode
;
559 static xtensa_opcode xtensa_waiti_opcode
;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section
= TRUE
;
565 static bfd_boolean align_targets
= TRUE
;
566 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
567 static bfd_boolean has_a0_b_retw
= FALSE
;
568 static bfd_boolean workaround_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
570 static bfd_boolean workaround_short_loop
= FALSE
;
571 static bfd_boolean maybe_has_short_loop
= FALSE
;
572 static bfd_boolean workaround_close_loop_end
= FALSE
;
573 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops
= FALSE
;
585 xtensa_setup_hw_workarounds (int earliest
, int latest
)
587 if (earliest
> latest
)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest
< 105000 || latest
< 105000)
593 workaround_a0_b_retw
|= TRUE
;
594 workaround_b_j_loop_end
|= TRUE
;
595 workaround_short_loop
|= TRUE
;
596 workaround_close_loop_end
|= TRUE
;
597 workaround_all_short_loops
|= TRUE
;
604 option_density
= OPTION_MD_BASE
,
611 option_no_link_relax
,
619 option_text_section_literals
,
620 option_no_text_section_literals
,
622 option_absolute_literals
,
623 option_no_absolute_literals
,
625 option_align_targets
,
626 option_no_align_targets
,
628 option_warn_unaligned_targets
,
633 option_workaround_a0_b_retw
,
634 option_no_workaround_a0_b_retw
,
636 option_workaround_b_j_loop_end
,
637 option_no_workaround_b_j_loop_end
,
639 option_workaround_short_loop
,
640 option_no_workaround_short_loop
,
642 option_workaround_all_short_loops
,
643 option_no_workaround_all_short_loops
,
645 option_workaround_close_loop_end
,
646 option_no_workaround_close_loop_end
,
648 option_no_workarounds
,
650 #ifdef XTENSA_SECTION_RENAME
651 option_rename_section_name
,
655 option_prefer_const16
,
657 option_target_hardware
660 const char *md_shortopts
= "";
662 struct option md_longopts
[] =
664 { "density", no_argument
, NULL
, option_density
},
665 { "no-density", no_argument
, NULL
, option_no_density
},
667 /* Both "relax" and "generics" are deprecated and treated as equivalent
668 to the "transform" option. */
669 { "relax", no_argument
, NULL
, option_relax
},
670 { "no-relax", no_argument
, NULL
, option_no_relax
},
671 { "generics", no_argument
, NULL
, option_generics
},
672 { "no-generics", no_argument
, NULL
, option_no_generics
},
674 { "transform", no_argument
, NULL
, option_transform
},
675 { "no-transform", no_argument
, NULL
, option_no_transform
},
676 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
677 { "no-text-section-literals", no_argument
, NULL
,
678 option_no_text_section_literals
},
679 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
680 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
681 /* This option was changed from -align-target to -target-align
682 because it conflicted with the "-al" option. */
683 { "target-align", no_argument
, NULL
, option_align_targets
},
684 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
685 { "warn-unaligned-targets", no_argument
, NULL
,
686 option_warn_unaligned_targets
},
687 { "longcalls", no_argument
, NULL
, option_longcalls
},
688 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
690 { "no-workaround-a0-b-retw", no_argument
, NULL
,
691 option_no_workaround_a0_b_retw
},
692 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
694 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
695 option_no_workaround_b_j_loop_end
},
696 { "workaround-b-j-loop-end", no_argument
, NULL
,
697 option_workaround_b_j_loop_end
},
699 { "no-workaround-short-loops", no_argument
, NULL
,
700 option_no_workaround_short_loop
},
701 { "workaround-short-loops", no_argument
, NULL
,
702 option_workaround_short_loop
},
704 { "no-workaround-all-short-loops", no_argument
, NULL
,
705 option_no_workaround_all_short_loops
},
706 { "workaround-all-short-loop", no_argument
, NULL
,
707 option_workaround_all_short_loops
},
709 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
710 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
712 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
714 { "no-workaround-close-loop-end", no_argument
, NULL
,
715 option_no_workaround_close_loop_end
},
716 { "workaround-close-loop-end", no_argument
, NULL
,
717 option_workaround_close_loop_end
},
719 #ifdef XTENSA_SECTION_RENAME
720 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
721 #endif /* XTENSA_SECTION_RENAME */
723 { "link-relax", no_argument
, NULL
, option_link_relax
},
724 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
726 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
728 { NULL
, no_argument
, NULL
, 0 }
731 size_t md_longopts_size
= sizeof md_longopts
;
735 md_parse_option (int c
, char *arg
)
740 as_warn (_("--density option is ignored"));
742 case option_no_density
:
743 as_warn (_("--no-density option is ignored"));
745 case option_link_relax
:
748 case option_no_link_relax
:
751 case option_generics
:
752 as_warn (_("--generics is deprecated; use --transform instead"));
753 return md_parse_option (option_transform
, arg
);
754 case option_no_generics
:
755 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
756 return md_parse_option (option_no_transform
, arg
);
758 as_warn (_("--relax is deprecated; use --transform instead"));
759 return md_parse_option (option_transform
, arg
);
760 case option_no_relax
:
761 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
762 return md_parse_option (option_no_transform
, arg
);
763 case option_longcalls
:
764 directive_state
[directive_longcalls
] = TRUE
;
766 case option_no_longcalls
:
767 directive_state
[directive_longcalls
] = FALSE
;
769 case option_text_section_literals
:
770 use_literal_section
= FALSE
;
772 case option_no_text_section_literals
:
773 use_literal_section
= TRUE
;
775 case option_absolute_literals
:
776 if (!absolute_literals_supported
)
778 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
781 directive_state
[directive_absolute_literals
] = TRUE
;
783 case option_no_absolute_literals
:
784 directive_state
[directive_absolute_literals
] = FALSE
;
787 case option_workaround_a0_b_retw
:
788 workaround_a0_b_retw
= TRUE
;
790 case option_no_workaround_a0_b_retw
:
791 workaround_a0_b_retw
= FALSE
;
793 case option_workaround_b_j_loop_end
:
794 workaround_b_j_loop_end
= TRUE
;
796 case option_no_workaround_b_j_loop_end
:
797 workaround_b_j_loop_end
= FALSE
;
800 case option_workaround_short_loop
:
801 workaround_short_loop
= TRUE
;
803 case option_no_workaround_short_loop
:
804 workaround_short_loop
= FALSE
;
807 case option_workaround_all_short_loops
:
808 workaround_all_short_loops
= TRUE
;
810 case option_no_workaround_all_short_loops
:
811 workaround_all_short_loops
= FALSE
;
814 case option_workaround_close_loop_end
:
815 workaround_close_loop_end
= TRUE
;
817 case option_no_workaround_close_loop_end
:
818 workaround_close_loop_end
= FALSE
;
821 case option_no_workarounds
:
822 workaround_a0_b_retw
= FALSE
;
823 workaround_b_j_loop_end
= FALSE
;
824 workaround_short_loop
= FALSE
;
825 workaround_all_short_loops
= FALSE
;
826 workaround_close_loop_end
= FALSE
;
829 case option_align_targets
:
830 align_targets
= TRUE
;
832 case option_no_align_targets
:
833 align_targets
= FALSE
;
836 case option_warn_unaligned_targets
:
837 warn_unaligned_branch_targets
= TRUE
;
840 #ifdef XTENSA_SECTION_RENAME
841 case option_rename_section_name
:
842 build_section_rename (arg
);
844 #endif /* XTENSA_SECTION_RENAME */
847 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
848 should be emitted or not. FIXME: Not implemented. */
851 case option_prefer_l32r
:
853 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
857 case option_prefer_const16
:
859 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
863 case option_target_hardware
:
865 int earliest
, latest
= 0;
866 if (*arg
== 0 || *arg
== '-')
867 as_fatal (_("invalid target hardware version"));
869 earliest
= strtol (arg
, &arg
, 0);
873 else if (*arg
== '-')
876 as_fatal (_("invalid target hardware version"));
877 latest
= strtol (arg
, &arg
, 0);
880 as_fatal (_("invalid target hardware version"));
882 xtensa_setup_hw_workarounds (earliest
, latest
);
886 case option_transform
:
887 /* This option has no affect other than to use the defaults,
888 which are already set. */
891 case option_no_transform
:
892 /* This option turns off all transformations of any kind.
893 However, because we want to preserve the state of other
894 directives, we only change its own field. Thus, before
895 you perform any transformation, always check if transform
896 is available. If you use the functions we provide for this
897 purpose, you will be ok. */
898 directive_state
[directive_transform
] = FALSE
;
908 md_show_usage (FILE *stream
)
912 --[no-]text-section-literals\n\
913 [Do not] put literals in the text section\n\
914 --[no-]absolute-literals\n\
915 [Do not] default to use non-PC-relative literals\n\
916 --[no-]target-align [Do not] try to align branch targets\n\
917 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
918 --[no-]transform [Do not] transform instructions\n"
919 #ifdef XTENSA_SECTION_RENAME
920 "--rename-section old=new(:old1=new1)*\n\
921 Rename section 'old' to 'new'\n"
922 #endif /* XTENSA_SECTION_RENAME */
927 /* Functions related to the list of current label symbols. */
930 xtensa_add_insn_label (symbolS
*sym
)
934 if (!free_insn_labels
)
935 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
938 l
= free_insn_labels
;
939 free_insn_labels
= l
->next
;
943 l
->next
= insn_labels
;
949 xtensa_clear_insn_labels (void)
953 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
960 /* The "loops_ok" argument is provided to allow ignoring labels that
961 define loop ends. This fixes a bug where the NOPs to align a
962 loop opcode were included in a previous zero-cost loop:
981 This argument is used to prevent moving the NOP to before the
982 loop-end label, which is what you want in this special case. */
985 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
989 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
991 symbolS
*lit_sym
= lit
->sym
;
992 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
994 S_SET_VALUE (lit_sym
, new_offset
);
995 symbol_set_frag (lit_sym
, new_frag
);
1001 /* Directive data and functions. */
1003 typedef struct state_stackS_struct
1005 directiveE directive
;
1006 bfd_boolean negated
;
1007 bfd_boolean old_state
;
1011 struct state_stackS_struct
*prev
;
1014 state_stackS
*directive_state_stack
;
1016 const pseudo_typeS md_pseudo_table
[] =
1018 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1019 { "literal_position", xtensa_literal_position
, 0 },
1020 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1021 { "long", xtensa_elf_cons
, 4 },
1022 { "word", xtensa_elf_cons
, 4 },
1023 { "short", xtensa_elf_cons
, 2 },
1024 { "begin", xtensa_begin_directive
, 0 },
1025 { "end", xtensa_end_directive
, 0 },
1026 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1027 { "literal", xtensa_literal_pseudo
, 0 },
1028 { "frequency", xtensa_frequency_pseudo
, 0 },
1034 use_transform (void)
1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end
);
1039 return directive_state
[directive_transform
];
1044 use_longcalls (void)
1046 /* After md_end, you should be checking frag by frag, rather
1047 than state directives. */
1048 assert (!past_xtensa_end
);
1049 return directive_state
[directive_longcalls
] && use_transform ();
1054 do_align_targets (void)
1056 /* After md_end, you should be checking frag by frag, rather
1057 than state directives. */
1058 assert (!past_xtensa_end
);
1059 return align_targets
&& use_transform ();
1064 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1068 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1070 as_where (&file
, &line
);
1072 stack
->directive
= directive
;
1073 stack
->negated
= negated
;
1074 stack
->old_state
= directive_state
[directive
];
1077 stack
->datum
= datum
;
1078 stack
->prev
= directive_state_stack
;
1079 directive_state_stack
= stack
;
1081 directive_state
[directive
] = !negated
;
1086 directive_pop (directiveE
*directive
,
1087 bfd_boolean
*negated
,
1092 state_stackS
*top
= directive_state_stack
;
1094 if (!directive_state_stack
)
1096 as_bad (_("unmatched end directive"));
1097 *directive
= directive_none
;
1101 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1102 *directive
= top
->directive
;
1103 *negated
= top
->negated
;
1106 *datum
= top
->datum
;
1107 directive_state_stack
= top
->prev
;
1113 directive_balance (void)
1115 while (directive_state_stack
)
1117 directiveE directive
;
1118 bfd_boolean negated
;
1123 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1124 as_warn_where ((char *) file
, line
,
1125 _(".begin directive with no matching .end directive"));
1131 inside_directive (directiveE dir
)
1133 state_stackS
*top
= directive_state_stack
;
1135 while (top
&& top
->directive
!= dir
)
1138 return (top
!= NULL
);
1143 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1147 char *directive_string
;
1149 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1154 input_line_pointer
+= 3;
1157 len
= strspn (input_line_pointer
,
1158 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1160 /* This code is a hack to make .begin [no-][generics|relax] exactly
1161 equivalent to .begin [no-]transform. We should remove it when
1162 we stop accepting those options. */
1164 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1166 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1167 directive_string
= "transform";
1169 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1171 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1172 directive_string
= "transform";
1175 directive_string
= input_line_pointer
;
1177 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1179 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1181 input_line_pointer
+= len
;
1182 *directive
= (directiveE
) i
;
1183 if (*negated
&& !directive_info
[i
].can_be_negated
)
1184 as_bad (_("directive %s cannot be negated"),
1185 directive_info
[i
].name
);
1190 as_bad (_("unknown directive"));
1191 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1196 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1198 directiveE directive
;
1199 bfd_boolean negated
;
1204 get_directive (&directive
, &negated
);
1205 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1207 discard_rest_of_line ();
1211 if (cur_vinsn
.inside_bundle
)
1212 as_bad (_("directives are not valid inside bundles"));
1216 case directive_literal
:
1217 if (!inside_directive (directive_literal
))
1219 /* Previous labels go with whatever follows this directive, not with
1220 the literal, so save them now. */
1221 saved_insn_labels
= insn_labels
;
1224 as_warn (_(".begin literal is deprecated; use .literal instead"));
1225 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1226 xtensa_switch_to_literal_fragment (state
);
1227 directive_push (directive_literal
, negated
, state
);
1230 case directive_literal_prefix
:
1231 /* Have to flush pending output because a movi relaxed to an l32r
1232 might produce a literal. */
1233 md_flush_pending_output ();
1234 /* Check to see if the current fragment is a literal
1235 fragment. If it is, then this operation is not allowed. */
1236 if (generating_literals
)
1238 as_bad (_("cannot set literal_prefix inside literal fragment"));
1242 /* Allocate the literal state for this section and push
1243 onto the directive stack. */
1244 ls
= xmalloc (sizeof (lit_state
));
1247 *ls
= default_lit_sections
;
1249 directive_push (directive_literal_prefix
, negated
, ls
);
1251 /* Parse the new prefix from the input_line_pointer. */
1253 len
= strspn (input_line_pointer
,
1254 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1255 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1257 /* Process the new prefix. */
1258 xtensa_literal_prefix (input_line_pointer
, len
);
1260 /* Skip the name in the input line. */
1261 input_line_pointer
+= len
;
1264 case directive_freeregs
:
1265 /* This information is currently unused, but we'll accept the statement
1266 and just discard the rest of the line. This won't check the syntax,
1267 but it will accept every correct freeregs directive. */
1268 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1269 directive_push (directive_freeregs
, negated
, 0);
1272 case directive_schedule
:
1273 md_flush_pending_output ();
1274 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1275 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1276 directive_push (directive_schedule
, negated
, 0);
1277 xtensa_set_frag_assembly_state (frag_now
);
1280 case directive_density
:
1281 as_warn (_(".begin [no-]density is ignored"));
1284 case directive_absolute_literals
:
1285 md_flush_pending_output ();
1286 if (!absolute_literals_supported
&& !negated
)
1288 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1291 xtensa_set_frag_assembly_state (frag_now
);
1292 directive_push (directive
, negated
, 0);
1296 md_flush_pending_output ();
1297 xtensa_set_frag_assembly_state (frag_now
);
1298 directive_push (directive
, negated
, 0);
1302 demand_empty_rest_of_line ();
1307 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1309 directiveE begin_directive
, end_directive
;
1310 bfd_boolean begin_negated
, end_negated
;
1314 emit_state
**state_ptr
;
1317 if (cur_vinsn
.inside_bundle
)
1318 as_bad (_("directives are not valid inside bundles"));
1320 get_directive (&end_directive
, &end_negated
);
1322 md_flush_pending_output ();
1324 switch (end_directive
)
1326 case (directiveE
) XTENSA_UNDEFINED
:
1327 discard_rest_of_line ();
1330 case directive_density
:
1331 as_warn (_(".end [no-]density is ignored"));
1332 demand_empty_rest_of_line ();
1335 case directive_absolute_literals
:
1336 if (!absolute_literals_supported
&& !end_negated
)
1338 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1339 demand_empty_rest_of_line ();
1348 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1349 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1350 (const void **) state_ptr
);
1352 if (begin_directive
!= directive_none
)
1354 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1356 as_bad (_("does not match begin %s%s at %s:%d"),
1357 begin_negated
? "no-" : "",
1358 directive_info
[begin_directive
].name
, file
, line
);
1362 switch (end_directive
)
1364 case directive_literal
:
1365 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1366 xtensa_restore_emit_state (state
);
1367 xtensa_set_frag_assembly_state (frag_now
);
1369 if (!inside_directive (directive_literal
))
1371 /* Restore the list of current labels. */
1372 xtensa_clear_insn_labels ();
1373 insn_labels
= saved_insn_labels
;
1377 case directive_literal_prefix
:
1378 /* Restore the default collection sections from saved state. */
1379 s
= (lit_state
*) state
;
1382 if (use_literal_section
)
1383 default_lit_sections
= *s
;
1385 /* free the state storage */
1389 case directive_schedule
:
1390 case directive_freeregs
:
1394 xtensa_set_frag_assembly_state (frag_now
);
1400 demand_empty_rest_of_line ();
1404 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1406 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1409 xtensa_dwarf2_directive_loc (int x
)
1411 xtensa_loc_directive_seen
= TRUE
;
1412 dwarf2_directive_loc (x
);
1417 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1419 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1421 xtensa_loc_directive_seen
= FALSE
;
1422 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1426 /* Place an aligned literal fragment at the current location. */
1429 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1431 md_flush_pending_output ();
1433 if (inside_directive (directive_literal
))
1434 as_warn (_(".literal_position inside literal directive; ignoring"));
1435 xtensa_mark_literal_pool_location ();
1437 demand_empty_rest_of_line ();
1438 xtensa_clear_insn_labels ();
1442 /* Support .literal label, expr, ... */
1445 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1448 char *p
, *base_name
;
1452 if (inside_directive (directive_literal
))
1454 as_bad (_(".literal not allowed inside .begin literal region"));
1455 ignore_rest_of_line ();
1459 md_flush_pending_output ();
1461 /* Previous labels go with whatever follows this directive, not with
1462 the literal, so save them now. */
1463 saved_insn_labels
= insn_labels
;
1466 /* If we are using text-section literals, then this is the right value... */
1469 base_name
= input_line_pointer
;
1471 xtensa_switch_to_literal_fragment (&state
);
1473 /* ...but if we aren't using text-section-literals, then we
1474 need to put them in the section we just switched to. */
1475 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1478 /* All literals are aligned to four-byte boundaries. */
1479 frag_align (2, 0, 0);
1480 record_alignment (now_seg
, 2);
1482 c
= get_symbol_end ();
1483 /* Just after name is now '\0'. */
1484 p
= input_line_pointer
;
1488 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1490 as_bad (_("expected comma or colon after symbol name; "
1491 "rest of line ignored"));
1492 ignore_rest_of_line ();
1493 xtensa_restore_emit_state (&state
);
1501 input_line_pointer
++; /* skip ',' or ':' */
1503 xtensa_elf_cons (4);
1505 xtensa_restore_emit_state (&state
);
1507 /* Restore the list of current labels. */
1508 xtensa_clear_insn_labels ();
1509 insn_labels
= saved_insn_labels
;
1514 xtensa_literal_prefix (char const *start
, int len
)
1516 char *name
, *linkonce_suffix
;
1517 char *newname
, *newname4
;
1518 size_t linkonce_len
;
1520 /* Get a null-terminated copy of the name. */
1521 name
= xmalloc (len
+ 1);
1524 strncpy (name
, start
, len
);
1527 /* Allocate the sections (interesting note: the memory pointing to
1528 the name is actually used for the name by the new section). */
1530 newname
= xmalloc (len
+ strlen (".literal") + 1);
1531 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1533 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1534 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1535 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1537 strcpy (newname
, ".gnu.linkonce.literal");
1538 strcpy (newname4
, ".gnu.linkonce.lit4");
1540 strcat (newname
, linkonce_suffix
);
1541 strcat (newname4
, linkonce_suffix
);
1545 int suffix_pos
= len
;
1547 /* If the section name ends with ".text", then replace that suffix
1548 instead of appending an additional suffix. */
1549 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1552 strcpy (newname
, name
);
1553 strcpy (newname4
, name
);
1555 strcpy (newname
+ suffix_pos
, ".literal");
1556 strcpy (newname4
+ suffix_pos
, ".lit4");
1559 /* Note that cache_literal_section does not create a segment if
1560 it already exists. */
1561 default_lit_sections
.lit_seg
= NULL
;
1562 default_lit_sections
.lit4_seg
= NULL
;
1564 /* Canonicalizing section names allows renaming literal
1565 sections to occur correctly. */
1566 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1567 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1573 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1576 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1578 float fall_through_f
, target_f
;
1580 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1581 if (fall_through_f
< 0)
1583 as_bad (_("fall through frequency must be greater than 0"));
1584 ignore_rest_of_line ();
1588 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1591 as_bad (_("branch target frequency must be greater than 0"));
1592 ignore_rest_of_line ();
1596 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1598 demand_empty_rest_of_line ();
1602 /* Like normal .long/.short/.word, except support @plt, etc.
1603 Clobbers input_line_pointer, checks end-of-line. */
1606 xtensa_elf_cons (int nbytes
)
1609 bfd_reloc_code_real_type reloc
;
1611 md_flush_pending_output ();
1613 if (cur_vinsn
.inside_bundle
)
1614 as_bad (_("directives are not valid inside bundles"));
1616 if (is_it_end_of_statement ())
1618 demand_empty_rest_of_line ();
1625 if (exp
.X_op
== O_symbol
1626 && *input_line_pointer
== '@'
1627 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1630 reloc_howto_type
*reloc_howto
=
1631 bfd_reloc_type_lookup (stdoutput
, reloc
);
1633 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1634 as_bad (_("unsupported relocation"));
1635 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1636 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1637 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1638 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1639 as_bad (_("opcode-specific %s relocation used outside "
1640 "an instruction"), reloc_howto
->name
);
1641 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1642 as_bad (_("%s relocations do not fit in %d bytes"),
1643 reloc_howto
->name
, nbytes
);
1646 char *p
= frag_more ((int) nbytes
);
1647 xtensa_set_frag_assembly_state (frag_now
);
1648 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1649 nbytes
, &exp
, 0, reloc
);
1653 emit_expr (&exp
, (unsigned int) nbytes
);
1655 while (*input_line_pointer
++ == ',');
1657 input_line_pointer
--; /* Put terminator back into stream. */
1658 demand_empty_rest_of_line ();
1662 /* Parsing and Idiom Translation. */
1664 /* Parse @plt, etc. and return the desired relocation. */
1665 static bfd_reloc_code_real_type
1666 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1672 bfd_reloc_code_real_type reloc
;
1680 struct map_bfd
*ptr
;
1682 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1684 static struct map_bfd mapping
[] =
1686 MAP ("l", BFD_RELOC_LO16
),
1687 MAP ("h", BFD_RELOC_HI16
),
1688 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1689 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1693 return BFD_RELOC_NONE
;
1695 for (ch
= *str
, str2
= ident
;
1696 (str2
< ident
+ sizeof (ident
) - 1
1697 && (ISALNUM (ch
) || ch
== '@'));
1700 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1707 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1708 if (ch
== ptr
->string
[0]
1709 && len
== ptr
->length
1710 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1712 /* Now check for "identifier@suffix+constant". */
1713 if (*str
== '-' || *str
== '+')
1715 char *orig_line
= input_line_pointer
;
1716 expressionS new_exp
;
1718 input_line_pointer
= str
;
1719 expression (&new_exp
);
1720 if (new_exp
.X_op
== O_constant
)
1722 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1723 str
= input_line_pointer
;
1726 if (&input_line_pointer
!= str_p
)
1727 input_line_pointer
= orig_line
;
1734 return BFD_RELOC_UNUSED
;
1739 expression_end (const char *name
)
1762 #define ERROR_REG_NUM ((unsigned) -1)
1765 tc_get_register (const char *prefix
)
1768 const char *next_expr
;
1769 const char *old_line_pointer
;
1772 old_line_pointer
= input_line_pointer
;
1774 if (*input_line_pointer
== '$')
1775 ++input_line_pointer
;
1777 /* Accept "sp" as a synonym for "a1". */
1778 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1779 && expression_end (input_line_pointer
+ 2))
1781 input_line_pointer
+= 2;
1782 return 1; /* AR[1] */
1785 while (*input_line_pointer
++ == *prefix
++)
1787 --input_line_pointer
;
1792 as_bad (_("bad register name: %s"), old_line_pointer
);
1793 return ERROR_REG_NUM
;
1796 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1798 as_bad (_("bad register number: %s"), input_line_pointer
);
1799 return ERROR_REG_NUM
;
1804 while (ISDIGIT ((int) *input_line_pointer
))
1805 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1807 if (!(next_expr
= expression_end (input_line_pointer
)))
1809 as_bad (_("bad register name: %s"), old_line_pointer
);
1810 return ERROR_REG_NUM
;
1813 input_line_pointer
= (char *) next_expr
;
1820 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1822 xtensa_isa isa
= xtensa_default_isa
;
1824 /* Check if this is an immediate operand. */
1825 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1827 bfd_reloc_code_real_type reloc
;
1828 segT t
= expression (tok
);
1829 if (t
== absolute_section
1830 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1832 assert (tok
->X_op
== O_constant
);
1833 tok
->X_op
= O_symbol
;
1834 tok
->X_add_symbol
= &abs_symbol
;
1837 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1838 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1839 && (reloc
!= BFD_RELOC_NONE
))
1844 case BFD_RELOC_UNUSED
:
1845 as_bad (_("unsupported relocation"));
1848 case BFD_RELOC_XTENSA_PLT
:
1849 tok
->X_op
= O_pltrel
;
1852 case BFD_RELOC_LO16
:
1853 if (tok
->X_op
== O_constant
)
1854 tok
->X_add_number
&= 0xffff;
1859 case BFD_RELOC_HI16
:
1860 if (tok
->X_op
== O_constant
)
1861 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1870 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1871 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1873 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1876 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1877 as_bad (_("register number out of range"));
1880 tok
->X_op
= O_register
;
1881 tok
->X_add_symbol
= 0;
1882 tok
->X_add_number
= reg
;
1887 /* Split up the arguments for an opcode or pseudo-op. */
1890 tokenize_arguments (char **args
, char *str
)
1892 char *old_input_line_pointer
;
1893 bfd_boolean saw_comma
= FALSE
;
1894 bfd_boolean saw_arg
= FALSE
;
1895 bfd_boolean saw_colon
= FALSE
;
1897 char *arg_end
, *arg
;
1900 /* Save and restore input_line_pointer around this function. */
1901 old_input_line_pointer
= input_line_pointer
;
1902 input_line_pointer
= str
;
1904 while (*input_line_pointer
)
1907 switch (*input_line_pointer
)
1914 input_line_pointer
++;
1915 if (saw_comma
|| saw_colon
|| !saw_arg
)
1921 input_line_pointer
++;
1922 if (saw_comma
|| saw_colon
|| !saw_arg
)
1928 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1931 arg_end
= input_line_pointer
+ 1;
1932 while (!expression_end (arg_end
))
1935 arg_len
= arg_end
- input_line_pointer
;
1936 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1937 args
[num_args
] = arg
;
1941 strncpy (arg
, input_line_pointer
, arg_len
);
1942 arg
[arg_len
] = '\0';
1944 input_line_pointer
= arg_end
;
1954 if (saw_comma
|| saw_colon
)
1956 input_line_pointer
= old_input_line_pointer
;
1961 as_bad (_("extra comma"));
1963 as_bad (_("extra colon"));
1965 as_bad (_("missing argument"));
1967 as_bad (_("missing comma or colon"));
1968 input_line_pointer
= old_input_line_pointer
;
1973 /* Parse the arguments to an opcode. Return TRUE on error. */
1976 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1978 expressionS
*tok
, *last_tok
;
1979 xtensa_opcode opcode
= insn
->opcode
;
1980 bfd_boolean had_error
= TRUE
;
1981 xtensa_isa isa
= xtensa_default_isa
;
1982 int n
, num_regs
= 0;
1983 int opcode_operand_count
;
1984 int opnd_cnt
, last_opnd_cnt
;
1985 unsigned int next_reg
= 0;
1986 char *old_input_line_pointer
;
1988 if (insn
->insn_type
== ITYPE_LITERAL
)
1989 opcode_operand_count
= 1;
1991 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1994 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1996 /* Save and restore input_line_pointer around this function. */
1997 old_input_line_pointer
= input_line_pointer
;
2003 /* Skip invisible operands. */
2004 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2010 for (n
= 0; n
< num_args
; n
++)
2012 input_line_pointer
= arg_strings
[n
];
2013 if (*input_line_pointer
== ':')
2015 xtensa_regfile opnd_rf
;
2016 input_line_pointer
++;
2019 assert (opnd_cnt
> 0);
2021 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2023 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2024 as_warn (_("incorrect register number, ignoring"));
2029 if (opnd_cnt
>= opcode_operand_count
)
2031 as_warn (_("too many arguments"));
2034 assert (opnd_cnt
< MAX_INSN_ARGS
);
2036 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2037 next_reg
= tok
->X_add_number
+ 1;
2039 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2041 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2043 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2044 /* minus 1 because we are seeing one right now */
2050 last_opnd_cnt
= opnd_cnt
;
2057 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2061 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2064 insn
->ntok
= tok
- insn
->tok
;
2068 input_line_pointer
= old_input_line_pointer
;
2074 get_invisible_operands (TInsn
*insn
)
2076 xtensa_isa isa
= xtensa_default_isa
;
2077 static xtensa_insnbuf slotbuf
= NULL
;
2079 xtensa_opcode opc
= insn
->opcode
;
2080 int slot
, opnd
, fmt_found
;
2084 slotbuf
= xtensa_insnbuf_alloc (isa
);
2086 /* Find format/slot where this can be encoded. */
2089 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2091 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2093 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2099 if (fmt_found
) break;
2104 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2108 /* First encode all the visible operands
2109 (to deal with shared field operands). */
2110 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2112 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2113 && (insn
->tok
[opnd
].X_op
== O_register
2114 || insn
->tok
[opnd
].X_op
== O_constant
))
2116 val
= insn
->tok
[opnd
].X_add_number
;
2117 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2118 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2122 /* Then pull out the values for the invisible ones. */
2123 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2125 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2127 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2128 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2129 insn
->tok
[opnd
].X_add_number
= val
;
2130 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2131 insn
->tok
[opnd
].X_op
= O_register
;
2133 insn
->tok
[opnd
].X_op
= O_constant
;
2142 xg_reverse_shift_count (char **cnt_argp
)
2144 char *cnt_arg
, *new_arg
;
2145 cnt_arg
= *cnt_argp
;
2147 /* replace the argument with "31-(argument)" */
2148 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2149 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2152 *cnt_argp
= new_arg
;
2156 /* If "arg" is a constant expression, return non-zero with the value
2160 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2163 char *save_ptr
= input_line_pointer
;
2165 input_line_pointer
= arg
;
2167 input_line_pointer
= save_ptr
;
2169 if (exp
.X_op
== O_constant
)
2171 *valp
= exp
.X_add_number
;
2180 xg_replace_opname (char **popname
, char *newop
)
2183 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2184 strcpy (*popname
, newop
);
2189 xg_check_num_args (int *pnum_args
,
2194 int num_args
= *pnum_args
;
2196 if (num_args
< expected_num
)
2198 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2199 num_args
, opname
, expected_num
);
2203 if (num_args
> expected_num
)
2205 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2206 num_args
, opname
, expected_num
);
2207 while (num_args
-- > expected_num
)
2209 free (arg_strings
[num_args
]);
2210 arg_strings
[num_args
] = 0;
2212 *pnum_args
= expected_num
;
2220 /* If the register is not specified as part of the opcode,
2221 then get it from the operand and move it to the opcode. */
2224 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 int is_user
, is_write
;
2231 bfd_boolean has_underbar
= FALSE
;
2236 has_underbar
= TRUE
;
2239 is_user
= (opname
[1] == 'u');
2240 is_write
= (opname
[0] == 'w');
2242 /* Opname == [rw]ur or [rwx]sr... */
2244 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2247 /* Check if the argument is a symbolic register name. */
2248 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2249 /* Handle WSR to "INTSET" as a special case. */
2250 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2251 && !strcasecmp (arg_strings
[1], "intset"))
2252 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2253 if (sr
== XTENSA_UNDEFINED
2254 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2256 /* Maybe it's a register number.... */
2258 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2260 as_bad (_("invalid register '%s' for '%s' instruction"),
2261 arg_strings
[1], opname
);
2264 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2265 if (sr
== XTENSA_UNDEFINED
)
2267 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2273 /* Remove the last argument, which is now part of the opcode. */
2274 free (arg_strings
[1]);
2278 /* Translate the opcode. */
2279 sr_name
= xtensa_sysreg_name (isa
, sr
);
2280 /* Another special case for "WSR.INTSET".... */
2281 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2283 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2284 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2287 *popname
= new_opname
;
2294 xtensa_translate_old_userreg_ops (char **popname
)
2296 xtensa_isa isa
= xtensa_default_isa
;
2298 char *opname
, *new_opname
;
2299 const char *sr_name
;
2300 bfd_boolean has_underbar
= FALSE
;
2303 if (opname
[0] == '_')
2305 has_underbar
= TRUE
;
2309 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2310 if (sr
!= XTENSA_UNDEFINED
)
2312 /* The new default name ("nnn") is different from the old default
2313 name ("URnnn"). The old default is handled below, and we don't
2314 want to recognize [RW]nnn, so do nothing if the name is the (new)
2316 static char namebuf
[10];
2317 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2318 if (strcmp (namebuf
, opname
+ 1) == 0)
2326 /* Only continue if the reg name is "URnnn". */
2327 if (opname
[1] != 'u' || opname
[2] != 'r')
2329 val
= strtoul (opname
+ 3, &end
, 10);
2333 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2334 if (sr
== XTENSA_UNDEFINED
)
2336 as_bad (_("invalid register number (%ld) for '%s'"),
2342 /* Translate the opcode. */
2343 sr_name
= xtensa_sysreg_name (isa
, sr
);
2344 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2345 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2346 opname
[0], sr_name
);
2348 *popname
= new_opname
;
2355 xtensa_translate_zero_immed (char *old_op
,
2365 assert (opname
[0] != '_');
2367 if (strcmp (opname
, old_op
) != 0)
2370 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2372 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2374 xg_replace_opname (popname
, new_op
);
2375 free (arg_strings
[1]);
2376 arg_strings
[1] = arg_strings
[2];
2385 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2386 Returns non-zero if an error was found. */
2389 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2391 char *opname
= *popname
;
2392 bfd_boolean has_underbar
= FALSE
;
2394 if (cur_vinsn
.inside_bundle
)
2399 has_underbar
= TRUE
;
2403 if (strcmp (opname
, "mov") == 0)
2405 if (use_transform () && !has_underbar
&& density_supported
)
2406 xg_replace_opname (popname
, "mov.n");
2409 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2411 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2412 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2413 strcpy (arg_strings
[2], arg_strings
[1]);
2419 if (strcmp (opname
, "bbsi.l") == 0)
2421 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2423 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2424 if (target_big_endian
)
2425 xg_reverse_shift_count (&arg_strings
[1]);
2429 if (strcmp (opname
, "bbci.l") == 0)
2431 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2433 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2434 if (target_big_endian
)
2435 xg_reverse_shift_count (&arg_strings
[1]);
2439 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2440 && strcmp (opname
, "nop") == 0)
2442 if (use_transform () && !has_underbar
&& density_supported
)
2443 xg_replace_opname (popname
, "nop.n");
2446 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2448 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2449 arg_strings
[0] = (char *) xmalloc (3);
2450 arg_strings
[1] = (char *) xmalloc (3);
2451 arg_strings
[2] = (char *) xmalloc (3);
2452 strcpy (arg_strings
[0], "a1");
2453 strcpy (arg_strings
[1], "a1");
2454 strcpy (arg_strings
[2], "a1");
2460 /* Recognize [RW]UR and [RWX]SR. */
2461 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2462 && (opname
[1] == 'u' || opname
[1] == 's'))
2463 || (opname
[0] == 'x' && opname
[1] == 's'))
2465 && opname
[3] == '\0')
2466 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2468 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2469 [RW]<name> if <name> is the non-default name of a user register. */
2470 if ((opname
[0] == 'r' || opname
[0] == 'w')
2471 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2472 return xtensa_translate_old_userreg_ops (popname
);
2474 /* Relax branches that don't allow comparisons against an immediate value
2475 of zero to the corresponding branches with implicit zero immediates. */
2476 if (!has_underbar
&& use_transform ())
2478 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2479 pnum_args
, arg_strings
))
2482 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2483 pnum_args
, arg_strings
))
2486 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2487 pnum_args
, arg_strings
))
2490 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2491 pnum_args
, arg_strings
))
2499 /* Functions for dealing with the Xtensa ISA. */
2501 /* Currently the assembler only allows us to use a single target per
2502 fragment. Because of this, only one operand for a given
2503 instruction may be symbolic. If there is a PC-relative operand,
2504 the last one is chosen. Otherwise, the result is the number of the
2505 last immediate operand, and if there are none of those, we fail and
2509 get_relaxable_immed (xtensa_opcode opcode
)
2511 int last_immed
= -1;
2514 if (opcode
== XTENSA_UNDEFINED
)
2517 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2518 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2520 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2522 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2524 if (last_immed
== -1
2525 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2532 static xtensa_opcode
2533 get_opcode_from_buf (const char *buf
, int slot
)
2535 static xtensa_insnbuf insnbuf
= NULL
;
2536 static xtensa_insnbuf slotbuf
= NULL
;
2537 xtensa_isa isa
= xtensa_default_isa
;
2542 insnbuf
= xtensa_insnbuf_alloc (isa
);
2543 slotbuf
= xtensa_insnbuf_alloc (isa
);
2546 xtensa_insnbuf_from_chars (isa
, insnbuf
, buf
, 0);
2547 fmt
= xtensa_format_decode (isa
, insnbuf
);
2548 if (fmt
== XTENSA_UNDEFINED
)
2549 return XTENSA_UNDEFINED
;
2551 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2552 return XTENSA_UNDEFINED
;
2554 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2555 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2559 #ifdef TENSILICA_DEBUG
2561 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2564 xtensa_print_insn_table (void)
2566 int num_opcodes
, num_operands
;
2567 xtensa_opcode opcode
;
2568 xtensa_isa isa
= xtensa_default_isa
;
2570 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2571 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2574 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2575 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2576 for (opn
= 0; opn
< num_operands
; opn
++)
2578 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2580 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2582 xtensa_regfile opnd_rf
=
2583 xtensa_operand_regfile (isa
, opcode
, opn
);
2584 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2586 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2587 fputs ("[lLr] ", stderr
);
2589 fputs ("i ", stderr
);
2591 fprintf (stderr
, "\n");
2597 print_vliw_insn (xtensa_insnbuf vbuf
)
2599 xtensa_isa isa
= xtensa_default_isa
;
2600 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2601 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2604 fprintf (stderr
, "format = %d\n", f
);
2606 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2608 xtensa_opcode opcode
;
2612 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2613 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2614 opname
= xtensa_opcode_name (isa
, opcode
);
2616 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2617 fprintf (stderr
, " operands = ");
2619 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2623 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2625 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2626 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2627 fprintf (stderr
, "%d ", val
);
2629 fprintf (stderr
, "\n");
2631 xtensa_insnbuf_free (isa
, sbuf
);
2634 #endif /* TENSILICA_DEBUG */
2638 is_direct_call_opcode (xtensa_opcode opcode
)
2640 xtensa_isa isa
= xtensa_default_isa
;
2641 int n
, num_operands
;
2643 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2646 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2647 for (n
= 0; n
< num_operands
; n
++)
2649 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2650 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2657 /* Convert from BFD relocation type code to slot and operand number.
2658 Returns non-zero on failure. */
2661 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2663 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2664 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2666 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2669 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2670 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2672 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2682 /* Convert from slot number to BFD relocation type code for the
2683 standard PC-relative relocations. Return BFD_RELOC_NONE on
2686 static bfd_reloc_code_real_type
2687 encode_reloc (int slot
)
2689 if (slot
< 0 || slot
> 14)
2690 return BFD_RELOC_NONE
;
2692 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2696 /* Convert from slot numbers to BFD relocation type code for the
2697 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2699 static bfd_reloc_code_real_type
2700 encode_alt_reloc (int slot
)
2702 if (slot
< 0 || slot
> 14)
2703 return BFD_RELOC_NONE
;
2705 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2710 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2713 xtensa_opcode opcode
,
2719 uint32 valbuf
= value
;
2721 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2723 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2725 as_bad_where ((char *) file
, line
,
2726 _("operand %u is out of range for '%s'"), value
,
2727 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2729 as_bad_where ((char *) file
, line
,
2730 _("operand %u is invalid for '%s'"), value
,
2731 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2735 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2741 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2744 xtensa_opcode opcode
,
2748 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2749 fmt
, slot
, slotbuf
, &val
);
2750 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2755 /* Checks for rules from xtensa-relax tables. */
2757 /* The routine xg_instruction_matches_option_term must return TRUE
2758 when a given option term is true. The meaning of all of the option
2759 terms is given interpretation by this function. This is needed when
2760 an option depends on the state of a directive, but there are no such
2761 options in use right now. */
2764 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2765 const ReqOrOption
*option
)
2767 if (strcmp (option
->option_name
, "realnop") == 0
2768 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2770 /* These conditions were evaluated statically when building the
2771 relaxation table. There's no need to reevaluate them now. */
2776 as_fatal (_("internal error: unknown option name '%s'"),
2777 option
->option_name
);
2783 xg_instruction_matches_or_options (TInsn
*insn
,
2784 const ReqOrOptionList
*or_option
)
2786 const ReqOrOption
*option
;
2787 /* Must match each of the AND terms. */
2788 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2790 if (xg_instruction_matches_option_term (insn
, option
))
2798 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2800 const ReqOption
*req_options
;
2801 /* Must match each of the AND terms. */
2802 for (req_options
= options
;
2803 req_options
!= NULL
;
2804 req_options
= req_options
->next
)
2806 /* Must match one of the OR clauses. */
2807 if (!xg_instruction_matches_or_options (insn
,
2808 req_options
->or_option_terms
))
2815 /* Return the transition rule that matches or NULL if none matches. */
2818 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2820 PreconditionList
*condition_l
;
2822 if (rule
->opcode
!= insn
->opcode
)
2825 for (condition_l
= rule
->conditions
;
2826 condition_l
!= NULL
;
2827 condition_l
= condition_l
->next
)
2831 Precondition
*cond
= condition_l
->precond
;
2836 /* The expression must be the constant. */
2837 assert (cond
->op_num
< insn
->ntok
);
2838 exp1
= &insn
->tok
[cond
->op_num
];
2839 if (expr_is_const (exp1
))
2844 if (get_expr_const (exp1
) != cond
->op_data
)
2848 if (get_expr_const (exp1
) == cond
->op_data
)
2855 else if (expr_is_register (exp1
))
2860 if (get_expr_register (exp1
) != cond
->op_data
)
2864 if (get_expr_register (exp1
) == cond
->op_data
)
2876 assert (cond
->op_num
< insn
->ntok
);
2877 assert (cond
->op_data
< insn
->ntok
);
2878 exp1
= &insn
->tok
[cond
->op_num
];
2879 exp2
= &insn
->tok
[cond
->op_data
];
2884 if (!expr_is_equal (exp1
, exp2
))
2888 if (expr_is_equal (exp1
, exp2
))
2900 if (!xg_instruction_matches_options (insn
, rule
->options
))
2908 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2910 bfd_boolean a_greater
= FALSE
;
2911 bfd_boolean b_greater
= FALSE
;
2913 ReqOptionList
*l_a
= a
->options
;
2914 ReqOptionList
*l_b
= b
->options
;
2916 /* We only care if they both are the same except for
2917 a const16 vs. an l32r. */
2919 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2921 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2922 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2923 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2925 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2927 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2929 /* This is the case we care about. */
2930 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2931 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2938 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2939 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2949 l_or_a
= l_or_a
->next
;
2950 l_or_b
= l_or_b
->next
;
2952 if (l_or_a
|| l_or_b
)
2961 /* Incomparable if the substitution was used differently in two cases. */
2962 if (a_greater
&& b_greater
)
2974 static TransitionRule
*
2975 xg_instruction_match (TInsn
*insn
)
2977 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2979 assert (insn
->opcode
< table
->num_opcodes
);
2981 /* Walk through all of the possible transitions. */
2982 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2984 TransitionRule
*rule
= l
->rule
;
2985 if (xg_instruction_matches_rule (insn
, rule
))
2992 /* Various Other Internal Functions. */
2995 is_unique_insn_expansion (TransitionRule
*r
)
2997 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2999 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3006 xg_get_build_instr_size (BuildInstr
*insn
)
3008 assert (insn
->typ
== INSTR_INSTR
);
3009 return xg_get_single_size (insn
->opcode
);
3014 xg_is_narrow_insn (TInsn
*insn
)
3016 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3019 assert (insn
->insn_type
== ITYPE_INSN
);
3020 assert (insn
->opcode
< table
->num_opcodes
);
3022 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3024 TransitionRule
*rule
= l
->rule
;
3026 if (xg_instruction_matches_rule (insn
, rule
)
3027 && is_unique_insn_expansion (rule
))
3029 /* It only generates one instruction... */
3030 assert (insn
->insn_type
== ITYPE_INSN
);
3031 /* ...and it is a larger instruction. */
3032 if (xg_get_single_size (insn
->opcode
)
3033 < xg_get_build_instr_size (rule
->to_instr
))
3041 return (num_match
== 1);
3046 xg_is_single_relaxable_insn (TInsn
*insn
)
3048 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3051 assert (insn
->insn_type
== ITYPE_INSN
);
3052 assert (insn
->opcode
< table
->num_opcodes
);
3054 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3056 TransitionRule
*rule
= l
->rule
;
3058 if (xg_instruction_matches_rule (insn
, rule
)
3059 && is_unique_insn_expansion (rule
))
3061 /* It only generates one instruction... */
3062 assert (insn
->insn_type
== ITYPE_INSN
);
3063 /* ... and it is a larger instruction. */
3064 if (xg_get_single_size (insn
->opcode
)
3065 <= xg_get_build_instr_size (rule
->to_instr
))
3073 return (num_match
== 1);
3077 /* Return the maximum number of bytes this opcode can expand to. */
3080 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3082 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3084 int max_size
= xg_get_single_size (opcode
);
3086 assert (opcode
< table
->num_opcodes
);
3088 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3090 TransitionRule
*rule
= l
->rule
;
3091 BuildInstr
*build_list
;
3096 build_list
= rule
->to_instr
;
3097 if (is_unique_insn_expansion (rule
))
3099 assert (build_list
->typ
== INSTR_INSTR
);
3100 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3103 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3105 switch (build_list
->typ
)
3108 this_size
+= xg_get_single_size (build_list
->opcode
);
3110 case INSTR_LITERAL_DEF
:
3111 case INSTR_LABEL_DEF
:
3116 if (this_size
> max_size
)
3117 max_size
= this_size
;
3123 /* Return the maximum number of literal bytes this opcode can generate. */
3126 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3128 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3132 assert (opcode
< table
->num_opcodes
);
3134 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3136 TransitionRule
*rule
= l
->rule
;
3137 BuildInstr
*build_list
;
3142 build_list
= rule
->to_instr
;
3143 if (is_unique_insn_expansion (rule
))
3145 assert (build_list
->typ
== INSTR_INSTR
);
3146 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3149 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3151 switch (build_list
->typ
)
3153 case INSTR_LITERAL_DEF
:
3154 /* Hard-coded 4-byte literal. */
3158 case INSTR_LABEL_DEF
:
3163 if (this_size
> max_size
)
3164 max_size
= this_size
;
3171 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3173 int steps_taken
= 0;
3174 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3177 assert (insn
->insn_type
== ITYPE_INSN
);
3178 assert (insn
->opcode
< table
->num_opcodes
);
3180 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3182 TransitionRule
*rule
= l
->rule
;
3184 if (xg_instruction_matches_rule (insn
, rule
))
3186 if (steps_taken
== lateral_steps
)
3196 get_special_literal_symbol (void)
3198 static symbolS
*sym
= NULL
;
3201 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3207 get_special_label_symbol (void)
3209 static symbolS
*sym
= NULL
;
3212 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3218 xg_valid_literal_expression (const expressionS
*exp
)
3235 /* This will check to see if the value can be converted into the
3236 operand type. It will return TRUE if it does not fit. */
3239 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3241 uint32 valbuf
= value
;
3242 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3248 /* Assumes: All immeds are constants. Check that all constants fit
3249 into their immeds; return FALSE if not. */
3252 xg_immeds_fit (const TInsn
*insn
)
3254 xtensa_isa isa
= xtensa_default_isa
;
3258 assert (insn
->insn_type
== ITYPE_INSN
);
3259 for (i
= 0; i
< n
; ++i
)
3261 const expressionS
*expr
= &insn
->tok
[i
];
3262 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3269 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3274 /* The symbol should have a fixup associated with it. */
3283 /* This should only be called after we have an initial
3284 estimate of the addresses. */
3287 xg_symbolic_immeds_fit (const TInsn
*insn
,
3293 xtensa_isa isa
= xtensa_default_isa
;
3301 assert (insn
->insn_type
== ITYPE_INSN
);
3303 for (i
= 0; i
< n
; ++i
)
3305 const expressionS
*expr
= &insn
->tok
[i
];
3306 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3313 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3319 /* Check for the worst case. */
3320 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3325 /* We only allow symbols for pc-relative stuff.
3326 If pc_frag == 0, then we don't have frag locations yet. */
3330 /* If it is PC-relative and the symbol is not in the same
3331 segment as the PC.... */
3332 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0
3333 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3336 /* If it is a weak symbol, then assume it won't reach. This will
3337 only affect calls when longcalls are enabled, because if
3338 longcalls are disabled, then the call is marked as a specific
3340 if (S_IS_WEAK (expr
->X_add_symbol
))
3343 symbolP
= expr
->X_add_symbol
;
3344 sym_frag
= symbol_get_frag (symbolP
);
3345 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3346 pc
= pc_frag
->fr_address
+ pc_offset
;
3348 /* If frag has yet to be reached on this pass, assume it
3349 will move by STRETCH just as we did. If this is not so,
3350 it will be because some frag between grows, and that will
3351 force another pass. Beware zero-length frags. There
3352 should be a faster way to do this. */
3355 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3356 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3361 new_offset
= target
;
3362 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3363 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3368 /* The symbol should have a fixup associated with it. */
3377 /* Return TRUE on success. */
3380 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3385 memset (targ
, 0, sizeof (TInsn
));
3386 targ
->loc
= insn
->loc
;
3391 targ
->opcode
= bi
->opcode
;
3392 targ
->insn_type
= ITYPE_INSN
;
3393 targ
->is_specific_opcode
= FALSE
;
3395 for (; op
!= NULL
; op
= op
->next
)
3397 int op_num
= op
->op_num
;
3398 int op_data
= op
->op_data
;
3400 assert (op
->op_num
< MAX_INSN_ARGS
);
3402 if (targ
->ntok
<= op_num
)
3403 targ
->ntok
= op_num
+ 1;
3408 set_expr_const (&targ
->tok
[op_num
], op_data
);
3411 assert (op_data
< insn
->ntok
);
3412 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3415 sym
= get_special_literal_symbol ();
3416 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3419 sym
= get_special_label_symbol ();
3420 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3422 case OP_OPERAND_HI16U
:
3423 case OP_OPERAND_LOW16U
:
3424 assert (op_data
< insn
->ntok
);
3425 if (expr_is_const (&insn
->tok
[op_data
]))
3428 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3429 val
= xg_apply_userdef_op_fn (op
->typ
,
3432 targ
->tok
[op_num
].X_add_number
= val
;
3436 /* For const16 we can create relocations for these. */
3437 if (targ
->opcode
== XTENSA_UNDEFINED
3438 || (targ
->opcode
!= xtensa_const16_opcode
))
3440 assert (op_data
< insn
->ntok
);
3441 /* Need to build a O_lo16 or O_hi16. */
3442 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3443 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3445 if (op
->typ
== OP_OPERAND_HI16U
)
3446 targ
->tok
[op_num
].X_op
= O_hi16
;
3447 else if (op
->typ
== OP_OPERAND_LOW16U
)
3448 targ
->tok
[op_num
].X_op
= O_lo16
;
3455 /* currently handles:
3458 OP_OPERAND_F32MINUS */
3459 if (xg_has_userdef_op_fn (op
->typ
))
3461 assert (op_data
< insn
->ntok
);
3462 if (expr_is_const (&insn
->tok
[op_data
]))
3465 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3466 val
= xg_apply_userdef_op_fn (op
->typ
,
3469 targ
->tok
[op_num
].X_add_number
= val
;
3472 return FALSE
; /* We cannot use a relocation for this. */
3481 case INSTR_LITERAL_DEF
:
3483 targ
->opcode
= XTENSA_UNDEFINED
;
3484 targ
->insn_type
= ITYPE_LITERAL
;
3485 targ
->is_specific_opcode
= FALSE
;
3486 for (; op
!= NULL
; op
= op
->next
)
3488 int op_num
= op
->op_num
;
3489 int op_data
= op
->op_data
;
3490 assert (op
->op_num
< MAX_INSN_ARGS
);
3492 if (targ
->ntok
<= op_num
)
3493 targ
->ntok
= op_num
+ 1;
3498 assert (op_data
< insn
->ntok
);
3499 /* We can only pass resolvable literals through. */
3500 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3502 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3514 case INSTR_LABEL_DEF
:
3516 targ
->opcode
= XTENSA_UNDEFINED
;
3517 targ
->insn_type
= ITYPE_LABEL
;
3518 targ
->is_specific_opcode
= FALSE
;
3519 /* Literal with no ops is a label? */
3520 assert (op
== NULL
);
3531 /* Return TRUE on success. */
3534 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3536 for (; bi
!= NULL
; bi
= bi
->next
)
3538 TInsn
*next_insn
= istack_push_space (istack
);
3540 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3547 /* Return TRUE on valid expansion. */
3550 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3552 int stack_size
= istack
->ninsn
;
3553 int steps_taken
= 0;
3554 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3557 assert (insn
->insn_type
== ITYPE_INSN
);
3558 assert (insn
->opcode
< table
->num_opcodes
);
3560 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3562 TransitionRule
*rule
= l
->rule
;
3564 if (xg_instruction_matches_rule (insn
, rule
))
3566 if (lateral_steps
== steps_taken
)
3570 /* This is it. Expand the rule to the stack. */
3571 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3574 /* Check to see if it fits. */
3575 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3577 TInsn
*insn
= &istack
->insn
[i
];
3579 if (insn
->insn_type
== ITYPE_INSN
3580 && !tinsn_has_symbolic_operands (insn
)
3581 && !xg_immeds_fit (insn
))
3583 istack
->ninsn
= stack_size
;
3597 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3599 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3602 assert (insn
->insn_type
== ITYPE_INSN
);
3603 assert (insn
->opcode
< table
->num_opcodes
);
3605 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3607 TransitionRule
*rule
= l
->rule
;
3608 if (xg_instruction_matches_rule (insn
, rule
)
3609 && is_unique_insn_expansion (rule
))
3611 /* Is it a larger instruction? */
3612 if (xg_get_single_size (insn
->opcode
)
3613 <= xg_get_build_instr_size (rule
->to_instr
))
3615 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3624 /* Relax the assembly instruction at least "min_steps".
3625 Return the number of steps taken. */
3628 xg_assembly_relax (IStack
*istack
,
3631 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3632 offsetT pc_offset
, /* offset in fragment */
3633 int min_steps
, /* minimum conversion steps */
3634 long stretch
) /* number of bytes stretched so far */
3636 int steps_taken
= 0;
3638 /* assert (has no symbolic operands)
3639 Some of its immeds don't fit.
3640 Try to build a relaxed version.
3641 This may go through a couple of stages
3642 of single instruction transformations before
3645 TInsn single_target
;
3647 int lateral_steps
= 0;
3648 int istack_size
= istack
->ninsn
;
3650 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3651 && steps_taken
>= min_steps
)
3653 istack_push (istack
, insn
);
3656 current_insn
= *insn
;
3658 /* Walk through all of the single instruction expansions. */
3659 while (xg_is_single_relaxable_insn (¤t_insn
))
3661 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3663 assert (!error_val
);
3665 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3669 if (steps_taken
>= min_steps
)
3671 istack_push (istack
, &single_target
);
3675 current_insn
= single_target
;
3678 /* Now check for a multi-instruction expansion. */
3679 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3681 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3684 if (steps_taken
>= min_steps
)
3686 istack_push (istack
, ¤t_insn
);
3691 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3693 if (steps_taken
>= min_steps
)
3697 istack
->ninsn
= istack_size
;
3700 /* It's not going to work -- use the original. */
3701 istack_push (istack
, insn
);
3707 xg_force_frag_space (int size
)
3709 /* This may have the side effect of creating a new fragment for the
3710 space to go into. I just do not like the name of the "frag"
3717 xg_finish_frag (char *last_insn
,
3718 enum xtensa_relax_statesE frag_state
,
3719 enum xtensa_relax_statesE slot0_state
,
3721 bfd_boolean is_insn
)
3723 /* Finish off this fragment so that it has at LEAST the desired
3724 max_growth. If it doesn't fit in this fragment, close this one
3725 and start a new one. In either case, return a pointer to the
3726 beginning of the growth area. */
3730 xg_force_frag_space (max_growth
);
3732 old_frag
= frag_now
;
3734 frag_now
->fr_opcode
= last_insn
;
3736 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3738 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3739 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3741 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3742 xtensa_set_frag_assembly_state (frag_now
);
3744 /* Just to make sure that we did not split it up. */
3745 assert (old_frag
->fr_next
== frag_now
);
3749 /* Return TRUE if the target frag is one of the next non-empty frags. */
3752 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3757 for (; fragP
; fragP
= fragP
->fr_next
)
3759 if (fragP
== target
)
3761 if (fragP
->fr_fix
!= 0)
3763 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3765 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3766 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3768 if (fragP
->fr_type
== rs_space
)
3776 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3778 xtensa_isa isa
= xtensa_default_isa
;
3780 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3785 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3786 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3789 for (i
= 0; i
< num_ops
; i
++)
3791 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3797 if (target_op
== -1)
3800 if (insn
->ntok
<= target_op
)
3803 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3806 sym
= insn
->tok
[target_op
].X_add_symbol
;
3810 if (insn
->tok
[target_op
].X_add_number
!= 0)
3813 target_frag
= symbol_get_frag (sym
);
3814 if (target_frag
== NULL
)
3817 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3818 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3826 xg_add_branch_and_loop_targets (TInsn
*insn
)
3828 xtensa_isa isa
= xtensa_default_isa
;
3829 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3831 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3834 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3835 && insn
->tok
[i
].X_op
== O_symbol
)
3836 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3840 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3841 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3845 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3847 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3848 && insn
->tok
[i
].X_op
== O_symbol
)
3850 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3851 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3852 if (S_IS_DEFINED (sym
))
3853 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3860 /* Return FALSE if no error. */
3863 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3868 switch (instr_spec
->typ
)
3871 new_insn
->insn_type
= ITYPE_INSN
;
3872 new_insn
->opcode
= instr_spec
->opcode
;
3873 new_insn
->is_specific_opcode
= FALSE
;
3874 new_insn
->loc
= old_insn
->loc
;
3876 case INSTR_LITERAL_DEF
:
3877 new_insn
->insn_type
= ITYPE_LITERAL
;
3878 new_insn
->opcode
= XTENSA_UNDEFINED
;
3879 new_insn
->is_specific_opcode
= FALSE
;
3880 new_insn
->loc
= old_insn
->loc
;
3882 case INSTR_LABEL_DEF
:
3883 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3887 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3890 const expressionS
*src_exp
;
3896 /* The expression must be the constant. */
3897 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3898 exp
= &new_insn
->tok
[b_op
->op_num
];
3899 set_expr_const (exp
, b_op
->op_data
);
3903 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3904 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3905 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3906 exp
= &new_insn
->tok
[b_op
->op_num
];
3907 copy_expr (exp
, src_exp
);
3912 as_bad (_("can't handle generation of literal/labels yet"));
3916 as_bad (_("can't handle undefined OP TYPE"));
3921 new_insn
->ntok
= num_ops
;
3926 /* Return TRUE if it was simplified. */
3929 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3931 TransitionRule
*rule
;
3932 BuildInstr
*insn_spec
;
3934 if (old_insn
->is_specific_opcode
|| !density_supported
)
3937 rule
= xg_instruction_match (old_insn
);
3941 insn_spec
= rule
->to_instr
;
3942 /* There should only be one. */
3943 assert (insn_spec
!= NULL
);
3944 assert (insn_spec
->next
== NULL
);
3945 if (insn_spec
->next
!= NULL
)
3948 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3954 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3955 l32i.n. (2) Check the number of operands. (3) Place the instruction
3956 tokens into the stack or if we can relax it at assembly time, place
3957 multiple instructions/literals onto the stack. Return FALSE if no
3961 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3965 memset (&new_insn
, 0, sizeof (TInsn
));
3967 /* Narrow it if we can. xg_simplify_insn now does all the
3968 appropriate checking (e.g., for the density option). */
3969 if (xg_simplify_insn (orig_insn
, &new_insn
))
3970 orig_insn
= &new_insn
;
3972 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3974 if (orig_insn
->ntok
< noperands
)
3976 as_bad (_("found %d operands for '%s': Expected %d"),
3978 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3982 if (orig_insn
->ntok
> noperands
)
3983 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3985 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3988 /* If there are not enough operands, we will assert above. If there
3989 are too many, just cut out the extras here. */
3991 orig_insn
->ntok
= noperands
;
3995 Instructions with all constant immeds:
3996 Assemble them and relax the instruction if possible.
3997 Give error if not possible; no fixup needed.
3999 Instructions with symbolic immeds:
4000 Assemble them with a Fix up (that may cause instruction expansion).
4001 Also close out the fragment if the fixup may cause instruction expansion.
4003 There are some other special cases where we need alignment.
4004 1) before certain instructions with required alignment (OPCODE_ALIGN)
4005 2) before labels that have jumps (LABEL_ALIGN)
4006 3) after call instructions (RETURN_ALIGN)
4007 Multiple of these may be possible on the same fragment.
4008 If so, make sure to satisfy the required alignment.
4009 Then try to get the desired alignment. */
4011 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4014 if (orig_insn
->is_specific_opcode
|| !use_transform ())
4016 istack_push (istack
, orig_insn
);
4020 if (tinsn_has_symbolic_operands (orig_insn
))
4022 if (tinsn_has_complex_operands (orig_insn
))
4023 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4025 istack_push (istack
, orig_insn
);
4029 if (xg_immeds_fit (orig_insn
))
4030 istack_push (istack
, orig_insn
);
4032 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4039 /* Return TRUE if the section flags are marked linkonce
4040 or the name is .gnu.linkonce*. */
4043 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4045 flagword flags
, link_once_flags
;
4047 flags
= bfd_get_section_flags (abfd
, sec
);
4048 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4050 /* Flags might not be set yet. */
4051 if (!link_once_flags
)
4053 static size_t len
= sizeof ".gnu.linkonce.t.";
4055 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4056 link_once_flags
= SEC_LINK_ONCE
;
4058 return (link_once_flags
!= 0);
4063 xtensa_add_literal_sym (symbolS
*sym
)
4067 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4069 l
->next
= literal_syms
;
4075 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4077 static int lit_num
= 0;
4078 static char name
[256];
4081 sprintf (name
, ".L_lit_sym%d", lit_num
);
4083 /* Create a local symbol. If it is in a linkonce section, we have to
4084 be careful to make sure that if it is used in a relocation that the
4085 symbol will be in the output file. */
4086 if (get_is_linkonce_section (stdoutput
, sec
))
4088 symbolP
= symbol_new (name
, sec
, 0, frag
);
4089 S_CLEAR_EXTERNAL (symbolP
);
4090 /* symbolP->local = 1; */
4093 symbolP
= symbol_new (name
, sec
, 0, frag
);
4095 xtensa_add_literal_sym (symbolP
);
4097 frag
->tc_frag_data
.is_literal
= TRUE
;
4103 /* Currently all literals that are generated here are 32-bit L32R targets. */
4106 xg_assemble_literal (/* const */ TInsn
*insn
)
4109 symbolS
*lit_sym
= NULL
;
4111 /* size = 4 for L32R. It could easily be larger when we move to
4112 larger constants. Add a parameter later. */
4113 offsetT litsize
= 4;
4114 offsetT litalign
= 2; /* 2^2 = 4 */
4115 expressionS saved_loc
;
4116 expressionS
* emit_val
;
4118 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4120 assert (insn
->insn_type
== ITYPE_LITERAL
);
4121 assert (insn
->ntok
== 1); /* must be only one token here */
4123 xtensa_switch_to_literal_fragment (&state
);
4125 emit_val
= &insn
->tok
[0];
4126 if (emit_val
->X_op
== O_big
)
4128 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4131 /* This happens when someone writes a "movi a2, big_number". */
4132 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4133 _("invalid immediate"));
4134 xtensa_restore_emit_state (&state
);
4139 /* Force a 4-byte align here. Note that this opens a new frag, so all
4140 literals done with this function have a frag to themselves. That's
4141 important for the way text section literals work. */
4142 frag_align (litalign
, 0, 0);
4143 record_alignment (now_seg
, litalign
);
4145 if (emit_val
->X_op
== O_pltrel
)
4147 char *p
= frag_more (litsize
);
4148 xtensa_set_frag_assembly_state (frag_now
);
4149 if (emit_val
->X_add_symbol
)
4150 emit_val
->X_op
= O_symbol
;
4152 emit_val
->X_op
= O_constant
;
4153 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4154 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4157 emit_expr (emit_val
, litsize
);
4159 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4160 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4161 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4162 lit_sym
= frag_now
->fr_symbol
;
4163 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4166 xtensa_restore_emit_state (&state
);
4172 xg_assemble_literal_space (/* const */ int size
, int slot
)
4175 /* We might have to do something about this alignment. It only
4176 takes effect if something is placed here. */
4177 offsetT litalign
= 2; /* 2^2 = 4 */
4178 fragS
*lit_saved_frag
;
4180 assert (size
% 4 == 0);
4182 xtensa_switch_to_literal_fragment (&state
);
4184 /* Force a 4-byte align here. */
4185 frag_align (litalign
, 0, 0);
4186 record_alignment (now_seg
, litalign
);
4188 xg_force_frag_space (size
);
4190 lit_saved_frag
= frag_now
;
4191 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4192 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4193 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4194 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4197 xtensa_restore_emit_state (&state
);
4198 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4202 /* Put in a fixup record based on the opcode.
4203 Return TRUE on success. */
4206 xg_add_opcode_fix (TInsn
*tinsn
,
4214 xtensa_opcode opcode
= tinsn
->opcode
;
4215 bfd_reloc_code_real_type reloc
;
4216 reloc_howto_type
*howto
;
4220 reloc
= BFD_RELOC_NONE
;
4222 /* First try the special cases for "alternate" relocs. */
4223 if (opcode
== xtensa_l32r_opcode
)
4225 if (fragP
->tc_frag_data
.use_absolute_literals
)
4226 reloc
= encode_alt_reloc (slot
);
4228 else if (opcode
== xtensa_const16_opcode
)
4230 if (expr
->X_op
== O_lo16
)
4232 reloc
= encode_reloc (slot
);
4233 expr
->X_op
= O_symbol
;
4235 else if (expr
->X_op
== O_hi16
)
4237 reloc
= encode_alt_reloc (slot
);
4238 expr
->X_op
= O_symbol
;
4242 if (opnum
!= get_relaxable_immed (opcode
))
4244 as_bad (_("invalid relocation for operand %i of '%s'"),
4245 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4249 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4250 into the symbol table where the generic portions of the assembler
4251 won't know what to do with them. */
4252 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4254 as_bad (_("invalid expression for operand %i of '%s'"),
4255 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4259 /* Next try the generic relocs. */
4260 if (reloc
== BFD_RELOC_NONE
)
4261 reloc
= encode_reloc (slot
);
4262 if (reloc
== BFD_RELOC_NONE
)
4264 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4268 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4271 as_bad (_("undefined symbol for opcode \"%s\""),
4272 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4276 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4277 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4278 howto
->pc_relative
, reloc
);
4280 if (expr
->X_add_symbol
4281 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4282 || S_IS_WEAK (expr
->X_add_symbol
)))
4283 the_fix
->fx_plt
= TRUE
;
4285 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4286 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4287 the_fix
->tc_fix_data
.slot
= slot
;
4294 xg_emit_insn_to_buf (TInsn
*tinsn
,
4299 bfd_boolean build_fix
)
4301 static xtensa_insnbuf insnbuf
= NULL
;
4302 bfd_boolean has_symbolic_immed
= FALSE
;
4303 bfd_boolean ok
= TRUE
;
4305 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4307 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4308 if (has_symbolic_immed
&& build_fix
)
4311 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4312 expressionS
*exp
= &tinsn
->tok
[opnum
];
4314 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4317 fragP
->tc_frag_data
.is_insn
= TRUE
;
4318 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4324 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4326 symbolS
*sym
= get_special_literal_symbol ();
4330 assert (insn
->insn_type
== ITYPE_INSN
);
4331 for (i
= 0; i
< insn
->ntok
; i
++)
4332 if (insn
->tok
[i
].X_add_symbol
== sym
)
4333 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4339 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4341 symbolS
*sym
= get_special_label_symbol ();
4343 /* assert (!insn->is_literal); */
4344 for (i
= 0; i
< insn
->ntok
; i
++)
4345 if (insn
->tok
[i
].X_add_symbol
== sym
)
4346 insn
->tok
[i
].X_add_symbol
= label_sym
;
4351 /* Return TRUE if the instruction can write to the specified
4352 integer register. */
4355 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4359 xtensa_isa isa
= xtensa_default_isa
;
4361 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4363 for (i
= 0; i
< num_ops
; i
++)
4366 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4367 if ((inout
== 'o' || inout
== 'm')
4368 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4370 xtensa_regfile opnd_rf
=
4371 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4372 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4374 if ((insn
->tok
[i
].X_op
== O_register
)
4375 && (insn
->tok
[i
].X_add_number
== regnum
))
4385 is_bad_loopend_opcode (const TInsn
*tinsn
)
4387 xtensa_opcode opcode
= tinsn
->opcode
;
4389 if (opcode
== XTENSA_UNDEFINED
)
4392 if (opcode
== xtensa_call0_opcode
4393 || opcode
== xtensa_callx0_opcode
4394 || opcode
== xtensa_call4_opcode
4395 || opcode
== xtensa_callx4_opcode
4396 || opcode
== xtensa_call8_opcode
4397 || opcode
== xtensa_callx8_opcode
4398 || opcode
== xtensa_call12_opcode
4399 || opcode
== xtensa_callx12_opcode
4400 || opcode
== xtensa_isync_opcode
4401 || opcode
== xtensa_ret_opcode
4402 || opcode
== xtensa_ret_n_opcode
4403 || opcode
== xtensa_retw_opcode
4404 || opcode
== xtensa_retw_n_opcode
4405 || opcode
== xtensa_waiti_opcode
4406 || opcode
== xtensa_rsr_lcount_opcode
)
4413 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4414 This allows the debugger to add unaligned labels.
4415 Also, the assembler generates stabs labels that need
4416 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4419 is_unaligned_label (symbolS
*sym
)
4421 const char *name
= S_GET_NAME (sym
);
4422 static size_t fake_size
= 0;
4426 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4429 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4431 fake_size
= strlen (FAKE_LABEL_NAME
);
4434 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4435 && (name
[fake_size
] == 'F'
4436 || name
[fake_size
] == 'L'
4437 || (name
[fake_size
] == 'e'
4438 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4446 next_non_empty_frag (const fragS
*fragP
)
4448 fragS
*next_fragP
= fragP
->fr_next
;
4450 /* Sometimes an empty will end up here due storage allocation issues.
4451 So we have to skip until we find something legit. */
4452 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4453 next_fragP
= next_fragP
->fr_next
;
4455 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4463 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4465 xtensa_opcode out_opcode
;
4466 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4468 if (next_fragP
== NULL
)
4471 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4472 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4474 *opcode
= out_opcode
;
4482 frag_format_size (const fragS
*fragP
)
4484 static xtensa_insnbuf insnbuf
= NULL
;
4485 xtensa_isa isa
= xtensa_default_isa
;
4490 insnbuf
= xtensa_insnbuf_alloc (isa
);
4493 return XTENSA_UNDEFINED
;
4495 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
, 0);
4497 fmt
= xtensa_format_decode (isa
, insnbuf
);
4498 if (fmt
== XTENSA_UNDEFINED
)
4499 return XTENSA_UNDEFINED
;
4500 fmt_size
= xtensa_format_length (isa
, fmt
);
4502 /* If the next format won't be changing due to relaxation, just
4503 return the length of the first format. */
4504 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4507 /* If during relaxation we have to pull an instruction out of a
4508 multi-slot instruction, we will return the more conservative
4509 number. This works because alignment on bigger instructions
4510 is more restrictive than alignment on smaller instructions.
4511 This is more conservative than we would like, but it happens
4514 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4517 /* If we aren't doing one of our own relaxations or it isn't
4518 slot-based, then the insn size won't change. */
4519 if (fragP
->fr_type
!= rs_machine_dependent
)
4521 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4524 /* If an instruction is about to grow, return the longer size. */
4525 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4526 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4529 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4530 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4537 next_frag_format_size (const fragS
*fragP
)
4539 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4540 return frag_format_size (next_fragP
);
4544 /* If the next legit fragment is an end-of-loop marker,
4545 switch its state so it will instantiate a NOP. */
4548 update_next_frag_state (fragS
*fragP
, bfd_boolean unreachable
)
4550 fragS
*next_fragP
= fragP
->fr_next
;
4551 fragS
*new_target
= NULL
;
4555 /* We are guaranteed there will be one of these... */
4556 while (!(next_fragP
->fr_type
== rs_machine_dependent
4557 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4558 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4559 next_fragP
= next_fragP
->fr_next
;
4561 assert (next_fragP
->fr_type
== rs_machine_dependent
4562 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4563 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4565 /* ...and one of these. */
4566 new_target
= next_fragP
->fr_next
;
4567 while (!(new_target
->fr_type
== rs_machine_dependent
4568 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4569 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4570 new_target
= new_target
->fr_next
;
4572 assert (new_target
->fr_type
== rs_machine_dependent
4573 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4574 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4580 next_fragP
->fr_subtype
= RELAX_UNREACHABLE
;
4581 next_fragP
->tc_frag_data
.is_unreachable
= TRUE
;
4582 new_target
->fr_subtype
= RELAX_DESIRE_ALIGN
;
4583 new_target
->tc_frag_data
.is_branch_target
= TRUE
;
4585 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4587 if (next_fragP
->fr_type
== rs_machine_dependent
4588 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4590 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4594 next_fragP
= next_fragP
->fr_next
;
4601 next_fragP
->fr_subtype
= RELAX_MAYBE_UNREACHABLE
;
4602 next_fragP
->tc_frag_data
.is_unreachable
= FALSE
;
4603 new_target
->fr_subtype
= RELAX_MAYBE_DESIRE_ALIGN
;
4604 new_target
->tc_frag_data
.is_branch_target
= FALSE
;
4611 next_frag_is_branch_target (const fragS
*fragP
)
4613 /* Sometimes an empty will end up here due to storage allocation issues,
4614 so we have to skip until we find something legit. */
4615 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4617 if (fragP
->tc_frag_data
.is_branch_target
)
4619 if (fragP
->fr_fix
!= 0)
4627 next_frag_is_loop_target (const fragS
*fragP
)
4629 /* Sometimes an empty will end up here due storage allocation issues.
4630 So we have to skip until we find something legit. */
4631 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4633 if (fragP
->tc_frag_data
.is_loop_target
)
4635 if (fragP
->fr_fix
!= 0)
4643 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4645 const fragS
*next_fragp
= fragp
->fr_next
;
4646 xtensa_opcode next_opcode
;
4648 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4651 /* Sometimes an empty will end up here due to storage allocation issues,
4652 so we have to skip until we find something legit. */
4653 while (next_fragp
->fr_fix
== 0)
4654 next_fragp
= next_fragp
->fr_next
;
4656 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4659 /* There is some implicit knowledge encoded in here.
4660 The LOOP instructions that are NOT RELAX_IMMED have
4661 been relaxed. Note that we can assume that the LOOP
4662 instruction is in slot 0 because loops aren't bundleable. */
4663 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4664 return get_expanded_loop_offset (next_opcode
);
4670 /* Mark a location where we can later insert literal frags. Update
4671 the section's literal_pool_loc, so subsequent literals can be
4672 placed nearest to their use. */
4675 xtensa_mark_literal_pool_location (void)
4677 /* Any labels pointing to the current location need
4678 to be adjusted to after the literal pool. */
4680 fragS
*pool_location
;
4682 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4685 frag_align (2, 0, 0);
4686 record_alignment (now_seg
, 2);
4688 /* We stash info in the fr_var of these frags
4689 so we can later move the literal's fixes into this
4690 frchain's fix list. We can use fr_var because fr_var's
4691 interpretation depends solely on the fr_type and subtype. */
4692 pool_location
= frag_now
;
4693 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
4694 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4695 xtensa_set_frag_assembly_state (frag_now
);
4696 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
4697 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4698 xtensa_set_frag_assembly_state (frag_now
);
4700 /* Now put a frag into the literal pool that points to this location. */
4701 set_literal_pool_location (now_seg
, pool_location
);
4702 xtensa_switch_to_non_abs_literal_fragment (&s
);
4703 frag_align (2, 0, 0);
4704 record_alignment (now_seg
, 2);
4706 /* Close whatever frag is there. */
4707 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4708 xtensa_set_frag_assembly_state (frag_now
);
4709 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4710 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4711 xtensa_restore_emit_state (&s
);
4712 xtensa_set_frag_assembly_state (frag_now
);
4716 /* Build a nop of the correct size into tinsn. */
4719 build_nop (TInsn
*tinsn
, int size
)
4725 tinsn
->opcode
= xtensa_nop_n_opcode
;
4727 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4728 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4732 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4734 tinsn
->opcode
= xtensa_or_opcode
;
4735 set_expr_const (&tinsn
->tok
[0], 1);
4736 set_expr_const (&tinsn
->tok
[1], 1);
4737 set_expr_const (&tinsn
->tok
[2], 1);
4741 tinsn
->opcode
= xtensa_nop_opcode
;
4743 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4748 /* Assemble a NOP of the requested size in the buffer. User must have
4749 allocated "buf" with at least "size" bytes. */
4752 assemble_nop (size_t size
, char *buf
)
4754 static xtensa_insnbuf insnbuf
= NULL
;
4757 build_nop (&tinsn
, size
);
4760 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4762 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4763 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4767 /* Return the number of bytes for the offset of the expanded loop
4768 instruction. This should be incorporated into the relaxation
4769 specification but is hard-coded here. This is used to auto-align
4770 the loop instruction. It is invalid to call this function if the
4771 configuration does not have loops or if the opcode is not a loop
4775 get_expanded_loop_offset (xtensa_opcode opcode
)
4777 /* This is the OFFSET of the loop instruction in the expanded loop.
4778 This MUST correspond directly to the specification of the loop
4779 expansion. It will be validated on fragment conversion. */
4780 assert (opcode
!= XTENSA_UNDEFINED
);
4781 if (opcode
== xtensa_loop_opcode
)
4783 if (opcode
== xtensa_loopnez_opcode
)
4785 if (opcode
== xtensa_loopgtz_opcode
)
4787 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4793 get_literal_pool_location (segT seg
)
4795 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4800 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4802 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4806 /* Set frag assembly state should be called when a new frag is
4807 opened and after a frag has been closed. */
4810 xtensa_set_frag_assembly_state (fragS
*fragP
)
4812 if (!density_supported
)
4813 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4815 /* This function is called from subsegs_finish, which is called
4816 after xtensa_end, so we can't use "use_transform" or
4817 "use_schedule" here. */
4818 if (!directive_state
[directive_transform
])
4819 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4820 fragP
->tc_frag_data
.use_absolute_literals
=
4821 directive_state
[directive_absolute_literals
];
4822 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4827 relaxable_section (asection
*sec
)
4829 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4834 xtensa_find_unmarked_state_frags (void)
4838 /* Walk over each fragment of all of the current segments. For each
4839 unmarked fragment, mark it with the same info as the previous
4841 for (seclist
= &stdoutput
->sections
;
4842 seclist
&& *seclist
;
4843 seclist
= &(*seclist
)->next
)
4845 segT sec
= *seclist
;
4846 segment_info_type
*seginfo
;
4849 flags
= bfd_get_section_flags (stdoutput
, sec
);
4850 if (flags
& SEC_DEBUGGING
)
4852 if (!(flags
& SEC_ALLOC
))
4855 seginfo
= seg_info (sec
);
4856 if (seginfo
&& seginfo
->frchainP
)
4858 fragS
*last_fragP
= 0;
4859 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4860 fragP
= fragP
->fr_next
)
4862 if (fragP
->fr_fix
!= 0
4863 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4865 if (last_fragP
== 0)
4867 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4868 _("assembly state not set for first frag in section %s"),
4873 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4874 fragP
->tc_frag_data
.is_no_density
=
4875 last_fragP
->tc_frag_data
.is_no_density
;
4876 fragP
->tc_frag_data
.is_no_transform
=
4877 last_fragP
->tc_frag_data
.is_no_transform
;
4878 fragP
->tc_frag_data
.use_absolute_literals
=
4879 last_fragP
->tc_frag_data
.use_absolute_literals
;
4882 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4891 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4893 void *unused ATTRIBUTE_UNUSED
)
4895 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4896 segment_info_type
*seginfo
= seg_info (sec
);
4897 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4899 if (flags
& SEC_CODE
)
4901 xtensa_isa isa
= xtensa_default_isa
;
4902 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4903 while (frag
!= NULL
)
4905 if (frag
->tc_frag_data
.is_branch_target
)
4911 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4912 fmt
= xtensa_format_decode (isa
, insnbuf
);
4913 op_size
= xtensa_format_length (isa
, fmt
);
4914 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4915 if (frag_addr
+ op_size
> (int) xtensa_fetch_width
)
4916 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4917 _("unaligned branch target: %d bytes at 0x%lx"),
4918 op_size
, frag
->fr_address
);
4920 frag
= frag
->fr_next
;
4922 xtensa_insnbuf_free (isa
, insnbuf
);
4928 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4930 void *unused ATTRIBUTE_UNUSED
)
4932 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4933 segment_info_type
*seginfo
= seg_info (sec
);
4934 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4935 xtensa_isa isa
= xtensa_default_isa
;
4937 if (flags
& SEC_CODE
)
4939 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4940 while (frag
!= NULL
)
4942 if (frag
->tc_frag_data
.is_first_loop_insn
)
4948 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4949 fmt
= xtensa_format_decode (isa
, insnbuf
);
4950 op_size
= xtensa_format_length (isa
, fmt
);
4951 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4953 if (frag_addr
+ op_size
> (signed) xtensa_fetch_width
)
4954 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4955 _("unaligned loop: %d bytes at 0x%lx"),
4956 op_size
, frag
->fr_address
);
4958 frag
= frag
->fr_next
;
4960 xtensa_insnbuf_free (isa
, insnbuf
);
4966 xg_apply_tentative_value (fixS
*fixP
, valueT val
)
4968 xtensa_isa isa
= xtensa_default_isa
;
4969 static xtensa_insnbuf insnbuf
= NULL
;
4970 static xtensa_insnbuf slotbuf
= NULL
;
4973 bfd_boolean alt_reloc
;
4974 xtensa_opcode opcode
;
4975 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4977 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4979 as_fatal (_("unexpected fix"));
4983 insnbuf
= xtensa_insnbuf_alloc (isa
);
4984 slotbuf
= xtensa_insnbuf_alloc (isa
);
4987 xtensa_insnbuf_from_chars (isa
, insnbuf
, fixpos
, 0);
4988 fmt
= xtensa_format_decode (isa
, insnbuf
);
4989 if (fmt
== XTENSA_UNDEFINED
)
4990 as_fatal (_("undecodable fix"));
4991 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4992 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4993 if (opcode
== XTENSA_UNDEFINED
)
4994 as_fatal (_("undecodable fix"));
4996 /* CONST16 immediates are not PC-relative, despite the fact that we
4997 reuse the normal PC-relative operand relocations for the low part
4998 of a CONST16 operand. The code in tc_gen_reloc does not decode
4999 the opcodes so it is more convenient to detect this special case
5001 if (opcode
== xtensa_const16_opcode
)
5004 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5005 get_relaxable_immed (opcode
), val
,
5006 fixP
->fx_file
, fixP
->fx_line
);
5008 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5009 xtensa_insnbuf_to_chars (isa
, insnbuf
, fixpos
, 0);
5013 /* External Functions and Other GAS Hooks. */
5016 xtensa_target_format (void)
5018 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5023 xtensa_file_arch_init (bfd
*abfd
)
5025 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5030 md_number_to_chars (char *buf
, valueT val
, int n
)
5032 if (target_big_endian
)
5033 number_to_chars_bigendian (buf
, val
, n
);
5035 number_to_chars_littleendian (buf
, val
, n
);
5039 /* This function is called once, at assembler startup time. It should
5040 set up all the tables, etc. that the MD part of the assembler will
5046 segT current_section
= now_seg
;
5047 int current_subsec
= now_subseg
;
5050 xtensa_default_isa
= xtensa_isa_init (0, 0);
5051 isa
= xtensa_default_isa
;
5055 /* Set up the .literal, .fini.literal and .init.literal sections. */
5056 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5057 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5058 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5059 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5060 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5062 subseg_set (current_section
, current_subsec
);
5064 xg_init_vinsn (&cur_vinsn
);
5066 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5067 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5068 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5069 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5070 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5071 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5072 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5073 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5074 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5075 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5076 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5077 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5078 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5079 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5080 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5081 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5082 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5083 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5084 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5085 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5086 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5087 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5088 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5089 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5090 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5091 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5092 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5093 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5094 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5096 init_op_placement_info_table ();
5098 /* Set up the assembly state. */
5099 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5100 xtensa_set_frag_assembly_state (frag_now
);
5104 /* TC_INIT_FIX_DATA hook */
5107 xtensa_init_fix_data (fixS
*x
)
5109 x
->tc_fix_data
.slot
= 0;
5110 x
->tc_fix_data
.X_add_symbol
= NULL
;
5111 x
->tc_fix_data
.X_add_number
= 0;
5115 /* tc_frob_label hook */
5118 xtensa_frob_label (symbolS
*sym
)
5120 /* Since the label was already attached to a frag associated with the
5121 previous basic block, it now needs to be reset to the current frag. */
5122 symbol_set_frag (sym
, frag_now
);
5123 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5125 if (generating_literals
)
5126 xtensa_add_literal_sym (sym
);
5128 xtensa_add_insn_label (sym
);
5130 if (symbol_get_tc (sym
)->is_loop_target
5131 && (get_last_insn_flags (now_seg
, now_subseg
)
5132 & FLAG_IS_BAD_LOOPEND
) != 0)
5133 as_bad (_("invalid last instruction for a zero-overhead loop"));
5135 /* No target aligning in the absolute section. */
5136 if (now_seg
!= absolute_section
5137 && do_align_targets ()
5138 && !is_unaligned_label (sym
)
5139 && !generating_literals
)
5141 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5142 xtensa_set_frag_assembly_state (frag_now
);
5144 /* The only time this type of frag grows is when there is a
5145 negatable branch that needs to be relaxed as the last
5146 instruction in a zero-overhead loop. Because alignment frags
5147 are so common, marking them all as possibly growing four
5148 bytes makes any worst-case analysis appear much worse than it
5149 is. So, we make fr_var not actually reflect the amount of
5150 memory allocated at the end of this frag, but rather the
5151 amount of memory this frag might grow. The "4, 0" below
5152 allocates four bytes at the end of the frag for room to grow
5153 if we need to relax a loop end with a NOP. Frags prior to
5154 this one might grow to align this one, but the frag itself
5155 won't grow unless it meets the condition above. */
5157 #define RELAX_LOOP_END_BYTES 4
5159 frag_var (rs_machine_dependent
,
5160 RELAX_LOOP_END_BYTES
, (int) freq
,
5161 RELAX_DESIRE_ALIGN_IF_TARGET
,
5162 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5163 xtensa_set_frag_assembly_state (frag_now
);
5164 xtensa_move_labels (frag_now
, 0, TRUE
);
5167 /* We need to mark the following properties even if we aren't aligning. */
5169 /* If the label is already known to be a branch target, i.e., a
5170 forward branch, mark the frag accordingly. Backward branches
5171 are handled by xg_add_branch_and_loop_targets. */
5172 if (symbol_get_tc (sym
)->is_branch_target
)
5173 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5175 /* Loops only go forward, so they can be identified here. */
5176 if (symbol_get_tc (sym
)->is_loop_target
)
5177 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5181 /* tc_unrecognized_line hook */
5184 xtensa_unrecognized_line (int ch
)
5189 if (cur_vinsn
.inside_bundle
== 0)
5191 /* PR8110: Cannot emit line number info inside a FLIX bundle
5192 when using --gstabs. Temporarily disable debug info. */
5193 generate_lineno_debug ();
5194 if (debug_type
== DEBUG_STABS
)
5196 xt_saved_debug_type
= debug_type
;
5197 debug_type
= DEBUG_NONE
;
5200 cur_vinsn
.inside_bundle
= 1;
5204 as_bad (_("extra opening brace"));
5210 if (cur_vinsn
.inside_bundle
)
5211 finish_vinsn (&cur_vinsn
);
5214 as_bad (_("extra closing brace"));
5219 as_bad (_("syntax error"));
5226 /* md_flush_pending_output hook */
5229 xtensa_flush_pending_output (void)
5231 if (cur_vinsn
.inside_bundle
)
5232 as_bad (_("missing closing brace"));
5234 /* If there is a non-zero instruction fragment, close it. */
5235 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5237 frag_wane (frag_now
);
5239 xtensa_set_frag_assembly_state (frag_now
);
5241 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5243 xtensa_clear_insn_labels ();
5247 /* We had an error while parsing an instruction. The string might look
5248 like this: "insn arg1, arg2 }". If so, we need to see the closing
5249 brace and reset some fields. Otherwise, the vinsn never gets closed
5250 and the num_slots field will grow past the end of the array of slots,
5251 and bad things happen. */
5254 error_reset_cur_vinsn (void)
5256 if (cur_vinsn
.inside_bundle
)
5258 if (*input_line_pointer
== '}'
5259 || *(input_line_pointer
- 1) == '}'
5260 || *(input_line_pointer
- 2) == '}')
5261 xg_clear_vinsn (&cur_vinsn
);
5267 md_assemble (char *str
)
5269 xtensa_isa isa
= xtensa_default_isa
;
5272 bfd_boolean has_underbar
= FALSE
;
5273 char *arg_strings
[MAX_INSN_ARGS
];
5275 TInsn orig_insn
; /* Original instruction from the input. */
5277 tinsn_init (&orig_insn
);
5279 /* Split off the opcode. */
5280 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5281 opname
= xmalloc (opnamelen
+ 1);
5282 memcpy (opname
, str
, opnamelen
);
5283 opname
[opnamelen
] = '\0';
5285 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5288 as_bad (_("syntax error"));
5292 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5295 /* Check for an underbar prefix. */
5298 has_underbar
= TRUE
;
5302 orig_insn
.insn_type
= ITYPE_INSN
;
5304 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5306 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5307 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5309 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5310 if (fmt
== XTENSA_UNDEFINED
)
5312 as_bad (_("unknown opcode or format name '%s'"), opname
);
5313 error_reset_cur_vinsn ();
5316 if (!cur_vinsn
.inside_bundle
)
5318 as_bad (_("format names only valid inside bundles"));
5319 error_reset_cur_vinsn ();
5322 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5323 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5325 cur_vinsn
.format
= fmt
;
5326 free (has_underbar
? opname
- 1 : opname
);
5327 error_reset_cur_vinsn ();
5331 /* Special case: The call instructions should be marked "specific opcode"
5332 to keep them from expanding. */
5333 if (!use_longcalls () && is_direct_call_opcode (orig_insn
.opcode
))
5334 orig_insn
.is_specific_opcode
= TRUE
;
5336 /* Parse the arguments. */
5337 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5339 as_bad (_("syntax error"));
5340 error_reset_cur_vinsn ();
5344 /* Free the opcode and argument strings, now that they've been parsed. */
5345 free (has_underbar
? opname
- 1 : opname
);
5347 while (num_args
-- > 0)
5348 free (arg_strings
[num_args
]);
5350 /* Get expressions for invisible operands. */
5351 if (get_invisible_operands (&orig_insn
))
5353 error_reset_cur_vinsn ();
5357 /* Check for the right number and type of arguments. */
5358 if (tinsn_check_arguments (&orig_insn
))
5360 error_reset_cur_vinsn ();
5364 dwarf2_where (&orig_insn
.loc
);
5366 xg_add_branch_and_loop_targets (&orig_insn
);
5368 /* Special-case for "entry" instruction. */
5369 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5371 /* Check that the third opcode (#2) is >= 16. */
5372 if (orig_insn
.ntok
>= 3)
5374 expressionS
*exp
= &orig_insn
.tok
[2];
5378 if (exp
->X_add_number
< 16)
5379 as_warn (_("entry instruction with stack decrement < 16"));
5383 as_warn (_("entry instruction with non-constant decrement"));
5389 assemble_tokens (opcode, tok, ntok);
5390 expand the tokens from the orig_insn into the
5391 stack of instructions that will not expand
5392 unless required at relaxation time. */
5394 if (!cur_vinsn
.inside_bundle
)
5395 emit_single_op (&orig_insn
);
5396 else /* We are inside a bundle. */
5398 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5399 cur_vinsn
.num_slots
++;
5400 if (*input_line_pointer
== '}'
5401 || *(input_line_pointer
- 1) == '}'
5402 || *(input_line_pointer
- 2) == '}')
5403 finish_vinsn (&cur_vinsn
);
5406 /* We've just emitted a new instruction so clear the list of labels. */
5407 xtensa_clear_insn_labels ();
5411 /* HANDLE_ALIGN hook */
5413 /* For a .align directive, we mark the previous block with the alignment
5414 information. This will be placed in the object file in the
5415 property section corresponding to this section. */
5418 xtensa_handle_align (fragS
*fragP
)
5421 && ! fragP
->tc_frag_data
.is_literal
5422 && (fragP
->fr_type
== rs_align
5423 || fragP
->fr_type
== rs_align_code
)
5424 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5425 && fragP
->fr_offset
> 0
5426 && now_seg
!= bss_section
)
5428 fragP
->tc_frag_data
.is_align
= TRUE
;
5429 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5432 if (fragP
->fr_type
== rs_align_test
)
5435 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5437 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5438 _("unaligned entry instruction"));
5443 /* TC_FRAG_INIT hook */
5446 xtensa_frag_init (fragS
*frag
)
5448 xtensa_set_frag_assembly_state (frag
);
5453 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5459 /* Round up a section size to the appropriate boundary. */
5462 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5464 return size
; /* Byte alignment is fine. */
5469 md_pcrel_from (fixS
*fixP
)
5472 static xtensa_insnbuf insnbuf
= NULL
;
5473 static xtensa_insnbuf slotbuf
= NULL
;
5476 xtensa_opcode opcode
;
5479 xtensa_isa isa
= xtensa_default_isa
;
5480 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5481 bfd_boolean alt_reloc
;
5486 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5491 insnbuf
= xtensa_insnbuf_alloc (isa
);
5492 slotbuf
= xtensa_insnbuf_alloc (isa
);
5495 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5496 xtensa_insnbuf_from_chars (isa
, insnbuf
, insn_p
, 0);
5497 fmt
= xtensa_format_decode (isa
, insnbuf
);
5499 if (fmt
== XTENSA_UNDEFINED
)
5500 as_fatal (_("bad instruction format"));
5502 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5503 as_fatal (_("invalid relocation"));
5505 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5506 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5508 /* Check for "alternate" relocation (operand not specified). */
5509 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5511 if (opcode
!= xtensa_l32r_opcode
5512 && opcode
!= xtensa_const16_opcode
)
5513 as_fatal (_("invalid relocation for '%s' instruction"),
5514 xtensa_opcode_name (isa
, opcode
));
5518 opnum
= get_relaxable_immed (opcode
);
5520 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5521 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5523 as_bad_where (fixP
->fx_file
,
5525 _("invalid relocation for operand %d of '%s'"),
5526 opnum
, xtensa_opcode_name (isa
, opcode
));
5529 return 0 - opnd_value
;
5533 /* TC_FORCE_RELOCATION hook */
5536 xtensa_force_relocation (fixS
*fix
)
5538 switch (fix
->fx_r_type
)
5540 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5541 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5542 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5543 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5544 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5545 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5546 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5547 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5548 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5549 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5550 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5551 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5552 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5553 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5554 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5555 case BFD_RELOC_VTABLE_INHERIT
:
5556 case BFD_RELOC_VTABLE_ENTRY
:
5562 if (linkrelax
&& fix
->fx_addsy
5563 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5566 return generic_force_reloc (fix
);
5570 /* NO_PSEUDO_DOT hook */
5572 /* This function has nothing to do with pseudo dots, but this is the
5573 nearest macro to where the check needs to take place. FIXME: This
5577 xtensa_check_inside_bundle (void)
5579 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5580 as_bad (_("directives are not valid inside bundles"));
5582 /* This function must always return FALSE because it is called via a
5583 macro that has nothing to do with bundling. */
5588 /* md_elf_section_change_hook */
5591 xtensa_elf_section_change_hook (void)
5593 /* Set up the assembly state. */
5594 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5595 xtensa_set_frag_assembly_state (frag_now
);
5599 /* tc_fix_adjustable hook */
5602 xtensa_fix_adjustable (fixS
*fixP
)
5604 /* An offset is not allowed in combination with the difference of two
5605 symbols, but that cannot be easily detected after a local symbol
5606 has been adjusted to a (section+offset) form. Return 0 so that such
5607 an fix will not be adjusted. */
5608 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5609 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5612 /* We need the symbol name for the VTABLE entries. */
5613 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5614 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5618 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || S_IS_WEAK (fixP
->fx_addsy
)))
5622 /* We may someday want to enable this code to preserve relocations for
5623 non-PC-relative fixes, possibly under control of a PIC flag. */
5624 return (fixP
->fx_pcrel
5625 || (fixP
->fx_subsy
!= NULL
5626 && (S_GET_SEGMENT (fixP
->fx_subsy
)
5627 == S_GET_SEGMENT (fixP
->fx_addsy
)))
5628 || S_IS_LOCAL (fixP
->fx_addsy
));
5636 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
5638 if (fixP
->fx_pcrel
== 0 && fixP
->fx_addsy
== 0)
5640 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5642 switch (fixP
->fx_r_type
)
5644 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5648 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
5649 as_bad (_("unhandled local relocation fix %s"),
5650 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5656 /* The only one we support that isn't an instruction field. */
5657 md_number_to_chars (fixpos
, *valP
, fixP
->fx_size
);
5661 case BFD_RELOC_VTABLE_INHERIT
:
5662 case BFD_RELOC_VTABLE_ENTRY
:
5667 as_bad (_("unhandled local relocation fix %s"),
5668 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5675 md_atof (int type
, char *litP
, int *sizeP
)
5678 LITTLENUM_TYPE words
[4];
5694 return "bad call to md_atof";
5697 t
= atof_ieee (input_line_pointer
, type
, words
);
5699 input_line_pointer
= t
;
5703 for (i
= prec
- 1; i
>= 0; i
--)
5706 if (target_big_endian
)
5707 idx
= (prec
- 1 - i
);
5709 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5718 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5720 return fragP
->tc_frag_data
.text_expansion
[0];
5724 /* Translate internal representation of relocation info to BFD target
5728 tc_gen_reloc (asection
*section
, fixS
*fixp
)
5731 bfd_boolean apply_tentative_value
= FALSE
;
5733 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5734 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5735 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5736 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5738 /* Make sure none of our internal relocations make it this far.
5739 They'd better have been fully resolved by this point. */
5740 assert ((int) fixp
->fx_r_type
> 0);
5742 if (linkrelax
&& fixp
->fx_subsy
5743 && (fixp
->fx_r_type
== BFD_RELOC_8
5744 || fixp
->fx_r_type
== BFD_RELOC_16
5745 || fixp
->fx_r_type
== BFD_RELOC_32
))
5748 bfd_vma diff_value
, diff_mask
= 0;
5750 switch (fixp
->fx_r_type
)
5753 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5758 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5763 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5765 diff_mask
= 0xffffffff;
5771 /* An offset is only allowed when it results from adjusting a local
5772 symbol into a section-relative offset. If the offset came from the
5773 original expression, tc_fix_adjustable will have prevented the fix
5774 from being converted to a section-relative form so that we can flag
5776 if (fixp
->fx_offset
!= 0 && !symbol_section_p (fixp
->fx_addsy
))
5778 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5779 _("cannot represent subtraction with an offset"));
5780 free (reloc
->sym_ptr_ptr
);
5785 assert (S_GET_SEGMENT (fixp
->fx_addsy
)
5786 == S_GET_SEGMENT (fixp
->fx_subsy
));
5788 diff_value
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
5789 - S_GET_VALUE (fixp
->fx_subsy
));
5791 /* Check for overflow. */
5792 if ((diff_value
& ~diff_mask
) != 0)
5794 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5795 _("value of %ld too large"), diff_value
);
5796 free (reloc
->sym_ptr_ptr
);
5801 md_number_to_chars (fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
,
5802 diff_value
, diff_size
);
5803 reloc
->addend
= fixp
->fx_offset
- diff_value
;
5807 reloc
->addend
= fixp
->fx_offset
;
5809 switch (fixp
->fx_r_type
)
5811 case BFD_RELOC_XTENSA_SLOT0_OP
:
5812 case BFD_RELOC_XTENSA_SLOT1_OP
:
5813 case BFD_RELOC_XTENSA_SLOT2_OP
:
5814 case BFD_RELOC_XTENSA_SLOT3_OP
:
5815 case BFD_RELOC_XTENSA_SLOT4_OP
:
5816 case BFD_RELOC_XTENSA_SLOT5_OP
:
5817 case BFD_RELOC_XTENSA_SLOT6_OP
:
5818 case BFD_RELOC_XTENSA_SLOT7_OP
:
5819 case BFD_RELOC_XTENSA_SLOT8_OP
:
5820 case BFD_RELOC_XTENSA_SLOT9_OP
:
5821 case BFD_RELOC_XTENSA_SLOT10_OP
:
5822 case BFD_RELOC_XTENSA_SLOT11_OP
:
5823 case BFD_RELOC_XTENSA_SLOT12_OP
:
5824 case BFD_RELOC_XTENSA_SLOT13_OP
:
5825 case BFD_RELOC_XTENSA_SLOT14_OP
:
5826 /* As a special case, the immediate value for a CONST16 opcode
5827 should not be applied, since this kind of relocation is
5828 handled specially for CONST16 and is not really PC-relative.
5829 Rather than decode the opcode here, just wait and handle it
5830 in xg_apply_tentative_value. */
5831 apply_tentative_value
= TRUE
;
5834 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5835 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5836 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5837 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5838 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5839 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5840 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5841 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5842 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5843 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5844 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5845 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5846 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5847 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5848 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5849 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5851 case BFD_RELOC_XTENSA_PLT
:
5852 case BFD_RELOC_VTABLE_INHERIT
:
5853 case BFD_RELOC_VTABLE_ENTRY
:
5856 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
5857 as_warn (_("emitting simplification relocation"));
5861 as_warn (_("emitting unknown relocation"));
5865 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5866 if (reloc
->howto
== NULL
)
5868 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5869 _("cannot represent `%s' relocation in object file"),
5870 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5871 free (reloc
->sym_ptr_ptr
);
5876 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5877 as_fatal (_("internal error? cannot generate `%s' relocation"),
5878 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5880 /* Write the tentative value of a PC-relative relocation to a local symbol
5881 into the instruction. The value will be ignored by the linker, and it
5882 makes the object file disassembly readable when the linkrelax flag is
5883 set and all branch targets are encoded in relocations. */
5885 if (linkrelax
&& apply_tentative_value
&& fixp
->fx_pcrel
)
5888 assert (fixp
->fx_addsy
);
5889 if (S_GET_SEGMENT (fixp
->fx_addsy
) == section
&& !fixp
->fx_plt
5890 && !S_FORCE_RELOC (fixp
->fx_addsy
, 1))
5892 val
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
5893 - md_pcrel_from (fixp
));
5894 xg_apply_tentative_value (fixp
, val
);
5902 /* Checks for resource conflicts between instructions. */
5904 /* The func unit stuff could be implemented as bit-vectors rather
5905 than the iterative approach here. If it ends up being too
5906 slow, we will switch it. */
5909 new_resource_table (void *data
,
5912 unit_num_copies_func uncf
,
5913 opcode_num_units_func onuf
,
5914 opcode_funcUnit_use_unit_func ouuf
,
5915 opcode_funcUnit_use_stage_func ousf
)
5918 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5920 rt
->cycles
= cycles
;
5921 rt
->allocated_cycles
= cycles
;
5923 rt
->unit_num_copies
= uncf
;
5924 rt
->opcode_num_units
= onuf
;
5925 rt
->opcode_unit_use
= ouuf
;
5926 rt
->opcode_unit_stage
= ousf
;
5928 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5929 for (i
= 0; i
< cycles
; i
++)
5930 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5937 clear_resource_table (resource_table
*rt
)
5940 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5941 for (j
= 0; j
< rt
->num_units
; j
++)
5942 rt
->units
[i
][j
] = 0;
5946 /* We never shrink it, just fake it into thinking so. */
5949 resize_resource_table (resource_table
*rt
, int cycles
)
5953 rt
->cycles
= cycles
;
5954 if (cycles
<= rt
->allocated_cycles
)
5957 old_cycles
= rt
->allocated_cycles
;
5958 rt
->allocated_cycles
= cycles
;
5960 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5961 for (i
= 0; i
< old_cycles
; i
++)
5962 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5963 for (i
= old_cycles
; i
< cycles
; i
++)
5964 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5969 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5972 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5974 for (i
= 0; i
< uses
; i
++)
5976 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5977 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5978 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5979 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5980 if (copies_in_use
>= copies
)
5988 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5991 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5993 for (i
= 0; i
< uses
; i
++)
5995 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5996 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5997 /* Note that this allows resources to be oversubscribed. That's
5998 essential to the way the optional scheduler works.
5999 resources_available reports when a resource is over-subscribed,
6000 so it's easy to tell. */
6001 rt
->units
[stage
+ cycle
][unit
]++;
6007 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6010 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6012 for (i
= 0; i
< uses
; i
++)
6014 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6015 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6016 rt
->units
[stage
+ cycle
][unit
]--;
6017 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
6022 /* Wrapper functions make parameterized resource reservation
6026 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6028 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6034 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6036 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6041 /* Note that this function does not check issue constraints, but
6042 solely whether the hardware is available to execute the given
6043 instructions together. It also doesn't check if the tinsns
6044 write the same state, or access the same tieports. That is
6045 checked by check_t1_t2_read_write. */
6048 resources_conflict (vliw_insn
*vinsn
)
6051 static resource_table
*rt
= NULL
;
6053 /* This is the most common case by far. Optimize it. */
6054 if (vinsn
->num_slots
== 1)
6059 xtensa_isa isa
= xtensa_default_isa
;
6060 rt
= new_resource_table
6061 (isa
, xtensa_isa_num_pipe_stages (isa
),
6062 xtensa_isa_num_funcUnits (isa
),
6063 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6064 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6065 opcode_funcUnit_use_unit
,
6066 opcode_funcUnit_use_stage
);
6069 clear_resource_table (rt
);
6071 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6073 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6075 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6082 /* finish_vinsn, emit_single_op and helper functions. */
6084 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6085 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6086 static void bundle_single_op (TInsn
*);
6087 static void xg_assemble_vliw_tokens (vliw_insn
*);
6090 /* We have reached the end of a bundle; emit into the frag. */
6093 finish_vinsn (vliw_insn
*vinsn
)
6100 if (find_vinsn_conflicts (vinsn
))
6103 /* First, find a format that works. */
6104 if (vinsn
->format
== XTENSA_UNDEFINED
)
6105 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6107 if (vinsn
->format
== XTENSA_UNDEFINED
)
6109 as_where (&file_name
, &line
);
6110 as_bad_where (file_name
, line
,
6111 _("couldn't find a valid instruction format"));
6112 fprintf (stderr
, _(" ops were: "));
6113 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6114 fprintf (stderr
, _(" %s;"),
6115 xtensa_opcode_name (xtensa_default_isa
,
6116 vinsn
->slots
[i
].opcode
));
6117 fprintf (stderr
, _("\n"));
6118 xg_clear_vinsn (vinsn
);
6122 if (vinsn
->num_slots
6123 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6125 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6126 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6127 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6129 xg_clear_vinsn (vinsn
);
6133 if (resources_conflict (vinsn
))
6135 as_where (&file_name
, &line
);
6136 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6137 fprintf (stderr
, " ops were: ");
6138 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6139 fprintf (stderr
, " %s;",
6140 xtensa_opcode_name (xtensa_default_isa
,
6141 vinsn
->slots
[i
].opcode
));
6142 fprintf (stderr
, "\n");
6143 xg_clear_vinsn (vinsn
);
6147 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6149 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6151 symbolS
*lit_sym
= NULL
;
6153 bfd_boolean e
= FALSE
;
6154 bfd_boolean saved_density
= density_supported
;
6156 /* We don't want to narrow ops inside multi-slot bundles. */
6157 if (vinsn
->num_slots
> 1)
6158 density_supported
= FALSE
;
6160 istack_init (&slotstack
);
6161 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6163 vinsn
->slots
[i
].opcode
=
6164 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6166 vinsn
->slots
[i
].ntok
= 0;
6169 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6175 density_supported
= saved_density
;
6179 xg_clear_vinsn (vinsn
);
6183 for (j
= 0; j
< slotstack
.ninsn
- 1; j
++)
6185 TInsn
*insn
= &slotstack
.insn
[j
];
6186 if (insn
->insn_type
== ITYPE_LITERAL
)
6188 assert (lit_sym
== NULL
);
6189 lit_sym
= xg_assemble_literal (insn
);
6194 xg_resolve_literals (insn
, lit_sym
);
6195 emit_single_op (insn
);
6199 if (vinsn
->num_slots
> 1)
6201 if (opcode_fits_format_slot
6202 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6205 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6209 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6210 if (vinsn
->format
== XTENSA_UNDEFINED
)
6211 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6213 vinsn
->slots
[i
].opcode
6214 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6217 vinsn
->slots
[i
].ntok
= 0;
6222 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6223 vinsn
->format
= XTENSA_UNDEFINED
;
6228 /* Now check resource conflicts on the modified bundle. */
6229 if (resources_conflict (vinsn
))
6231 as_where (&file_name
, &line
);
6232 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6233 fprintf (stderr
, " ops were: ");
6234 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6235 fprintf (stderr
, " %s;",
6236 xtensa_opcode_name (xtensa_default_isa
,
6237 vinsn
->slots
[i
].opcode
));
6238 fprintf (stderr
, "\n");
6239 xg_clear_vinsn (vinsn
);
6243 /* First, find a format that works. */
6244 if (vinsn
->format
== XTENSA_UNDEFINED
)
6245 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6247 xg_assemble_vliw_tokens (vinsn
);
6249 xg_clear_vinsn (vinsn
);
6253 /* Given an vliw instruction, what conflicts are there in register
6254 usage and in writes to states and queues?
6256 This function does two things:
6257 1. Reports an error when a vinsn contains illegal combinations
6258 of writes to registers states or queues.
6259 2. Marks individual tinsns as not relaxable if the combination
6260 contains antidependencies.
6262 Job 2 handles things like swap semantics in instructions that need
6263 to be relaxed. For example,
6267 normally would be relaxed to
6272 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6274 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6276 then we can't relax it into
6279 { add a0, a1, a0 ; add a2, a0, a4 ; }
6281 because the value of a0 is trashed before the second add can read it. */
6283 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6286 find_vinsn_conflicts (vliw_insn
*vinsn
)
6290 xtensa_isa isa
= xtensa_default_isa
;
6292 assert (!past_xtensa_end
);
6294 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6296 TInsn
*op1
= &vinsn
->slots
[i
];
6297 if (op1
->is_specific_opcode
)
6298 op1
->keep_wide
= TRUE
;
6300 op1
->keep_wide
= FALSE
;
6303 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6305 TInsn
*op1
= &vinsn
->slots
[i
];
6307 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6310 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6314 TInsn
*op2
= &vinsn
->slots
[j
];
6315 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6316 switch (conflict_type
)
6319 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6320 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6321 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6324 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6325 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6326 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6329 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6330 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6331 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6334 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6335 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6336 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6339 /* Everything is OK. */
6342 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6343 || conflict_type
== 'a');
6350 as_bad (_("multiple branches or jumps in the same bundle"));
6358 /* Check how the result registers of t1 and t2 relate.
6361 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6362 case B: no relationship between what is read and written (both could
6363 read the same reg though)
6364 case C: t1 writes a register t2 writes (a register conflict within a
6366 case D: t1 writes a state that t2 also writes
6367 case E: t1 writes a tie queue that t2 also writes
6368 case F: two volatile queue writes
6372 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6374 xtensa_isa isa
= xtensa_default_isa
;
6375 xtensa_regfile t1_regfile
, t2_regfile
;
6377 int t1_base_reg
, t1_last_reg
;
6378 int t2_base_reg
, t2_last_reg
;
6379 char t1_inout
, t2_inout
;
6381 char conflict
= 'b';
6386 bfd_boolean t1_volatile
= FALSE
;
6387 bfd_boolean t2_volatile
= FALSE
;
6389 /* Check registers. */
6390 for (j
= 0; j
< t2
->ntok
; j
++)
6392 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6395 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6396 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6397 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6399 for (i
= 0; i
< t1
->ntok
; i
++)
6401 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6404 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6406 if (t1_regfile
!= t2_regfile
)
6409 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6410 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6412 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6413 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6415 if (t1_inout
== 'm' || t1_inout
== 'o'
6416 || t2_inout
== 'm' || t2_inout
== 'o')
6423 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6424 t1_last_reg
= (t1_base_reg
6425 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6427 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6429 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6431 if (t1_reg
!= t2_reg
)
6434 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6440 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6446 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6454 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6455 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6456 for (j
= 0; j
< t2_states
; j
++)
6458 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6459 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6460 for (i
= 0; i
< t1_states
; i
++)
6462 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6463 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6467 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6473 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6479 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6484 /* Check tieports. */
6485 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6486 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6487 for (j
= 0; j
< t2_interfaces
; j
++)
6489 xtensa_interface t2_int
6490 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6491 t2_inout
= xtensa_interface_inout (isa
, j
);
6492 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1
6495 for (i
= 0; i
< t1_interfaces
; i
++)
6497 xtensa_interface t1_int
6498 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6499 t1_inout
= xtensa_interface_inout (isa
, i
);
6500 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1
6504 if (t1_int
!= t2_int
)
6507 if (t2_inout
== 'i' && t1_inout
== 'o')
6513 if (t1_inout
== 'i' && t2_inout
== 'o')
6519 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6524 if (t1_volatile
&& t2_volatile
)
6531 static xtensa_format
6532 xg_find_narrowest_format (vliw_insn
*vinsn
)
6534 /* Right now we assume that the ops within the vinsn are properly
6535 ordered for the slots that the programmer wanted them in. In
6536 other words, we don't rearrange the ops in hopes of finding a
6537 better format. The scheduler handles that. */
6539 xtensa_isa isa
= xtensa_default_isa
;
6540 xtensa_format format
;
6541 vliw_insn v_copy
= *vinsn
;
6542 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6544 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6547 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6551 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6553 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6555 v_copy
.slots
[slot
].opcode
=
6556 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6557 v_copy
.slots
[slot
].ntok
= 0;
6560 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6563 else if (v_copy
.num_slots
> 1)
6566 /* Try the widened version. */
6567 if (!v_copy
.slots
[slot
].keep_wide
6568 && !v_copy
.slots
[slot
].is_specific_opcode
6569 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6570 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6571 && opcode_fits_format_slot (widened
.opcode
,
6574 /* The xg_is_narrow clause requires some explanation:
6576 addi can be "widened" to an addmi, which is then
6577 expanded to an addmi/addi pair if the immediate
6578 requires it, but here we must have a single widen
6581 xg_is_narrow tells us that addi isn't really
6582 narrow. The widen_spec_list says that there are
6585 v_copy
.slots
[slot
] = widened
;
6590 if (fit
== v_copy
.num_slots
)
6593 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6594 vinsn
->format
= format
;
6600 if (format
== xtensa_isa_num_formats (isa
))
6601 return XTENSA_UNDEFINED
;
6607 /* Return the additional space needed in a frag
6608 for possible relaxations of any ops in a VLIW insn.
6609 Also fill out the relaxations that might be required of
6610 each tinsn in the vinsn. */
6613 relaxation_requirements (vliw_insn
*vinsn
)
6615 int extra_space
= 0;
6618 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6620 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6621 if (!tinsn_has_symbolic_operands (tinsn
))
6623 /* A narrow instruction could be widened later to help
6624 alignment issues. */
6625 if (xg_is_narrow_insn (tinsn
)
6626 && !tinsn
->is_specific_opcode
6627 && vinsn
->num_slots
== 1)
6629 /* Difference in bytes between narrow and wide insns... */
6631 tinsn
->subtype
= RELAX_NARROW
;
6632 tinsn
->record_fix
= TRUE
;
6637 tinsn
->record_fix
= FALSE
;
6638 /* No extra_space needed. */
6643 if (workaround_b_j_loop_end
6644 && tinsn
->opcode
== xtensa_jx_opcode
6645 && use_transform ())
6647 /* Add 2 of these. */
6648 extra_space
+= 3; /* for the nop size */
6649 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6652 /* Need to assemble it with space for the relocation. */
6653 if (xg_is_relaxable_insn (tinsn
, 0)
6654 && !tinsn
->is_specific_opcode
)
6656 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6657 int max_literal_size
=
6658 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6660 tinsn
->literal_space
= max_literal_size
;
6662 tinsn
->subtype
= RELAX_IMMED
;
6663 tinsn
->record_fix
= FALSE
;
6664 extra_space
+= max_size
;
6668 tinsn
->record_fix
= TRUE
;
6669 /* No extra space needed. */
6678 bundle_single_op (TInsn
*orig_insn
)
6680 xtensa_isa isa
= xtensa_default_isa
;
6685 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6686 assert (v
.format
!= XTENSA_UNDEFINED
);
6687 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6690 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6693 v
.slots
[slot
].opcode
=
6694 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6695 v
.slots
[slot
].ntok
= 0;
6696 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6699 v
.slots
[slot
] = *orig_insn
;
6702 for ( ; slot
< v
.num_slots
; slot
++)
6704 v
.slots
[slot
].opcode
=
6705 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6706 v
.slots
[slot
].ntok
= 0;
6707 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6716 emit_single_op (TInsn
*orig_insn
)
6719 IStack istack
; /* put instructions into here */
6720 symbolS
*lit_sym
= NULL
;
6721 symbolS
*label_sym
= NULL
;
6723 istack_init (&istack
);
6725 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6726 Because the scheduling and bundling characteristics of movi and
6727 l32r or const16 are so different, we can do much better if we relax
6728 it prior to scheduling and bundling, rather than after. */
6729 if ((orig_insn
->opcode
== xtensa_movi_opcode
6730 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6731 && !cur_vinsn
.inside_bundle
6732 && (orig_insn
->tok
[1].X_op
== O_symbol
6733 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6734 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6736 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6739 for (i
= 0; i
< istack
.ninsn
; i
++)
6741 TInsn
*insn
= &istack
.insn
[i
];
6742 switch (insn
->insn_type
)
6745 assert (lit_sym
== NULL
);
6746 lit_sym
= xg_assemble_literal (insn
);
6750 static int relaxed_sym_idx
= 0;
6751 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6752 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6754 assert (label_sym
== NULL
);
6755 label_sym
= symbol_find_or_make (label
);
6762 xg_resolve_literals (insn
, lit_sym
);
6764 xg_resolve_labels (insn
, label_sym
);
6765 bundle_single_op (insn
);
6776 /* Emit a vliw instruction to the current fragment. */
6779 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6781 bfd_boolean finish_frag
= FALSE
;
6782 bfd_boolean is_jump
= FALSE
;
6783 bfd_boolean is_branch
= FALSE
;
6784 xtensa_isa isa
= xtensa_default_isa
;
6790 struct dwarf2_line_info best_loc
;
6792 best_loc
.line
= INT_MAX
;
6794 if (generating_literals
)
6796 static int reported
= 0;
6798 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6799 _("cannot assemble into a literal fragment"));
6806 if (frag_now_fix () != 0
6807 && (! frag_now
->tc_frag_data
.is_insn
6808 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6809 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6810 || (directive_state
[directive_absolute_literals
]
6811 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6813 frag_wane (frag_now
);
6815 xtensa_set_frag_assembly_state (frag_now
);
6818 if (workaround_a0_b_retw
6819 && vinsn
->num_slots
== 1
6820 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6821 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6822 && use_transform ())
6824 has_a0_b_retw
= TRUE
;
6826 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6827 After the first assembly pass we will check all of them and
6828 add a nop if needed. */
6829 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6830 frag_var (rs_machine_dependent
, 4, 4,
6831 RELAX_ADD_NOP_IF_A0_B_RETW
,
6832 frag_now
->fr_symbol
,
6833 frag_now
->fr_offset
,
6835 xtensa_set_frag_assembly_state (frag_now
);
6836 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6837 frag_var (rs_machine_dependent
, 4, 4,
6838 RELAX_ADD_NOP_IF_A0_B_RETW
,
6839 frag_now
->fr_symbol
,
6840 frag_now
->fr_offset
,
6842 xtensa_set_frag_assembly_state (frag_now
);
6845 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6847 /* See if the instruction implies an aligned section. */
6848 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6849 record_alignment (now_seg
, 2);
6851 /* Also determine the best line number for debug info. */
6852 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6853 ? vinsn
->slots
[i
].loc
: best_loc
;
6856 /* Special cases for instructions that force an alignment... */
6857 /* None of these opcodes are bundle-able. */
6858 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6862 xtensa_set_frag_assembly_state (frag_now
);
6863 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6865 max_fill
= get_text_align_max_fill_size
6866 (get_text_align_power (xtensa_fetch_width
),
6867 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6869 if (use_transform ())
6870 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6871 RELAX_ALIGN_NEXT_OPCODE
,
6872 frag_now
->fr_symbol
,
6873 frag_now
->fr_offset
,
6876 frag_var (rs_machine_dependent
, 0, 0,
6877 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6878 xtensa_set_frag_assembly_state (frag_now
);
6880 xtensa_move_labels (frag_now
, 0, FALSE
);
6883 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6884 && !vinsn
->slots
[0].is_specific_opcode
)
6886 xtensa_mark_literal_pool_location ();
6887 xtensa_move_labels (frag_now
, 0, TRUE
);
6888 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6891 if (vinsn
->num_slots
== 1)
6893 if (workaround_a0_b_retw
&& use_transform ())
6894 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6895 is_register_writer (&vinsn
->slots
[0], "a", 0));
6897 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6898 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6901 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6903 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6905 extra_space
= relaxation_requirements (vinsn
);
6907 /* vinsn_to_insnbuf will produce the error. */
6908 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6910 f
= (char *) frag_more (insn_size
+ extra_space
);
6911 xtensa_set_frag_assembly_state (frag_now
);
6912 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6915 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6916 if (vinsn
->format
== XTENSA_UNDEFINED
)
6919 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, f
, 0);
6921 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6923 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6925 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6926 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6927 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6928 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6929 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6930 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6931 if (tinsn
->literal_space
!= 0)
6932 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6934 if (tinsn
->subtype
== RELAX_NARROW
)
6935 assert (vinsn
->num_slots
== 1);
6936 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6938 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6941 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6942 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6946 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6947 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6951 frag_variant (rs_machine_dependent
,
6952 extra_space
, extra_space
, RELAX_SLOTS
,
6953 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6954 xtensa_set_frag_assembly_state (frag_now
);
6957 /* Special cases for loops:
6958 close_loop_end should be inserted AFTER short_loop.
6959 Make sure that CLOSE loops are processed BEFORE short_loops
6960 when converting them. */
6962 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6963 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6964 && !vinsn
->slots
[0].is_specific_opcode
)
6966 if (workaround_short_loop
&& use_transform ())
6968 maybe_has_short_loop
= TRUE
;
6969 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6970 frag_var (rs_machine_dependent
, 4, 4,
6971 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6972 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6973 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6974 frag_var (rs_machine_dependent
, 4, 4,
6975 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6976 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6979 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6980 loop at least 12 bytes away from another loop's end. */
6981 if (workaround_close_loop_end
&& use_transform ())
6983 maybe_has_close_loop_end
= TRUE
;
6984 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6985 frag_var (rs_machine_dependent
, 12, 12,
6986 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6987 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6991 if (use_transform ())
6995 assert (finish_frag
);
6996 frag_var (rs_machine_dependent
,
6997 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6999 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7000 xtensa_set_frag_assembly_state (frag_now
);
7002 else if (is_branch
&& align_targets
)
7004 assert (finish_frag
);
7005 frag_var (rs_machine_dependent
,
7006 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7007 RELAX_MAYBE_UNREACHABLE
,
7008 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7009 xtensa_set_frag_assembly_state (frag_now
);
7010 frag_var (rs_machine_dependent
,
7012 RELAX_MAYBE_DESIRE_ALIGN
,
7013 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7014 xtensa_set_frag_assembly_state (frag_now
);
7018 /* Now, if the original opcode was a call... */
7019 if (do_align_targets ()
7020 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7022 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7023 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7024 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7025 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7026 xtensa_set_frag_assembly_state (frag_now
);
7029 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7031 frag_wane (frag_now
);
7033 xtensa_set_frag_assembly_state (frag_now
);
7038 /* xtensa_end and helper functions. */
7040 static void xtensa_cleanup_align_frags (void);
7041 static void xtensa_fix_target_frags (void);
7042 static void xtensa_mark_narrow_branches (void);
7043 static void xtensa_mark_zcl_first_insns (void);
7044 static void xtensa_fix_a0_b_retw_frags (void);
7045 static void xtensa_fix_b_j_loop_end_frags (void);
7046 static void xtensa_fix_close_loop_end_frags (void);
7047 static void xtensa_fix_short_loop_frags (void);
7048 static void xtensa_sanity_check (void);
7053 directive_balance ();
7054 xtensa_flush_pending_output ();
7056 past_xtensa_end
= TRUE
;
7058 xtensa_move_literals ();
7060 xtensa_reorder_segments ();
7061 xtensa_cleanup_align_frags ();
7062 xtensa_fix_target_frags ();
7063 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7064 xtensa_fix_a0_b_retw_frags ();
7065 if (workaround_b_j_loop_end
)
7066 xtensa_fix_b_j_loop_end_frags ();
7068 /* "close_loop_end" should be processed BEFORE "short_loop". */
7069 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7070 xtensa_fix_close_loop_end_frags ();
7072 if (workaround_short_loop
&& maybe_has_short_loop
)
7073 xtensa_fix_short_loop_frags ();
7074 xtensa_mark_narrow_branches ();
7075 xtensa_mark_zcl_first_insns ();
7077 xtensa_sanity_check ();
7082 xtensa_cleanup_align_frags (void)
7086 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7089 /* Walk over all of the fragments in a subsection. */
7090 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7092 if ((fragP
->fr_type
== rs_align
7093 || fragP
->fr_type
== rs_align_code
7094 || (fragP
->fr_type
== rs_machine_dependent
7095 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7096 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7097 && fragP
->fr_fix
== 0)
7099 fragS
*next
= fragP
->fr_next
;
7102 && next
->fr_fix
== 0
7103 && next
->fr_type
== rs_machine_dependent
7104 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7107 next
= next
->fr_next
;
7110 /* If we don't widen branch targets, then they
7111 will be easier to align. */
7112 if (fragP
->tc_frag_data
.is_branch_target
7113 && fragP
->fr_opcode
== fragP
->fr_literal
7114 && fragP
->fr_type
== rs_machine_dependent
7115 && fragP
->fr_subtype
== RELAX_SLOTS
7116 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7118 if (fragP
->fr_type
== rs_machine_dependent
7119 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7120 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7126 /* Re-process all of the fragments looking to convert all of the
7127 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7128 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7129 If the next fragment starts with a loop target, AND the previous
7130 fragment can be expanded to negate the branch, convert this to a
7131 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7133 static bfd_boolean
frag_can_negate_branch (fragS
*);
7136 xtensa_fix_target_frags (void)
7140 /* When this routine is called, all of the subsections are still intact
7141 so we walk over subsections instead of sections. */
7142 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7144 bfd_boolean prev_frag_can_negate_branch
= FALSE
;
7147 /* Walk over all of the fragments in a subsection. */
7148 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7150 if (fragP
->fr_type
== rs_machine_dependent
7151 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7153 if (next_frag_is_loop_target (fragP
))
7155 if (prev_frag_can_negate_branch
)
7157 fragP
->fr_subtype
= RELAX_LOOP_END
;
7158 /* See the comment near the frag_var with a
7159 RELAX_DESIRE_ALIGN to see why we do this. */
7160 fragP
->fr_var
= RELAX_LOOP_END_BYTES
;
7164 if (next_frag_is_branch_target (fragP
))
7165 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7170 else if (next_frag_is_branch_target (fragP
))
7171 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7175 if (fragP
->fr_fix
!= 0)
7176 prev_frag_can_negate_branch
= FALSE
;
7177 if (frag_can_negate_branch (fragP
))
7178 prev_frag_can_negate_branch
= TRUE
;
7185 frag_can_negate_branch (fragS
*fragP
)
7187 xtensa_isa isa
= xtensa_default_isa
;
7191 if (fragP
->fr_type
!= rs_machine_dependent
7192 || fragP
->fr_subtype
!= RELAX_SLOTS
)
7195 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7197 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, vinsn
.format
); slot
++)
7199 if ((fragP
->tc_frag_data
.slot_subtypes
[slot
] == RELAX_IMMED
)
7200 && xtensa_opcode_is_branch (isa
, vinsn
.slots
[slot
].opcode
) == 1)
7208 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7211 xtensa_mark_narrow_branches (void)
7215 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7218 /* Walk over all of the fragments in a subsection. */
7219 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7221 if (fragP
->fr_type
== rs_machine_dependent
7222 && fragP
->fr_subtype
== RELAX_SLOTS
7223 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7226 const expressionS
*expr
;
7229 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7230 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7232 expr
= &vinsn
.slots
[0].tok
[1];
7233 symbolP
= expr
->X_add_symbol
;
7235 if (vinsn
.num_slots
== 1
7236 && xtensa_opcode_is_branch (xtensa_default_isa
,
7237 vinsn
.slots
[0].opcode
)
7238 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7239 && is_narrow_branch_guaranteed_in_range (fragP
,
7242 fragP
->fr_subtype
= RELAX_SLOTS
;
7243 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7251 /* A branch is typically widened only when its target is out of
7252 range. However, we would like to widen them to align a subsequent
7253 branch target when possible.
7255 Because the branch relaxation code is so convoluted, the optimal solution
7256 (combining the two cases) is difficult to get right in all circumstances.
7257 We therefore go with an "almost as good" solution, where we only
7258 use for alignment narrow branches that definitely will not expand to a
7259 jump and a branch. These functions find and mark these cases. */
7261 /* the range in bytes of a bnez.n and beqz.n */
7262 #define MAX_IMMED6 68
7264 static size_t unrelaxed_frag_max_size (fragS
*);
7267 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7269 const expressionS
*expr
= &tinsn
->tok
[1];
7270 symbolS
*symbolP
= expr
->X_add_symbol
;
7271 fragS
*target_frag
= symbol_get_frag (symbolP
);
7272 size_t max_distance
= expr
->X_add_number
;
7273 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7274 if (is_branch_jmp_to_next (tinsn
, fragP
))
7277 /* The branch doesn't branch over it's own frag,
7278 but over the subsequent ones. */
7279 fragP
= fragP
->fr_next
;
7280 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7282 max_distance
+= unrelaxed_frag_max_size (fragP
);
7283 fragP
= fragP
->fr_next
;
7285 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7292 xtensa_mark_zcl_first_insns (void)
7296 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7299 /* Walk over all of the fragments in a subsection. */
7300 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7302 if (fragP
->fr_type
== rs_machine_dependent
7303 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7304 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7306 /* Find the loop frag. */
7307 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7308 /* Find the first insn frag. */
7309 targ_frag
= next_non_empty_frag (targ_frag
);
7311 /* Of course, sometimes (mostly for toy test cases) a
7312 zero-cost loop instruction is the last in a section. */
7315 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7316 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7325 /* Re-process all of the fragments looking to convert all of the
7326 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7327 conditional branch or a retw/retw.n, convert this frag to one that
7328 will generate a NOP. In any case close it off with a .fill 0. */
7330 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7333 xtensa_fix_a0_b_retw_frags (void)
7337 /* When this routine is called, all of the subsections are still intact
7338 so we walk over subsections instead of sections. */
7339 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7343 /* Walk over all of the fragments in a subsection. */
7344 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7346 if (fragP
->fr_type
== rs_machine_dependent
7347 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7349 if (next_instrs_are_b_retw (fragP
))
7351 if (fragP
->tc_frag_data
.is_no_transform
)
7352 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7354 relax_frag_add_nop (fragP
);
7364 next_instrs_are_b_retw (fragS
*fragP
)
7366 xtensa_opcode opcode
;
7368 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7369 static xtensa_insnbuf insnbuf
= NULL
;
7370 static xtensa_insnbuf slotbuf
= NULL
;
7371 xtensa_isa isa
= xtensa_default_isa
;
7374 bfd_boolean branch_seen
= FALSE
;
7378 insnbuf
= xtensa_insnbuf_alloc (isa
);
7379 slotbuf
= xtensa_insnbuf_alloc (isa
);
7382 if (next_fragP
== NULL
)
7385 /* Check for the conditional branch. */
7386 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7387 fmt
= xtensa_format_decode (isa
, insnbuf
);
7388 if (fmt
== XTENSA_UNDEFINED
)
7391 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7393 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7394 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7396 branch_seen
= (branch_seen
7397 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7403 offset
+= xtensa_format_length (isa
, fmt
);
7404 if (offset
== next_fragP
->fr_fix
)
7406 next_fragP
= next_non_empty_frag (next_fragP
);
7410 if (next_fragP
== NULL
)
7413 /* Check for the retw/retw.n. */
7414 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7415 fmt
= xtensa_format_decode (isa
, insnbuf
);
7417 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7418 have no problems. */
7419 if (fmt
== XTENSA_UNDEFINED
7420 || xtensa_format_num_slots (isa
, fmt
) != 1)
7423 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7424 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7426 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7433 /* Re-process all of the fragments looking to convert all of the
7434 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7435 loop end label, convert this frag to one that will generate a NOP.
7436 In any case close it off with a .fill 0. */
7438 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7441 xtensa_fix_b_j_loop_end_frags (void)
7445 /* When this routine is called, all of the subsections are still intact
7446 so we walk over subsections instead of sections. */
7447 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7451 /* Walk over all of the fragments in a subsection. */
7452 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7454 if (fragP
->fr_type
== rs_machine_dependent
7455 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7457 if (next_instr_is_loop_end (fragP
))
7459 if (fragP
->tc_frag_data
.is_no_transform
)
7460 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7462 relax_frag_add_nop (fragP
);
7472 next_instr_is_loop_end (fragS
*fragP
)
7474 const fragS
*next_fragP
;
7476 if (next_frag_is_loop_target (fragP
))
7479 next_fragP
= next_non_empty_frag (fragP
);
7480 if (next_fragP
== NULL
)
7483 if (!next_frag_is_loop_target (next_fragP
))
7486 /* If the size is >= 3 then there is more than one instruction here.
7487 The hardware bug will not fire. */
7488 if (next_fragP
->fr_fix
> 3)
7495 /* Re-process all of the fragments looking to convert all of the
7496 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7497 not MY loop's loop end within 12 bytes, add enough nops here to
7498 make it at least 12 bytes away. In any case close it off with a
7501 static size_t min_bytes_to_other_loop_end (fragS
*, fragS
*, offsetT
, size_t);
7504 xtensa_fix_close_loop_end_frags (void)
7508 /* When this routine is called, all of the subsections are still intact
7509 so we walk over subsections instead of sections. */
7510 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7514 fragS
*current_target
= NULL
;
7515 offsetT current_offset
= 0;
7517 /* Walk over all of the fragments in a subsection. */
7518 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7520 if (fragP
->fr_type
== rs_machine_dependent
7521 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7522 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7523 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7526 /* Read it. If the instruction is a loop, get the target. */
7528 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7529 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7530 t_insn
.opcode
) == 1)
7532 /* Get the current fragment target. */
7533 if (fragP
->tc_frag_data
.slot_symbols
[0])
7535 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7536 current_target
= symbol_get_frag (sym
);
7537 current_offset
= fragP
->fr_offset
;
7543 && fragP
->fr_type
== rs_machine_dependent
7544 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7547 size_t bytes_added
= 0;
7549 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7550 /* Max out at 12. */
7551 min_bytes
= min_bytes_to_other_loop_end
7552 (fragP
->fr_next
, current_target
, current_offset
,
7553 REQUIRED_LOOP_DIVIDING_BYTES
);
7555 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7557 if (fragP
->tc_frag_data
.is_no_transform
)
7558 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7561 while (min_bytes
+ bytes_added
7562 < REQUIRED_LOOP_DIVIDING_BYTES
)
7566 if (fragP
->fr_var
< length
)
7567 as_fatal (_("fr_var %lu < length %d"),
7568 fragP
->fr_var
, length
);
7571 assemble_nop (length
,
7572 fragP
->fr_literal
+ fragP
->fr_fix
);
7573 fragP
->fr_fix
+= length
;
7574 fragP
->fr_var
-= length
;
7576 bytes_added
+= length
;
7582 assert (fragP
->fr_type
!= rs_machine_dependent
7583 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7589 static size_t unrelaxed_frag_min_size (fragS
*);
7592 min_bytes_to_other_loop_end (fragS
*fragP
,
7593 fragS
*current_target
,
7594 offsetT current_offset
,
7598 fragS
*current_fragP
;
7600 for (current_fragP
= fragP
;
7602 current_fragP
= current_fragP
->fr_next
)
7604 if (current_fragP
->tc_frag_data
.is_loop_target
7605 && current_fragP
!= current_target
)
7606 return offset
+ current_offset
;
7608 offset
+= unrelaxed_frag_min_size (current_fragP
);
7610 if (offset
+ current_offset
>= max_size
)
7618 unrelaxed_frag_min_size (fragS
*fragP
)
7620 size_t size
= fragP
->fr_fix
;
7623 if (fragP
->fr_type
== rs_fill
)
7624 size
+= fragP
->fr_offset
;
7631 unrelaxed_frag_max_size (fragS
*fragP
)
7633 size_t size
= fragP
->fr_fix
;
7634 switch (fragP
->fr_type
)
7637 /* Empty frags created by the obstack allocation scheme
7638 end up with type 0. */
7643 size
+= fragP
->fr_offset
;
7651 /* No further adjustments needed. */
7653 case rs_machine_dependent
:
7654 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7655 size
+= fragP
->fr_var
;
7658 /* We had darn well better know how big it is. */
7667 /* Re-process all of the fragments looking to convert all
7668 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7671 1) the instruction size count to the loop end label
7672 is too short (<= 2 instructions),
7673 2) loop has a jump or branch in it
7676 1) workaround_all_short_loops is TRUE
7677 2) The generating loop was a 'loopgtz' or 'loopnez'
7678 3) the instruction size count to the loop end label is too short
7680 then convert this frag (and maybe the next one) to generate a NOP.
7681 In any case close it off with a .fill 0. */
7683 static size_t count_insns_to_loop_end (fragS
*, bfd_boolean
, size_t);
7684 static bfd_boolean
branch_before_loop_end (fragS
*);
7687 xtensa_fix_short_loop_frags (void)
7691 /* When this routine is called, all of the subsections are still intact
7692 so we walk over subsections instead of sections. */
7693 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7696 fragS
*current_target
= NULL
;
7697 offsetT current_offset
= 0;
7698 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7700 /* Walk over all of the fragments in a subsection. */
7701 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7703 /* Check on the current loop. */
7704 if (fragP
->fr_type
== rs_machine_dependent
7705 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7706 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7707 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7712 /* Read it. If the instruction is a loop, get the target. */
7713 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7714 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7715 t_insn
.opcode
) == 1)
7717 /* Get the current fragment target. */
7718 if (fragP
->tc_frag_data
.slot_symbols
[0])
7720 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7721 current_target
= symbol_get_frag (sym
);
7722 current_offset
= fragP
->fr_offset
;
7723 current_opcode
= t_insn
.opcode
;
7728 if (fragP
->fr_type
== rs_machine_dependent
7729 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7732 count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3);
7734 && (branch_before_loop_end (fragP
->fr_next
)
7735 || (workaround_all_short_loops
7736 && current_opcode
!= XTENSA_UNDEFINED
7737 && current_opcode
!= xtensa_loop_opcode
)))
7739 if (fragP
->tc_frag_data
.is_no_transform
)
7740 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7742 relax_frag_add_nop (fragP
);
7751 static size_t unrelaxed_frag_min_insn_count (fragS
*);
7754 count_insns_to_loop_end (fragS
*base_fragP
,
7755 bfd_boolean count_relax_add
,
7758 fragS
*fragP
= NULL
;
7759 size_t insn_count
= 0;
7763 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7765 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7766 if (insn_count
>= max_count
)
7769 if (count_relax_add
)
7771 if (fragP
->fr_type
== rs_machine_dependent
7772 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7774 /* In order to add the appropriate number of
7775 NOPs, we count an instruction for downstream
7778 if (insn_count
>= max_count
)
7788 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7790 xtensa_isa isa
= xtensa_default_isa
;
7791 static xtensa_insnbuf insnbuf
= NULL
;
7792 size_t insn_count
= 0;
7795 if (!fragP
->tc_frag_data
.is_insn
)
7799 insnbuf
= xtensa_insnbuf_alloc (isa
);
7801 /* Decode the fixed instructions. */
7802 while (offset
< fragP
->fr_fix
)
7806 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7807 fmt
= xtensa_format_decode (isa
, insnbuf
);
7809 if (fmt
== XTENSA_UNDEFINED
)
7811 as_fatal (_("undecodable instruction in instruction frag"));
7814 offset
+= xtensa_format_length (isa
, fmt
);
7822 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7825 branch_before_loop_end (fragS
*base_fragP
)
7829 for (fragP
= base_fragP
;
7830 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7831 fragP
= fragP
->fr_next
)
7833 if (unrelaxed_frag_has_b_j (fragP
))
7841 unrelaxed_frag_has_b_j (fragS
*fragP
)
7843 static xtensa_insnbuf insnbuf
= NULL
;
7844 xtensa_isa isa
= xtensa_default_isa
;
7847 if (!fragP
->tc_frag_data
.is_insn
)
7851 insnbuf
= xtensa_insnbuf_alloc (isa
);
7853 /* Decode the fixed instructions. */
7854 while (offset
< fragP
->fr_fix
)
7859 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7860 fmt
= xtensa_format_decode (isa
, insnbuf
);
7861 if (fmt
== XTENSA_UNDEFINED
)
7864 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7866 xtensa_opcode opcode
=
7867 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7868 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7869 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7872 offset
+= xtensa_format_length (isa
, fmt
);
7878 /* Checks to be made after initial assembly but before relaxation. */
7880 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7881 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7884 xtensa_sanity_check (void)
7891 as_where (&file_name
, &line
);
7892 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7896 /* Walk over all of the fragments in a subsection. */
7897 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7899 /* Currently we only check for empty loops here. */
7900 if (fragP
->fr_type
== rs_machine_dependent
7901 && fragP
->fr_subtype
== RELAX_IMMED
)
7903 static xtensa_insnbuf insnbuf
= NULL
;
7906 if (fragP
->fr_opcode
!= NULL
)
7909 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7910 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7911 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7913 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7914 t_insn
.opcode
) == 1)
7916 if (is_empty_loop (&t_insn
, fragP
))
7918 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7919 as_bad (_("invalid empty loop"));
7921 if (!is_local_forward_loop (&t_insn
, fragP
))
7923 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7924 as_bad (_("loop target does not follow "
7925 "loop instruction in section"));
7932 new_logical_line (file_name
, line
);
7936 #define LOOP_IMMED_OPN 1
7938 /* Return TRUE if the loop target is the next non-zero fragment. */
7941 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7943 const expressionS
*expr
;
7947 if (insn
->insn_type
!= ITYPE_INSN
)
7950 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7953 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7956 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7958 if (expr
->X_op
!= O_symbol
)
7961 symbolP
= expr
->X_add_symbol
;
7965 if (symbol_get_frag (symbolP
) == NULL
)
7968 if (S_GET_VALUE (symbolP
) != 0)
7971 /* Walk through the zero-size fragments from this one. If we find
7972 the target fragment, then this is a zero-size loop. */
7974 for (next_fragP
= fragP
->fr_next
;
7976 next_fragP
= next_fragP
->fr_next
)
7978 if (next_fragP
== symbol_get_frag (symbolP
))
7980 if (next_fragP
->fr_fix
!= 0)
7988 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7990 const expressionS
*expr
;
7994 if (insn
->insn_type
!= ITYPE_INSN
)
7997 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
8000 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8003 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8005 if (expr
->X_op
!= O_symbol
)
8008 symbolP
= expr
->X_add_symbol
;
8012 if (symbol_get_frag (symbolP
) == NULL
)
8015 /* Walk through fragments until we find the target.
8016 If we do not find the target, then this is an invalid loop. */
8018 for (next_fragP
= fragP
->fr_next
;
8020 next_fragP
= next_fragP
->fr_next
)
8022 if (next_fragP
== symbol_get_frag (symbolP
))
8030 /* Alignment Functions. */
8033 get_text_align_power (int target_size
)
8036 for (i
= 0; i
< sizeof (size_t); i
++)
8038 if (target_size
<= (1 << i
))
8047 get_text_align_max_fill_size (int align_pow
,
8048 bfd_boolean use_nops
,
8049 bfd_boolean use_no_density
)
8052 return (1 << align_pow
);
8054 return 3 * (1 << align_pow
);
8056 return 1 + (1 << align_pow
);
8060 /* get_text_align_fill_size ()
8064 target_size = size of next instruction
8065 align_pow = get_text_align_power (target_size).
8069 address = current address + loop instruction size;
8070 target_size = 3 (for 2 or 3 byte target)
8071 = 4 (for 4 byte target)
8072 = 8 (for 8 byte target)
8073 align_pow = get_text_align_power (target_size);
8075 use_no_density = set appropriately
8077 address = current address + loop instruction size;
8079 align_pow = get_text_align_power (target_size);
8081 use_no_density = 0. */
8084 get_text_align_fill_size (addressT address
,
8087 bfd_boolean use_nops
,
8088 bfd_boolean use_no_density
)
8092 align_pow: log2 (required alignment).
8094 target_size: alignment must allow the new_address and
8095 new_address+target_size-1.
8097 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8099 use_no_density: if use_nops and use_no_density, we can only use
8102 Usually the align_pow is the power of 2 that is greater than
8103 or equal to the target_size. This handles the 2-byte, 3-byte
8104 and 8-byte instructions.
8108 (1) aligning an instruction properly, but without using NOPs.
8109 E.G.: a 3-byte instruction can go on any address where address mod 4
8110 is zero or one. The aligner uses this case to find the optimal
8111 number of fill bytes for relax_frag_for_align.
8113 (2) aligning an instruction properly, but where we might need to use
8114 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8115 or similar to get the optimal location. */
8117 size_t alignment
= (1 << align_pow
);
8119 assert (target_size
!= 0);
8123 unsigned fill_bytes
;
8124 for (fill_bytes
= 0; fill_bytes
< alignment
; fill_bytes
++)
8126 addressT end_address
= address
+ target_size
- 1 + fill_bytes
;
8127 addressT start_address
= address
+ fill_bytes
;
8128 if ((end_address
>> align_pow
) == (start_address
>> align_pow
))
8134 /* This is the slightly harder case. */
8135 assert ((int) alignment
>= target_size
);
8136 assert (target_size
> 0);
8137 if (!use_no_density
)
8140 for (i
= 0; i
< alignment
* 2; i
++)
8144 if ((address
+ i
) >> align_pow
8145 == (address
+ i
+ target_size
- 1) >> align_pow
)
8153 /* Can only fill multiples of 3. */
8154 for (i
= 0; i
<= alignment
* 3; i
+= 3)
8156 if ((address
+ i
) >> align_pow
8157 == (address
+ i
+ target_size
- 1) >> align_pow
)
8166 /* This will assert if it is not possible. */
8169 get_text_align_nop_count (size_t fill_size
, bfd_boolean use_no_density
)
8174 assert (fill_size
% 3 == 0);
8175 return (fill_size
/ 3);
8178 assert (fill_size
!= 1); /* Bad argument. */
8180 while (fill_size
> 1)
8182 size_t insn_size
= 3;
8183 if (fill_size
== 2 || fill_size
== 4)
8185 fill_size
-= insn_size
;
8188 assert (fill_size
!= 1); /* Bad algorithm. */
8194 get_text_align_nth_nop_size (size_t fill_size
,
8196 bfd_boolean use_no_density
)
8200 assert (get_text_align_nop_count (fill_size
, use_no_density
) > n
);
8205 while (fill_size
> 1)
8207 size_t insn_size
= 3;
8208 if (fill_size
== 2 || fill_size
== 4)
8210 fill_size
-= insn_size
;
8220 /* For the given fragment, find the appropriate address
8221 for it to begin at if we are using NOPs to align it. */
8224 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8226 /* The rule is: get next fragment's FIRST instruction. Find
8227 the smallest number of bytes that need to be added to
8228 ensure that the next fragment's FIRST instruction will fit
8231 E.G., 2 bytes : 0, 1, 2 mod 4
8234 If the FIRST instruction MIGHT be relaxed,
8235 assume that it will become a 3-byte instruction.
8237 Note again here that LOOP instructions are not bundleable,
8238 and this relaxation only applies to LOOP opcodes. */
8240 size_t fill_size
= 0;
8241 int first_insn_size
;
8243 addressT pre_opcode_bytes
;
8246 xtensa_opcode opcode
;
8247 bfd_boolean is_loop
;
8249 assert (fragP
->fr_type
== rs_machine_dependent
);
8250 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8252 /* Find the loop frag. */
8253 first_insn
= next_non_empty_frag (fragP
);
8254 /* Now find the first insn frag. */
8255 first_insn
= next_non_empty_frag (first_insn
);
8257 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8259 loop_insn_size
= xg_get_single_size (opcode
);
8261 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8262 pre_opcode_bytes
+= loop_insn_size
;
8264 /* For loops, the alignment depends on the size of the
8265 instruction following the loop, not the LOOP instruction. */
8267 if (first_insn
== NULL
)
8270 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8272 first_insn_size
= frag_format_size (first_insn
);
8274 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8275 first_insn_size
= 3; /* ISA specifies this */
8277 /* If it was 8, then we'll need a larger alignment for the section. */
8278 alignment
= get_text_align_power (first_insn_size
);
8280 /* Is now_seg valid? */
8281 record_alignment (now_seg
, alignment
);
8283 fill_size
= get_text_align_fill_size
8284 (address
+ pre_opcode_bytes
,
8285 get_text_align_power (first_insn_size
),
8286 first_insn_size
, TRUE
, fragP
->tc_frag_data
.is_no_density
);
8288 return address
+ fill_size
;
8292 /* 3 mechanisms for relaxing an alignment:
8294 Align to a power of 2.
8295 Align so the next fragment's instruction does not cross a word boundary.
8296 Align the current instruction so that if the next instruction
8297 were 3 bytes, it would not cross a word boundary.
8301 zeros - This is easy; always insert zeros.
8302 nops - 3-byte and 2-byte instructions
8306 >=5 : 3-byte instruction + fn (n-3)
8307 widening - widen previous instructions. */
8310 get_aligned_diff (fragS
*fragP
, addressT address
, addressT
*max_diff
)
8312 addressT target_address
, loop_insn_offset
;
8314 xtensa_opcode loop_opcode
;
8315 bfd_boolean is_loop
;
8316 int text_align_power
;
8319 assert (fragP
->fr_type
== rs_machine_dependent
);
8320 switch (fragP
->fr_subtype
)
8322 case RELAX_DESIRE_ALIGN
:
8323 target_size
= next_frag_format_size (fragP
);
8324 if (target_size
== XTENSA_UNDEFINED
)
8326 text_align_power
= get_text_align_power (xtensa_fetch_width
);
8327 opt_diff
= get_text_align_fill_size (address
, text_align_power
,
8328 target_size
, FALSE
, FALSE
);
8330 *max_diff
= opt_diff
+ xtensa_fetch_width
8331 - (target_size
+ ((address
+ opt_diff
) % xtensa_fetch_width
));
8332 assert (*max_diff
>= opt_diff
);
8335 case RELAX_ALIGN_NEXT_OPCODE
:
8336 target_size
= next_frag_format_size (fragP
);
8337 loop_insn_offset
= 0;
8338 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8341 /* If the loop has been expanded then the LOOP instruction
8342 could be at an offset from this fragment. */
8343 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8345 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8347 if (target_size
== 2)
8348 target_size
= 3; /* ISA specifies this */
8350 /* In an ideal world, which is what we are shooting for here,
8351 we wouldn't need to use any NOPs immediately prior to the
8352 LOOP instruction. If this approach fails, relax_frag_loop_align
8353 will call get_noop_aligned_address. */
8355 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8356 text_align_power
= get_text_align_power (target_size
),
8357 opt_diff
= get_text_align_fill_size (target_address
, text_align_power
,
8358 target_size
, FALSE
, FALSE
);
8360 *max_diff
= xtensa_fetch_width
8361 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8362 - target_size
+ opt_diff
;
8363 assert (*max_diff
>= opt_diff
);
8374 /* md_relax_frag Hook and Helper Functions. */
8376 static long relax_frag_loop_align (fragS
*, long);
8377 static long relax_frag_for_align (fragS
*, long);
8378 static long relax_frag_immed
8379 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8382 /* Return the number of bytes added to this fragment, given that the
8383 input has been stretched already by "stretch". */
8386 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8388 xtensa_isa isa
= xtensa_default_isa
;
8389 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8390 long new_stretch
= 0;
8393 static xtensa_insnbuf vbuf
= NULL
;
8394 int slot
, num_slots
;
8397 as_where (&file_name
, &line
);
8398 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8400 fragP
->tc_frag_data
.unreported_expansion
= 0;
8402 switch (fragP
->fr_subtype
)
8404 case RELAX_ALIGN_NEXT_OPCODE
:
8405 /* Always convert. */
8406 if (fragP
->tc_frag_data
.relax_seen
)
8407 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8410 case RELAX_LOOP_END
:
8414 case RELAX_LOOP_END_ADD_NOP
:
8415 /* Add a NOP and switch to .fill 0. */
8416 new_stretch
= relax_frag_add_nop (fragP
);
8420 case RELAX_DESIRE_ALIGN
:
8421 /* Do nothing. The narrowing before this frag will either align
8426 case RELAX_LITERAL_FINAL
:
8429 case RELAX_LITERAL_NR
:
8431 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8432 assert (unreported
== lit_size
);
8433 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8434 fragP
->fr_var
-= lit_size
;
8435 fragP
->fr_fix
+= lit_size
;
8441 vbuf
= xtensa_insnbuf_alloc (isa
);
8443 xtensa_insnbuf_from_chars (isa
, vbuf
, fragP
->fr_opcode
, 0);
8444 fmt
= xtensa_format_decode (isa
, vbuf
);
8445 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8447 for (slot
= 0; slot
< num_slots
; slot
++)
8449 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8452 if (fragP
->tc_frag_data
.relax_seen
)
8453 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8457 case RELAX_IMMED_STEP1
:
8458 case RELAX_IMMED_STEP2
:
8459 /* Place the immediate. */
8460 new_stretch
+= relax_frag_immed
8461 (now_seg
, fragP
, stretch
,
8462 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8463 fmt
, slot
, stretched_p
, FALSE
);
8467 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8473 case RELAX_LITERAL_POOL_BEGIN
:
8474 case RELAX_LITERAL_POOL_END
:
8475 case RELAX_MAYBE_UNREACHABLE
:
8476 case RELAX_MAYBE_DESIRE_ALIGN
:
8477 /* No relaxation required. */
8480 case RELAX_FILL_NOP
:
8481 case RELAX_UNREACHABLE
:
8482 if (fragP
->tc_frag_data
.relax_seen
)
8483 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8487 as_bad (_("bad relaxation state"));
8490 /* Tell gas we need another relaxation pass. */
8491 if (! fragP
->tc_frag_data
.relax_seen
)
8493 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8497 new_logical_line (file_name
, line
);
8503 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8505 addressT old_address
, old_next_address
, old_size
;
8506 addressT new_address
, new_next_address
, new_size
;
8509 /* All the frags with relax_frag_for_alignment prior to this one in the
8510 section have been done, hopefully eliminating the need for a NOP here.
8511 But, this will put it in if necessary. */
8513 /* Calculate the old address of this fragment and the next fragment. */
8514 old_address
= fragP
->fr_address
- stretch
;
8515 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8516 fragP
->tc_frag_data
.text_expansion
[0]);
8517 old_size
= old_next_address
- old_address
;
8519 /* Calculate the new address of this fragment and the next fragment. */
8520 new_address
= fragP
->fr_address
;
8522 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8523 new_size
= new_next_address
- new_address
;
8525 growth
= new_size
- old_size
;
8527 /* Fix up the text_expansion field and return the new growth. */
8528 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8533 /* Add a NOP instruction. */
8536 relax_frag_add_nop (fragS
*fragP
)
8538 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8539 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8540 assemble_nop (length
, nop_buf
);
8541 fragP
->tc_frag_data
.is_insn
= TRUE
;
8543 if (fragP
->fr_var
< length
)
8545 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
8549 fragP
->fr_fix
+= length
;
8550 fragP
->fr_var
-= length
;
8555 static long future_alignment_required (fragS
*, long);
8558 relax_frag_for_align (fragS
*fragP
, long stretch
)
8560 /* Overview of the relaxation procedure for alignment:
8561 We can widen with NOPs or by widening instructions or by filling
8562 bytes after jump instructions. Find the opportune places and widen
8563 them if necessary. */
8568 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8569 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8570 || (fragP
->fr_subtype
== RELAX_SLOTS
8571 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8573 stretch_me
= future_alignment_required (fragP
, stretch
);
8574 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8580 /* We expanded on a previous pass. Can we shrink now? */
8581 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8582 if (shrink
<= stretch
&& stretch
> 0)
8584 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8590 /* Below here, diff > 0. */
8591 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8597 /* Return the address of the next frag that should be aligned.
8599 By "address" we mean the address it _would_ be at if there
8600 is no action taken to align it between here and the target frag.
8601 In other words, if no narrows and no fill nops are used between
8602 here and the frag to align, _even_if_ some of the frags we use
8603 to align targets have already expanded on a previous relaxation
8606 Also, count each frag that may be used to help align the target.
8608 Return 0 if there are no frags left in the chain that need to be
8612 find_address_of_next_align_frag (fragS
**fragPP
,
8616 bfd_boolean
*paddable
)
8618 fragS
*fragP
= *fragPP
;
8619 addressT address
= fragP
->fr_address
;
8621 /* Do not reset the counts to 0. */
8625 /* Limit this to a small search. */
8631 address
+= fragP
->fr_fix
;
8633 if (fragP
->fr_type
== rs_fill
)
8634 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8635 else if (fragP
->fr_type
== rs_machine_dependent
)
8637 switch (fragP
->fr_subtype
)
8639 case RELAX_UNREACHABLE
:
8643 case RELAX_FILL_NOP
:
8645 if (!fragP
->tc_frag_data
.is_no_density
)
8650 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8655 /* FIXME: shouldn't this add the expansion of all slots? */
8656 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8660 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8663 case RELAX_ALIGN_NEXT_OPCODE
:
8664 case RELAX_DESIRE_ALIGN
:
8668 case RELAX_MAYBE_UNREACHABLE
:
8669 case RELAX_MAYBE_DESIRE_ALIGN
:
8674 /* Just punt if we don't know the type. */
8681 /* Just punt if we don't know the type. */
8685 fragP
= fragP
->fr_next
;
8693 static long bytes_to_stretch (fragS
*, int, int, int, int);
8695 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8696 I'll leave this in until I am more confident this works. */
8698 #define LOOKAHEAD_ALIGNER 1
8701 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8703 fragS
*this_frag
= fragP
;
8707 int narrow_nops
= 0;
8708 bfd_boolean paddable
= FALSE
;
8709 offsetT local_opt_diff
;
8712 int stretch_amount
= 0;
8713 int local_stretch_amount
;
8714 int global_stretch_amount
;
8716 address
= find_address_of_next_align_frag
8717 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8721 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8722 opt_diff
= local_opt_diff
;
8723 assert (opt_diff
>= 0);
8724 assert (max_diff
>= opt_diff
);
8727 #ifdef LOOKAHEAD_ALIGNER
8729 fragP
= fragP
->fr_next
;
8731 while (fragP
&& opt_diff
< max_diff
&& address
)
8733 /* We only use these to determine if we can exit early
8734 because there will be plenty of ways to align future
8736 unsigned int glob_widens
= 0;
8739 bfd_boolean glob_pad
= 0;
8740 address
= find_address_of_next_align_frag
8741 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8742 /* If there is a padable portion, then skip. */
8743 if (glob_pad
|| (glob_widens
>= xtensa_fetch_width
))
8748 offsetT next_m_diff
;
8749 offsetT next_o_diff
;
8751 /* Downrange frags haven't had stretch added to them yet. */
8754 /* The address also includes any text expansion from this
8755 frag in a previous pass, but we don't want that. */
8756 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8758 /* Assume we are going to move at least opt_diff. In
8759 reality, we might not be able to, but assuming that
8760 we will helps catch cases where moving opt_diff pushes
8761 the next target from aligned to unaligned. */
8762 address
+= opt_diff
;
8764 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8766 /* Now cleanup for the adjustments to address. */
8767 next_o_diff
+= opt_diff
;
8768 next_m_diff
+= opt_diff
;
8769 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8770 opt_diff
= next_o_diff
;
8771 if (next_m_diff
< max_diff
)
8772 max_diff
= next_m_diff
;
8773 fragP
= fragP
->fr_next
;
8776 #endif /* LOOKAHEAD_ALIGNER */
8777 /* If there are enough wideners in between, do it. */
8780 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8782 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8787 local_stretch_amount
8788 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8789 num_widens
, local_opt_diff
);
8790 #ifdef LOOKAHEAD_ALIGNER
8791 global_stretch_amount
8792 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8793 num_widens
, opt_diff
);
8794 /* If the condition below is true, then the frag couldn't
8795 stretch the correct amount for the global case, so we just
8796 optimize locally. We'll rely on the subsequent frags to get
8797 the correct alignment in the global case. */
8798 if (global_stretch_amount
< local_stretch_amount
)
8799 stretch_amount
= local_stretch_amount
;
8801 stretch_amount
= global_stretch_amount
;
8802 #else /* ! LOOKAHEAD_ALIGNER */
8803 stretch_amount
= local_stretch_amount
;
8804 #endif /* ! LOOKAHEAD_ALIGNER */
8805 if (this_frag
->fr_subtype
== RELAX_SLOTS
8806 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8807 assert (stretch_amount
<= 1);
8808 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8810 if (this_frag
->tc_frag_data
.is_no_density
)
8811 assert (stretch_amount
== 3 || stretch_amount
== 0);
8813 assert (stretch_amount
<= 3);
8816 return stretch_amount
;
8820 /* The idea: widen everything you can to get a target or loop aligned,
8821 then start using NOPs.
8823 When we must have a NOP, here is a table of how we decide
8824 (so you don't have to fight through the control flow below):
8826 wide_nops = the number of wide NOPs available for aligning
8827 narrow_nops = the number of narrow NOPs available for aligning
8828 (a subset of wide_nops)
8829 widens = the number of narrow instructions that should be widened
8836 b 0 1 1 (case 3a makes this case unnecessary)
8839 c 0 1 2 (case 4a makes this case unnecessary)
8842 c 0 2 1 (case 5b makes this case unnecessary)
8845 c 0 1 4 (case 6b makes this case unneccesary)
8846 d 1 1 1 (case 6a makes this case unnecessary)
8847 e 0 2 2 (case 6a makes this case unnecessary)
8848 f 0 3 0 (case 6a makes this case unnecessary)
8851 c 1 1 2 (case 7b makes this case unnecessary)
8852 d 0 1 5 (case 7a makes this case unnecessary)
8853 e 0 2 3 (case 7b makes this case unnecessary)
8854 f 0 3 1 (case 7b makes this case unnecessary)
8855 g 1 2 1 (case 7b makes this case unnecessary)
8859 bytes_to_stretch (fragS
*this_frag
,
8865 int bytes_short
= desired_diff
- num_widens
;
8867 assert (desired_diff
>= 0 && desired_diff
< 8);
8868 if (desired_diff
== 0)
8871 assert (wide_nops
> 0 || num_widens
> 0);
8873 /* Always prefer widening to NOP-filling. */
8874 if (bytes_short
< 0)
8876 /* There are enough RELAX_NARROW frags after this one
8877 to align the target without widening this frag in any way. */
8881 if (bytes_short
== 0)
8883 /* Widen every narrow between here and the align target
8884 and the align target will be properly aligned. */
8885 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8891 /* From here we will need at least one NOP to get an alignment.
8892 However, we may not be able to align at all, in which case,
8894 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8896 switch (desired_diff
)
8901 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8902 return 2; /* case 2 */
8908 return 3; /* case 3a */
8910 if (num_widens
>= 1 && wide_nops
== 1)
8911 return 3; /* case 4a */
8912 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8913 return 2; /* case 4b */
8916 if (num_widens
>= 2 && wide_nops
== 1)
8917 return 3; /* case 5a */
8918 /* We will need two nops. Are there enough nops
8919 between here and the align target? */
8920 if (wide_nops
< 2 || narrow_nops
== 0)
8922 /* Are there other nops closer that can serve instead? */
8923 if (wide_nops
> 2 && narrow_nops
> 1)
8925 /* Take the density one first, because there might not be
8926 another density one available. */
8927 if (!this_frag
->tc_frag_data
.is_no_density
)
8928 return 2; /* case 5b narrow */
8930 return 3; /* case 5b wide */
8934 return 3; /* case 6a */
8935 else if (num_widens
>= 3 && wide_nops
== 1)
8936 return 3; /* case 6b */
8939 if (wide_nops
== 1 && num_widens
>= 4)
8940 return 3; /* case 7a */
8941 else if (wide_nops
== 2 && num_widens
>= 1)
8942 return 3; /* case 7b */
8950 /* We will need a NOP no matter what, but should we widen
8951 this instruction to help?
8953 This is a RELAX_FRAG_NARROW frag. */
8954 switch (desired_diff
)
8963 if (wide_nops
>= 1 && num_widens
== 1)
8964 return 1; /* case 4a */
8967 if (wide_nops
>= 1 && num_widens
== 2)
8968 return 1; /* case 5a */
8972 return 0; /* case 6a */
8973 else if (wide_nops
>= 1 && num_widens
== 3)
8974 return 1; /* case 6b */
8977 if (wide_nops
>= 1 && num_widens
== 4)
8978 return 1; /* case 7a */
8979 else if (wide_nops
>= 2 && num_widens
== 1)
8980 return 1; /* case 7b */
8993 relax_frag_immed (segT segP
,
9000 bfd_boolean estimate_only
)
9003 vliw_insn orig_vinsn
;
9005 bfd_boolean negatable_branch
= FALSE
;
9006 bfd_boolean branch_jmp_to_next
= FALSE
;
9007 bfd_boolean wide_insn
= FALSE
;
9008 xtensa_isa isa
= xtensa_default_isa
;
9010 offsetT frag_offset
;
9013 int num_text_bytes
, num_literal_bytes
;
9014 int literal_diff
, total_text_diff
, this_text_diff
, first
;
9016 assert (fragP
->fr_opcode
!= NULL
);
9018 xg_init_vinsn (&orig_vinsn
);
9019 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
9020 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9023 tinsn
= orig_vinsn
.slots
[slot
];
9024 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9026 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
9029 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9030 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9032 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9034 old_size
= xtensa_format_length (isa
, fmt
);
9036 /* Special case: replace a branch to the next instruction with a NOP.
9037 This is required to work around a hardware bug in T1040.0 and also
9038 serves as an optimization. */
9040 if (branch_jmp_to_next
9041 && ((old_size
== 2) || (old_size
== 3))
9042 && !next_frag_is_loop_target (fragP
))
9045 /* Here is the fun stuff: Get the immediate field from this
9046 instruction. If it fits, we are done. If not, find the next
9047 instruction sequence that fits. */
9049 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9050 istack_init (&istack
);
9051 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9052 min_steps
, stretch
);
9053 if (num_steps
< min_steps
)
9055 as_fatal (_("internal error: relaxation failed"));
9059 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9061 as_fatal (_("internal error: relaxation requires too many steps"));
9065 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9067 /* Figure out the number of bytes needed. */
9069 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9071 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9073 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9075 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9078 num_text_bytes
+= old_size
;
9079 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9080 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9082 total_text_diff
= num_text_bytes
- old_size
;
9083 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9085 /* It MUST get larger. If not, we could get an infinite loop. */
9086 assert (num_text_bytes
>= 0);
9087 assert (literal_diff
>= 0);
9088 assert (total_text_diff
>= 0);
9090 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9091 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9092 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9093 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9095 /* Find the associated expandable literal for this. */
9096 if (literal_diff
!= 0)
9098 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9101 assert (literal_diff
== 4);
9102 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9104 /* We expect that the literal section state has NOT been
9106 assert (lit_fragP
->fr_type
== rs_machine_dependent
9107 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9108 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9110 /* We need to mark this section for another iteration
9116 /* FIXME: When a negatable branch expands and then contracts in a
9117 subsequent pass, update_next_frag_state correctly updates the
9118 type of the frag to RELAX_MAYBE_UNREACHABLE, but it doesn't undo
9119 any expansion relax_frag_for_align may have expected it to. For
9120 now, change back to only call it when the branch expands. */
9121 if (negatable_branch
&& istack
.ninsn
> 1)
9122 update_next_frag_state (fragP
, FALSE
/* istack.ninsn > 1 */);
9124 return this_text_diff
;
9128 /* md_convert_frag Hook and Helper Functions. */
9130 static void convert_frag_align_next_opcode (fragS
*);
9131 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9132 static void convert_frag_fill_nop (fragS
*);
9133 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9136 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9138 static xtensa_insnbuf vbuf
= NULL
;
9139 xtensa_isa isa
= xtensa_default_isa
;
9146 as_where (&file_name
, &line
);
9147 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9149 switch (fragp
->fr_subtype
)
9151 case RELAX_ALIGN_NEXT_OPCODE
:
9152 /* Always convert. */
9153 convert_frag_align_next_opcode (fragp
);
9156 case RELAX_DESIRE_ALIGN
:
9157 /* Do nothing. If not aligned already, too bad. */
9161 case RELAX_LITERAL_FINAL
:
9166 vbuf
= xtensa_insnbuf_alloc (isa
);
9168 xtensa_insnbuf_from_chars (isa
, vbuf
, fragp
->fr_opcode
, 0);
9169 fmt
= xtensa_format_decode (isa
, vbuf
);
9170 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9172 for (slot
= 0; slot
< num_slots
; slot
++)
9174 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9177 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9181 case RELAX_IMMED_STEP1
:
9182 case RELAX_IMMED_STEP2
:
9183 /* Place the immediate. */
9186 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9191 /* This is OK because some slots could have
9192 relaxations and others have none. */
9198 case RELAX_UNREACHABLE
:
9199 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9200 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9201 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9205 case RELAX_MAYBE_UNREACHABLE
:
9206 case RELAX_MAYBE_DESIRE_ALIGN
:
9210 case RELAX_FILL_NOP
:
9211 convert_frag_fill_nop (fragp
);
9214 case RELAX_LITERAL_NR
:
9215 if (use_literal_section
)
9217 /* This should have been handled during relaxation. When
9218 relaxing a code segment, literals sometimes need to be
9219 added to the corresponding literal segment. If that
9220 literal segment has already been relaxed, then we end up
9221 in this situation. Marking the literal segments as data
9222 would make this happen less often (since GAS always relaxes
9223 code before data), but we could still get into trouble if
9224 there are instructions in a segment that is not marked as
9225 containing code. Until we can implement a better solution,
9226 cheat and adjust the addresses of all the following frags.
9227 This could break subsequent alignments, but the linker's
9228 literal coalescing will do that anyway. */
9231 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9232 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9233 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9236 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9240 as_bad (_("invalid relaxation fragment result"));
9245 new_logical_line (file_name
, line
);
9250 convert_frag_align_next_opcode (fragS
*fragp
)
9252 char *nop_buf
; /* Location for Writing. */
9255 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9256 addressT aligned_address
;
9257 size_t fill_size
, nop_count
;
9259 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9261 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9262 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9263 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9265 for (i
= 0; i
< nop_count
; i
++)
9268 nop_size
= get_text_align_nth_nop_size (fill_size
, i
, use_no_density
);
9270 assemble_nop (nop_size
, nop_buf
);
9271 nop_buf
+= nop_size
;
9274 fragp
->fr_fix
+= fill_size
;
9275 fragp
->fr_var
-= fill_size
;
9280 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9282 TInsn tinsn
, single_target
;
9283 xtensa_format single_fmt
;
9284 int size
, old_size
, diff
, error_val
;
9285 offsetT frag_offset
;
9288 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9290 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9292 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9293 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9294 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9299 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9301 /* No conversion. */
9306 assert (fragP
->fr_opcode
!= NULL
);
9308 /* Frags in this relaxation state should only contain
9309 single instruction bundles. */
9310 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9312 /* Just convert it to a wide form.... */
9314 old_size
= xg_get_single_size (tinsn
.opcode
);
9316 tinsn_init (&single_target
);
9317 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9319 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9322 as_bad (_("unable to widen instruction"));
9326 size
= xg_get_single_size (single_target
.opcode
);
9327 single_fmt
= xg_get_single_format (single_target
.opcode
);
9329 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9330 fragP
, frag_offset
, TRUE
);
9332 diff
= size
- old_size
;
9334 assert (diff
<= fragP
->fr_var
);
9335 fragP
->fr_var
-= diff
;
9336 fragP
->fr_fix
+= diff
;
9344 convert_frag_fill_nop (fragS
*fragP
)
9346 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9347 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9348 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9349 - fragP
->fr_address
- fragP
->fr_fix
));
9352 /* No conversion. */
9356 assemble_nop (size
, loc
);
9357 fragP
->tc_frag_data
.is_insn
= TRUE
;
9358 fragP
->fr_var
-= size
;
9359 fragP
->fr_fix
+= size
;
9364 static fixS
*fix_new_exp_in_seg
9365 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9366 bfd_reloc_code_real_type
);
9367 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9370 convert_frag_immed (segT segP
,
9376 char *immed_instr
= fragP
->fr_opcode
;
9378 bfd_boolean expanded
= FALSE
;
9379 bfd_boolean branch_jmp_to_next
= FALSE
;
9380 char *fr_opcode
= fragP
->fr_opcode
;
9381 vliw_insn orig_vinsn
;
9382 xtensa_isa isa
= xtensa_default_isa
;
9383 bfd_boolean wide_insn
= FALSE
;
9385 bfd_boolean is_loop
;
9387 assert (fr_opcode
!= NULL
);
9389 xg_init_vinsn (&orig_vinsn
);
9391 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9392 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9395 orig_tinsn
= orig_vinsn
.slots
[slot
];
9396 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9398 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9400 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9401 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9403 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9405 /* Conversion just inserts a NOP and marks the fix as completed. */
9406 bytes
= xtensa_format_length (isa
, fmt
);
9409 orig_vinsn
.slots
[slot
].opcode
=
9410 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9411 orig_vinsn
.slots
[slot
].ntok
= 0;
9415 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9416 assert (bytes
== 2 || bytes
== 3);
9417 build_nop (&orig_vinsn
.slots
[0], bytes
);
9418 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9420 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9421 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
, fr_opcode
, 0);
9424 else if (!orig_tinsn
.is_specific_opcode
)
9426 /* Here is the fun stuff: Get the immediate field from this
9427 instruction. If it fits, we're done. If not, find the next
9428 instruction sequence that fits. */
9432 symbolS
*lit_sym
= NULL
;
9434 int target_offset
= 0;
9437 symbolS
*gen_label
= NULL
;
9438 offsetT frag_offset
;
9439 bfd_boolean first
= TRUE
;
9440 bfd_boolean last_is_jump
;
9442 /* It does not fit. Find something that does and
9443 convert immediately. */
9444 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9445 istack_init (&istack
);
9446 xg_assembly_relax (&istack
, &orig_tinsn
,
9447 segP
, fragP
, frag_offset
, min_steps
, 0);
9449 old_size
= xtensa_format_length (isa
, fmt
);
9451 /* Assemble this right inline. */
9453 /* First, create the mapping from a label name to the REAL label. */
9455 for (i
= 0; i
< istack
.ninsn
; i
++)
9457 TInsn
*tinsn
= &istack
.insn
[i
];
9460 switch (tinsn
->insn_type
)
9463 if (lit_sym
!= NULL
)
9464 as_bad (_("multiple literals in expansion"));
9465 /* First find the appropriate space in the literal pool. */
9466 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9467 if (lit_frag
== NULL
)
9468 as_bad (_("no registered fragment for literal"));
9469 if (tinsn
->ntok
!= 1)
9470 as_bad (_("number of literal tokens != 1"));
9472 /* Set the literal symbol and add a fixup. */
9473 lit_sym
= lit_frag
->fr_symbol
;
9477 if (align_targets
&& !is_loop
)
9479 fragS
*unreach
= fragP
->fr_next
;
9480 while (!(unreach
->fr_type
== rs_machine_dependent
9481 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9482 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9484 unreach
= unreach
->fr_next
;
9487 assert (unreach
->fr_type
== rs_machine_dependent
9488 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9489 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9491 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9493 assert (gen_label
== NULL
);
9494 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9495 fr_opcode
- fragP
->fr_literal
9496 + target_offset
, fragP
);
9500 if (first
&& wide_insn
)
9502 target_offset
+= xtensa_format_length (isa
, fmt
);
9504 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9505 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9508 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9515 last_is_jump
= FALSE
;
9516 for (i
= 0; i
< istack
.ninsn
; i
++)
9518 TInsn
*tinsn
= &istack
.insn
[i
];
9522 bfd_reloc_code_real_type reloc_type
;
9524 switch (tinsn
->insn_type
)
9527 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9528 /* Already checked. */
9529 assert (lit_frag
!= NULL
);
9530 assert (lit_sym
!= NULL
);
9531 assert (tinsn
->ntok
== 1);
9533 target_seg
= S_GET_SEGMENT (lit_sym
);
9534 assert (target_seg
);
9535 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9536 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9538 reloc_type
= BFD_RELOC_32
;
9539 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9540 &tinsn
->tok
[0], FALSE
, reloc_type
);
9547 xg_resolve_labels (tinsn
, gen_label
);
9548 xg_resolve_literals (tinsn
, lit_sym
);
9549 if (wide_insn
&& first
)
9552 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9554 tinsn
->record_fix
= TRUE
;
9555 orig_vinsn
.slots
[slot
] = *tinsn
;
9559 orig_vinsn
.slots
[slot
].opcode
=
9560 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9561 orig_vinsn
.slots
[slot
].ntok
= 0;
9562 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9564 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9565 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9567 fragP
->tc_frag_data
.is_insn
= TRUE
;
9568 size
= xtensa_format_length (isa
, fmt
);
9569 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9571 xtensa_format single_fmt
=
9572 xg_get_single_format (tinsn
->opcode
);
9575 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9576 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9577 size
+= xg_get_single_size (tinsn
->opcode
);
9582 xtensa_format single_format
;
9583 size
= xg_get_single_size (tinsn
->opcode
);
9584 single_format
= xg_get_single_format (tinsn
->opcode
);
9585 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9587 immed_instr
- fragP
->fr_literal
, TRUE
);
9589 /* Code to recognize branch-around expansion
9590 so the fragment is properly marked as ending in a
9592 if ((((i
== istack
.ninsn
- 2)
9593 && (istack
.insn
[istack
.ninsn
-1].insn_type
9595 || i
== istack
.ninsn
-1)
9596 && xtensa_opcode_is_jump (xtensa_default_isa
,
9598 && fragP
->fr_next
!= NULL
9599 && ! fragP
->fr_next
->tc_frag_data
.is_unreachable
)
9601 /* Create a new unreachable frag of zero size. */
9602 size_t frag_size
= sizeof (fragS
);
9603 fragS
*new_fragP
= (fragS
*) xmalloc (frag_size
);
9604 memset (new_fragP
, 0, frag_size
);
9605 new_fragP
->fr_address
= fragP
->fr_next
->fr_address
;
9606 new_fragP
->fr_next
= fragP
->fr_next
;
9607 new_fragP
->fr_fix
= 0;
9608 new_fragP
->fr_var
= 0;
9609 new_fragP
->fr_type
= rs_fill
;
9610 new_fragP
->tc_frag_data
.is_unreachable
= TRUE
;
9611 /* The rest are zeros.... */
9612 /* Link it in to the chain. */
9613 fragP
->fr_next
= new_fragP
;
9617 immed_instr
+= size
;
9623 diff
= total_size
- old_size
;
9627 assert (diff
<= fragP
->fr_var
);
9628 fragP
->fr_var
-= diff
;
9629 fragP
->fr_fix
+= diff
;
9633 xg_free_vinsn (&orig_vinsn
);
9635 /* Check for undefined immediates in LOOP instructions. */
9639 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9640 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9642 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9645 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9646 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9648 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9653 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9654 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9656 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9658 /* Add an expansion note on the expanded instruction. */
9659 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9660 &orig_tinsn
.tok
[0], TRUE
,
9661 BFD_RELOC_XTENSA_ASM_EXPAND
);
9666 /* Add a new fix expression into the desired segment. We have to
9667 switch to that segment to do this. */
9670 fix_new_exp_in_seg (segT new_seg
,
9677 bfd_reloc_code_real_type r_type
)
9681 subsegT subseg
= now_subseg
;
9683 assert (new_seg
!= 0);
9684 subseg_set (new_seg
, new_subseg
);
9686 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9687 subseg_set (seg
, subseg
);
9692 /* Relax a loop instruction so that it can span loop >256 bytes.
9698 addi as, as, lo8 (label-.L1)
9699 addmi as, as, mid8 (label-.L1)
9710 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9715 unsigned long target
;
9716 static xtensa_insnbuf insnbuf
= NULL
;
9717 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9718 xtensa_isa isa
= xtensa_default_isa
;
9719 addressT loop_offset
;
9720 addressT addi_offset
= 9;
9721 addressT addmi_offset
= 12;
9723 size_t target_count
;
9726 insnbuf
= xtensa_insnbuf_alloc (isa
);
9728 /* Get the loop offset. */
9729 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9731 /* Validate that there really is a LOOP at the loop_offset. Because
9732 loops are not bundleable, we can assume that the instruction will be
9734 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9735 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9737 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9738 addi_offset
+= loop_offset
;
9739 addmi_offset
+= loop_offset
;
9741 assert (tinsn
->ntok
== 2);
9742 if (tinsn
->tok
[1].X_op
== O_constant
)
9743 target
= tinsn
->tok
[1].X_add_number
;
9744 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9746 /* Find the fragment. */
9747 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9748 assert (S_GET_SEGMENT (sym
) == segP
9749 || S_GET_SEGMENT (sym
) == absolute_section
);
9750 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9754 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9759 know (symbolP
->sy_frag
);
9760 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9761 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9763 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9764 loop_length_hi
= loop_length
& ~0x0ff;
9765 loop_length_lo
= loop_length
& 0x0ff;
9766 if (loop_length_lo
>= 128)
9768 loop_length_lo
-= 256;
9769 loop_length_hi
+= 256;
9772 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9773 32512. If the loop is larger than that, then we just fail. */
9774 if (loop_length_hi
> 32512)
9775 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9776 _("loop too long for LOOP instruction"));
9778 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9779 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9781 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9782 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9784 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9785 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9787 fragP
->tc_frag_data
.is_insn
= TRUE
;
9788 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addi_offset
, 0);
9790 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9791 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9792 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addmi_offset
, 0);
9794 /* Walk through all of the frags from here to the loop end
9795 and mark them as no_transform to keep them from being modified
9796 by the linker. If we ever have a relocation for the
9797 addi/addmi of the difference of two symbols we can remove this. */
9800 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9801 next_fragP
= next_fragP
->fr_next
)
9803 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9804 if (next_fragP
->tc_frag_data
.is_loop_target
)
9806 if (target_count
== 2)
9812 /* A map that keeps information on a per-subsegment basis. This is
9813 maintained during initial assembly, but is invalid once the
9814 subsegments are smashed together. I.E., it cannot be used during
9817 typedef struct subseg_map_struct
9825 float total_freq
; /* fall-through + branch target frequency */
9826 float target_freq
; /* branch target frequency alone */
9828 struct subseg_map_struct
*next
;
9832 static subseg_map
*sseg_map
= NULL
;
9835 get_subseg_info (segT seg
, subsegT subseg
)
9837 subseg_map
*subseg_e
;
9839 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9841 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9849 add_subseg_info (segT seg
, subsegT subseg
)
9851 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9852 memset (subseg_e
, 0, sizeof (subseg_map
));
9853 subseg_e
->seg
= seg
;
9854 subseg_e
->subseg
= subseg
;
9855 subseg_e
->flags
= 0;
9856 /* Start off considering every branch target very important. */
9857 subseg_e
->target_freq
= 1.0;
9858 subseg_e
->total_freq
= 1.0;
9859 subseg_e
->next
= sseg_map
;
9860 sseg_map
= subseg_e
;
9866 get_last_insn_flags (segT seg
, subsegT subseg
)
9868 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9870 return subseg_e
->flags
;
9876 set_last_insn_flags (segT seg
,
9881 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9883 subseg_e
= add_subseg_info (seg
, subseg
);
9885 subseg_e
->flags
|= fl
;
9887 subseg_e
->flags
&= ~fl
;
9892 get_subseg_total_freq (segT seg
, subsegT subseg
)
9894 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9896 return subseg_e
->total_freq
;
9902 get_subseg_target_freq (segT seg
, subsegT subseg
)
9904 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9906 return subseg_e
->target_freq
;
9912 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9914 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9916 subseg_e
= add_subseg_info (seg
, subseg
);
9917 subseg_e
->total_freq
= total_f
;
9918 subseg_e
->target_freq
= target_f
;
9922 /* Segment Lists and emit_state Stuff. */
9924 /* Remove the segment from the global sections list. */
9927 xtensa_remove_section (segT sec
)
9929 /* Handle brain-dead bfd_section_list_remove macro, which
9930 expect the address of the prior section's "next" field, not
9931 just the address of the section to remove. */
9933 segT
*ps_next_ptr
= &stdoutput
->sections
;
9934 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9935 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9937 assert (*ps_next_ptr
!= NULL
);
9939 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9944 xtensa_insert_section (segT after_sec
, segT sec
)
9946 segT
*after_sec_next
;
9947 if (after_sec
== NULL
)
9948 after_sec_next
= &stdoutput
->sections
;
9950 after_sec_next
= &after_sec
->next
;
9952 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9957 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9962 segT literal_section
= head
->seg
;
9964 /* Move the literal section to the front of the section list. */
9965 assert (literal_section
);
9966 xtensa_remove_section (literal_section
);
9967 xtensa_insert_section (NULL
, literal_section
);
9974 static void mark_literal_frags (seg_list
*);
9977 xtensa_move_literals (void)
9980 frchainS
*frchain_from
, *frchain_to
;
9981 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9982 fragS
**frag_splice
;
9985 fixS
*fix
, *next_fix
, **fix_splice
;
9988 mark_literal_frags (literal_head
->next
);
9989 mark_literal_frags (init_literal_head
->next
);
9990 mark_literal_frags (fini_literal_head
->next
);
9992 if (use_literal_section
)
9995 segment
= literal_head
->next
;
9998 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9999 search_frag
= frchain_from
->frch_root
;
10000 literal_pool
= NULL
;
10002 frag_splice
= &(frchain_from
->frch_root
);
10004 while (!search_frag
->tc_frag_data
.literal_frag
)
10006 assert (search_frag
->fr_fix
== 0
10007 || search_frag
->fr_type
== rs_align
);
10008 search_frag
= search_frag
->fr_next
;
10011 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10012 == RELAX_LITERAL_POOL_BEGIN
);
10013 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10015 /* Make sure that all the frags in this series are closed, and
10016 that there is at least one left over of zero-size. This
10017 prevents us from making a segment with an frchain without any
10019 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10020 xtensa_set_frag_assembly_state (frag_now
);
10021 last_frag
= frag_now
;
10022 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10023 xtensa_set_frag_assembly_state (frag_now
);
10025 while (search_frag
!= frag_now
)
10027 next_frag
= search_frag
->fr_next
;
10029 /* First, move the frag out of the literal section and
10030 to the appropriate place. */
10031 if (search_frag
->tc_frag_data
.literal_frag
)
10033 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10034 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10035 /* Note that we set this fr_var to be a fix
10036 chain when we created the literal pool location
10037 as RELAX_LITERAL_POOL_BEGIN. */
10038 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
10040 insert_after
= literal_pool
;
10042 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
10043 insert_after
= insert_after
->fr_next
;
10045 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
10047 *frag_splice
= next_frag
;
10048 search_frag
->fr_next
= insert_after
->fr_next
;
10049 insert_after
->fr_next
= search_frag
;
10050 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10052 /* Now move any fixups associated with this frag to the
10054 fix
= frchain_from
->fix_root
;
10055 fix_splice
= &(frchain_from
->fix_root
);
10058 next_fix
= fix
->fx_next
;
10059 if (fix
->fx_frag
== search_frag
)
10061 *fix_splice
= next_fix
;
10062 fix
->fx_next
= frchain_to
->fix_root
;
10063 frchain_to
->fix_root
= fix
;
10064 if (frchain_to
->fix_tail
== NULL
)
10065 frchain_to
->fix_tail
= fix
;
10068 fix_splice
= &(fix
->fx_next
);
10071 search_frag
= next_frag
;
10074 if (frchain_from
->fix_root
!= NULL
)
10076 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10077 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10079 assert (frchain_from
->fix_root
== NULL
);
10081 frchain_from
->fix_tail
= NULL
;
10082 xtensa_restore_emit_state (&state
);
10083 segment
= segment
->next
;
10086 /* Now fix up the SEGMENT value for all the literal symbols. */
10087 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10089 symbolS
*lit_sym
= lit
->sym
;
10090 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10092 S_SET_SEGMENT (lit_sym
, dest_seg
);
10097 /* Walk over all the frags for segments in a list and mark them as
10098 containing literals. As clunky as this is, we can't rely on frag_var
10099 and frag_variant to get called in all situations. */
10102 mark_literal_frags (seg_list
*segment
)
10104 frchainS
*frchain_from
;
10105 fragS
*search_frag
;
10109 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10110 search_frag
= frchain_from
->frch_root
;
10111 while (search_frag
)
10113 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10114 search_frag
= search_frag
->fr_next
;
10116 segment
= segment
->next
;
10122 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10124 /* Move all of the sections in the section list to come
10125 after "after" in the gnu segment list. */
10130 segT literal_section
= head
->seg
;
10132 /* Move the literal section after "after". */
10133 assert (literal_section
);
10134 if (literal_section
!= after
)
10136 xtensa_remove_section (literal_section
);
10137 xtensa_insert_section (after
, literal_section
);
10145 /* Push all the literal segments to the end of the gnu list. */
10148 xtensa_reorder_segments (void)
10155 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10161 /* Now that we have the last section, push all the literal
10162 sections to the end. */
10163 xtensa_reorder_seg_list (literal_head
, last_sec
);
10164 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10165 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10167 /* Now perform the final error check. */
10168 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10170 assert (new_count
== old_count
);
10174 /* Change the emit state (seg, subseg, and frag related stuff) to the
10175 correct location. Return a emit_state which can be passed to
10176 xtensa_restore_emit_state to return to current fragment. */
10179 xtensa_switch_to_literal_fragment (emit_state
*result
)
10181 if (directive_state
[directive_absolute_literals
])
10183 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10184 &default_lit_sections
.lit4_seg
, FALSE
);
10185 xtensa_switch_section_emit_state (result
,
10186 default_lit_sections
.lit4_seg
, 0);
10189 xtensa_switch_to_non_abs_literal_fragment (result
);
10191 /* Do a 4-byte align here. */
10192 frag_align (2, 0, 0);
10193 record_alignment (now_seg
, 2);
10198 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10200 /* When we mark a literal pool location, we want to put a frag in
10201 the literal pool that points to it. But to do that, we want to
10202 switch_to_literal_fragment. But literal sections don't have
10203 literal pools, so their location is always null, so we would
10204 recurse forever. This is kind of hacky, but it works. */
10206 static bfd_boolean recursive
= FALSE
;
10207 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10208 bfd_boolean is_init
=
10209 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10211 bfd_boolean is_fini
=
10212 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10214 if (pool_location
== NULL
10215 && !use_literal_section
10217 && !is_init
&& ! is_fini
)
10219 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10221 xtensa_mark_literal_pool_location ();
10225 /* Special case: If we are in the ".fini" or ".init" section, then
10226 we will ALWAYS be generating to the ".fini.literal" and
10227 ".init.literal" sections. */
10231 cache_literal_section (init_literal_head
,
10232 default_lit_sections
.init_lit_seg_name
,
10233 &default_lit_sections
.init_lit_seg
, TRUE
);
10234 xtensa_switch_section_emit_state (result
,
10235 default_lit_sections
.init_lit_seg
, 0);
10239 cache_literal_section (fini_literal_head
,
10240 default_lit_sections
.fini_lit_seg_name
,
10241 &default_lit_sections
.fini_lit_seg
, TRUE
);
10242 xtensa_switch_section_emit_state (result
,
10243 default_lit_sections
.fini_lit_seg
, 0);
10247 cache_literal_section (literal_head
,
10248 default_lit_sections
.lit_seg_name
,
10249 &default_lit_sections
.lit_seg
, TRUE
);
10250 xtensa_switch_section_emit_state (result
,
10251 default_lit_sections
.lit_seg
, 0);
10254 if (!use_literal_section
10255 && !is_init
&& !is_fini
10256 && get_literal_pool_location (now_seg
) != pool_location
)
10258 /* Close whatever frag is there. */
10259 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10260 xtensa_set_frag_assembly_state (frag_now
);
10261 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10262 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10263 xtensa_set_frag_assembly_state (frag_now
);
10268 /* Call this function before emitting data into the literal section.
10269 This is a helper function for xtensa_switch_to_literal_fragment.
10270 This is similar to a .section new_now_seg subseg. */
10273 xtensa_switch_section_emit_state (emit_state
*state
,
10275 subsegT new_now_subseg
)
10277 state
->name
= now_seg
->name
;
10278 state
->now_seg
= now_seg
;
10279 state
->now_subseg
= now_subseg
;
10280 state
->generating_literals
= generating_literals
;
10281 generating_literals
++;
10282 subseg_new (segment_name (new_now_seg
), new_now_subseg
);
10286 /* Use to restore the emitting into the normal place. */
10289 xtensa_restore_emit_state (emit_state
*state
)
10291 generating_literals
= state
->generating_literals
;
10292 subseg_new (state
->name
, state
->now_subseg
);
10296 /* Get a segment of a given name. If the segment is already
10297 present, return it; otherwise, create a new one. */
10300 cache_literal_section (seg_list
*head
,
10303 bfd_boolean is_code
)
10305 segT current_section
= now_seg
;
10306 int current_subsec
= now_subseg
;
10312 /* Check if the named section exists. */
10313 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10315 if (!strcmp (segment_name (seg
), name
))
10321 /* Create a new literal section. */
10322 seg
= subseg_new (name
, (subsegT
) 0);
10325 /* Add the newly created literal segment to the specified list. */
10326 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10328 n
->next
= head
->next
;
10331 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10332 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10333 | (is_code
? SEC_CODE
: SEC_DATA
));
10334 bfd_set_section_alignment (stdoutput
, seg
, 2);
10338 subseg_set (current_section
, current_subsec
);
10342 /* Property Tables Stuff. */
10344 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10345 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10346 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10348 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10349 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10351 static bfd_boolean
get_frag_is_literal (const fragS
*);
10352 static void xtensa_create_property_segments
10353 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10354 static void xtensa_create_xproperty_segments
10355 (frag_flags_fn
, const char *, xt_section_type
);
10356 static segment_info_type
*retrieve_segment_info (segT
);
10357 static segT
retrieve_xtensa_section (char *);
10358 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10359 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10360 static void add_xt_block_frags
10361 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10362 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10363 static void xtensa_frag_flags_init (frag_flags
*);
10364 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10365 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10366 static void add_xt_prop_frags
10367 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10369 /* Set up property tables after relaxation. */
10372 xtensa_post_relax_hook (void)
10374 xtensa_move_seg_list_to_beginning (literal_head
);
10375 xtensa_move_seg_list_to_beginning (init_literal_head
);
10376 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10378 xtensa_find_unmarked_state_frags ();
10380 if (use_literal_section
)
10381 xtensa_create_property_segments (get_frag_is_literal
,
10383 XTENSA_LIT_SEC_NAME
,
10385 xtensa_create_xproperty_segments (get_frag_property_flags
,
10386 XTENSA_PROP_SEC_NAME
,
10389 if (warn_unaligned_branch_targets
)
10390 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10391 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10395 /* This function is only meaningful after xtensa_move_literals. */
10398 get_frag_is_literal (const fragS
*fragP
)
10400 assert (fragP
!= NULL
);
10401 return fragP
->tc_frag_data
.is_literal
;
10406 xtensa_create_property_segments (frag_predicate property_function
,
10407 frag_predicate end_property_function
,
10408 const char *section_name_base
,
10409 xt_section_type sec_type
)
10413 /* Walk over all of the current segments.
10414 Walk over each fragment
10415 For each non-empty fragment,
10416 Build a property record (append where possible). */
10418 for (seclist
= &stdoutput
->sections
;
10419 seclist
&& *seclist
;
10420 seclist
= &(*seclist
)->next
)
10422 segT sec
= *seclist
;
10425 flags
= bfd_get_section_flags (stdoutput
, sec
);
10426 if (flags
& SEC_DEBUGGING
)
10428 if (!(flags
& SEC_ALLOC
))
10431 if (section_has_property (sec
, property_function
))
10433 char *property_section_name
=
10434 xtensa_get_property_section_name (sec
, section_name_base
);
10435 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10436 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10437 xtensa_block_info
**xt_blocks
=
10438 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10439 /* Walk over all of the frchains here and add new sections. */
10440 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10441 end_property_function
);
10445 /* Now we fill them out.... */
10447 for (seclist
= &stdoutput
->sections
;
10448 seclist
&& *seclist
;
10449 seclist
= &(*seclist
)->next
)
10451 segment_info_type
*seginfo
;
10452 xtensa_block_info
*block
;
10453 segT sec
= *seclist
;
10455 seginfo
= seg_info (sec
);
10456 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10460 xtensa_block_info
*cur_block
;
10461 /* This is a section with some data. */
10465 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10468 rec_size
= num_recs
* 8;
10469 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10471 /* In order to make this work with the assembler, we have to
10472 build some frags and then build the "fixups" for it. It
10473 would be easier to just set the contents then set the
10478 /* Allocate a fragment and leak it. */
10482 frchainS
*frchainP
;
10486 frag_size
= sizeof (fragS
) + rec_size
;
10487 fragP
= (fragS
*) xmalloc (frag_size
);
10489 memset (fragP
, 0, frag_size
);
10490 fragP
->fr_address
= 0;
10491 fragP
->fr_next
= NULL
;
10492 fragP
->fr_fix
= rec_size
;
10494 fragP
->fr_type
= rs_fill
;
10495 /* The rest are zeros. */
10497 frchainP
= seginfo
->frchainP
;
10498 frchainP
->frch_root
= fragP
;
10499 frchainP
->frch_last
= fragP
;
10501 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10502 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10504 seginfo
->fix_root
= fixes
;
10505 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10507 frag_data
= &fragP
->fr_literal
[0];
10508 for (i
= 0; i
< num_recs
; i
++)
10510 fixS
*fix
= &fixes
[i
];
10511 assert (cur_block
);
10513 /* Write the fixup. */
10514 if (i
!= num_recs
- 1)
10515 fix
->fx_next
= &fixes
[i
+ 1];
10517 fix
->fx_next
= NULL
;
10520 fix
->fx_frag
= fragP
;
10521 fix
->fx_where
= i
* 8;
10522 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10523 fix
->fx_offset
= cur_block
->offset
;
10524 fix
->fx_r_type
= BFD_RELOC_32
;
10525 fix
->fx_file
= "Internal Assembly";
10528 /* Write the length. */
10529 md_number_to_chars (&frag_data
[4 + 8 * i
],
10530 cur_block
->size
, 4);
10531 cur_block
= cur_block
->next
;
10540 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10541 const char *section_name_base
,
10542 xt_section_type sec_type
)
10546 /* Walk over all of the current segments.
10547 Walk over each fragment.
10548 For each fragment that has instructions,
10549 build an instruction record (append where possible). */
10551 for (seclist
= &stdoutput
->sections
;
10552 seclist
&& *seclist
;
10553 seclist
= &(*seclist
)->next
)
10555 segT sec
= *seclist
;
10558 flags
= bfd_get_section_flags (stdoutput
, sec
);
10559 if (flags
& SEC_DEBUGGING
)
10561 if (!(flags
& SEC_ALLOC
))
10564 if (section_has_xproperty (sec
, flag_fn
))
10566 char *property_section_name
=
10567 xtensa_get_property_section_name (sec
, section_name_base
);
10568 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10569 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10570 xtensa_block_info
**xt_blocks
=
10571 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10572 /* Walk over all of the frchains here and add new sections. */
10573 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10577 /* Now we fill them out.... */
10579 for (seclist
= &stdoutput
->sections
;
10580 seclist
&& *seclist
;
10581 seclist
= &(*seclist
)->next
)
10583 segment_info_type
*seginfo
;
10584 xtensa_block_info
*block
;
10585 segT sec
= *seclist
;
10587 seginfo
= seg_info (sec
);
10588 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10592 xtensa_block_info
*cur_block
;
10593 /* This is a section with some data. */
10597 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10600 rec_size
= num_recs
* (8 + 4);
10601 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10603 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10605 /* In order to make this work with the assembler, we have to build
10606 some frags then build the "fixups" for it. It would be easier to
10607 just set the contents then set the arlents. */
10611 /* Allocate a fragment and (unfortunately) leak it. */
10615 frchainS
*frchainP
;
10619 frag_size
= sizeof (fragS
) + rec_size
;
10620 fragP
= (fragS
*) xmalloc (frag_size
);
10622 memset (fragP
, 0, frag_size
);
10623 fragP
->fr_address
= 0;
10624 fragP
->fr_next
= NULL
;
10625 fragP
->fr_fix
= rec_size
;
10627 fragP
->fr_type
= rs_fill
;
10628 /* The rest are zeros. */
10630 frchainP
= seginfo
->frchainP
;
10631 frchainP
->frch_root
= fragP
;
10632 frchainP
->frch_last
= fragP
;
10634 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10635 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10637 seginfo
->fix_root
= fixes
;
10638 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10640 frag_data
= &fragP
->fr_literal
[0];
10641 for (i
= 0; i
< num_recs
; i
++)
10643 fixS
*fix
= &fixes
[i
];
10644 assert (cur_block
);
10646 /* Write the fixup. */
10647 if (i
!= num_recs
- 1)
10648 fix
->fx_next
= &fixes
[i
+ 1];
10650 fix
->fx_next
= NULL
;
10653 fix
->fx_frag
= fragP
;
10654 fix
->fx_where
= i
* (8 + 4);
10655 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10656 fix
->fx_offset
= cur_block
->offset
;
10657 fix
->fx_r_type
= BFD_RELOC_32
;
10658 fix
->fx_file
= "Internal Assembly";
10661 /* Write the length. */
10662 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10663 cur_block
->size
, 4);
10664 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10665 frag_flags_to_number (&cur_block
->flags
),
10667 cur_block
= cur_block
->next
;
10675 static segment_info_type
*
10676 retrieve_segment_info (segT seg
)
10678 segment_info_type
*seginfo
;
10679 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10682 frchainS
*frchainP
;
10684 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10685 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10686 seginfo
->fix_root
= NULL
;
10687 seginfo
->fix_tail
= NULL
;
10688 seginfo
->bfd_section
= seg
;
10690 /* We will not be dealing with these, only our special ones. */
10692 if (seg
== bfd_abs_section_ptr
)
10693 abs_seg_info
= seginfo
;
10694 else if (seg
== bfd_und_section_ptr
)
10695 und_seg_info
= seginfo
;
10698 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10700 seg_fix_rootP
= &segment_info
[seg
].fix_root
;
10701 seg_fix_tailP
= &segment_info
[seg
].fix_tail
;
10704 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10705 frchainP
->frch_root
= NULL
;
10706 frchainP
->frch_last
= NULL
;
10707 frchainP
->frch_next
= NULL
;
10708 frchainP
->frch_seg
= seg
;
10709 frchainP
->frch_subseg
= 0;
10710 frchainP
->fix_root
= NULL
;
10711 frchainP
->fix_tail
= NULL
;
10712 /* Do not init the objstack. */
10713 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10714 /* frchainP->frch_frag_now = fragP; */
10715 frchainP
->frch_frag_now
= NULL
;
10717 seginfo
->frchainP
= frchainP
;
10725 retrieve_xtensa_section (char *sec_name
)
10727 bfd
*abfd
= stdoutput
;
10728 flagword flags
, out_flags
, link_once_flags
;
10731 flags
= bfd_get_section_flags (abfd
, now_seg
);
10732 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10733 if (link_once_flags
)
10734 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10735 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10737 s
= bfd_make_section_old_way (abfd
, sec_name
);
10739 as_bad (_("could not create section %s"), sec_name
);
10740 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10741 as_bad (_("invalid flag combination on section %s"), sec_name
);
10748 section_has_property (segT sec
, frag_predicate property_function
)
10750 segment_info_type
*seginfo
= seg_info (sec
);
10753 if (seginfo
&& seginfo
->frchainP
)
10755 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10757 if (property_function (fragP
)
10758 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10767 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10769 segment_info_type
*seginfo
= seg_info (sec
);
10772 if (seginfo
&& seginfo
->frchainP
)
10774 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10776 frag_flags prop_flags
;
10777 property_function (fragP
, &prop_flags
);
10778 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10786 /* Two types of block sections exist right now: literal and insns. */
10789 add_xt_block_frags (segT sec
,
10791 xtensa_block_info
**xt_block
,
10792 frag_predicate property_function
,
10793 frag_predicate end_property_function
)
10795 segment_info_type
*seg_info
;
10796 segment_info_type
*xt_seg_info
;
10797 bfd_vma seg_offset
;
10800 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10801 seg_info
= retrieve_segment_info (sec
);
10803 /* Build it if needed. */
10804 while (*xt_block
!= NULL
)
10805 xt_block
= &(*xt_block
)->next
;
10806 /* We are either at NULL at the beginning or at the end. */
10808 /* Walk through the frags. */
10811 if (seg_info
->frchainP
)
10813 for (fragP
= seg_info
->frchainP
->frch_root
;
10815 fragP
= fragP
->fr_next
)
10817 if (property_function (fragP
)
10818 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10820 if (*xt_block
!= NULL
)
10822 if ((*xt_block
)->offset
+ (*xt_block
)->size
10823 == fragP
->fr_address
)
10824 (*xt_block
)->size
+= fragP
->fr_fix
;
10826 xt_block
= &((*xt_block
)->next
);
10828 if (*xt_block
== NULL
)
10830 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10831 xmalloc (sizeof (xtensa_block_info
));
10832 new_block
->sec
= sec
;
10833 new_block
->offset
= fragP
->fr_address
;
10834 new_block
->size
= fragP
->fr_fix
;
10835 new_block
->next
= NULL
;
10836 xtensa_frag_flags_init (&new_block
->flags
);
10837 *xt_block
= new_block
;
10839 if (end_property_function
10840 && end_property_function (fragP
))
10842 xt_block
= &((*xt_block
)->next
);
10850 /* Break the encapsulation of add_xt_prop_frags here. */
10853 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10855 if (prop_flags
->is_literal
10856 || prop_flags
->is_insn
10857 || prop_flags
->is_data
10858 || prop_flags
->is_unreachable
)
10865 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10867 memset (prop_flags
, 0, sizeof (frag_flags
));
10872 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10874 xtensa_frag_flags_init (prop_flags
);
10875 if (fragP
->tc_frag_data
.is_literal
)
10876 prop_flags
->is_literal
= TRUE
;
10877 if (fragP
->tc_frag_data
.is_unreachable
)
10878 prop_flags
->is_unreachable
= TRUE
;
10879 else if (fragP
->tc_frag_data
.is_insn
)
10881 prop_flags
->is_insn
= TRUE
;
10882 if (fragP
->tc_frag_data
.is_loop_target
)
10883 prop_flags
->insn
.is_loop_target
= TRUE
;
10884 if (fragP
->tc_frag_data
.is_branch_target
)
10885 prop_flags
->insn
.is_branch_target
= TRUE
;
10886 if (fragP
->tc_frag_data
.is_specific_opcode
10887 || fragP
->tc_frag_data
.is_no_transform
)
10888 prop_flags
->insn
.is_no_transform
= TRUE
;
10889 if (fragP
->tc_frag_data
.is_no_density
)
10890 prop_flags
->insn
.is_no_density
= TRUE
;
10891 if (fragP
->tc_frag_data
.use_absolute_literals
)
10892 prop_flags
->insn
.is_abslit
= TRUE
;
10894 if (fragP
->tc_frag_data
.is_align
)
10896 prop_flags
->is_align
= TRUE
;
10897 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10898 if (xtensa_frag_flags_is_empty (prop_flags
))
10899 prop_flags
->is_data
= TRUE
;
10905 frag_flags_to_number (const frag_flags
*prop_flags
)
10908 if (prop_flags
->is_literal
)
10909 num
|= XTENSA_PROP_LITERAL
;
10910 if (prop_flags
->is_insn
)
10911 num
|= XTENSA_PROP_INSN
;
10912 if (prop_flags
->is_data
)
10913 num
|= XTENSA_PROP_DATA
;
10914 if (prop_flags
->is_unreachable
)
10915 num
|= XTENSA_PROP_UNREACHABLE
;
10916 if (prop_flags
->insn
.is_loop_target
)
10917 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10918 if (prop_flags
->insn
.is_branch_target
)
10920 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10921 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10924 if (prop_flags
->insn
.is_no_density
)
10925 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10926 if (prop_flags
->insn
.is_no_transform
)
10927 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10928 if (prop_flags
->insn
.is_no_reorder
)
10929 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10930 if (prop_flags
->insn
.is_abslit
)
10931 num
|= XTENSA_PROP_INSN_ABSLIT
;
10933 if (prop_flags
->is_align
)
10935 num
|= XTENSA_PROP_ALIGN
;
10936 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10944 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10945 const frag_flags
*prop_flags_2
)
10947 /* Cannot combine with an end marker. */
10949 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10951 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10953 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10956 if (prop_flags_1
->is_insn
)
10958 /* Properties of the beginning of the frag. */
10959 if (prop_flags_2
->insn
.is_loop_target
)
10961 if (prop_flags_2
->insn
.is_branch_target
)
10963 if (prop_flags_1
->insn
.is_no_density
!=
10964 prop_flags_2
->insn
.is_no_density
)
10966 if (prop_flags_1
->insn
.is_no_transform
!=
10967 prop_flags_2
->insn
.is_no_transform
)
10969 if (prop_flags_1
->insn
.is_no_reorder
!=
10970 prop_flags_2
->insn
.is_no_reorder
)
10972 if (prop_flags_1
->insn
.is_abslit
!=
10973 prop_flags_2
->insn
.is_abslit
)
10977 if (prop_flags_1
->is_align
)
10985 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10990 if (!xt_block
->flags
.is_align
)
10991 return xt_block
->size
;
10993 end_addr
= xt_block
->offset
+ xt_block
->size
;
10994 align_bits
= xt_block
->flags
.alignment
;
10995 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10996 return end_addr
- xt_block
->offset
;
11001 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11002 const xtensa_block_info
*xt_block_2
)
11004 if (xt_block
->sec
!= xt_block_2
->sec
)
11006 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11007 != xt_block_2
->offset
)
11010 if (xt_block_2
->size
== 0
11011 && (!xt_block_2
->flags
.is_unreachable
11012 || xt_block
->flags
.is_unreachable
))
11014 if (xt_block_2
->flags
.is_align
11015 && xt_block
->flags
.is_align
)
11017 /* Nothing needed. */
11018 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11023 if (xt_block_2
->flags
.is_align
)
11025 /* Push alignment to previous entry. */
11026 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11027 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11032 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11033 &xt_block_2
->flags
))
11036 xt_block
->size
+= xt_block_2
->size
;
11038 if (xt_block_2
->flags
.is_align
)
11040 xt_block
->flags
.is_align
= TRUE
;
11041 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11049 add_xt_prop_frags (segT sec
,
11051 xtensa_block_info
**xt_block
,
11052 frag_flags_fn property_function
)
11054 segment_info_type
*seg_info
;
11055 segment_info_type
*xt_seg_info
;
11056 bfd_vma seg_offset
;
11059 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
11060 seg_info
= retrieve_segment_info (sec
);
11061 /* Build it if needed. */
11062 while (*xt_block
!= NULL
)
11064 xt_block
= &(*xt_block
)->next
;
11066 /* We are either at NULL at the beginning or at the end. */
11068 /* Walk through the frags. */
11071 if (seg_info
->frchainP
)
11073 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
11074 fragP
= fragP
->fr_next
)
11076 xtensa_block_info tmp_block
;
11077 tmp_block
.sec
= sec
;
11078 tmp_block
.offset
= fragP
->fr_address
;
11079 tmp_block
.size
= fragP
->fr_fix
;
11080 tmp_block
.next
= NULL
;
11081 property_function (fragP
, &tmp_block
.flags
);
11083 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11084 /* && fragP->fr_fix != 0) */
11086 if ((*xt_block
) == NULL
11087 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11089 xtensa_block_info
*new_block
;
11090 if ((*xt_block
) != NULL
)
11091 xt_block
= &(*xt_block
)->next
;
11092 new_block
= (xtensa_block_info
*)
11093 xmalloc (sizeof (xtensa_block_info
));
11094 *new_block
= tmp_block
;
11095 *xt_block
= new_block
;
11103 /* op_placement_info_table */
11105 /* op_placement_info makes it easier to determine which
11106 ops can go in which slots. */
11109 init_op_placement_info_table (void)
11111 xtensa_isa isa
= xtensa_default_isa
;
11112 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11113 xtensa_opcode opcode
;
11116 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11118 op_placement_table
= (op_placement_info_table
)
11119 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11120 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11122 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11124 op_placement_info
*opi
= &op_placement_table
[opcode
];
11125 /* FIXME: Make tinsn allocation dynamic. */
11126 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
11127 as_fatal (_("too many operands in instruction"));
11128 opi
->single
= XTENSA_UNDEFINED
;
11129 opi
->single_size
= 0;
11130 opi
->widest
= XTENSA_UNDEFINED
;
11131 opi
->widest_size
= 0;
11132 opi
->narrowest
= XTENSA_UNDEFINED
;
11133 opi
->narrowest_size
= 0x7F;
11135 opi
->num_formats
= 0;
11137 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11139 opi
->slots
[fmt
] = 0;
11140 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11142 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11144 int fmt_length
= xtensa_format_length (isa
, fmt
);
11146 set_bit (fmt
, opi
->formats
);
11147 set_bit (slot
, opi
->slots
[fmt
]);
11148 /* opi->slot_count[fmt]++; */
11149 if (fmt_length
< opi
->narrowest_size
)
11151 opi
->narrowest
= fmt
;
11152 opi
->narrowest_size
= fmt_length
;
11154 if (fmt_length
> opi
->widest_size
)
11157 opi
->widest_size
= fmt_length
;
11159 if (xtensa_format_num_slots (isa
, fmt
) == 1)
11161 if (opi
->single_size
== 0
11162 || fmt_length
< opi
->single_size
)
11165 opi
->single_size
= fmt_length
;
11171 opi
->num_formats
++;
11174 xtensa_insnbuf_free (isa
, ibuf
);
11179 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11181 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11185 /* If the opcode is available in a single slot format, return its size. */
11188 xg_get_single_size (xtensa_opcode opcode
)
11190 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11191 return op_placement_table
[opcode
].single_size
;
11195 static xtensa_format
11196 xg_get_single_format (xtensa_opcode opcode
)
11198 return op_placement_table
[opcode
].single
;
11202 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11205 istack_init (IStack
*stack
)
11207 memset (stack
, 0, sizeof (IStack
));
11213 istack_empty (IStack
*stack
)
11215 return (stack
->ninsn
== 0);
11220 istack_full (IStack
*stack
)
11222 return (stack
->ninsn
== MAX_ISTACK
);
11226 /* Return a pointer to the top IStack entry.
11227 It is an error to call this if istack_empty () is TRUE. */
11230 istack_top (IStack
*stack
)
11232 int rec
= stack
->ninsn
- 1;
11233 assert (!istack_empty (stack
));
11234 return &stack
->insn
[rec
];
11238 /* Add a new TInsn to an IStack.
11239 It is an error to call this if istack_full () is TRUE. */
11242 istack_push (IStack
*stack
, TInsn
*insn
)
11244 int rec
= stack
->ninsn
;
11245 assert (!istack_full (stack
));
11246 stack
->insn
[rec
] = *insn
;
11251 /* Clear space for the next TInsn on the IStack and return a pointer
11252 to it. It is an error to call this if istack_full () is TRUE. */
11255 istack_push_space (IStack
*stack
)
11257 int rec
= stack
->ninsn
;
11259 assert (!istack_full (stack
));
11260 insn
= &stack
->insn
[rec
];
11261 memset (insn
, 0, sizeof (TInsn
));
11267 /* Remove the last pushed instruction. It is an error to call this if
11268 istack_empty () returns TRUE. */
11271 istack_pop (IStack
*stack
)
11273 int rec
= stack
->ninsn
- 1;
11274 assert (!istack_empty (stack
));
11276 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11280 /* TInsn functions. */
11283 tinsn_init (TInsn
*dst
)
11285 memset (dst
, 0, sizeof (TInsn
));
11289 /* Get the ``num''th token of the TInsn.
11290 It is illegal to call this if num > insn->ntoks. */
11293 tinsn_get_tok (TInsn
*insn
, int num
)
11295 assert (num
< insn
->ntok
);
11296 return &insn
->tok
[num
];
11300 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11303 tinsn_has_symbolic_operands (const TInsn
*insn
)
11306 int n
= insn
->ntok
;
11308 assert (insn
->insn_type
== ITYPE_INSN
);
11310 for (i
= 0; i
< n
; ++i
)
11312 switch (insn
->tok
[i
].X_op
)
11326 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11328 xtensa_isa isa
= xtensa_default_isa
;
11330 int n
= insn
->ntok
;
11332 assert (insn
->insn_type
== ITYPE_INSN
);
11334 for (i
= 0; i
< n
; ++i
)
11336 switch (insn
->tok
[i
].X_op
)
11344 /* Errors for these types are caught later. */
11349 /* Symbolic immediates are only allowed on the last immediate
11350 operand. At this time, CONST16 is the only opcode where we
11351 support non-PC-relative relocations. (It isn't necessary
11352 to complain about non-PC-relative relocations here, but
11353 otherwise, no error is reported until the relocations are
11354 generated, and the assembler won't get that far if there
11355 are any other errors. It's nice to see all the problems
11357 if (i
!= get_relaxable_immed (insn
->opcode
)
11358 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11359 && insn
->opcode
!= xtensa_const16_opcode
))
11361 as_bad (_("invalid symbolic operand %d on '%s'"),
11362 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11371 /* For assembly code with complex expressions (e.g. subtraction),
11372 we have to build them in the literal pool so that
11373 their results are calculated correctly after relaxation.
11374 The relaxation only handles expressions that
11375 boil down to SYMBOL + OFFSET. */
11378 tinsn_has_complex_operands (const TInsn
*insn
)
11381 int n
= insn
->ntok
;
11382 assert (insn
->insn_type
== ITYPE_INSN
);
11383 for (i
= 0; i
< n
; ++i
)
11385 switch (insn
->tok
[i
].X_op
)
11401 /* Convert the constant operands in the tinsn to insnbuf.
11402 Return TRUE if there is a symbol in the immediate field.
11404 Before this is called,
11405 1) the number of operands are correct
11406 2) the tinsn is a ITYPE_INSN
11407 3) ONLY the relaxable_ is built
11408 4) All operands are O_constant, O_symbol. All constants fit
11409 The return value tells whether there are any remaining O_symbols. */
11412 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11414 static xtensa_insnbuf slotbuf
= 0;
11415 xtensa_isa isa
= xtensa_default_isa
;
11416 xtensa_opcode opcode
= tinsn
->opcode
;
11417 xtensa_format fmt
= xg_get_single_format (opcode
);
11418 bfd_boolean has_fixup
= FALSE
;
11419 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11426 slotbuf
= xtensa_insnbuf_alloc (isa
);
11428 assert (tinsn
->insn_type
== ITYPE_INSN
);
11429 if (noperands
!= tinsn
->ntok
)
11430 as_fatal (_("operand number mismatch"));
11432 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11433 as_fatal (_("cannot encode opcode"));
11435 for (i
= 0; i
< noperands
; ++i
)
11437 expressionS
*expr
= &tinsn
->tok
[i
];
11438 switch (expr
->X_op
)
11441 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11443 /* The register number has already been checked in
11444 expression_maybe_register, so we don't need to check here. */
11445 opnd_value
= expr
->X_add_number
;
11446 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11447 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11448 slotbuf
, opnd_value
);
11452 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11454 as_where (&file_name
, &line
);
11455 /* It is a constant and we called this function,
11456 then we have to try to fit it. */
11457 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11458 expr
->X_add_number
, file_name
, line
);
11467 xtensa_format_encode (isa
, fmt
, insnbuf
);
11468 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11474 /* Convert the constant operands in the tinsn to slotbuf.
11475 Return TRUE if there is a symbol in the immediate field.
11476 (Eventually this should replace tinsn_to_insnbuf.) */
11478 /* Before this is called,
11479 1) the number of operands are correct
11480 2) the tinsn is a ITYPE_INSN
11481 3) ONLY the relaxable_ is built
11482 4) All operands are
11483 O_constant, O_symbol
11486 The return value tells whether there are any remaining O_symbols. */
11489 tinsn_to_slotbuf (xtensa_format fmt
,
11492 xtensa_insnbuf slotbuf
)
11494 xtensa_isa isa
= xtensa_default_isa
;
11495 xtensa_opcode opcode
= tinsn
->opcode
;
11496 bfd_boolean has_fixup
= FALSE
;
11497 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11500 *((int *) &slotbuf
[0]) = 0;
11501 *((int *) &slotbuf
[1]) = 0;
11502 assert (tinsn
->insn_type
== ITYPE_INSN
);
11503 if (noperands
!= tinsn
->ntok
)
11504 as_fatal (_("operand number mismatch"));
11506 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11508 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11509 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11513 for (i
= 0; i
< noperands
; i
++)
11515 expressionS
*expr
= &tinsn
->tok
[i
];
11520 switch (expr
->X_op
)
11523 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11525 /* The register number has already been checked in
11526 expression_maybe_register, so we don't need to check here. */
11527 opnd_value
= expr
->X_add_number
;
11528 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11529 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11532 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11536 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11538 as_where (&file_name
, &line
);
11539 /* It is a constant and we called this function
11540 then we have to try to fit it. */
11541 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11542 expr
->X_add_number
, file_name
, line
);
11555 /* Check the instruction arguments. Return TRUE on failure. */
11558 tinsn_check_arguments (const TInsn
*insn
)
11560 xtensa_isa isa
= xtensa_default_isa
;
11561 xtensa_opcode opcode
= insn
->opcode
;
11563 if (opcode
== XTENSA_UNDEFINED
)
11565 as_bad (_("invalid opcode"));
11569 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11571 as_bad (_("too few operands"));
11575 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11577 as_bad (_("too many operands"));
11584 /* Load an instruction from its encoded form. */
11587 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11591 xg_init_vinsn (&vinsn
);
11592 vinsn_from_chars (&vinsn
, f
);
11594 *tinsn
= vinsn
.slots
[slot
];
11595 xg_free_vinsn (&vinsn
);
11600 tinsn_from_insnbuf (TInsn
*tinsn
,
11601 xtensa_insnbuf slotbuf
,
11606 xtensa_isa isa
= xtensa_default_isa
;
11608 /* Find the immed. */
11609 tinsn_init (tinsn
);
11610 tinsn
->insn_type
= ITYPE_INSN
;
11611 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11612 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11613 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11614 for (i
= 0; i
< tinsn
->ntok
; i
++)
11616 set_expr_const (&tinsn
->tok
[i
],
11617 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11618 tinsn
->opcode
, i
));
11623 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11626 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11628 xtensa_opcode opcode
= tinsn
->opcode
;
11631 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11633 opnum
= get_relaxable_immed (opcode
);
11634 assert (opnum
>= 0);
11635 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11637 set_expr_symbol_offset_diff
11638 (&tinsn
->tok
[opnum
],
11639 fragP
->tc_frag_data
.slot_symbols
[slot
],
11640 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11641 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11645 set_expr_symbol_offset
11646 (&tinsn
->tok
[opnum
],
11647 fragP
->tc_frag_data
.slot_symbols
[slot
],
11648 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11655 get_num_stack_text_bytes (IStack
*istack
)
11658 int text_bytes
= 0;
11660 for (i
= 0; i
< istack
->ninsn
; i
++)
11662 TInsn
*tinsn
= &istack
->insn
[i
];
11663 if (tinsn
->insn_type
== ITYPE_INSN
)
11664 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11671 get_num_stack_literal_bytes (IStack
*istack
)
11676 for (i
= 0; i
< istack
->ninsn
; i
++)
11678 TInsn
*tinsn
= &istack
->insn
[i
];
11679 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11686 /* vliw_insn functions. */
11689 xg_init_vinsn (vliw_insn
*v
)
11692 xtensa_isa isa
= xtensa_default_isa
;
11694 xg_clear_vinsn (v
);
11696 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11697 if (v
->insnbuf
== NULL
)
11698 as_fatal (_("out of memory"));
11700 for (i
= 0; i
< MAX_SLOTS
; i
++)
11702 tinsn_init (&v
->slots
[i
]);
11703 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11704 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11705 if (v
->slotbuf
[i
] == NULL
)
11706 as_fatal (_("out of memory"));
11712 xg_clear_vinsn (vliw_insn
*v
)
11715 v
->format
= XTENSA_UNDEFINED
;
11717 v
->inside_bundle
= FALSE
;
11719 if (xt_saved_debug_type
!= DEBUG_NONE
)
11720 debug_type
= xt_saved_debug_type
;
11722 for (i
= 0; i
< MAX_SLOTS
; i
++)
11724 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11725 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11731 vinsn_has_specific_opcodes (vliw_insn
*v
)
11735 for (i
= 0; i
< v
->num_slots
; i
++)
11737 if (v
->slots
[i
].is_specific_opcode
)
11745 xg_free_vinsn (vliw_insn
*v
)
11748 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11749 for (i
= 0; i
< MAX_SLOTS
; i
++)
11750 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11754 /* Before this is called, we should have
11755 filled out the following fields:
11757 1) the number of operands for each opcode are correct
11758 2) the tinsn in the slots are ITYPE_INSN
11759 3) ONLY the relaxable_ is built
11760 4) All operands are
11761 O_constant, O_symbol
11764 The return value tells whether there are any remaining O_symbols. */
11767 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11770 bfd_boolean record_fixup
)
11772 xtensa_isa isa
= xtensa_default_isa
;
11773 xtensa_format fmt
= vinsn
->format
;
11774 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11776 bfd_boolean has_fixup
= FALSE
;
11778 xtensa_format_encode (isa
, fmt
, insnbuf
);
11780 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11782 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11783 bfd_boolean tinsn_has_fixup
=
11784 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11785 vinsn
->slotbuf
[slot
]);
11787 xtensa_format_set_slot (isa
, fmt
, slot
,
11788 insnbuf
, vinsn
->slotbuf
[slot
]);
11789 /* tinsn_has_fixup tracks if there is a fixup at all.
11790 record_fixup controls globally. I.E., we use this
11791 function from several places, some of which are after
11792 fixups have already been recorded. Finally,
11793 tinsn->record_fixup controls based on the individual ops,
11794 which may or may not need it based on the relaxation
11796 if (tinsn_has_fixup
&& record_fixup
)
11799 xtensa_opcode opcode
= tinsn
->opcode
;
11800 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11803 for (i
= 0; i
< noperands
; i
++)
11805 expressionS
* expr
= &tinsn
->tok
[i
];
11806 switch (expr
->X_op
)
11811 if (get_relaxable_immed (opcode
) == i
)
11813 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11815 if (!xg_add_opcode_fix
11816 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11817 frag_offset
- fragP
->fr_literal
))
11818 as_bad (_("instruction with constant operands does not fit"));
11822 tinsn
->symbol
= expr
->X_add_symbol
;
11823 tinsn
->offset
= expr
->X_add_number
;
11827 as_bad (_("invalid operand %d on '%s'"),
11828 i
, xtensa_opcode_name (isa
, opcode
));
11836 if (get_relaxable_immed (opcode
) == i
)
11838 if (tinsn
->record_fix
)
11839 as_bad (_("invalid subtract operand"));
11842 tinsn
->symbol
= expr
->X_add_symbol
;
11843 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11844 tinsn
->offset
= expr
->X_add_number
;
11848 as_bad (_("invalid operand %d on '%s'"),
11849 i
, xtensa_opcode_name (isa
, opcode
));
11853 as_bad (_("invalid expression for operand %d on '%s'"),
11854 i
, xtensa_opcode_name (isa
, opcode
));
11866 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11868 static xtensa_insnbuf insnbuf
= NULL
;
11869 static xtensa_insnbuf slotbuf
= NULL
;
11872 xtensa_isa isa
= xtensa_default_isa
;
11876 insnbuf
= xtensa_insnbuf_alloc (isa
);
11877 slotbuf
= xtensa_insnbuf_alloc (isa
);
11880 xtensa_insnbuf_from_chars (isa
, insnbuf
, f
, 0);
11881 fmt
= xtensa_format_decode (isa
, insnbuf
);
11882 if (fmt
== XTENSA_UNDEFINED
)
11883 as_fatal (_("cannot decode instruction format"));
11884 vinsn
->format
= fmt
;
11885 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11887 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11889 TInsn
*tinsn
= &vinsn
->slots
[i
];
11890 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11891 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11896 /* Expression utilities. */
11898 /* Return TRUE if the expression is an integer constant. */
11901 expr_is_const (const expressionS
*s
)
11903 return (s
->X_op
== O_constant
);
11907 /* Get the expression constant.
11908 Calling this is illegal if expr_is_const () returns TRUE. */
11911 get_expr_const (const expressionS
*s
)
11913 assert (expr_is_const (s
));
11914 return s
->X_add_number
;
11918 /* Set the expression to a constant value. */
11921 set_expr_const (expressionS
*s
, offsetT val
)
11923 s
->X_op
= O_constant
;
11924 s
->X_add_number
= val
;
11925 s
->X_add_symbol
= NULL
;
11926 s
->X_op_symbol
= NULL
;
11931 expr_is_register (const expressionS
*s
)
11933 return (s
->X_op
== O_register
);
11937 /* Get the expression constant.
11938 Calling this is illegal if expr_is_const () returns TRUE. */
11941 get_expr_register (const expressionS
*s
)
11943 assert (expr_is_register (s
));
11944 return s
->X_add_number
;
11948 /* Set the expression to a symbol + constant offset. */
11951 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11953 s
->X_op
= O_symbol
;
11954 s
->X_add_symbol
= sym
;
11955 s
->X_op_symbol
= NULL
; /* unused */
11956 s
->X_add_number
= offset
;
11960 /* Set the expression to symbol - minus_sym + offset. */
11963 set_expr_symbol_offset_diff (expressionS
*s
,
11965 symbolS
*minus_sym
,
11968 s
->X_op
= O_subtract
;
11969 s
->X_add_symbol
= sym
;
11970 s
->X_op_symbol
= minus_sym
; /* unused */
11971 s
->X_add_number
= offset
;
11975 /* Return TRUE if the two expressions are equal. */
11978 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11980 if (s1
->X_op
!= s2
->X_op
)
11982 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11984 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11986 if (s1
->X_add_number
!= s2
->X_add_number
)
11993 copy_expr (expressionS
*dst
, const expressionS
*src
)
11995 memcpy (dst
, src
, sizeof (expressionS
));
11999 /* Support for Tensilica's "--rename-section" option. */
12001 #ifdef XTENSA_SECTION_RENAME
12003 struct rename_section_struct
12007 struct rename_section_struct
*next
;
12010 static struct rename_section_struct
*section_rename
;
12013 /* Parse the string oldname=new_name:oldname2=new_name2
12014 and call add_section_rename. */
12017 build_section_rename (const char *arg
)
12019 char *this_arg
= NULL
;
12020 char *next_arg
= NULL
;
12022 for (this_arg
= strdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12026 next_arg
= strchr (this_arg
, ':');
12034 char *old_name
= this_arg
;
12035 char *new_name
= strchr (this_arg
, '=');
12037 if (*old_name
== '\0')
12039 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12042 if (!new_name
|| new_name
[1] == '\0')
12044 as_warn (_("ignoring invalid '-rename-section' "
12045 "specification: '%s'"), old_name
);
12050 add_section_rename (old_name
, new_name
);
12057 add_section_rename (char *old_name
, char *new_name
)
12059 struct rename_section_struct
*r
= section_rename
;
12061 /* Check for invalid section renaming. */
12062 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12064 if (strcmp (r
->old_name
, old_name
) == 0)
12065 as_bad (_("section %s renamed multiple times"), old_name
);
12066 if (strcmp (r
->new_name
, new_name
) == 0)
12067 as_bad (_("multiple sections remapped to output section %s"),
12072 r
= (struct rename_section_struct
*)
12073 xmalloc (sizeof (struct rename_section_struct
));
12074 r
->old_name
= strdup (old_name
);
12075 r
->new_name
= strdup (new_name
);
12076 r
->next
= section_rename
;
12077 section_rename
= r
;
12082 xtensa_section_rename (const char *name
)
12084 struct rename_section_struct
*r
= section_rename
;
12086 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12088 if (strcmp (r
->old_name
, name
) == 0)
12089 return r
->new_name
;
12095 #endif /* XTENSA_SECTION_RENAME */