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[thirdparty/binutils-gdb.git] / gas / config / tc-z80.c
1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800
2 Copyright (C) 2005-2023 Free Software Foundation, Inc.
3 Contributed by Arnold Metselaar <arnold_m@operamail.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "subsegs.h"
25 #include "elf/z80.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 /* Exported constants. */
30 const char comment_chars[] = ";\0";
31 const char line_comment_chars[] = "#;\0";
32 const char line_separator_chars[] = "\0";
33 const char EXP_CHARS[] = "eE\0";
34 const char FLT_CHARS[] = "RrDdFfSsHh\0";
35
36 /* For machine specific options. */
37 const char * md_shortopts = ""; /* None yet. */
38
39 enum options
40 {
41 OPTION_MARCH = OPTION_MD_BASE,
42 OPTION_MACH_Z80,
43 OPTION_MACH_R800,
44 OPTION_MACH_Z180,
45 OPTION_MACH_EZ80_Z80,
46 OPTION_MACH_EZ80_ADL,
47 OPTION_MACH_INST,
48 OPTION_MACH_NO_INST,
49 OPTION_MACH_IUD,
50 OPTION_MACH_WUD,
51 OPTION_MACH_FUD,
52 OPTION_MACH_IUP,
53 OPTION_MACH_WUP,
54 OPTION_MACH_FUP,
55 OPTION_FP_SINGLE_FORMAT,
56 OPTION_FP_DOUBLE_FORMAT,
57 OPTION_COMPAT_LL_PREFIX,
58 OPTION_COMPAT_COLONLESS,
59 OPTION_COMPAT_SDCC
60 };
61
62 #define INS_Z80 (1 << 0)
63 #define INS_R800 (1 << 1)
64 #define INS_GBZ80 (1 << 2)
65 #define INS_Z180 (1 << 3)
66 #define INS_EZ80 (1 << 4)
67 #define INS_Z80N (1 << 5)
68 #define INS_MARCH_MASK 0xffff
69
70 #define INS_IDX_HALF (1 << 16)
71 #define INS_IN_F_C (1 << 17)
72 #define INS_OUT_C_0 (1 << 18)
73 #define INS_SLI (1 << 19)
74 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
75 #define INS_TUNE_MASK 0xffff0000
76
77 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
78
79 #define INS_ALL 0
80 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
81 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD)
82
83 struct option md_longopts[] =
84 {
85 { "march", required_argument, NULL, OPTION_MARCH},
86 { "z80", no_argument, NULL, OPTION_MACH_Z80},
87 { "r800", no_argument, NULL, OPTION_MACH_R800},
88 { "z180", no_argument, NULL, OPTION_MACH_Z180},
89 { "ez80", no_argument, NULL, OPTION_MACH_EZ80_Z80},
90 { "ez80-adl", no_argument, NULL, OPTION_MACH_EZ80_ADL},
91 { "fp-s", required_argument, NULL, OPTION_FP_SINGLE_FORMAT},
92 { "fp-d", required_argument, NULL, OPTION_FP_DOUBLE_FORMAT},
93 { "strict", no_argument, NULL, OPTION_MACH_FUD},
94 { "full", no_argument, NULL, OPTION_MACH_IUP},
95 { "with-inst", required_argument, NULL, OPTION_MACH_INST},
96 { "Wnins", required_argument, NULL, OPTION_MACH_INST},
97 { "without-inst", required_argument, NULL, OPTION_MACH_NO_INST},
98 { "local-prefix", required_argument, NULL, OPTION_COMPAT_LL_PREFIX},
99 { "colonless", no_argument, NULL, OPTION_COMPAT_COLONLESS},
100 { "sdcc", no_argument, NULL, OPTION_COMPAT_SDCC},
101 { "Fins", required_argument, NULL, OPTION_MACH_NO_INST},
102 { "ignore-undocumented-instructions", no_argument, NULL, OPTION_MACH_IUD },
103 { "Wnud", no_argument, NULL, OPTION_MACH_IUD },
104 { "warn-undocumented-instructions", no_argument, NULL, OPTION_MACH_WUD },
105 { "Wud", no_argument, NULL, OPTION_MACH_WUD },
106 { "forbid-undocumented-instructions", no_argument, NULL, OPTION_MACH_FUD },
107 { "Fud", no_argument, NULL, OPTION_MACH_FUD },
108 { "ignore-unportable-instructions", no_argument, NULL, OPTION_MACH_IUP },
109 { "Wnup", no_argument, NULL, OPTION_MACH_IUP },
110 { "warn-unportable-instructions", no_argument, NULL, OPTION_MACH_WUP },
111 { "Wup", no_argument, NULL, OPTION_MACH_WUP },
112 { "forbid-unportable-instructions", no_argument, NULL, OPTION_MACH_FUP },
113 { "Fup", no_argument, NULL, OPTION_MACH_FUP },
114
115 { NULL, no_argument, NULL, 0 }
116 } ;
117
118 size_t md_longopts_size = sizeof (md_longopts);
119
120 extern int coff_flags;
121 /* Instruction classes that silently assembled. */
122 static int ins_ok = INS_Z80 | INS_UNDOC;
123 /* Instruction classes that generate errors. */
124 static int ins_err = ~(INS_Z80 | INS_UNDOC);
125 /* eZ80 CPU mode (ADL or Z80) */
126 static int cpu_mode = 0; /* 0 - Z80, 1 - ADL */
127 /* accept SDCC specific instruction encoding */
128 static int sdcc_compat = 0;
129 /* accept colonless labels */
130 static int colonless_labels = 0;
131 /* local label prefix (NULL - default) */
132 static const char *local_label_prefix = NULL;
133 /* floating point support */
134 typedef const char *(*str_to_float_t)(char *litP, int *sizeP);
135 static str_to_float_t str_to_float;
136 static str_to_float_t str_to_double;
137
138 /* mode of current instruction */
139 #define INST_MODE_S 0 /* short data mode */
140 #define INST_MODE_IS 0 /* short instruction mode */
141 #define INST_MODE_L 2 /* long data mode */
142 #define INST_MODE_IL 1 /* long instruction mode */
143 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
144 static char inst_mode;
145
146 struct match_info
147 {
148 const char *name;
149 int ins_ok;
150 int ins_err;
151 int cpu_mode;
152 const char *comment;
153 };
154
155 static const struct match_info
156 match_cpu_table [] =
157 {
158 {"z80", INS_Z80, 0, 0, "Zilog Z80" },
159 {"ez80", INS_EZ80, 0, 0, "Zilog eZ80" },
160 {"gbz80", INS_GBZ80, INS_UNDOC|INS_UNPORT, 0, "GameBoy Z80" },
161 {"r800", INS_R800, INS_UNPORT, 0, "Ascii R800" },
162 {"z180", INS_Z180, INS_UNDOC|INS_UNPORT, 0, "Zilog Z180" },
163 {"z80n", INS_Z80N, 0, 0, "Z80 Next" }
164 };
165
166 static const struct match_info
167 match_ext_table [] =
168 {
169 {"full", INS_UNDOC|INS_UNPORT, 0, 0, "assemble all known instructions" },
170 {"adl", 0, 0, 1, "eZ80 ADL mode by default" },
171 {"xyhl", INS_IDX_HALF, 0, 0, "instructions with halves of index registers" },
172 {"infc", INS_IN_F_C, 0, 0, "instruction IN F,(C)" },
173 {"outc0", INS_OUT_C_0, 0, 0, "instruction OUT (C),0" },
174 {"sli", INS_SLI, 0, 0, "instruction known as SLI, SLL, or SL1" },
175 {"xdcb", INS_ROT_II_LD, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" }
176 };
177
178
179 static int signed_overflow (signed long value, unsigned bitsize);
180 static int unsigned_overflow (unsigned long value, unsigned bitsize);
181 static int is_overflow (long value, unsigned bitsize);
182
183 static void
184 setup_march (const char *name, int *ok, int *err, int *mode)
185 {
186 unsigned i;
187 size_t len = strcspn (name, "+-");
188 for (i = 0; i < ARRAY_SIZE (match_cpu_table); ++i)
189 if (!strncasecmp (name, match_cpu_table[i].name, len)
190 && strlen (match_cpu_table[i].name) == len)
191 {
192 *ok = match_cpu_table[i].ins_ok;
193 *err = match_cpu_table[i].ins_err;
194 *mode = match_cpu_table[i].cpu_mode;
195 break;
196 }
197
198 if (i >= ARRAY_SIZE (match_cpu_table))
199 as_fatal (_("Invalid CPU is specified: %s"), name);
200
201 while (name[len])
202 {
203 name = &name[len + 1];
204 len = strcspn (name, "+-");
205 for (i = 0; i < ARRAY_SIZE (match_ext_table); ++i)
206 if (!strncasecmp (name, match_ext_table[i].name, len)
207 && strlen (match_ext_table[i].name) == len)
208 {
209 if (name[-1] == '+')
210 {
211 *ok |= match_ext_table[i].ins_ok;
212 *err &= ~match_ext_table[i].ins_ok;
213 *mode |= match_ext_table[i].cpu_mode;
214 }
215 else
216 {
217 *ok &= ~match_ext_table[i].ins_ok;
218 *err |= match_ext_table[i].ins_ok;
219 *mode &= ~match_ext_table[i].cpu_mode;
220 }
221 break;
222 }
223 if (i >= ARRAY_SIZE (match_ext_table))
224 as_fatal (_("Invalid EXTENSION is specified: %s"), name);
225 }
226 }
227
228 static int
229 setup_instruction (const char *inst, int *add, int *sub)
230 {
231 int n;
232 if (!strcmp (inst, "idx-reg-halves"))
233 n = INS_IDX_HALF;
234 else if (!strcmp (inst, "sli"))
235 n = INS_SLI;
236 else if (!strcmp (inst, "op-ii-ld"))
237 n = INS_ROT_II_LD;
238 else if (!strcmp (inst, "in-f-c"))
239 n = INS_IN_F_C;
240 else if (!strcmp (inst, "out-c-0"))
241 n = INS_OUT_C_0;
242 else
243 return 0;
244 *add |= n;
245 *sub &= ~n;
246 return 1;
247 }
248
249 static const char *
250 str_to_zeda32 (char *litP, int *sizeP);
251 static const char *
252 str_to_float48 (char *litP, int *sizeP);
253 static const char *
254 str_to_ieee754_h (char *litP, int *sizeP);
255 static const char *
256 str_to_ieee754_s (char *litP, int *sizeP);
257 static const char *
258 str_to_ieee754_d (char *litP, int *sizeP);
259
260 static str_to_float_t
261 get_str_to_float (const char *arg)
262 {
263 if (strcasecmp (arg, "zeda32") == 0)
264 return str_to_zeda32;
265
266 if (strcasecmp (arg, "math48") == 0)
267 return str_to_float48;
268
269 if (strcasecmp (arg, "half") != 0)
270 return str_to_ieee754_h;
271
272 if (strcasecmp (arg, "single") != 0)
273 return str_to_ieee754_s;
274
275 if (strcasecmp (arg, "double") != 0)
276 return str_to_ieee754_d;
277
278 if (strcasecmp (arg, "ieee754") == 0)
279 as_fatal (_("invalid floating point numbers type `%s'"), arg);
280 return NULL;
281 }
282
283 static int
284 setup_instruction_list (const char *list, int *add, int *sub)
285 {
286 char buf[16];
287 const char *b;
288 const char *e;
289 int sz;
290 int res = 0;
291 for (b = list; *b != '\0';)
292 {
293 e = strchr (b, ',');
294 if (e == NULL)
295 sz = strlen (b);
296 else
297 sz = e - b;
298 if (sz == 0 || sz >= (int)sizeof (buf))
299 {
300 as_bad (_("invalid INST in command line: %s"), b);
301 return 0;
302 }
303 memcpy (buf, b, sz);
304 buf[sz] = '\0';
305 if (setup_instruction (buf, add, sub))
306 res++;
307 else
308 {
309 as_bad (_("invalid INST in command line: %s"), buf);
310 return 0;
311 }
312 b = &b[sz];
313 if (*b == ',')
314 ++b;
315 }
316 return res;
317 }
318
319 int
320 md_parse_option (int c, const char* arg)
321 {
322 switch (c)
323 {
324 default:
325 return 0;
326 case OPTION_MARCH:
327 setup_march (arg, & ins_ok, & ins_err, & cpu_mode);
328 break;
329 case OPTION_MACH_Z80:
330 setup_march ("z80", & ins_ok, & ins_err, & cpu_mode);
331 break;
332 case OPTION_MACH_R800:
333 setup_march ("r800", & ins_ok, & ins_err, & cpu_mode);
334 break;
335 case OPTION_MACH_Z180:
336 setup_march ("z180", & ins_ok, & ins_err, & cpu_mode);
337 break;
338 case OPTION_MACH_EZ80_Z80:
339 setup_march ("ez80", & ins_ok, & ins_err, & cpu_mode);
340 break;
341 case OPTION_MACH_EZ80_ADL:
342 setup_march ("ez80+adl", & ins_ok, & ins_err, & cpu_mode);
343 break;
344 case OPTION_FP_SINGLE_FORMAT:
345 str_to_float = get_str_to_float (arg);
346 break;
347 case OPTION_FP_DOUBLE_FORMAT:
348 str_to_double = get_str_to_float (arg);
349 break;
350 case OPTION_MACH_INST:
351 if ((ins_ok & INS_GBZ80) == 0)
352 return setup_instruction_list (arg, & ins_ok, & ins_err);
353 break;
354 case OPTION_MACH_NO_INST:
355 if ((ins_ok & INS_GBZ80) == 0)
356 return setup_instruction_list (arg, & ins_err, & ins_ok);
357 break;
358 case OPTION_MACH_WUD:
359 case OPTION_MACH_IUD:
360 if ((ins_ok & INS_GBZ80) == 0)
361 {
362 ins_ok |= INS_UNDOC;
363 ins_err &= ~INS_UNDOC;
364 }
365 break;
366 case OPTION_MACH_WUP:
367 case OPTION_MACH_IUP:
368 if ((ins_ok & INS_GBZ80) == 0)
369 {
370 ins_ok |= INS_UNDOC | INS_UNPORT;
371 ins_err &= ~(INS_UNDOC | INS_UNPORT);
372 }
373 break;
374 case OPTION_MACH_FUD:
375 if ((ins_ok & (INS_R800 | INS_GBZ80)) == 0)
376 {
377 ins_ok &= (INS_UNDOC | INS_UNPORT);
378 ins_err |= INS_UNDOC | INS_UNPORT;
379 }
380 break;
381 case OPTION_MACH_FUP:
382 ins_ok &= ~INS_UNPORT;
383 ins_err |= INS_UNPORT;
384 break;
385 case OPTION_COMPAT_LL_PREFIX:
386 local_label_prefix = (arg && *arg) ? arg : NULL;
387 break;
388 case OPTION_COMPAT_SDCC:
389 sdcc_compat = 1;
390 break;
391 case OPTION_COMPAT_COLONLESS:
392 colonless_labels = 1;
393 break;
394 }
395
396 return 1;
397 }
398
399 void
400 md_show_usage (FILE * f)
401 {
402 unsigned i;
403 fprintf (f, _("\n\
404 CPU model options:\n\
405 -march=CPU[+EXT...][-EXT...]\n\
406 \t\t\t generate code for CPU, where CPU is one of:\n"));
407 for (i = 0; i < ARRAY_SIZE(match_cpu_table); ++i)
408 fprintf (f, " %-8s\t\t %s\n", match_cpu_table[i].name, match_cpu_table[i].comment);
409 fprintf (f, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n"));
410 for (i = 0; i < ARRAY_SIZE(match_ext_table); ++i)
411 fprintf (f, " %-8s\t\t %s\n", match_ext_table[i].name, match_ext_table[i].comment);
412 fprintf (f, _("\n\
413 Compatibility options:\n\
414 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
415 -colonless\t\t permit colonless labels\n\
416 -sdcc\t\t\t accept SDCC specific instruction syntax\n\
417 -fp-s=FORMAT\t\t set single precision FP numbers format\n\
418 -fp-d=FORMAT\t\t set double precision FP numbers format\n\
419 Where FORMAT one of:\n\
420 ieee754\t\t IEEE754 compatible (depends on directive)\n\
421 half\t\t\t IEEE754 half precision (16 bit)\n\
422 single\t\t IEEE754 single precision (32 bit)\n\
423 double\t\t IEEE754 double precision (64 bit)\n\
424 zeda32\t\t Zeda z80float library 32 bit format\n\
425 math48\t\t 48 bit format from Math48 library\n\
426 \n\
427 Default: -march=z80+xyhl+infc\n"));
428 }
429
430 static symbolS * zero;
431
432 struct reg_entry
433 {
434 const char* name;
435 int number;
436 int isa;
437 };
438 #define R_STACKABLE (0x80)
439 #define R_ARITH (0x40)
440 #define R_IX (0x20)
441 #define R_IY (0x10)
442 #define R_INDEX (R_IX | R_IY)
443
444 #define REG_A (7)
445 #define REG_B (0)
446 #define REG_C (1)
447 #define REG_D (2)
448 #define REG_E (3)
449 #define REG_H (4)
450 #define REG_L (5)
451 #define REG_F (6 | 8)
452 #define REG_I (9)
453 #define REG_R (10)
454 #define REG_MB (11)
455
456 #define REG_AF (3 | R_STACKABLE)
457 #define REG_BC (0 | R_STACKABLE | R_ARITH)
458 #define REG_DE (1 | R_STACKABLE | R_ARITH)
459 #define REG_HL (2 | R_STACKABLE | R_ARITH)
460 #define REG_IX (REG_HL | R_IX)
461 #define REG_IY (REG_HL | R_IY)
462 #define REG_SP (3 | R_ARITH)
463
464 static const struct reg_entry regtable[] =
465 {
466 {"a", REG_A, INS_ALL },
467 {"af", REG_AF, INS_ALL },
468 {"b", REG_B, INS_ALL },
469 {"bc", REG_BC, INS_ALL },
470 {"c", REG_C, INS_ALL },
471 {"d", REG_D, INS_ALL },
472 {"de", REG_DE, INS_ALL },
473 {"e", REG_E, INS_ALL },
474 {"f", REG_F, INS_IN_F_C | INS_Z80N | INS_R800 },
475 {"h", REG_H, INS_ALL },
476 {"hl", REG_HL, INS_ALL },
477 {"i", REG_I, INS_NOT_GBZ80 },
478 {"ix", REG_IX, INS_NOT_GBZ80 },
479 {"ixh", REG_H | R_IX, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
480 {"ixl", REG_L | R_IX, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
481 {"iy", REG_IY, INS_NOT_GBZ80 },
482 {"iyh", REG_H | R_IY, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
483 {"iyl", REG_L | R_IY, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
484 {"l", REG_L, INS_ALL },
485 {"mb", REG_MB, INS_EZ80 },
486 {"r", REG_R, INS_NOT_GBZ80 },
487 {"sp", REG_SP, INS_ALL },
488 } ;
489
490 #define BUFLEN 8 /* Large enough for any keyword. */
491
492 void
493 md_begin (void)
494 {
495 expressionS nul, reg;
496 char * p;
497 unsigned int i, j, k;
498 char buf[BUFLEN];
499
500 memset (&reg, 0, sizeof (reg));
501 memset (&nul, 0, sizeof (nul));
502
503 if (ins_ok & INS_EZ80) /* if select EZ80 cpu then */
504 listing_lhs_width = 6; /* use 6 bytes per line in the listing */
505
506 reg.X_op = O_register;
507 reg.X_md = 0;
508 reg.X_add_symbol = reg.X_op_symbol = 0;
509 for ( i = 0 ; i < ARRAY_SIZE ( regtable ) ; ++i )
510 {
511 if (regtable[i].isa && !(regtable[i].isa & ins_ok))
512 continue;
513 reg.X_add_number = regtable[i].number;
514 k = strlen ( regtable[i].name );
515 buf[k] = 0;
516 if ( k+1 < BUFLEN )
517 {
518 for ( j = ( 1<<k ) ; j ; --j )
519 {
520 for ( k = 0 ; regtable[i].name[k] ; ++k )
521 {
522 buf[k] = ( j & ( 1<<k ) ) ? TOUPPER (regtable[i].name[k]) : regtable[i].name[k];
523 }
524 symbolS * psym = symbol_find_or_make (buf);
525 S_SET_SEGMENT (psym, reg_section);
526 symbol_set_value_expression (psym, &reg);
527 }
528 }
529 }
530 p = input_line_pointer;
531 input_line_pointer = (char *) "0";
532 nul.X_md=0;
533 expression (& nul);
534 input_line_pointer = p;
535 zero = make_expr_symbol (& nul);
536 /* We do not use relaxation (yet). */
537 linkrelax = 0;
538 }
539
540 void
541 z80_md_finish (void)
542 {
543 int mach_type;
544
545 switch (ins_ok & INS_MARCH_MASK)
546 {
547 case INS_Z80:
548 mach_type = bfd_mach_z80;
549 break;
550 case INS_R800:
551 mach_type = bfd_mach_r800;
552 break;
553 case INS_Z180:
554 mach_type = bfd_mach_z180;
555 break;
556 case INS_GBZ80:
557 mach_type = bfd_mach_gbz80;
558 break;
559 case INS_EZ80:
560 mach_type = cpu_mode ? bfd_mach_ez80_adl : bfd_mach_ez80_z80;
561 break;
562 case INS_Z80N:
563 mach_type = bfd_mach_z80n;
564 break;
565 default:
566 mach_type = 0;
567 }
568 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_type);
569 }
570
571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
572 void
573 z80_elf_final_processing (void)
574 {/* nothing to do, all is done by BFD itself */
575 /*
576 unsigned elf_flags;
577 elf_elfheader (stdoutput)->e_flags = elf_flags;
578 */
579 }
580 #endif
581
582 static const char *
583 skip_space (const char *s)
584 {
585 while (*s == ' ' || *s == '\t')
586 ++s;
587 return s;
588 }
589
590 /* A non-zero return-value causes a continue in the
591 function read_a_source_file () in ../read.c. */
592 int
593 z80_start_line_hook (void)
594 {
595 char *p, quote;
596 char buf[4];
597
598 /* Convert one character constants. */
599 for (p = input_line_pointer; *p && *p != '\n'; ++p)
600 {
601 switch (*p)
602 {
603 case '\'':
604 if (p[1] != 0 && p[1] != '\'' && p[2] == '\'')
605 {
606 snprintf (buf, 4, "%3d", (unsigned char)p[1]);
607 *p++ = buf[0];
608 *p++ = buf[1];
609 *p++ = buf[2];
610 break;
611 }
612 /* Fall through. */
613 case '"':
614 for (quote = *p++; quote != *p && '\n' != *p; ++p)
615 /* No escapes. */ ;
616 if (quote != *p)
617 {
618 as_bad (_("-- unterminated string"));
619 ignore_rest_of_line ();
620 return 1;
621 }
622 break;
623 case '#': /* force to use next expression as immediate value in SDCC */
624 if (!sdcc_compat)
625 break;
626 if (ISSPACE(p[1]) && *skip_space (p + 1) == '(')
627 { /* ld a,# (expr)... -> ld a,0+(expr)... */
628 *p++ = '0';
629 *p = '+';
630 }
631 else /* ld a,#(expr)... -> ld a,+(expr); ld a,#expr -> ld a, expr */
632 *p = (p[1] == '(') ? '+' : ' ';
633 break;
634 }
635 }
636 /* Check for <label>[:] =|([.](EQU|DEFL)) <value>. */
637 if (is_name_beginner (*input_line_pointer))
638 {
639 char *name;
640 char c, *rest, *line_start;
641 int len;
642
643 line_start = input_line_pointer;
644 if (ignore_input ())
645 return 0;
646 c = get_symbol_name (&name);
647 rest = input_line_pointer + 1;
648 if (c == ':' && *rest == ':')
649 {
650 /* remove second colon if SDCC compatibility enabled */
651 if (sdcc_compat)
652 *rest = ' ';
653 ++rest;
654 }
655 rest = (char*)skip_space (rest);
656 if (*rest == '=')
657 len = (rest[1] == '=') ? 2 : 1;
658 else
659 {
660 if (*rest == '.')
661 ++rest;
662 if (strncasecmp (rest, "EQU", 3) == 0)
663 len = 3;
664 else if (strncasecmp (rest, "DEFL", 4) == 0)
665 len = 4;
666 else
667 len = 0;
668 }
669 if (len && (len <= 2 || !ISALPHA (rest[len])))
670 {
671 /* Handle assignment here. */
672 if (line_start[-1] == '\n')
673 {
674 bump_line_counters ();
675 LISTING_NEWLINE ();
676 }
677 input_line_pointer = rest + len - 1;
678 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
679 switch (len)
680 {
681 case 1: /* label = expr */
682 case 4: /* label DEFL expr */
683 equals (name, 1);
684 break;
685 case 2: /* label == expr */
686 case 3: /* label EQU expr */
687 equals (name, 0);
688 break;
689 }
690 return 1;
691 }
692 else
693 {
694 /* Restore line and pointer. */
695 (void) restore_line_pointer (c);
696 input_line_pointer = line_start;
697 }
698 }
699 return 0;
700 }
701
702 symbolS *
703 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
704 {
705 return NULL;
706 }
707
708 const char *
709 md_atof (int type, char *litP, int *sizeP)
710 {
711 switch (type)
712 {
713 case 'f':
714 case 'F':
715 case 's':
716 case 'S':
717 if (str_to_float)
718 return str_to_float (litP, sizeP);
719 break;
720 case 'd':
721 case 'D':
722 case 'r':
723 case 'R':
724 if (str_to_double)
725 return str_to_double (litP, sizeP);
726 break;
727 }
728 return ieee_md_atof (type, litP, sizeP, false);
729 }
730
731 valueT
732 md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size)
733 {
734 return size;
735 }
736
737 long
738 md_pcrel_from (fixS * fixp)
739 {
740 return fixp->fx_where + fixp->fx_frag->fr_address;
741 }
742
743 typedef const char * (asfunc)(char, char, const char*);
744
745 typedef struct _table_t
746 {
747 const char* name;
748 unsigned char prefix;
749 unsigned char opcode;
750 asfunc * fp;
751 unsigned inss; /*0 - all CPU types or list of supported INS_* */
752 } table_t;
753
754 /* Compares the key for structs that start with a char * to the key. */
755 static int
756 key_cmp (const void * a, const void * b)
757 {
758 const char *str_a, *str_b;
759
760 str_a = *((const char**)a);
761 str_b = *((const char**)b);
762 return strcmp (str_a, str_b);
763 }
764
765 char buf[BUFLEN];
766 const char *key = buf;
767
768 /* Prevent an error on a line from also generating
769 a "junk at end of line" error message. */
770 static char err_flag;
771
772 static void
773 error (const char * message)
774 {
775 if (err_flag)
776 return;
777
778 as_bad ("%s", message);
779 err_flag = 1;
780 }
781
782 static void
783 ill_op (void)
784 {
785 error (_("illegal operand"));
786 }
787
788 static void
789 wrong_mach (int ins_type)
790 {
791 if (ins_type & ins_err)
792 ill_op ();
793 else
794 as_warn (_("undocumented instruction"));
795 }
796
797 static void
798 check_mach (int ins_type)
799 {
800 if ((ins_type & ins_ok) == 0)
801 wrong_mach (ins_type);
802 }
803
804 /* Check whether an expression is indirect. */
805 static int
806 is_indir (const char *s)
807 {
808 char quote;
809 const char *p;
810 int indir, depth;
811
812 /* Indirection is indicated with parentheses. */
813 indir = (*s == '(');
814
815 for (p = s, depth = 0; *p && *p != ','; ++p)
816 {
817 switch (*p)
818 {
819 case '"':
820 case '\'':
821 for (quote = *p++; quote != *p && *p != '\n'; ++p)
822 if (*p == '\\' && p[1])
823 ++p;
824 break;
825 case '(':
826 ++ depth;
827 break;
828 case ')':
829 -- depth;
830 if (depth == 0)
831 {
832 p = skip_space (p + 1);
833 if (*p && *p != ',')
834 indir = 0;
835 --p;
836 }
837 if (depth < 0)
838 error (_("mismatched parentheses"));
839 break;
840 }
841 }
842
843 if (depth != 0)
844 error (_("mismatched parentheses"));
845
846 return indir;
847 }
848
849 /* Check whether a symbol involves a register. */
850 static bool
851 contains_register (symbolS *sym)
852 {
853 if (sym)
854 {
855 expressionS * ex = symbol_get_value_expression (sym);
856
857 switch (ex->X_op)
858 {
859 case O_register:
860 return true;
861
862 case O_add:
863 case O_subtract:
864 if (ex->X_op_symbol && contains_register (ex->X_op_symbol))
865 return true;
866 /* Fall through. */
867 case O_uminus:
868 case O_symbol:
869 if (ex->X_add_symbol && contains_register (ex->X_add_symbol))
870 return true;
871 break;
872
873 default:
874 break;
875 }
876 }
877
878 return false;
879 }
880
881 /* Parse general expression, not looking for indexed addressing. */
882 static const char *
883 parse_exp_not_indexed (const char *s, expressionS *op)
884 {
885 const char *p;
886 int indir;
887 int make_shift = -1;
888
889 memset (op, 0, sizeof (*op));
890 p = skip_space (s);
891 if (sdcc_compat && (*p == '<' || *p == '>'))
892 {
893 switch (*p)
894 {
895 case '<': /* LSB request */
896 make_shift = 0;
897 break;
898 case '>': /* MSB request */
899 make_shift = cpu_mode ? 16 : 8;
900 break;
901 }
902 s = ++p;
903 p = skip_space (p);
904 }
905
906 if (make_shift == -1)
907 indir = is_indir (p);
908 else
909 indir = 0;
910 op->X_md = indir;
911 if (indir && (ins_ok & INS_GBZ80))
912 { /* check for instructions like ld a,(hl+), ld (hl-),a */
913 p = skip_space (p+1);
914 if (!strncasecmp (p, "hl", 2))
915 {
916 p = skip_space(p+2);
917 if (*skip_space(p+1) == ')' && (*p == '+' || *p == '-'))
918 {
919 op->X_op = O_md1;
920 op->X_add_symbol = NULL;
921 op->X_add_number = (*p == '+') ? REG_HL : -REG_HL;
922 input_line_pointer = (char*)skip_space(p + 1) + 1;
923 return input_line_pointer;
924 }
925 }
926 }
927 input_line_pointer = (char*) s ;
928 expression (op);
929 resolve_register (op);
930 switch (op->X_op)
931 {
932 case O_absent:
933 error (_("missing operand"));
934 break;
935 case O_illegal:
936 error (_("bad expression syntax"));
937 break;
938 default:
939 break;
940 }
941
942 if (make_shift >= 0)
943 {
944 /* replace [op] by [op >> shift] */
945 expressionS data;
946 op->X_add_symbol = make_expr_symbol (op);
947 op->X_add_number = 0;
948 op->X_op = O_right_shift;
949 memset (&data, 0, sizeof (data));
950 data.X_op = O_constant;
951 data.X_add_number = make_shift;
952 op->X_op_symbol = make_expr_symbol (&data);
953 }
954 return input_line_pointer;
955 }
956
957 static int
958 unify_indexed (expressionS *op)
959 {
960 if (O_register != symbol_get_value_expression (op->X_add_symbol)->X_op)
961 return 0;
962
963 int rnum = symbol_get_value_expression (op->X_add_symbol)->X_add_number;
964 if ( ((REG_IX != rnum) && (REG_IY != rnum)) || contains_register (op->X_op_symbol))
965 {
966 ill_op ();
967 return 0;
968 }
969
970 /* Convert subtraction to addition of negative value. */
971 if (O_subtract == op->X_op)
972 {
973 expressionS minus;
974 memset (&minus, 0, sizeof (minus));
975 minus.X_op = O_uminus;
976 minus.X_add_symbol = op->X_op_symbol;
977 op->X_op_symbol = make_expr_symbol (&minus);
978 op->X_op = O_add;
979 }
980
981 /* Clear X_add_number of the expression. */
982 if (op->X_add_number != 0)
983 {
984 expressionS add;
985 memset (&add, 0, sizeof (add));
986 add.X_op = O_symbol;
987 add.X_add_number = op->X_add_number;
988 add.X_add_symbol = op->X_op_symbol;
989 op->X_add_symbol = make_expr_symbol (&add);
990 }
991 else
992 op->X_add_symbol = op->X_op_symbol;
993
994 op->X_add_number = rnum;
995 op->X_op_symbol = 0;
996 return 1;
997 }
998
999 /* Parse expression, change operator to O_md1 for indexed addressing. */
1000 static const char *
1001 parse_exp (const char *s, expressionS *op)
1002 {
1003 const char* res = parse_exp_not_indexed (s, op);
1004 switch (op->X_op)
1005 {
1006 case O_add:
1007 case O_subtract:
1008 if (unify_indexed (op) && op->X_md)
1009 op->X_op = O_md1;
1010 break;
1011 case O_register:
1012 if (op->X_md && ((REG_IX == op->X_add_number) || (REG_IY == op->X_add_number)))
1013 {
1014 op->X_add_symbol = zero;
1015 op->X_op = O_md1;
1016 }
1017 break;
1018 case O_constant:
1019 /* parse SDCC syntax where index register offset placed before parentheses */
1020 if (sdcc_compat && is_indir (res))
1021 {
1022 expressionS off;
1023 off = *op;
1024 res = parse_exp (res, op);
1025 if (op->X_op != O_md1 || op->X_add_symbol != zero)
1026 ill_op ();
1027 else
1028 op->X_add_symbol = make_expr_symbol (&off);
1029 }
1030 break;
1031 default:
1032 break;
1033 }
1034 return res;
1035 }
1036
1037 /* Condition codes, including some synonyms provided by HiTech zas. */
1038 static const struct reg_entry cc_tab[] =
1039 {
1040 { "age", 6 << 3, INS_ALL },
1041 { "alt", 7 << 3, INS_ALL },
1042 { "c", 3 << 3, INS_ALL },
1043 { "di", 4 << 3, INS_ALL },
1044 { "ei", 5 << 3, INS_ALL },
1045 { "lge", 2 << 3, INS_ALL },
1046 { "llt", 3 << 3, INS_ALL },
1047 { "m", 7 << 3, INS_ALL },
1048 { "nc", 2 << 3, INS_ALL },
1049 { "nz", 0 << 3, INS_ALL },
1050 { "p", 6 << 3, INS_ALL },
1051 { "pe", 5 << 3, INS_ALL },
1052 { "po", 4 << 3, INS_ALL },
1053 { "z", 1 << 3, INS_ALL },
1054 } ;
1055
1056 /* Parse condition code. */
1057 static const char *
1058 parse_cc (const char *s, char * op)
1059 {
1060 const char *p;
1061 int i;
1062 struct reg_entry * cc_p;
1063
1064 for (i = 0; i < BUFLEN; ++i)
1065 {
1066 if (!ISALPHA (s[i])) /* Condition codes consist of letters only. */
1067 break;
1068 buf[i] = TOLOWER (s[i]);
1069 }
1070
1071 if ((i < BUFLEN)
1072 && ((s[i] == 0) || (s[i] == ',')))
1073 {
1074 buf[i] = 0;
1075 cc_p = bsearch (&key, cc_tab, ARRAY_SIZE (cc_tab),
1076 sizeof (cc_tab[0]), key_cmp);
1077 }
1078 else
1079 cc_p = NULL;
1080
1081 if (cc_p)
1082 {
1083 *op = cc_p->number;
1084 p = s + i;
1085 }
1086 else
1087 p = NULL;
1088
1089 return p;
1090 }
1091
1092 static const char *
1093 emit_insn (char prefix, char opcode, const char * args)
1094 {
1095 char *p;
1096
1097 if (prefix)
1098 {
1099 p = frag_more (2);
1100 *p++ = prefix;
1101 }
1102 else
1103 p = frag_more (1);
1104 *p = opcode;
1105 return args;
1106 }
1107
1108 void z80_cons_fix_new (fragS *frag_p, int offset, int nbytes, expressionS *exp)
1109 {
1110 bfd_reloc_code_real_type r[4] =
1111 {
1112 BFD_RELOC_8,
1113 BFD_RELOC_16,
1114 BFD_RELOC_24,
1115 BFD_RELOC_32
1116 };
1117
1118 if (nbytes < 1 || nbytes > 4)
1119 {
1120 as_bad (_("unsupported BFD relocation size %u"), nbytes);
1121 }
1122 else
1123 {
1124 fix_new_exp (frag_p, offset, nbytes, exp, 0, r[nbytes-1]);
1125 }
1126 }
1127
1128 static void
1129 emit_data_val (expressionS * val, int size)
1130 {
1131 char *p;
1132 bfd_reloc_code_real_type r_type;
1133
1134 p = frag_more (size);
1135 if (val->X_op == O_constant)
1136 {
1137 int i;
1138
1139 /* PR 28791:
1140 Check for overflow, but ignore values that were generated by bit
1141 manipulation operators (eg ~0xe6 and -7). This does mean that
1142 manipluated overlarge values will not be reported (eg ~0x1234),
1143 but it does help to maintain compatibility with earlier versions
1144 of the assembler. */
1145 if (! val->X_extrabit
1146 && is_overflow (val->X_add_number, size*8))
1147 as_warn ( _("%d-bit overflow (%+ld)"), size*8, val->X_add_number);
1148 for (i = 0; i < size; ++i)
1149 p[i] = (char)(val->X_add_number >> (i*8));
1150 return;
1151 }
1152
1153 switch (size)
1154 {
1155 case 1: r_type = BFD_RELOC_8; break;
1156 case 2: r_type = BFD_RELOC_16; break;
1157 case 3: r_type = BFD_RELOC_24; break;
1158 case 4: r_type = BFD_RELOC_32; break;
1159 case 8: r_type = BFD_RELOC_64; break;
1160 default:
1161 as_fatal (_("invalid data size %d"), size);
1162 }
1163
1164 if ( (val->X_op == O_register)
1165 || (val->X_op == O_md1)
1166 || contains_register (val->X_add_symbol)
1167 || contains_register (val->X_op_symbol))
1168 ill_op ();
1169
1170 if (size <= 2 && val->X_op_symbol)
1171 {
1172 bool simplify = true;
1173 int shift = symbol_get_value_expression (val->X_op_symbol)->X_add_number;
1174 if (val->X_op == O_bit_and && shift == (1 << (size*8))-1)
1175 shift = 0;
1176 else if (val->X_op != O_right_shift)
1177 shift = -1;
1178
1179 if (size == 1)
1180 {
1181 switch (shift)
1182 {
1183 case 0: r_type = BFD_RELOC_Z80_BYTE0; break;
1184 case 8: r_type = BFD_RELOC_Z80_BYTE1; break;
1185 case 16: r_type = BFD_RELOC_Z80_BYTE2; break;
1186 case 24: r_type = BFD_RELOC_Z80_BYTE3; break;
1187 default: simplify = false;
1188 }
1189 }
1190 else /* if (size == 2) */
1191 {
1192 switch (shift)
1193 {
1194 case 0: r_type = BFD_RELOC_Z80_WORD0; break;
1195 case 16: r_type = BFD_RELOC_Z80_WORD1; break;
1196 case 8:
1197 case 24: /* add two byte fixups */
1198 val->X_op = O_symbol;
1199 val->X_op_symbol = NULL;
1200 val->X_add_number = 0;
1201 if (shift == 8)
1202 {
1203 fix_new_exp (frag_now, p++ - frag_now->fr_literal, 1, val, false,
1204 BFD_RELOC_Z80_BYTE1);
1205 /* prepare to next byte */
1206 r_type = BFD_RELOC_Z80_BYTE2;
1207 }
1208 else
1209 r_type = BFD_RELOC_Z80_BYTE3; /* high byte will be 0 */
1210 size = 1;
1211 simplify = false;
1212 break;
1213 default: simplify = false;
1214 }
1215 }
1216
1217 if (simplify)
1218 {
1219 val->X_op = O_symbol;
1220 val->X_op_symbol = NULL;
1221 val->X_add_number = 0;
1222 }
1223 }
1224
1225 fix_new_exp (frag_now, p - frag_now->fr_literal, size, val, false, r_type);
1226 }
1227
1228 static void
1229 emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
1230 {
1231 char *p;
1232
1233 if (r_type == BFD_RELOC_8)
1234 {
1235 emit_data_val (val, 1);
1236 return;
1237 }
1238 p = frag_more (1);
1239 *p = val->X_add_number;
1240 if (contains_register (val->X_add_symbol) || contains_register (val->X_op_symbol))
1241 {
1242 ill_op ();
1243 }
1244 else if ((r_type == BFD_RELOC_8_PCREL) && (val->X_op == O_constant))
1245 {
1246 as_bad (_("cannot make a relative jump to an absolute location"));
1247 }
1248 else if (val->X_op == O_constant)
1249 {
1250 if ((val->X_add_number < -128) || (val->X_add_number >= 128))
1251 {
1252 if (r_type == BFD_RELOC_Z80_DISP8)
1253 as_bad (_("index overflow (%+ld)"), val->X_add_number);
1254 else
1255 as_bad (_("offset overflow (%+ld)"), val->X_add_number);
1256 }
1257 }
1258 else
1259 {
1260 /* For symbols only, constants are stored at begin of function. */
1261 fix_new_exp (frag_now, p - frag_now->fr_literal, 1, val,
1262 r_type == BFD_RELOC_8_PCREL, r_type);
1263 }
1264 }
1265
1266 static void
1267 emit_word (expressionS * val)
1268 {
1269 emit_data_val (val, (inst_mode & INST_MODE_IL) ? 3 : 2);
1270 }
1271
1272 static void
1273 emit_mx (char prefix, char opcode, int shift, expressionS * arg)
1274 /* The operand m may be r, (hl), (ix+d), (iy+d),
1275 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */
1276 {
1277 char *q;
1278 int rnum;
1279
1280 rnum = arg->X_add_number;
1281 switch (arg->X_op)
1282 {
1283 case O_register:
1284 if (arg->X_md)
1285 {
1286 if (rnum != REG_HL)
1287 {
1288 ill_op ();
1289 break;
1290 }
1291 else
1292 rnum = 6;
1293 }
1294 else
1295 {
1296 if ((prefix == 0) && (rnum & R_INDEX))
1297 {
1298 prefix = (rnum & R_IX) ? 0xDD : 0xFD;
1299 if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N)))
1300 check_mach (INS_IDX_HALF);
1301 rnum &= ~R_INDEX;
1302 }
1303 if (rnum > 7)
1304 {
1305 ill_op ();
1306 break;
1307 }
1308 }
1309 q = frag_more (prefix ? 2 : 1);
1310 if (prefix)
1311 * q ++ = prefix;
1312 * q ++ = opcode + (rnum << shift);
1313 break;
1314 case O_md1:
1315 if (ins_ok & INS_GBZ80)
1316 {
1317 ill_op ();
1318 break;
1319 }
1320 q = frag_more (2);
1321 *q++ = (rnum & R_IX) ? 0xDD : 0xFD;
1322 *q = (prefix) ? prefix : (opcode + (6 << shift));
1323 {
1324 expressionS offset = *arg;
1325 offset.X_op = O_symbol;
1326 offset.X_add_number = 0;
1327 emit_byte (&offset, BFD_RELOC_Z80_DISP8);
1328 }
1329 if (prefix)
1330 {
1331 q = frag_more (1);
1332 *q = opcode+(6<<shift);
1333 }
1334 break;
1335 default:
1336 abort ();
1337 }
1338 }
1339
1340 /* The operand m may be r, (hl), (ix+d), (iy+d),
1341 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */
1342 static const char *
1343 emit_m (char prefix, char opcode, const char *args)
1344 {
1345 expressionS arg_m;
1346 const char *p;
1347
1348 p = parse_exp (args, &arg_m);
1349 switch (arg_m.X_op)
1350 {
1351 case O_md1:
1352 case O_register:
1353 emit_mx (prefix, opcode, 0, &arg_m);
1354 break;
1355 default:
1356 ill_op ();
1357 }
1358 return p;
1359 }
1360
1361 /* The operand m may be as above or one of the undocumented
1362 combinations (ix+d),r and (iy+d),r (if unportable instructions
1363 are allowed). */
1364
1365 static const char *
1366 emit_mr (char prefix, char opcode, const char *args)
1367 {
1368 expressionS arg_m, arg_r;
1369 const char *p;
1370
1371 p = parse_exp (args, & arg_m);
1372
1373 switch (arg_m.X_op)
1374 {
1375 case O_md1:
1376 if (*p == ',')
1377 {
1378 p = parse_exp (p + 1, & arg_r);
1379
1380 if ((arg_r.X_md == 0)
1381 && (arg_r.X_op == O_register)
1382 && (arg_r.X_add_number < 8))
1383 opcode += arg_r.X_add_number - 6; /* Emit_mx () will add 6. */
1384 else
1385 {
1386 ill_op ();
1387 break;
1388 }
1389 if (!(ins_ok & INS_Z80N))
1390 check_mach (INS_ROT_II_LD);
1391 }
1392 /* Fall through. */
1393 case O_register:
1394 emit_mx (prefix, opcode, 0, & arg_m);
1395 break;
1396 default:
1397 ill_op ();
1398 }
1399 return p;
1400 }
1401
1402 static void
1403 emit_sx (char prefix, char opcode, expressionS * arg_p)
1404 {
1405 char *q;
1406
1407 switch (arg_p->X_op)
1408 {
1409 case O_register:
1410 case O_md1:
1411 emit_mx (prefix, opcode, 0, arg_p);
1412 break;
1413 default:
1414 if (arg_p->X_md)
1415 ill_op ();
1416 else
1417 {
1418 q = frag_more (prefix ? 2 : 1);
1419 if (prefix)
1420 *q++ = prefix;
1421 *q = opcode ^ 0x46;
1422 emit_byte (arg_p, BFD_RELOC_8);
1423 }
1424 }
1425 }
1426
1427 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */
1428 static const char *
1429 emit_s (char prefix, char opcode, const char *args)
1430 {
1431 expressionS arg_s;
1432 const char *p;
1433
1434 p = parse_exp (args, & arg_s);
1435 if (*p == ',' && arg_s.X_md == 0 && arg_s.X_op == O_register && arg_s.X_add_number == REG_A)
1436 { /* possible instruction in generic format op A,x */
1437 if (!(ins_ok & INS_EZ80) && !sdcc_compat)
1438 ill_op ();
1439 ++p;
1440 p = parse_exp (p, & arg_s);
1441 }
1442 emit_sx (prefix, opcode, & arg_s);
1443 return p;
1444 }
1445
1446 static const char *
1447 emit_sub (char prefix, char opcode, const char *args)
1448 {
1449 expressionS arg_s;
1450 const char *p;
1451
1452 if (!(ins_ok & INS_GBZ80))
1453 return emit_s (prefix, opcode, args);
1454 p = parse_exp (args, & arg_s);
1455 if (*p++ != ',')
1456 {
1457 error (_("bad instruction syntax"));
1458 return p;
1459 }
1460
1461 if (arg_s.X_md != 0 || arg_s.X_op != O_register || arg_s.X_add_number != REG_A)
1462 ill_op ();
1463
1464 p = parse_exp (p, & arg_s);
1465
1466 emit_sx (prefix, opcode, & arg_s);
1467 return p;
1468 }
1469
1470 static const char *
1471 emit_swap (char prefix, char opcode, const char *args)
1472 {
1473 expressionS reg;
1474 const char *p;
1475 char *q;
1476
1477 if (!(ins_ok & INS_Z80N))
1478 return emit_mr (prefix, opcode, args);
1479
1480 /* check for alias swap a for swapnib of Z80N */
1481 p = parse_exp (args, &reg);
1482 if (reg.X_md != 0 || reg.X_op != O_register || reg.X_add_number != REG_A)
1483 ill_op ();
1484
1485 q = frag_more (2);
1486 *q++ = 0xED;
1487 *q = 0x23;
1488 return p;
1489 }
1490
1491 static const char *
1492 emit_call (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
1493 {
1494 expressionS addr;
1495 const char *p; char *q;
1496
1497 p = parse_exp_not_indexed (args, &addr);
1498 if (addr.X_md)
1499 ill_op ();
1500 else
1501 {
1502 q = frag_more (1);
1503 *q = opcode;
1504 emit_word (& addr);
1505 }
1506 return p;
1507 }
1508
1509 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */
1510 static const char *
1511 emit_incdec (char prefix, char opcode, const char * args)
1512 {
1513 expressionS operand;
1514 int rnum;
1515 const char *p; char *q;
1516
1517 p = parse_exp (args, &operand);
1518 rnum = operand.X_add_number;
1519 if ((! operand.X_md)
1520 && (operand.X_op == O_register)
1521 && (R_ARITH&rnum))
1522 {
1523 q = frag_more ((rnum & R_INDEX) ? 2 : 1);
1524 if (rnum & R_INDEX)
1525 *q++ = (rnum & R_IX) ? 0xDD : 0xFD;
1526 *q = prefix + ((rnum & 3) << 4);
1527 }
1528 else
1529 {
1530 if ((operand.X_op == O_md1) || (operand.X_op == O_register))
1531 emit_mx (0, opcode, 3, & operand);
1532 else
1533 ill_op ();
1534 }
1535 return p;
1536 }
1537
1538 static const char *
1539 emit_jr (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
1540 {
1541 expressionS addr;
1542 const char *p;
1543 char *q;
1544
1545 p = parse_exp_not_indexed (args, &addr);
1546 if (addr.X_md)
1547 ill_op ();
1548 else
1549 {
1550 q = frag_more (1);
1551 *q = opcode;
1552 addr.X_add_number--; /* pcrel computes after offset code */
1553 emit_byte (&addr, BFD_RELOC_8_PCREL);
1554 }
1555 return p;
1556 }
1557
1558 static const char *
1559 emit_jp (char prefix, char opcode, const char * args)
1560 {
1561 expressionS addr;
1562 const char *p;
1563 char *q;
1564 int rnum;
1565
1566 p = parse_exp_not_indexed (args, & addr);
1567 if (addr.X_md)
1568 {
1569 rnum = addr.X_add_number;
1570 if ((O_register == addr.X_op) && (REG_HL == (rnum & ~R_INDEX)))
1571 {
1572 q = frag_more ((rnum & R_INDEX) ? 2 : 1);
1573 if (rnum & R_INDEX)
1574 *q++ = (rnum & R_IX) ? 0xDD : 0xFD;
1575 *q = prefix;
1576 }
1577 else if (addr.X_op == O_register && rnum == REG_C && (ins_ok & INS_Z80N))
1578 {
1579 q = frag_more (2);
1580 *q++ = 0xED;
1581 *q = 0x98;
1582 }
1583 else
1584 ill_op ();
1585 }
1586 else
1587 {
1588 q = frag_more (1);
1589 *q = opcode;
1590 emit_word (& addr);
1591 }
1592 return p;
1593 }
1594
1595 static const char *
1596 emit_im (char prefix, char opcode, const char * args)
1597 {
1598 expressionS mode;
1599 const char *p;
1600 char *q;
1601
1602 p = parse_exp (args, & mode);
1603 if (mode.X_md || (mode.X_op != O_constant))
1604 ill_op ();
1605 else
1606 switch (mode.X_add_number)
1607 {
1608 case 1:
1609 case 2:
1610 ++mode.X_add_number;
1611 /* Fall through. */
1612 case 0:
1613 q = frag_more (2);
1614 *q++ = prefix;
1615 *q = opcode + 8*mode.X_add_number;
1616 break;
1617 default:
1618 ill_op ();
1619 }
1620 return p;
1621 }
1622
1623 static const char *
1624 emit_pop (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
1625 {
1626 expressionS regp;
1627 const char *p;
1628 char *q;
1629
1630 p = parse_exp (args, & regp);
1631 if ((!regp.X_md)
1632 && (regp.X_op == O_register)
1633 && (regp.X_add_number & R_STACKABLE))
1634 {
1635 int rnum;
1636
1637 rnum = regp.X_add_number;
1638 if (rnum&R_INDEX)
1639 {
1640 q = frag_more (2);
1641 *q++ = (rnum&R_IX)?0xDD:0xFD;
1642 }
1643 else
1644 q = frag_more (1);
1645 *q = opcode + ((rnum & 3) << 4);
1646 }
1647 else
1648 ill_op ();
1649
1650 return p;
1651 }
1652
1653 static const char *
1654 emit_push (char prefix, char opcode, const char * args)
1655 {
1656 expressionS arg;
1657 const char *p;
1658 char *q;
1659
1660 p = parse_exp (args, & arg);
1661 if (arg.X_op == O_register)
1662 return emit_pop (prefix, opcode, args);
1663
1664 if (arg.X_md || arg.X_op == O_md1 || !(ins_ok & INS_Z80N))
1665 ill_op ();
1666
1667 q = frag_more (2);
1668 *q++ = 0xED;
1669 *q = 0x8A;
1670
1671 q = frag_more (2);
1672 fix_new_exp (frag_now, q - frag_now->fr_literal, 2, &arg, false,
1673 BFD_RELOC_Z80_16_BE);
1674
1675 return p;
1676 }
1677
1678 static const char *
1679 emit_retcc (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
1680 {
1681 char cc, *q;
1682 const char *p;
1683
1684 p = parse_cc (args, &cc);
1685 q = frag_more (1);
1686 if (p)
1687 *q = opcode + cc;
1688 else
1689 *q = prefix;
1690 return p ? p : args;
1691 }
1692
1693 static const char *
1694 emit_adc (char prefix, char opcode, const char * args)
1695 {
1696 expressionS term;
1697 int rnum;
1698 const char *p;
1699 char *q;
1700
1701 p = parse_exp (args, &term);
1702 if (*p++ != ',')
1703 {
1704 error (_("bad instruction syntax"));
1705 return p;
1706 }
1707
1708 if ((term.X_md) || (term.X_op != O_register))
1709 ill_op ();
1710 else
1711 switch (term.X_add_number)
1712 {
1713 case REG_A:
1714 p = emit_s (0, prefix, p);
1715 break;
1716 case REG_HL:
1717 p = parse_exp (p, &term);
1718 if ((!term.X_md) && (term.X_op == O_register))
1719 {
1720 rnum = term.X_add_number;
1721 if (R_ARITH == (rnum & (R_ARITH | R_INDEX)))
1722 {
1723 q = frag_more (2);
1724 *q++ = 0xED;
1725 *q = opcode + ((rnum & 3) << 4);
1726 break;
1727 }
1728 }
1729 /* Fall through. */
1730 default:
1731 ill_op ();
1732 }
1733 return p;
1734 }
1735
1736 static const char *
1737 emit_add (char prefix, char opcode, const char * args)
1738 {
1739 expressionS term;
1740 int lhs, rhs;
1741 const char *p;
1742 char *q;
1743
1744 p = parse_exp (args, &term);
1745 if (*p++ != ',')
1746 {
1747 error (_("bad instruction syntax"));
1748 return p;
1749 }
1750
1751 if ((term.X_md) || (term.X_op != O_register))
1752 ill_op ();
1753 else
1754 switch (term.X_add_number)
1755 {
1756 case REG_A:
1757 p = emit_s (0, prefix, p);
1758 break;
1759 case REG_SP:
1760 p = parse_exp (p, &term);
1761 if (!(ins_ok & INS_GBZ80) || term.X_md || term.X_op == O_register)
1762 ill_op ();
1763 q = frag_more (1);
1764 *q = 0xE8;
1765 emit_byte (&term, BFD_RELOC_Z80_DISP8);
1766 break;
1767 case REG_BC:
1768 case REG_DE:
1769 if (!(ins_ok & INS_Z80N))
1770 {
1771 ill_op ();
1772 break;
1773 }
1774 /* Fall through. */
1775 case REG_HL:
1776 case REG_IX:
1777 case REG_IY:
1778 lhs = term.X_add_number;
1779 p = parse_exp (p, &term);
1780 rhs = term.X_add_number;
1781 if (term.X_md != 0 || term.X_op == O_md1)
1782 ill_op ();
1783 else if ((term.X_op == O_register) && (rhs & R_ARITH) && (rhs == lhs || (rhs & ~R_INDEX) != REG_HL))
1784 {
1785 if (1)
1786 {
1787 q = frag_more ((lhs & R_INDEX) ? 2 : 1);
1788 if (lhs & R_INDEX)
1789 *q++ = (lhs & R_IX) ? 0xDD : 0xFD;
1790 *q = opcode + ((rhs & 3) << 4);
1791 break;
1792 }
1793 }
1794 else if (!(lhs & R_INDEX) && (ins_ok & INS_Z80N))
1795 {
1796 if (term.X_op == O_register && rhs == REG_A)
1797 { /* ADD BC/DE/HL,A */
1798 q = frag_more (2);
1799 *q++ = 0xED;
1800 *q = 0x33 - (lhs & 3);
1801 break;
1802 }
1803 else if (term.X_op != O_register && term.X_op != O_md1)
1804 { /* ADD BC/DE/HL,nn */
1805 q = frag_more (2);
1806 *q++ = 0xED;
1807 *q = 0x36 - (lhs & 3);
1808 emit_word (&term);
1809 break;
1810 }
1811 }
1812 /* Fall through. */
1813 default:
1814 ill_op ();
1815 }
1816 return p;
1817 }
1818
1819 static const char *
1820 emit_bit (char prefix, char opcode, const char * args)
1821 {
1822 expressionS b;
1823 int bn;
1824 const char *p;
1825
1826 p = parse_exp (args, &b);
1827 if (*p++ != ',')
1828 error (_("bad instruction syntax"));
1829
1830 bn = b.X_add_number;
1831 if ((!b.X_md)
1832 && (b.X_op == O_constant)
1833 && (0 <= bn)
1834 && (bn < 8))
1835 {
1836 if (opcode == 0x40)
1837 /* Bit : no optional third operand. */
1838 p = emit_m (prefix, opcode + (bn << 3), p);
1839 else
1840 /* Set, res : resulting byte can be copied to register. */
1841 p = emit_mr (prefix, opcode + (bn << 3), p);
1842 }
1843 else
1844 ill_op ();
1845 return p;
1846 }
1847
1848 /* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
1849 static const char *
1850 emit_bshft (char prefix, char opcode, const char * args)
1851 {
1852 expressionS r1, r2;
1853 const char *p;
1854 char *q;
1855
1856 p = parse_exp (args, & r1);
1857 if (*p++ != ',')
1858 error (_("bad instruction syntax"));
1859 p = parse_exp (p, & r2);
1860 if (r1.X_md || r1.X_op != O_register || r1.X_add_number != REG_DE ||
1861 r2.X_md || r2.X_op != O_register || r2.X_add_number != REG_B)
1862 ill_op ();
1863 q = frag_more (2);
1864 *q++ = prefix;
1865 *q = opcode;
1866 return p;
1867 }
1868
1869 static const char *
1870 emit_jpcc (char prefix, char opcode, const char * args)
1871 {
1872 char cc;
1873 const char *p;
1874
1875 p = parse_cc (args, & cc);
1876 if (p && *p++ == ',')
1877 p = emit_call (0, opcode + cc, p);
1878 else
1879 p = (prefix == (char)0xC3)
1880 ? emit_jp (0xE9, prefix, args)
1881 : emit_call (0, prefix, args);
1882 return p;
1883 }
1884
1885 static const char *
1886 emit_jrcc (char prefix, char opcode, const char * args)
1887 {
1888 char cc;
1889 const char *p;
1890
1891 p = parse_cc (args, &cc);
1892 if (p && *p++ == ',')
1893 {
1894 if (cc > (3 << 3))
1895 error (_("condition code invalid for jr"));
1896 else
1897 p = emit_jr (0, opcode + cc, p);
1898 }
1899 else
1900 p = emit_jr (0, prefix, args);
1901
1902 return p;
1903 }
1904
1905 static const char *
1906 emit_ex (char prefix_in ATTRIBUTE_UNUSED,
1907 char opcode_in ATTRIBUTE_UNUSED, const char * args)
1908 {
1909 expressionS op;
1910 const char * p;
1911 char prefix, opcode;
1912
1913 p = parse_exp_not_indexed (args, &op);
1914 p = skip_space (p);
1915 if (*p++ != ',')
1916 {
1917 error (_("bad instruction syntax"));
1918 return p;
1919 }
1920
1921 prefix = opcode = 0;
1922 if (op.X_op == O_register)
1923 switch (op.X_add_number | (op.X_md ? 0x8000 : 0))
1924 {
1925 case REG_AF:
1926 if (TOLOWER (*p++) == 'a' && TOLOWER (*p++) == 'f')
1927 {
1928 /* The scrubber changes '\'' to '`' in this context. */
1929 if (*p == '`')
1930 ++p;
1931 opcode = 0x08;
1932 }
1933 break;
1934 case REG_DE:
1935 if (TOLOWER (*p++) == 'h' && TOLOWER (*p++) == 'l')
1936 opcode = 0xEB;
1937 break;
1938 case REG_SP|0x8000:
1939 p = parse_exp (p, & op);
1940 if (op.X_op == O_register
1941 && op.X_md == 0
1942 && (op.X_add_number & ~R_INDEX) == REG_HL)
1943 {
1944 opcode = 0xE3;
1945 if (R_INDEX & op.X_add_number)
1946 prefix = (R_IX & op.X_add_number) ? 0xDD : 0xFD;
1947 }
1948 break;
1949 }
1950 if (opcode)
1951 emit_insn (prefix, opcode, p);
1952 else
1953 ill_op ();
1954
1955 return p;
1956 }
1957
1958 static const char *
1959 emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
1960 const char * args)
1961 {
1962 expressionS reg, port;
1963 const char *p;
1964 char *q;
1965
1966 p = parse_exp (args, &reg);
1967 if (reg.X_md && reg.X_op == O_register && reg.X_add_number == REG_C)
1968 { /* permit instruction in (c) as alias for in f,(c) */
1969 port = reg;
1970 reg.X_md = 0;
1971 reg.X_add_number = REG_F;
1972 }
1973 else
1974 {
1975 if (*p++ != ',')
1976 {
1977 error (_("bad instruction syntax"));
1978 return p;
1979 }
1980 p = parse_exp (p, &port);
1981 }
1982 if (reg.X_md == 0
1983 && reg.X_op == O_register
1984 && (reg.X_add_number <= 7 || reg.X_add_number == REG_F)
1985 && (port.X_md))
1986 {
1987 if (port.X_op != O_md1 && port.X_op != O_register)
1988 {
1989 if (REG_A == reg.X_add_number)
1990 {
1991 q = frag_more (1);
1992 *q = 0xDB;
1993 emit_byte (&port, BFD_RELOC_8);
1994 }
1995 else
1996 ill_op ();
1997 }
1998 else
1999 {
2000 if (port.X_add_number == REG_C || port.X_add_number == REG_BC)
2001 {
2002 if (port.X_add_number == REG_BC && !(ins_ok & INS_EZ80))
2003 ill_op ();
2004 else if (reg.X_add_number == REG_F && !(ins_ok & (INS_R800|INS_Z80N)))
2005 check_mach (INS_IN_F_C);
2006 q = frag_more (2);
2007 *q++ = 0xED;
2008 *q = 0x40|((reg.X_add_number&7)<<3);
2009 }
2010 else
2011 ill_op ();
2012 }
2013 }
2014 else
2015 ill_op ();
2016 return p;
2017 }
2018
2019 static const char *
2020 emit_in0 (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
2021 const char * args)
2022 {
2023 expressionS reg, port;
2024 const char *p;
2025 char *q;
2026
2027 p = parse_exp (args, &reg);
2028 if (*p++ != ',')
2029 {
2030 error (_("bad instruction syntax"));
2031 return p;
2032 }
2033
2034 p = parse_exp (p, &port);
2035 if (reg.X_md == 0
2036 && reg.X_op == O_register
2037 && reg.X_add_number <= 7
2038 && port.X_md
2039 && port.X_op != O_md1
2040 && port.X_op != O_register)
2041 {
2042 q = frag_more (2);
2043 *q++ = 0xED;
2044 *q = 0x00|(reg.X_add_number << 3);
2045 emit_byte (&port, BFD_RELOC_8);
2046 }
2047 else
2048 ill_op ();
2049 return p;
2050 }
2051
2052 static const char *
2053 emit_out (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
2054 const char * args)
2055 {
2056 expressionS reg, port;
2057 const char *p;
2058 char *q;
2059
2060 p = parse_exp (args, & port);
2061 if (*p++ != ',')
2062 {
2063 error (_("bad instruction syntax"));
2064 return p;
2065 }
2066 p = parse_exp (p, &reg);
2067 if (!port.X_md)
2068 { ill_op (); return p; }
2069 /* Allow "out (c), 0" as unportable instruction. */
2070 if (reg.X_op == O_constant && reg.X_add_number == 0)
2071 {
2072 if (!(ins_ok & INS_Z80N))
2073 check_mach (INS_OUT_C_0);
2074 reg.X_op = O_register;
2075 reg.X_add_number = 6;
2076 }
2077 if (reg.X_md
2078 || reg.X_op != O_register
2079 || reg.X_add_number > 7)
2080 ill_op ();
2081 else
2082 if (port.X_op != O_register && port.X_op != O_md1)
2083 {
2084 if (REG_A == reg.X_add_number)
2085 {
2086 q = frag_more (1);
2087 *q = 0xD3;
2088 emit_byte (&port, BFD_RELOC_8);
2089 }
2090 else
2091 ill_op ();
2092 }
2093 else
2094 {
2095 if (REG_C == port.X_add_number || port.X_add_number == REG_BC)
2096 {
2097 if (port.X_add_number == REG_BC && !(ins_ok & INS_EZ80))
2098 ill_op ();
2099 q = frag_more (2);
2100 *q++ = 0xED;
2101 *q = 0x41 | (reg.X_add_number << 3);
2102 }
2103 else
2104 ill_op ();
2105 }
2106 return p;
2107 }
2108
2109 static const char *
2110 emit_out0 (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
2111 const char * args)
2112 {
2113 expressionS reg, port;
2114 const char *p;
2115 char *q;
2116
2117 p = parse_exp (args, & port);
2118 if (*p++ != ',')
2119 {
2120 error (_("bad instruction syntax"));
2121 return p;
2122 }
2123 p = parse_exp (p, &reg);
2124 if (port.X_md != 0
2125 && port.X_op != O_register
2126 && port.X_op != O_md1
2127 && reg.X_md == 0
2128 && reg.X_op == O_register
2129 && reg.X_add_number <= 7)
2130 {
2131 q = frag_more (2);
2132 *q++ = 0xED;
2133 *q = 0x01 | (reg.X_add_number << 3);
2134 emit_byte (&port, BFD_RELOC_8);
2135 }
2136 else
2137 ill_op ();
2138 return p;
2139 }
2140
2141 static const char *
2142 emit_rst (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
2143 {
2144 expressionS addr;
2145 const char *p;
2146 char *q;
2147
2148 p = parse_exp_not_indexed (args, &addr);
2149 if (addr.X_op != O_constant)
2150 {
2151 error ("rst needs constant address");
2152 return p;
2153 }
2154
2155 if (addr.X_add_number & ~(7 << 3))
2156 ill_op ();
2157 else
2158 {
2159 q = frag_more (1);
2160 *q = opcode + (addr.X_add_number & (7 << 3));
2161 }
2162 return p;
2163 }
2164
2165 /* For 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n. */
2166 static void
2167 emit_ld_m_n (expressionS *dst, expressionS *src)
2168 {
2169 char *q;
2170 char prefix;
2171 expressionS dst_offset;
2172
2173 switch (dst->X_add_number)
2174 {
2175 case REG_HL: prefix = 0x00; break;
2176 case REG_IX: prefix = 0xDD; break;
2177 case REG_IY: prefix = 0xFD; break;
2178 default:
2179 ill_op ();
2180 return;
2181 }
2182
2183 q = frag_more (prefix ? 2 : 1);
2184 if (prefix)
2185 *q++ = prefix;
2186 *q = 0x36;
2187 if (prefix)
2188 {
2189 dst_offset = *dst;
2190 dst_offset.X_op = O_symbol;
2191 dst_offset.X_add_number = 0;
2192 emit_byte (& dst_offset, BFD_RELOC_Z80_DISP8);
2193 }
2194 emit_byte (src, BFD_RELOC_8);
2195 }
2196
2197 /* For 8-bit load register to memory instructions: LD (<expression>),r. */
2198 static void
2199 emit_ld_m_r (expressionS *dst, expressionS *src)
2200 {
2201 char *q;
2202 char prefix = 0;
2203 expressionS dst_offset;
2204
2205 switch (dst->X_op)
2206 {
2207 case O_md1:
2208 if (ins_ok & INS_GBZ80)
2209 { /* LD (HL+),A or LD (HL-),A */
2210 if (src->X_op != O_register || src->X_add_number != REG_A)
2211 break;
2212 *frag_more (1) = (dst->X_add_number == REG_HL) ? 0x22 : 0x32;
2213 return;
2214 }
2215 else
2216 prefix = (dst->X_add_number == REG_IX) ? 0xDD : 0xFD;
2217 /* Fall through. */
2218 case O_register:
2219 switch (dst->X_add_number)
2220 {
2221 case REG_BC: /* LD (BC),A */
2222 case REG_DE: /* LD (DE),A */
2223 if (src->X_add_number == REG_A)
2224 {
2225 q = frag_more (1);
2226 *q = 0x02 | ((dst->X_add_number & 3) << 4);
2227 return;
2228 }
2229 break;
2230 case REG_IX:
2231 case REG_IY:
2232 case REG_HL: /* LD (HL),r or LD (ii+d),r */
2233 if (src->X_add_number <= 7)
2234 {
2235 q = frag_more (prefix ? 2 : 1);
2236 if (prefix)
2237 *q++ = prefix;
2238 *q = 0x70 | src->X_add_number;
2239 if (prefix)
2240 {
2241 dst_offset = *dst;
2242 dst_offset.X_op = O_symbol;
2243 dst_offset.X_add_number = 0;
2244 emit_byte (& dst_offset, BFD_RELOC_Z80_DISP8);
2245 }
2246 return;
2247 }
2248 break;
2249 default:;
2250 }
2251 break;
2252 default: /* LD (nn),A */
2253 if (src->X_add_number == REG_A)
2254 {
2255 q = frag_more (1);
2256 *q = (ins_ok & INS_GBZ80) ? 0xEA : 0x32;
2257 emit_word (dst);
2258 return;
2259 }
2260 break;
2261 }
2262 ill_op ();
2263 }
2264
2265 /* For 16-bit load register to memory instructions: LD (<expression>),rr. */
2266 static void
2267 emit_ld_m_rr (expressionS *dst, expressionS *src)
2268 {
2269 char *q;
2270 int prefix = 0;
2271 int opcode = 0;
2272 expressionS dst_offset;
2273
2274 switch (dst->X_op)
2275 {
2276 case O_md1: /* eZ80 instructions LD (ii+d),rr */
2277 case O_register: /* eZ80 instructions LD (HL),rr */
2278 if (!(ins_ok & INS_EZ80)) /* 16-bit indirect load group is supported by eZ80 only */
2279 ill_op ();
2280 switch (dst->X_add_number)
2281 {
2282 case REG_IX: prefix = 0xDD; break;
2283 case REG_IY: prefix = 0xFD; break;
2284 case REG_HL: prefix = 0xED; break;
2285 default:
2286 ill_op ();
2287 }
2288 switch (src->X_add_number)
2289 {
2290 case REG_BC: opcode = 0x0F; break;
2291 case REG_DE: opcode = 0x1F; break;
2292 case REG_HL: opcode = 0x2F; break;
2293 case REG_IX: opcode = (prefix != 0xFD) ? 0x3F : 0x3E; break;
2294 case REG_IY: opcode = (prefix != 0xFD) ? 0x3E : 0x3F; break;
2295 default:
2296 ill_op ();
2297 }
2298 q = frag_more (prefix ? 2 : 1);
2299 *q++ = prefix;
2300 *q = opcode;
2301 if (prefix == 0xFD || prefix == 0xDD)
2302 {
2303 dst_offset = *dst;
2304 dst_offset.X_op = O_symbol;
2305 dst_offset.X_add_number = 0;
2306 emit_byte (& dst_offset, BFD_RELOC_Z80_DISP8);
2307 }
2308 break;
2309 default: /* LD (nn),rr */
2310 if (ins_ok & INS_GBZ80)
2311 {
2312 /* GBZ80 supports only LD (nn),SP */
2313 if (src->X_add_number == REG_SP)
2314 {
2315 prefix = 0x00;
2316 opcode = 0x08;
2317 }
2318 else
2319 ill_op ();
2320 }
2321 else
2322 {
2323 switch (src->X_add_number)
2324 {
2325 case REG_BC: prefix = 0xED; opcode = 0x43; break;
2326 case REG_DE: prefix = 0xED; opcode = 0x53; break;
2327 case REG_HL: prefix = 0x00; opcode = 0x22; break;
2328 case REG_IX: prefix = 0xDD; opcode = 0x22; break;
2329 case REG_IY: prefix = 0xFD; opcode = 0x22; break;
2330 case REG_SP: prefix = 0xED; opcode = 0x73; break;
2331 default:
2332 ill_op ();
2333 }
2334 }
2335 q = frag_more (prefix ? 2 : 1);
2336 if (prefix)
2337 *q++ = prefix;
2338 *q = opcode;
2339 emit_word (dst);
2340 }
2341 }
2342
2343 static void
2344 emit_ld_r_m (expressionS *dst, expressionS *src)
2345 { /* for 8-bit memory load to register: LD r,(xxx) */
2346 char *q;
2347 char prefix = 0;
2348 char opcode = 0;
2349 expressionS src_offset;
2350
2351 if (dst->X_add_number == REG_A && src->X_op == O_register)
2352 { /* LD A,(BC) or LD A,(DE) */
2353 switch (src->X_add_number)
2354 {
2355 case REG_BC: opcode = 0x0A; break;
2356 case REG_DE: opcode = 0x1A; break;
2357 default: break;
2358 }
2359 if (opcode != 0)
2360 {
2361 q = frag_more (1);
2362 *q = opcode;
2363 return;
2364 }
2365 }
2366
2367 switch (src->X_op)
2368 {
2369 case O_md1:
2370 if (ins_ok & INS_GBZ80)
2371 { /* LD A,(HL+) or LD A,(HL-) */
2372 if (dst->X_op == O_register && dst->X_add_number == REG_A)
2373 *frag_more (1) = (src->X_add_number == REG_HL) ? 0x2A : 0x3A;
2374 else
2375 ill_op ();
2376 break;
2377 }
2378 /* Fall through. */
2379 case O_register:
2380 if (dst->X_add_number > 7)
2381 ill_op ();
2382 opcode = 0x46; /* LD B,(HL) */
2383 switch (src->X_add_number)
2384 {
2385 case REG_HL: prefix = 0x00; break;
2386 case REG_IX: prefix = 0xDD; break;
2387 case REG_IY: prefix = 0xFD; break;
2388 default:
2389 ill_op ();
2390 }
2391 q = frag_more (prefix ? 2 : 1);
2392 if (prefix)
2393 *q++ = prefix;
2394 *q = opcode | ((dst->X_add_number & 7) << 3);
2395 if (prefix)
2396 {
2397 src_offset = *src;
2398 src_offset.X_op = O_symbol;
2399 src_offset.X_add_number = 0;
2400 emit_byte (& src_offset, BFD_RELOC_Z80_DISP8);
2401 }
2402 break;
2403 default: /* LD A,(nn) */
2404 if (dst->X_add_number == REG_A)
2405 {
2406 q = frag_more (1);
2407 *q = (ins_ok & INS_GBZ80) ? 0xFA : 0x3A;
2408 emit_word (src);
2409 }
2410 else
2411 ill_op ();
2412 }
2413 }
2414
2415 static void
2416 emit_ld_r_n (expressionS *dst, expressionS *src)
2417 { /* for 8-bit immediate value load to register: LD r,n */
2418 char *q;
2419 char prefix = 0;
2420
2421 switch (dst->X_add_number)
2422 {
2423 case REG_H|R_IX:
2424 case REG_L|R_IX:
2425 prefix = 0xDD;
2426 break;
2427 case REG_H|R_IY:
2428 case REG_L|R_IY:
2429 prefix = 0xFD;
2430 break;
2431 case REG_A:
2432 case REG_B:
2433 case REG_C:
2434 case REG_D:
2435 case REG_E:
2436 case REG_H:
2437 case REG_L:
2438 break;
2439 default:
2440 ill_op ();
2441 }
2442
2443 q = frag_more (prefix ? 2 : 1);
2444 if (prefix)
2445 {
2446 if (ins_ok & INS_GBZ80)
2447 ill_op ();
2448 else if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N)))
2449 check_mach (INS_IDX_HALF);
2450 *q++ = prefix;
2451 }
2452 *q = 0x06 | ((dst->X_add_number & 7) << 3);
2453 emit_byte (src, BFD_RELOC_8);
2454 }
2455
2456 static void
2457 emit_ld_r_r (expressionS *dst, expressionS *src)
2458 { /* mostly 8-bit load register from register instructions: LD r,r */
2459 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */
2460 char *q;
2461 int prefix = 0;
2462 int opcode = 0;
2463 int ii_halves = 0;
2464
2465 switch (dst->X_add_number)
2466 {
2467 case REG_SP:
2468 switch (src->X_add_number)
2469 {
2470 case REG_HL: prefix = 0x00; break;
2471 case REG_IX: prefix = 0xDD; break;
2472 case REG_IY: prefix = 0xFD; break;
2473 default:
2474 ill_op ();
2475 }
2476 opcode = 0xF9;
2477 break;
2478 case REG_HL:
2479 if (!(ins_ok & INS_EZ80))
2480 ill_op ();
2481 if (src->X_add_number != REG_I)
2482 ill_op ();
2483 if (cpu_mode < 1)
2484 error (_("ADL mode instruction"));
2485 /* LD HL,I */
2486 prefix = 0xED;
2487 opcode = 0xD7;
2488 break;
2489 case REG_I:
2490 if (src->X_add_number == REG_HL)
2491 {
2492 if (!(ins_ok & INS_EZ80))
2493 ill_op ();
2494 if (cpu_mode < 1)
2495 error (_("ADL mode instruction"));
2496 prefix = 0xED;
2497 opcode = 0xC7;
2498 }
2499 else if (src->X_add_number == REG_A)
2500 {
2501 prefix = 0xED;
2502 opcode = 0x47;
2503 }
2504 else
2505 ill_op ();
2506 break;
2507 case REG_MB:
2508 if (!(ins_ok & INS_EZ80) || (src->X_add_number != REG_A))
2509 ill_op ();
2510 if (cpu_mode < 1)
2511 error (_("ADL mode instruction"));
2512 prefix = 0xED;
2513 opcode = 0x6D;
2514 break;
2515 case REG_R:
2516 if (src->X_add_number == REG_A) /* LD R,A */
2517 {
2518 prefix = 0xED;
2519 opcode = 0x4F;
2520 }
2521 else
2522 ill_op ();
2523 break;
2524 case REG_A:
2525 if (src->X_add_number == REG_I) /* LD A,I */
2526 {
2527 prefix = 0xED;
2528 opcode = 0x57;
2529 break;
2530 }
2531 else if (src->X_add_number == REG_R) /* LD A,R */
2532 {
2533 prefix = 0xED;
2534 opcode = 0x5F;
2535 break;
2536 }
2537 else if (src->X_add_number == REG_MB) /* LD A,MB */
2538 {
2539 if (!(ins_ok & INS_EZ80))
2540 ill_op ();
2541 else
2542 {
2543 if (cpu_mode < 1)
2544 error (_("ADL mode instruction"));
2545 prefix = 0xED;
2546 opcode = 0x6E;
2547 }
2548 break;
2549 }
2550 /* Fall through. */
2551 case REG_B:
2552 case REG_C:
2553 case REG_D:
2554 case REG_E:
2555 case REG_H:
2556 case REG_L:
2557 prefix = 0x00;
2558 break;
2559 case REG_H|R_IX:
2560 case REG_L|R_IX:
2561 prefix = 0xDD;
2562 ii_halves = 1;
2563 break;
2564 case REG_H|R_IY:
2565 case REG_L|R_IY:
2566 prefix = 0xFD;
2567 ii_halves = 1;
2568 break;
2569 default:
2570 ill_op ();
2571 }
2572
2573 if (opcode == 0)
2574 {
2575 switch (src->X_add_number)
2576 {
2577 case REG_A:
2578 case REG_B:
2579 case REG_C:
2580 case REG_D:
2581 case REG_E:
2582 break;
2583 case REG_H:
2584 case REG_L:
2585 if (prefix != 0)
2586 ill_op (); /* LD iiH/L,H/L are not permitted */
2587 break;
2588 case REG_H|R_IX:
2589 case REG_L|R_IX:
2590 if (prefix == 0xFD || dst->X_add_number == REG_H || dst->X_add_number == REG_L)
2591 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */
2592 prefix = 0xDD;
2593 ii_halves = 1;
2594 break;
2595 case REG_H|R_IY:
2596 case REG_L|R_IY:
2597 if (prefix == 0xDD || dst->X_add_number == REG_H || dst->X_add_number == REG_L)
2598 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */
2599 prefix = 0xFD;
2600 ii_halves = 1;
2601 break;
2602 default:
2603 ill_op ();
2604 }
2605 opcode = 0x40 + ((dst->X_add_number & 7) << 3) + (src->X_add_number & 7);
2606 }
2607 if ((ins_ok & INS_GBZ80) && prefix != 0)
2608 ill_op ();
2609 if (ii_halves && !(ins_ok & (INS_EZ80|INS_R800|INS_Z80N)))
2610 check_mach (INS_IDX_HALF);
2611 if (prefix == 0 && (ins_ok & INS_EZ80))
2612 {
2613 switch (opcode)
2614 {
2615 case 0x40: /* SIS prefix, in Z80 it is LD B,B */
2616 case 0x49: /* LIS prefix, in Z80 it is LD C,C */
2617 case 0x52: /* SIL prefix, in Z80 it is LD D,D */
2618 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */
2619 as_warn (_("unsupported instruction, assembled as NOP"));
2620 opcode = 0x00;
2621 break;
2622 default:;
2623 }
2624 }
2625 q = frag_more (prefix ? 2 : 1);
2626 if (prefix)
2627 *q++ = prefix;
2628 *q = opcode;
2629 }
2630
2631 static void
2632 emit_ld_rr_m (expressionS *dst, expressionS *src)
2633 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */
2634 char *q;
2635 int prefix = 0;
2636 int opcode = 0;
2637 expressionS src_offset;
2638
2639 /* GBZ80 has no support for 16-bit load from memory instructions */
2640 if (ins_ok & INS_GBZ80)
2641 ill_op ();
2642
2643 prefix = 0xED;
2644 switch (src->X_op)
2645 {
2646 case O_md1: /* LD rr,(ii+d) */
2647 prefix = (src->X_add_number == REG_IX) ? 0xDD : 0xFD;
2648 /* Fall through. */
2649 case O_register: /* LD rr,(HL) */
2650 /* currently only EZ80 has support for 16bit indirect memory load instructions */
2651 if (!(ins_ok & INS_EZ80))
2652 ill_op ();
2653 switch (dst->X_add_number)
2654 {
2655 case REG_BC: opcode = 0x07; break;
2656 case REG_DE: opcode = 0x17; break;
2657 case REG_HL: opcode = 0x27; break;
2658 case REG_IX: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x37 : 0x31; break;
2659 case REG_IY: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x31 : 0x37; break;
2660 default:
2661 ill_op ();
2662 }
2663 q = frag_more (2);
2664 *q++ = prefix;
2665 *q = opcode;
2666 if (prefix != 0xED)
2667 {
2668 src_offset = *src;
2669 src_offset.X_op = O_symbol;
2670 src_offset.X_add_number = 0;
2671 emit_byte (& src_offset, BFD_RELOC_Z80_DISP8);
2672 }
2673 break;
2674 default: /* LD rr,(nn) */
2675 switch (dst->X_add_number)
2676 {
2677 case REG_BC: prefix = 0xED; opcode = 0x4B; break;
2678 case REG_DE: prefix = 0xED; opcode = 0x5B; break;
2679 case REG_HL: prefix = 0x00; opcode = 0x2A; break;
2680 case REG_SP: prefix = 0xED; opcode = 0x7B; break;
2681 case REG_IX: prefix = 0xDD; opcode = 0x2A; break;
2682 case REG_IY: prefix = 0xFD; opcode = 0x2A; break;
2683 default:
2684 ill_op ();
2685 }
2686 q = frag_more (prefix ? 2 : 1);
2687 if (prefix)
2688 *q++ = prefix;
2689 *q = opcode;
2690 emit_word (src);
2691 }
2692 return;
2693 }
2694
2695 static void
2696 emit_ld_rr_nn (expressionS *dst, expressionS *src)
2697 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */
2698 char *q;
2699 int prefix = 0x00;
2700 int opcode = 0x21; /* LD HL,nn */
2701 switch (dst->X_add_number)
2702 {
2703 case REG_IX:
2704 prefix = 0xDD;
2705 break;
2706 case REG_IY:
2707 prefix = 0xFD;
2708 break;
2709 case REG_HL:
2710 break;
2711 case REG_BC:
2712 case REG_DE:
2713 case REG_SP:
2714 opcode = 0x01 + ((dst->X_add_number & 3) << 4);
2715 break;
2716 default:
2717 ill_op ();
2718 return;
2719 }
2720 if (prefix && (ins_ok & INS_GBZ80))
2721 ill_op ();
2722 q = frag_more (prefix ? 2 : 1);
2723 if (prefix)
2724 *q++ = prefix;
2725 *q = opcode;
2726 emit_word (src);
2727 }
2728
2729 static const char *
2730 emit_ld (char prefix_in ATTRIBUTE_UNUSED, char opcode_in ATTRIBUTE_UNUSED,
2731 const char * args)
2732 {
2733 expressionS dst, src;
2734 const char *p;
2735
2736 p = parse_exp (args, & dst);
2737 if (*p++ != ',')
2738 error (_("bad instruction syntax"));
2739 p = parse_exp (p, & src);
2740
2741 if (dst.X_md)
2742 {
2743 if (src.X_op == O_register)
2744 {
2745 if (src.X_add_number <= 7)
2746 emit_ld_m_r (& dst, & src); /* LD (xxx),r */
2747 else
2748 emit_ld_m_rr (& dst, & src); /* LD (xxx),rr */
2749 }
2750 else
2751 emit_ld_m_n (& dst, & src); /* LD (hl),n or LD (ix/y+r),n */
2752 }
2753 else if (dst.X_op == O_register)
2754 {
2755 if (src.X_md)
2756 {
2757 if (dst.X_add_number <= 7)
2758 emit_ld_r_m (& dst, & src);
2759 else
2760 emit_ld_rr_m (& dst, & src);
2761 }
2762 else if (src.X_op == O_register)
2763 emit_ld_r_r (& dst, & src);
2764 else if ((dst.X_add_number & ~R_INDEX) <= 7)
2765 emit_ld_r_n (& dst, & src);
2766 else
2767 emit_ld_rr_nn (& dst, & src);
2768 }
2769 else
2770 ill_op ();
2771
2772 return p;
2773 }
2774
2775 static const char *
2776 emit_lddldi (char prefix, char opcode, const char * args)
2777 {
2778 expressionS dst, src;
2779 const char *p;
2780 char *q;
2781
2782 if (!(ins_ok & INS_GBZ80))
2783 return emit_insn (prefix, opcode, args);
2784
2785 p = parse_exp (args, & dst);
2786 if (*p++ != ',')
2787 error (_("bad instruction syntax"));
2788 p = parse_exp (p, & src);
2789
2790 if (dst.X_op != O_register || src.X_op != O_register)
2791 ill_op ();
2792
2793 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */
2794 opcode = (opcode & 0x08) * 2 + 0x22;
2795
2796 if (dst.X_md != 0
2797 && dst.X_add_number == REG_HL
2798 && src.X_md == 0
2799 && src.X_add_number == REG_A)
2800 opcode |= 0x00; /* LDx (HL),A */
2801 else if (dst.X_md == 0
2802 && dst.X_add_number == REG_A
2803 && src.X_md != 0
2804 && src.X_add_number == REG_HL)
2805 opcode |= 0x08; /* LDx A,(HL) */
2806 else
2807 ill_op ();
2808
2809 q = frag_more (1);
2810 *q = opcode;
2811 return p;
2812 }
2813
2814 static const char *
2815 emit_ldh (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
2816 const char * args)
2817 {
2818 expressionS dst, src;
2819 const char *p;
2820 char *q;
2821
2822 p = parse_exp (args, & dst);
2823 if (*p++ != ',')
2824 {
2825 error (_("bad instruction syntax"));
2826 return p;
2827 }
2828
2829 p = parse_exp (p, & src);
2830 if (dst.X_md == 0
2831 && dst.X_op == O_register
2832 && dst.X_add_number == REG_A
2833 && src.X_md != 0
2834 && src.X_op != O_md1)
2835 {
2836 if (src.X_op != O_register)
2837 {
2838 q = frag_more (1);
2839 *q = 0xF0;
2840 emit_byte (& src, BFD_RELOC_8);
2841 }
2842 else if (src.X_add_number == REG_C)
2843 *frag_more (1) = 0xF2;
2844 else
2845 ill_op ();
2846 }
2847 else if (dst.X_md != 0
2848 && dst.X_op != O_md1
2849 && src.X_md == 0
2850 && src.X_op == O_register
2851 && src.X_add_number == REG_A)
2852 {
2853 if (dst.X_op == O_register)
2854 {
2855 if (dst.X_add_number == REG_C)
2856 {
2857 q = frag_more (1);
2858 *q = 0xE2;
2859 }
2860 else
2861 ill_op ();
2862 }
2863 else
2864 {
2865 q = frag_more (1);
2866 *q = 0xE0;
2867 emit_byte (& dst, BFD_RELOC_8);
2868 }
2869 }
2870 else
2871 ill_op ();
2872
2873 return p;
2874 }
2875
2876 static const char *
2877 emit_ldhl (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
2878 {
2879 expressionS dst, src;
2880 const char *p;
2881 char *q;
2882 p = parse_exp (args, & dst);
2883 if (*p++ != ',')
2884 {
2885 error (_("bad instruction syntax"));
2886 return p;
2887 }
2888
2889 p = parse_exp (p, & src);
2890 if (dst.X_md || dst.X_op != O_register || dst.X_add_number != REG_SP
2891 || src.X_md || src.X_op == O_register || src.X_op == O_md1)
2892 ill_op ();
2893 q = frag_more (1);
2894 *q = opcode;
2895 emit_byte (& src, BFD_RELOC_Z80_DISP8);
2896 return p;
2897 }
2898
2899 static const char *
2900 parse_lea_pea_args (const char * args, expressionS *op)
2901 {
2902 const char *p;
2903 p = parse_exp (args, op);
2904 if (sdcc_compat && *p == ',' && op->X_op == O_register)
2905 {
2906 expressionS off;
2907 p = parse_exp (p + 1, &off);
2908 op->X_op = O_add;
2909 op->X_add_symbol = make_expr_symbol (&off);
2910 }
2911 return p;
2912 }
2913
2914 static const char *
2915 emit_lea (char prefix, char opcode, const char * args)
2916 {
2917 expressionS dst, src;
2918 const char *p;
2919 char *q;
2920 int rnum;
2921
2922 p = parse_exp (args, & dst);
2923 if (dst.X_md != 0 || dst.X_op != O_register)
2924 ill_op ();
2925
2926 rnum = dst.X_add_number;
2927 switch (rnum)
2928 {
2929 case REG_BC:
2930 case REG_DE:
2931 case REG_HL:
2932 opcode = 0x02 | ((rnum & 0x03) << 4);
2933 break;
2934 case REG_IX:
2935 opcode = 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */
2936 break;
2937 case REG_IY:
2938 opcode = 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */
2939 break;
2940 default:
2941 ill_op ();
2942 }
2943
2944 if (*p++ != ',')
2945 error (_("bad instruction syntax"));
2946
2947 p = parse_lea_pea_args (p, & src);
2948 if (src.X_md != 0 || src.X_op != O_add /*&& src.X_op != O_register*/)
2949 ill_op ();
2950
2951 rnum = src.X_add_number;
2952 switch (src.X_op)
2953 {
2954 case O_add:
2955 break;
2956 case O_register: /* permit instructions like LEA rr,IX without displacement specified */
2957 src.X_add_symbol = zero;
2958 break;
2959 default:
2960 ill_op ();
2961 }
2962
2963 switch (rnum)
2964 {
2965 case REG_IX:
2966 opcode = (opcode == (char)0x33) ? 0x55 : (opcode|0x00);
2967 break;
2968 case REG_IY:
2969 opcode = (opcode == (char)0x32) ? 0x54 : (opcode|0x01);
2970 }
2971
2972 q = frag_more (2);
2973 *q++ = prefix;
2974 *q = opcode;
2975
2976 src.X_op = O_symbol;
2977 src.X_add_number = 0;
2978 emit_byte (& src, BFD_RELOC_Z80_DISP8);
2979
2980 return p;
2981 }
2982
2983 static const char *
2984 emit_mlt (char prefix, char opcode, const char * args)
2985 {
2986 expressionS arg;
2987 const char *p;
2988 char *q;
2989
2990 p = parse_exp (args, & arg);
2991 if (arg.X_md != 0 || arg.X_op != O_register || !(arg.X_add_number & R_ARITH))
2992 ill_op ();
2993
2994 q = frag_more (2);
2995 if (ins_ok & INS_Z80N)
2996 {
2997 if (arg.X_add_number != REG_DE)
2998 ill_op ();
2999 *q++ = 0xED;
3000 *q = 0x30;
3001 }
3002 else
3003 {
3004 *q++ = prefix;
3005 *q = opcode | ((arg.X_add_number & 3) << 4);
3006 }
3007
3008 return p;
3009 }
3010
3011 /* MUL D,E (Z80N only) */
3012 static const char *
3013 emit_mul (char prefix, char opcode, const char * args)
3014 {
3015 expressionS r1, r2;
3016 const char *p;
3017 char *q;
3018
3019 p = parse_exp (args, & r1);
3020 if (*p++ != ',')
3021 error (_("bad instruction syntax"));
3022 p = parse_exp (p, & r2);
3023
3024 if (r1.X_md != 0 || r1.X_op != O_register || r1.X_add_number != REG_D ||
3025 r2.X_md != 0 || r2.X_op != O_register || r2.X_add_number != REG_E)
3026 ill_op ();
3027
3028 q = frag_more (2);
3029 *q++ = prefix;
3030 *q = opcode;
3031
3032 return p;
3033 }
3034
3035 static const char *
3036 emit_nextreg (char prefix, char opcode ATTRIBUTE_UNUSED, const char * args)
3037 {
3038 expressionS rr, nn;
3039 const char *p;
3040 char *q;
3041
3042 p = parse_exp (args, & rr);
3043 if (*p++ != ',')
3044 error (_("bad instruction syntax"));
3045 p = parse_exp (p, & nn);
3046 if (rr.X_md != 0 || rr.X_op == O_register || rr.X_op == O_md1 ||
3047 nn.X_md != 0 || nn.X_op == O_md1)
3048 ill_op ();
3049 q = frag_more (2);
3050 *q++ = prefix;
3051 emit_byte (&rr, BFD_RELOC_8);
3052 if (nn.X_op == O_register && nn.X_add_number == REG_A)
3053 *q = 0x92;
3054 else if (nn.X_op != O_register)
3055 {
3056 *q = 0x91;
3057 emit_byte (&nn, BFD_RELOC_8);
3058 }
3059 else
3060 ill_op ();
3061 return p;
3062 }
3063
3064 static const char *
3065 emit_pea (char prefix, char opcode, const char * args)
3066 {
3067 expressionS arg;
3068 const char *p;
3069 char *q;
3070
3071 p = parse_lea_pea_args (args, & arg);
3072 if (arg.X_md != 0
3073 || (/*arg.X_op != O_register &&*/ arg.X_op != O_add)
3074 || !(arg.X_add_number & R_INDEX))
3075 ill_op ();
3076 /* PEA ii without displacement is mostly typo,
3077 because there is PUSH instruction which is shorter and faster */
3078 /*if (arg.X_op == O_register)
3079 as_warn (_("PEA is used without displacement, use PUSH instead"));*/
3080
3081 q = frag_more (2);
3082 *q++ = prefix;
3083 *q = opcode + (arg.X_add_number == REG_IY ? 1 : 0);
3084
3085 arg.X_op = O_symbol;
3086 arg.X_add_number = 0;
3087 emit_byte (& arg, BFD_RELOC_Z80_DISP8);
3088
3089 return p;
3090 }
3091
3092 static const char *
3093 emit_reti (char prefix, char opcode, const char * args)
3094 {
3095 if (ins_ok & INS_GBZ80)
3096 return emit_insn (0x00, 0xD9, args);
3097
3098 return emit_insn (prefix, opcode, args);
3099 }
3100
3101 static const char *
3102 emit_tst (char prefix, char opcode, const char *args)
3103 {
3104 expressionS arg_s;
3105 const char *p;
3106 char *q;
3107 int rnum;
3108
3109 p = parse_exp (args, & arg_s);
3110 if (*p == ',' && arg_s.X_md == 0 && arg_s.X_op == O_register && arg_s.X_add_number == REG_A)
3111 {
3112 if (!(ins_ok & INS_EZ80))
3113 ill_op ();
3114 ++p;
3115 p = parse_exp (p, & arg_s);
3116 }
3117
3118 rnum = arg_s.X_add_number;
3119 switch (arg_s.X_op)
3120 {
3121 case O_md1:
3122 ill_op ();
3123 break;
3124 case O_register:
3125 rnum = arg_s.X_add_number;
3126 if (arg_s.X_md != 0)
3127 {
3128 if (rnum != REG_HL)
3129 ill_op ();
3130 else
3131 rnum = 6;
3132 }
3133 q = frag_more (2);
3134 *q++ = prefix;
3135 *q = opcode | (rnum << 3);
3136 break;
3137 default:
3138 if (arg_s.X_md)
3139 ill_op ();
3140 q = frag_more (2);
3141 if (ins_ok & INS_Z80N)
3142 {
3143 *q++ = 0xED;
3144 *q = 0x27;
3145 }
3146 else
3147 {
3148 *q++ = prefix;
3149 *q = opcode | 0x60;
3150 }
3151 emit_byte (& arg_s, BFD_RELOC_8);
3152 }
3153 return p;
3154 }
3155
3156 static const char *
3157 emit_insn_n (char prefix, char opcode, const char *args)
3158 {
3159 expressionS arg;
3160 const char *p;
3161 char *q;
3162
3163 p = parse_exp (args, & arg);
3164 if (arg.X_md || arg.X_op == O_register || arg.X_op == O_md1)
3165 ill_op ();
3166
3167 q = frag_more (2);
3168 *q++ = prefix;
3169 *q = opcode;
3170 emit_byte (& arg, BFD_RELOC_8);
3171
3172 return p;
3173 }
3174
3175 static void
3176 emit_data (int size ATTRIBUTE_UNUSED)
3177 {
3178 const char *p, *q;
3179 char *u, quote;
3180 int cnt;
3181 expressionS exp;
3182
3183 if (is_it_end_of_statement ())
3184 {
3185 demand_empty_rest_of_line ();
3186 return;
3187 }
3188 p = skip_space (input_line_pointer);
3189
3190 do
3191 {
3192 if (*p == '\"' || *p == '\'')
3193 {
3194 for (quote = *p, q = ++p, cnt = 0; *p && quote != *p; ++p, ++cnt)
3195 ;
3196 u = frag_more (cnt);
3197 memcpy (u, q, cnt);
3198 if (!*p)
3199 as_warn (_("unterminated string"));
3200 else
3201 p = skip_space (p+1);
3202 }
3203 else
3204 {
3205 p = parse_exp (p, &exp);
3206 if (exp.X_op == O_md1 || exp.X_op == O_register)
3207 {
3208 ill_op ();
3209 break;
3210 }
3211 if (exp.X_md)
3212 as_warn (_("parentheses ignored"));
3213 emit_byte (&exp, BFD_RELOC_8);
3214 p = skip_space (p);
3215 }
3216 }
3217 while (*p++ == ',') ;
3218 input_line_pointer = (char *)(p-1);
3219 }
3220
3221 static void
3222 z80_cons (int size)
3223 {
3224 const char *p;
3225 expressionS exp;
3226
3227 if (is_it_end_of_statement ())
3228 {
3229 demand_empty_rest_of_line ();
3230 return;
3231 }
3232 p = skip_space (input_line_pointer);
3233
3234 do
3235 {
3236 p = parse_exp (p, &exp);
3237 if (exp.X_op == O_md1 || exp.X_op == O_register)
3238 {
3239 ill_op ();
3240 break;
3241 }
3242 if (exp.X_md)
3243 as_warn (_("parentheses ignored"));
3244 emit_data_val (&exp, size);
3245 p = skip_space (p);
3246 } while (*p++ == ',') ;
3247 input_line_pointer = (char *)(p-1);
3248 }
3249
3250 /* next functions were commented out because it is difficult to mix
3251 both ADL and Z80 mode instructions within one COFF file:
3252 objdump cannot recognize point of mode switching.
3253 */
3254 static void
3255 set_cpu_mode (int mode)
3256 {
3257 if (ins_ok & INS_EZ80)
3258 cpu_mode = mode;
3259 else
3260 error (_("CPU mode is unsupported by target"));
3261 }
3262
3263 static void
3264 assume (int arg ATTRIBUTE_UNUSED)
3265 {
3266 char *name;
3267 char c;
3268 int n;
3269
3270 input_line_pointer = (char*)skip_space (input_line_pointer);
3271 c = get_symbol_name (& name);
3272 if (strncasecmp (name, "ADL", 4) != 0)
3273 {
3274 ill_op ();
3275 return;
3276 }
3277
3278 restore_line_pointer (c);
3279 input_line_pointer = (char*)skip_space (input_line_pointer);
3280 if (*input_line_pointer++ != '=')
3281 {
3282 error (_("assignment expected"));
3283 return;
3284 }
3285 input_line_pointer = (char*)skip_space (input_line_pointer);
3286 n = get_single_number ();
3287
3288 set_cpu_mode (n);
3289 }
3290
3291 static const char *
3292 emit_mulub (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
3293 {
3294 const char *p;
3295
3296 p = skip_space (args);
3297 if (TOLOWER (*p++) != 'a' || *p++ != ',')
3298 ill_op ();
3299 else
3300 {
3301 char *q, reg;
3302
3303 reg = TOLOWER (*p++);
3304 switch (reg)
3305 {
3306 case 'b':
3307 case 'c':
3308 case 'd':
3309 case 'e':
3310 check_mach (INS_R800);
3311 if (!*skip_space (p))
3312 {
3313 q = frag_more (2);
3314 *q++ = prefix;
3315 *q = opcode + ((reg - 'b') << 3);
3316 break;
3317 }
3318 /* Fall through. */
3319 default:
3320 ill_op ();
3321 }
3322 }
3323 return p;
3324 }
3325
3326 static const char *
3327 emit_muluw (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
3328 {
3329 const char *p;
3330
3331 p = skip_space (args);
3332 if (TOLOWER (*p++) != 'h' || TOLOWER (*p++) != 'l' || *p++ != ',')
3333 ill_op ();
3334 else
3335 {
3336 expressionS reg;
3337 char *q;
3338
3339 p = parse_exp (p, & reg);
3340
3341 if ((!reg.X_md) && reg.X_op == O_register)
3342 switch (reg.X_add_number)
3343 {
3344 case REG_BC:
3345 case REG_SP:
3346 check_mach (INS_R800);
3347 q = frag_more (2);
3348 *q++ = prefix;
3349 *q = opcode + ((reg.X_add_number & 3) << 4);
3350 break;
3351 default:
3352 ill_op ();
3353 }
3354 }
3355 return p;
3356 }
3357
3358 static int
3359 assemble_suffix (const char **suffix)
3360 {
3361 static
3362 const char sf[8][4] =
3363 {
3364 "il",
3365 "is",
3366 "l",
3367 "lil",
3368 "lis",
3369 "s",
3370 "sil",
3371 "sis"
3372 };
3373 const char *p;
3374 const char (*t)[4];
3375 char sbuf[4];
3376 int i;
3377
3378 p = *suffix;
3379 if (*p++ != '.')
3380 return 0;
3381
3382 for (i = 0; (i < 3) && (ISALPHA (*p)); i++)
3383 sbuf[i] = TOLOWER (*p++);
3384 if (*p && !ISSPACE (*p))
3385 return 0;
3386 *suffix = p;
3387 sbuf[i] = 0;
3388
3389 t = bsearch (sbuf, sf, ARRAY_SIZE (sf), sizeof (sf[0]), (int(*)(const void*, const void*)) strcmp);
3390 if (t == NULL)
3391 return 0;
3392 i = t - sf;
3393 switch (i)
3394 {
3395 case 0: /* IL */
3396 i = cpu_mode ? 0x5B : 0x52;
3397 break;
3398 case 1: /* IS */
3399 i = cpu_mode ? 0x49 : 0x40;
3400 break;
3401 case 2: /* L */
3402 i = cpu_mode ? 0x5B : 0x49;
3403 break;
3404 case 3: /* LIL */
3405 i = 0x5B;
3406 break;
3407 case 4: /* LIS */
3408 i = 0x49;
3409 break;
3410 case 5: /* S */
3411 i = cpu_mode ? 0x52 : 0x40;
3412 break;
3413 case 6: /* SIL */
3414 i = 0x52;
3415 break;
3416 case 7: /* SIS */
3417 i = 0x40;
3418 break;
3419 }
3420 *frag_more (1) = (char)i;
3421 switch (i)
3422 {
3423 case 0x40: inst_mode = INST_MODE_FORCED | INST_MODE_S | INST_MODE_IS; break;
3424 case 0x49: inst_mode = INST_MODE_FORCED | INST_MODE_L | INST_MODE_IS; break;
3425 case 0x52: inst_mode = INST_MODE_FORCED | INST_MODE_S | INST_MODE_IL; break;
3426 case 0x5B: inst_mode = INST_MODE_FORCED | INST_MODE_L | INST_MODE_IL; break;
3427 }
3428 return 1;
3429 }
3430
3431 static void
3432 psect (int arg)
3433 {
3434 #if defined(OBJ_ELF)
3435 return obj_elf_section (arg);
3436 #elif defined(OBJ_COFF)
3437 return obj_coff_section (arg);
3438 #else
3439 #error Unknown object format
3440 #endif
3441 }
3442
3443 static void
3444 set_inss (int inss)
3445 {
3446 int old_ins;
3447
3448 if (!sdcc_compat)
3449 as_fatal (_("Invalid directive"));
3450
3451 old_ins = ins_ok;
3452 ins_ok &= INS_MARCH_MASK;
3453 ins_ok |= inss;
3454 if (old_ins != ins_ok)
3455 cpu_mode = 0;
3456 }
3457
3458 static void
3459 ignore (int arg ATTRIBUTE_UNUSED)
3460 {
3461 ignore_rest_of_line ();
3462 }
3463
3464 static void
3465 area (int arg)
3466 {
3467 char *p;
3468 if (!sdcc_compat)
3469 as_fatal (_("Invalid directive"));
3470 for (p = input_line_pointer; *p && *p != '(' && *p != '\n'; p++)
3471 ;
3472 if (*p == '(')
3473 {
3474 *p = '\n';
3475 psect (arg);
3476 *p++ = '(';
3477 ignore_rest_of_line ();
3478 }
3479 else
3480 psect (arg);
3481 }
3482
3483 /* Handle the .bss pseudo-op. */
3484
3485 static void
3486 s_bss (int ignore ATTRIBUTE_UNUSED)
3487 {
3488 subseg_set (bss_section, 0);
3489 demand_empty_rest_of_line ();
3490 }
3491
3492 /* Port specific pseudo ops. */
3493 const pseudo_typeS md_pseudo_table[] =
3494 {
3495 { ".area", area, 0},
3496 { ".assume", assume, 0},
3497 { ".ez80", set_inss, INS_EZ80},
3498 { ".gbz80", set_inss, INS_GBZ80},
3499 { ".module", ignore, 0},
3500 { ".optsdcc", ignore, 0},
3501 { ".r800", set_inss, INS_R800},
3502 { ".set", s_set, 0},
3503 { ".z180", set_inss, INS_Z180},
3504 { ".hd64", set_inss, INS_Z180},
3505 { ".z80", set_inss, INS_Z80},
3506 { ".z80n", set_inss, INS_Z80N},
3507 { "bss", s_bss, 0},
3508 { "db" , emit_data, 1},
3509 { "d24", z80_cons, 3},
3510 { "d32", z80_cons, 4},
3511 { "def24", z80_cons, 3},
3512 { "def32", z80_cons, 4},
3513 { "defb", emit_data, 1},
3514 { "defm", emit_data, 1},
3515 { "defs", s_space, 1}, /* Synonym for ds on some assemblers. */
3516 { "defw", z80_cons, 2},
3517 { "ds", s_space, 1}, /* Fill with bytes rather than words. */
3518 { "dw", z80_cons, 2},
3519 { "psect", psect, 0}, /* TODO: Translate attributes. */
3520 { "set", 0, 0}, /* Real instruction on z80. */
3521 { "xdef", s_globl, 0}, /* Synonym for .GLOBAL */
3522 { "xref", s_ignore, 0}, /* Synonym for .EXTERN */
3523 { NULL, 0, 0 }
3524 } ;
3525
3526 static table_t instab[] =
3527 {
3528 { "adc", 0x88, 0x4A, emit_adc, INS_ALL },
3529 { "add", 0x80, 0x09, emit_add, INS_ALL },
3530 { "and", 0x00, 0xA0, emit_s, INS_ALL },
3531 { "bit", 0xCB, 0x40, emit_bit, INS_ALL },
3532 { "brlc", 0xED, 0x2C, emit_bshft,INS_Z80N },
3533 { "bsla", 0xED, 0x28, emit_bshft,INS_Z80N },
3534 { "bsra", 0xED, 0x29, emit_bshft,INS_Z80N },
3535 { "bsrf", 0xED, 0x2B, emit_bshft,INS_Z80N },
3536 { "bsrl", 0xED, 0x2A, emit_bshft,INS_Z80N },
3537 { "call", 0xCD, 0xC4, emit_jpcc, INS_ALL },
3538 { "ccf", 0x00, 0x3F, emit_insn, INS_ALL },
3539 { "cp", 0x00, 0xB8, emit_s, INS_ALL },
3540 { "cpd", 0xED, 0xA9, emit_insn, INS_NOT_GBZ80 },
3541 { "cpdr", 0xED, 0xB9, emit_insn, INS_NOT_GBZ80 },
3542 { "cpi", 0xED, 0xA1, emit_insn, INS_NOT_GBZ80 },
3543 { "cpir", 0xED, 0xB1, emit_insn, INS_NOT_GBZ80 },
3544 { "cpl", 0x00, 0x2F, emit_insn, INS_ALL },
3545 { "daa", 0x00, 0x27, emit_insn, INS_ALL },
3546 { "dec", 0x0B, 0x05, emit_incdec,INS_ALL },
3547 { "di", 0x00, 0xF3, emit_insn, INS_ALL },
3548 { "djnz", 0x00, 0x10, emit_jr, INS_NOT_GBZ80 },
3549 { "ei", 0x00, 0xFB, emit_insn, INS_ALL },
3550 { "ex", 0x00, 0x00, emit_ex, INS_NOT_GBZ80 },
3551 { "exx", 0x00, 0xD9, emit_insn, INS_NOT_GBZ80 },
3552 { "halt", 0x00, 0x76, emit_insn, INS_ALL },
3553 { "im", 0xED, 0x46, emit_im, INS_NOT_GBZ80 },
3554 { "in", 0x00, 0x00, emit_in, INS_NOT_GBZ80 },
3555 { "in0", 0xED, 0x00, emit_in0, INS_Z180|INS_EZ80 },
3556 { "inc", 0x03, 0x04, emit_incdec,INS_ALL },
3557 { "ind", 0xED, 0xAA, emit_insn, INS_NOT_GBZ80 },
3558 { "ind2", 0xED, 0x8C, emit_insn, INS_EZ80 },
3559 { "ind2r",0xED, 0x9C, emit_insn, INS_EZ80 },
3560 { "indm", 0xED, 0x8A, emit_insn, INS_EZ80 },
3561 { "indmr",0xED, 0x9A, emit_insn, INS_EZ80 },
3562 { "indr", 0xED, 0xBA, emit_insn, INS_NOT_GBZ80 },
3563 { "indrx",0xED, 0xCA, emit_insn, INS_EZ80 },
3564 { "ini", 0xED, 0xA2, emit_insn, INS_NOT_GBZ80 },
3565 { "ini2", 0xED, 0x84, emit_insn, INS_EZ80 },
3566 { "ini2r",0xED, 0x94, emit_insn, INS_EZ80 },
3567 { "inim", 0xED, 0x82, emit_insn, INS_EZ80 },
3568 { "inimr",0xED, 0x92, emit_insn, INS_EZ80 },
3569 { "inir", 0xED, 0xB2, emit_insn, INS_NOT_GBZ80 },
3570 { "inirx",0xED, 0xC2, emit_insn, INS_EZ80 },
3571 { "jp", 0xC3, 0xC2, emit_jpcc, INS_ALL },
3572 { "jr", 0x18, 0x20, emit_jrcc, INS_ALL },
3573 { "ld", 0x00, 0x00, emit_ld, INS_ALL },
3574 { "ldd", 0xED, 0xA8, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
3575 { "lddr", 0xED, 0xB8, emit_insn, INS_NOT_GBZ80 },
3576 { "lddrx",0xED, 0xBC, emit_insn, INS_Z80N },
3577 { "lddx", 0xED, 0xAC, emit_insn, INS_Z80N },
3578 { "ldh", 0xE0, 0x00, emit_ldh, INS_GBZ80 },
3579 { "ldhl", 0x00, 0xF8, emit_ldhl, INS_GBZ80 },
3580 { "ldi", 0xED, 0xA0, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
3581 { "ldir", 0xED, 0xB0, emit_insn, INS_NOT_GBZ80 },
3582 { "ldirx",0xED, 0xB4, emit_insn, INS_Z80N },
3583 { "ldix", 0xED, 0xA4, emit_insn, INS_Z80N },
3584 { "ldpirx",0xED,0xB7, emit_insn, INS_Z80N },
3585 { "ldws", 0xED, 0xA5, emit_insn, INS_Z80N },
3586 { "lea", 0xED, 0x02, emit_lea, INS_EZ80 },
3587 { "mirror",0xED,0x24, emit_insn, INS_Z80N },
3588 { "mlt", 0xED, 0x4C, emit_mlt, INS_Z180|INS_EZ80|INS_Z80N },
3589 { "mul", 0xED, 0x30, emit_mul, INS_Z80N },
3590 { "mulub",0xED, 0xC5, emit_mulub,INS_R800 },
3591 { "muluw",0xED, 0xC3, emit_muluw,INS_R800 },
3592 { "neg", 0xED, 0x44, emit_insn, INS_NOT_GBZ80 },
3593 { "nextreg",0xED,0x91,emit_nextreg,INS_Z80N },
3594 { "nop", 0x00, 0x00, emit_insn, INS_ALL },
3595 { "or", 0x00, 0xB0, emit_s, INS_ALL },
3596 { "otd2r",0xED, 0xBC, emit_insn, INS_EZ80 },
3597 { "otdm", 0xED, 0x8B, emit_insn, INS_Z180|INS_EZ80 },
3598 { "otdmr",0xED, 0x9B, emit_insn, INS_Z180|INS_EZ80 },
3599 { "otdr", 0xED, 0xBB, emit_insn, INS_NOT_GBZ80 },
3600 { "otdrx",0xED, 0xCB, emit_insn, INS_EZ80 },
3601 { "oti2r",0xED, 0xB4, emit_insn, INS_EZ80 },
3602 { "otim", 0xED, 0x83, emit_insn, INS_Z180|INS_EZ80 },
3603 { "otimr",0xED, 0x93, emit_insn, INS_Z180|INS_EZ80 },
3604 { "otir", 0xED, 0xB3, emit_insn, INS_NOT_GBZ80 },
3605 { "otirx",0xED, 0xC3, emit_insn, INS_EZ80 },
3606 { "out", 0x00, 0x00, emit_out, INS_NOT_GBZ80 },
3607 { "out0", 0xED, 0x01, emit_out0, INS_Z180|INS_EZ80 },
3608 { "outd", 0xED, 0xAB, emit_insn, INS_NOT_GBZ80 },
3609 { "outd2",0xED, 0xAC, emit_insn, INS_EZ80 },
3610 { "outi", 0xED, 0xA3, emit_insn, INS_NOT_GBZ80 },
3611 { "outi2",0xED, 0xA4, emit_insn, INS_EZ80 },
3612 { "outinb",0xED,0x90, emit_insn, INS_Z80N },
3613 { "pea", 0xED, 0x65, emit_pea, INS_EZ80 },
3614 { "pixelad",0xED,0x94,emit_insn, INS_Z80N },
3615 { "pixeldn",0xED,0x93,emit_insn, INS_Z80N },
3616 { "pop", 0x00, 0xC1, emit_pop, INS_ALL },
3617 { "push", 0x00, 0xC5, emit_push, INS_ALL },
3618 { "res", 0xCB, 0x80, emit_bit, INS_ALL },
3619 { "ret", 0xC9, 0xC0, emit_retcc,INS_ALL },
3620 { "reti", 0xED, 0x4D, emit_reti, INS_ALL }, /*GBZ80 has its own opcode for it*/
3621 { "retn", 0xED, 0x45, emit_insn, INS_NOT_GBZ80 },
3622 { "rl", 0xCB, 0x10, emit_mr, INS_ALL },
3623 { "rla", 0x00, 0x17, emit_insn, INS_ALL },
3624 { "rlc", 0xCB, 0x00, emit_mr, INS_ALL },
3625 { "rlca", 0x00, 0x07, emit_insn, INS_ALL },
3626 { "rld", 0xED, 0x6F, emit_insn, INS_NOT_GBZ80 },
3627 { "rr", 0xCB, 0x18, emit_mr, INS_ALL },
3628 { "rra", 0x00, 0x1F, emit_insn, INS_ALL },
3629 { "rrc", 0xCB, 0x08, emit_mr, INS_ALL },
3630 { "rrca", 0x00, 0x0F, emit_insn, INS_ALL },
3631 { "rrd", 0xED, 0x67, emit_insn, INS_NOT_GBZ80 },
3632 { "rsmix",0xED, 0x7E, emit_insn, INS_EZ80 },
3633 { "rst", 0x00, 0xC7, emit_rst, INS_ALL },
3634 { "sbc", 0x98, 0x42, emit_adc, INS_ALL },
3635 { "scf", 0x00, 0x37, emit_insn, INS_ALL },
3636 { "set", 0xCB, 0xC0, emit_bit, INS_ALL },
3637 { "setae",0xED, 0x95, emit_insn, INS_Z80N },
3638 { "sl1", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N },
3639 { "sla", 0xCB, 0x20, emit_mr, INS_ALL },
3640 { "sli", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N },
3641 { "sll", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N },
3642 { "slp", 0xED, 0x76, emit_insn, INS_Z180|INS_EZ80 },
3643 { "sra", 0xCB, 0x28, emit_mr, INS_ALL },
3644 { "srl", 0xCB, 0x38, emit_mr, INS_ALL },
3645 { "stmix",0xED, 0x7D, emit_insn, INS_EZ80 },
3646 { "stop", 0x00, 0x10, emit_insn, INS_GBZ80 },
3647 { "sub", 0x00, 0x90, emit_sub, INS_ALL },
3648 { "swap", 0xCB, 0x30, emit_swap, INS_GBZ80|INS_Z80N },
3649 { "swapnib",0xED,0x23,emit_insn, INS_Z80N },
3650 { "test", 0xED, 0x27, emit_insn_n, INS_Z80N },
3651 { "tst", 0xED, 0x04, emit_tst, INS_Z180|INS_EZ80|INS_Z80N },
3652 { "tstio",0xED, 0x74, emit_insn_n,INS_Z180|INS_EZ80 },
3653 { "xor", 0x00, 0xA8, emit_s, INS_ALL },
3654 } ;
3655
3656 void
3657 md_assemble (char *str)
3658 {
3659 const char *p;
3660 char * old_ptr;
3661 int i;
3662 table_t *insp;
3663
3664 err_flag = 0;
3665 inst_mode = cpu_mode ? (INST_MODE_L | INST_MODE_IL) : (INST_MODE_S | INST_MODE_IS);
3666 old_ptr = input_line_pointer;
3667 p = skip_space (str);
3668 for (i = 0; (i < BUFLEN) && (ISALPHA (*p) || ISDIGIT (*p));)
3669 buf[i++] = TOLOWER (*p++);
3670
3671 if (i == BUFLEN)
3672 {
3673 buf[BUFLEN-3] = buf[BUFLEN-2] = '.'; /* Mark opcode as abbreviated. */
3674 buf[BUFLEN-1] = 0;
3675 as_bad (_("Unknown instruction '%s'"), buf);
3676 }
3677 else
3678 {
3679 dwarf2_emit_insn (0);
3680 if ((*p) && (!ISSPACE (*p)))
3681 {
3682 if (*p != '.' || !(ins_ok & INS_EZ80) || !assemble_suffix (&p))
3683 {
3684 as_bad (_("syntax error"));
3685 goto end;
3686 }
3687 }
3688 buf[i] = 0;
3689 p = skip_space (p);
3690 key = buf;
3691
3692 insp = bsearch (&key, instab, ARRAY_SIZE (instab),
3693 sizeof (instab[0]), key_cmp);
3694 if (!insp || (insp->inss && !(insp->inss & ins_ok)))
3695 {
3696 *frag_more (1) = 0;
3697 as_bad (_("Unknown instruction `%s'"), buf);
3698 }
3699 else
3700 {
3701 p = insp->fp (insp->prefix, insp->opcode, p);
3702 p = skip_space (p);
3703 if ((!err_flag) && *p)
3704 as_bad (_("junk at end of line, "
3705 "first unrecognized character is `%c'"), *p);
3706 }
3707 }
3708 end:
3709 input_line_pointer = old_ptr;
3710 }
3711
3712 static int
3713 signed_overflow (signed long value, unsigned bitsize)
3714 {
3715 signed long max = (signed long) ((1UL << (bitsize - 1)) - 1);
3716 return value < -max - 1 || value > max;
3717 }
3718
3719 static int
3720 unsigned_overflow (unsigned long value, unsigned bitsize)
3721 {
3722 return value >> (bitsize - 1) >> 1 != 0;
3723 }
3724
3725 static int
3726 is_overflow (long value, unsigned bitsize)
3727 {
3728 if (value < 0)
3729 return signed_overflow (value, bitsize);
3730 return unsigned_overflow ((unsigned long)value, bitsize);
3731 }
3732
3733 void
3734 md_apply_fix (fixS * fixP, valueT* valP, segT seg)
3735 {
3736 long val = *valP;
3737 char *p_lit = fixP->fx_where + fixP->fx_frag->fr_literal;
3738
3739 if (fixP->fx_addsy == NULL)
3740 fixP->fx_done = 1;
3741 else if (fixP->fx_pcrel)
3742 {
3743 segT s = S_GET_SEGMENT (fixP->fx_addsy);
3744 if (s == seg || s == absolute_section)
3745 {
3746 val += S_GET_VALUE (fixP->fx_addsy);
3747 fixP->fx_done = 1;
3748 }
3749 }
3750
3751 switch (fixP->fx_r_type)
3752 {
3753 case BFD_RELOC_8_PCREL:
3754 case BFD_RELOC_Z80_DISP8:
3755 case BFD_RELOC_8:
3756 case BFD_RELOC_16:
3757 case BFD_RELOC_24:
3758 case BFD_RELOC_32:
3759 case BFD_RELOC_Z80_16_BE:
3760 fixP->fx_no_overflow = 0;
3761 break;
3762 default:
3763 fixP->fx_no_overflow = 1;
3764 break;
3765 }
3766
3767 switch (fixP->fx_r_type)
3768 {
3769 case BFD_RELOC_8_PCREL:
3770 case BFD_RELOC_Z80_DISP8:
3771 if (fixP->fx_done && signed_overflow (val, 8))
3772 as_bad_where (fixP->fx_file, fixP->fx_line,
3773 _("8-bit signed offset out of range (%+ld)"), val);
3774 *p_lit++ = val;
3775 break;
3776
3777 case BFD_RELOC_Z80_BYTE0:
3778 *p_lit++ = val;
3779 break;
3780
3781 case BFD_RELOC_Z80_BYTE1:
3782 *p_lit++ = (val >> 8);
3783 break;
3784
3785 case BFD_RELOC_Z80_BYTE2:
3786 *p_lit++ = (val >> 16);
3787 break;
3788
3789 case BFD_RELOC_Z80_BYTE3:
3790 *p_lit++ = (val >> 24);
3791 break;
3792
3793 case BFD_RELOC_8:
3794 if (fixP->fx_done && is_overflow(val, 8))
3795 as_warn_where (fixP->fx_file, fixP->fx_line,
3796 _("8-bit overflow (%+ld)"), val);
3797 *p_lit++ = val;
3798 break;
3799
3800 case BFD_RELOC_Z80_WORD1:
3801 *p_lit++ = (val >> 16);
3802 *p_lit++ = (val >> 24);
3803 break;
3804
3805 case BFD_RELOC_Z80_WORD0:
3806 *p_lit++ = val;
3807 *p_lit++ = (val >> 8);
3808 break;
3809
3810 case BFD_RELOC_16:
3811 if (fixP->fx_done && is_overflow(val, 16))
3812 as_warn_where (fixP->fx_file, fixP->fx_line,
3813 _("16-bit overflow (%+ld)"), val);
3814 *p_lit++ = val;
3815 *p_lit++ = (val >> 8);
3816 break;
3817
3818 case BFD_RELOC_24: /* Def24 may produce this. */
3819 if (fixP->fx_done && is_overflow(val, 24))
3820 as_warn_where (fixP->fx_file, fixP->fx_line,
3821 _("24-bit overflow (%+ld)"), val);
3822 *p_lit++ = val;
3823 *p_lit++ = (val >> 8);
3824 *p_lit++ = (val >> 16);
3825 break;
3826
3827 case BFD_RELOC_32: /* Def32 and .long may produce this. */
3828 if (fixP->fx_done && is_overflow(val, 32))
3829 as_warn_where (fixP->fx_file, fixP->fx_line,
3830 _("32-bit overflow (%+ld)"), val);
3831 *p_lit++ = val;
3832 *p_lit++ = (val >> 8);
3833 *p_lit++ = (val >> 16);
3834 *p_lit++ = (val >> 24);
3835 break;
3836
3837 case BFD_RELOC_Z80_16_BE: /* Z80N PUSH nn instruction produce this. */
3838 *p_lit++ = val >> 8;
3839 *p_lit++ = val;
3840 break;
3841
3842 default:
3843 printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP->fx_r_type);
3844 abort ();
3845 }
3846 }
3847
3848 /* GAS will call this to generate a reloc. GAS will pass the
3849 resulting reloc to `bfd_install_relocation'. This currently works
3850 poorly, as `bfd_install_relocation' often does the wrong thing, and
3851 instances of `tc_gen_reloc' have been written to work around the
3852 problems, which in turns makes it difficult to fix
3853 `bfd_install_relocation'. */
3854
3855 /* If while processing a fixup, a reloc really
3856 needs to be created then it is done here. */
3857
3858 arelent *
3859 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED , fixS *fixp)
3860 {
3861 arelent *reloc;
3862
3863 if (fixp->fx_subsy != NULL)
3864 {
3865 as_bad_subtract (fixp);
3866 return NULL;
3867 }
3868
3869 reloc = XNEW (arelent);
3870 reloc->sym_ptr_ptr = XNEW (asymbol *);
3871 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3872 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3873 reloc->addend = fixp->fx_offset;
3874 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3875 if (reloc->howto == NULL)
3876 {
3877 as_bad_where (fixp->fx_file, fixp->fx_line,
3878 _("reloc %d not supported by object file format"),
3879 (int) fixp->fx_r_type);
3880 return NULL;
3881 }
3882
3883 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3884 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3885 reloc->address = fixp->fx_offset;
3886
3887 return reloc;
3888 }
3889
3890 int
3891 z80_tc_labels_without_colon (void)
3892 {
3893 return colonless_labels;
3894 }
3895
3896 int
3897 z80_tc_label_is_local (const char *name)
3898 {
3899 const char *n;
3900 const char *p;
3901 if (local_label_prefix == NULL)
3902 return 0;
3903 for (p = local_label_prefix, n = name; *p && *n && *n == *p; p++, n++)
3904 ;
3905 return *p == '\0';
3906 }
3907
3908 /* Parse floating point number from string and compute mantissa and
3909 exponent. Mantissa is normalized.
3910 */
3911 #define EXP_MIN -0x10000
3912 #define EXP_MAX 0x10000
3913 static int
3914 str_to_broken_float (bool *signP, uint64_t *mantissaP, int *expP)
3915 {
3916 char *p;
3917 bool sign;
3918 uint64_t mantissa = 0;
3919 int exponent = 0;
3920 int i;
3921
3922 p = (char*)skip_space (input_line_pointer);
3923 sign = (*p == '-');
3924 *signP = sign;
3925 if (sign || *p == '+')
3926 ++p;
3927 if (strncasecmp (p, "NaN", 3) == 0)
3928 {
3929 *mantissaP = 0;
3930 *expP = 0;
3931 input_line_pointer = p + 3;
3932 return 1;
3933 }
3934 if (strncasecmp (p, "inf", 3) == 0)
3935 {
3936 *mantissaP = 1ull << 63;
3937 *expP = EXP_MAX;
3938 input_line_pointer = p + 3;
3939 return 1;
3940 }
3941 for (; ISDIGIT (*p); ++p)
3942 {
3943 if (mantissa >> 60)
3944 {
3945 if (*p >= '5')
3946 mantissa++;
3947 break;
3948 }
3949 mantissa = mantissa * 10 + (*p - '0');
3950 }
3951 /* skip non-significant digits */
3952 for (; ISDIGIT (*p); ++p)
3953 exponent++;
3954
3955 if (*p == '.')
3956 {
3957 p++;
3958 if (!exponent) /* If no precision overflow. */
3959 {
3960 for (; ISDIGIT (*p); ++p, --exponent)
3961 {
3962 if (mantissa >> 60)
3963 {
3964 if (*p >= '5')
3965 mantissa++;
3966 break;
3967 }
3968 mantissa = mantissa * 10 + (*p - '0');
3969 }
3970 }
3971 for (; ISDIGIT (*p); ++p)
3972 ;
3973 }
3974 if (*p == 'e' || *p == 'E')
3975 {
3976 int es;
3977 int t = 0;
3978 ++p;
3979 es = (*p == '-');
3980 if (es || *p == '+')
3981 p++;
3982 for (; ISDIGIT (*p); ++p)
3983 {
3984 if (t < 100)
3985 t = t * 10 + (*p - '0');
3986 }
3987 exponent += (es) ? -t : t;
3988 }
3989 if (ISALNUM (*p) || *p == '.')
3990 return 0;
3991 input_line_pointer = p;
3992 if (mantissa == 0)
3993 {
3994 *mantissaP = 1ull << 63;
3995 *expP = EXP_MIN;
3996 return 1; /* result is 0 */
3997 }
3998 /* normalization */
3999 for (; mantissa <= ~0ull/10; --exponent)
4000 mantissa *= 10;
4001 /* Now we have sign, mantissa, and signed decimal exponent
4002 need to recompute to binary exponent. */
4003 for (i = 64; exponent > 0; --exponent)
4004 {
4005 /* be sure that no integer overflow */
4006 while (mantissa > ~0ull/10)
4007 {
4008 mantissa >>= 1;
4009 i += 1;
4010 }
4011 mantissa *= 10;
4012 }
4013 for (; exponent < 0; ++exponent)
4014 {
4015 while (!(mantissa >> 63))
4016 {
4017 mantissa <<= 1;
4018 i -= 1;
4019 }
4020 mantissa /= 10;
4021 }
4022 /* normalization */
4023 for (; !(mantissa >> 63); --i)
4024 mantissa <<= 1;
4025 *mantissaP = mantissa;
4026 *expP = i;
4027 return 1;
4028 }
4029
4030 static const char *
4031 str_to_zeda32(char *litP, int *sizeP)
4032 {
4033 uint64_t mantissa;
4034 bool sign;
4035 int exponent;
4036 unsigned i;
4037
4038 *sizeP = 4;
4039 if (!str_to_broken_float (&sign, &mantissa, &exponent))
4040 return _("invalid syntax");
4041 /* I do not know why decrement is needed */
4042 --exponent;
4043 /* shift by 39 bits right keeping 25 bit mantissa for rounding */
4044 mantissa >>= 39;
4045 /* do rounding */
4046 ++mantissa;
4047 /* make 24 bit mantissa */
4048 mantissa >>= 1;
4049 /* check for overflow */
4050 if (mantissa >> 24)
4051 {
4052 mantissa >>= 1;
4053 ++exponent;
4054 }
4055 /* check for 0 */
4056 if (exponent < -127)
4057 {
4058 exponent = -128;
4059 mantissa = 0;
4060 }
4061 else if (exponent > 127)
4062 {
4063 exponent = -128;
4064 mantissa = sign ? 0xc00000 : 0x400000;
4065 }
4066 else if (mantissa == 0)
4067 {
4068 exponent = -128;
4069 mantissa = 0x200000;
4070 }
4071 else if (!sign)
4072 mantissa &= (1ull << 23) - 1;
4073 for (i = 0; i < 24; i += 8)
4074 *litP++ = (char)(mantissa >> i);
4075 *litP = (char)(0x80 + exponent);
4076 return NULL;
4077 }
4078
4079 /*
4080 Math48 by Anders Hejlsberg support.
4081 Mantissa is 39 bits wide, exponent 8 bit wide.
4082 Format is:
4083 bit 47: sign
4084 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1)
4085 bit 7-0: exponent+128 (0 - value is null)
4086 MIN: 2.938735877e-39
4087 MAX: 1.701411835e+38
4088 */
4089 static const char *
4090 str_to_float48(char *litP, int *sizeP)
4091 {
4092 uint64_t mantissa;
4093 bool sign;
4094 int exponent;
4095 unsigned i;
4096
4097 *sizeP = 6;
4098 if (!str_to_broken_float (&sign, &mantissa, &exponent))
4099 return _("invalid syntax");
4100 /* shift by 23 bits right keeping 41 bit mantissa for rounding */
4101 mantissa >>= 23;
4102 /* do rounding */
4103 ++mantissa;
4104 /* make 40 bit mantissa */
4105 mantissa >>= 1;
4106 /* check for overflow */
4107 if (mantissa >> 40)
4108 {
4109 mantissa >>= 1;
4110 ++exponent;
4111 }
4112 if (exponent < -127)
4113 {
4114 memset (litP, 0, 6);
4115 return NULL;
4116 }
4117 if (exponent > 127)
4118 return _("overflow");
4119 if (!sign)
4120 mantissa &= (1ull << 39) - 1;
4121 *litP++ = (char)(0x80 + exponent);
4122 for (i = 0; i < 40; i += 8)
4123 *litP++ = (char)(mantissa >> i);
4124 return NULL;
4125 }
4126
4127 static const char *
4128 str_to_ieee754_h(char *litP, int *sizeP)
4129 {
4130 return ieee_md_atof ('h', litP, sizeP, false);
4131 }
4132
4133 static const char *
4134 str_to_ieee754_s(char *litP, int *sizeP)
4135 {
4136 return ieee_md_atof ('s', litP, sizeP, false);
4137 }
4138
4139 static const char *
4140 str_to_ieee754_d(char *litP, int *sizeP)
4141 {
4142 return ieee_md_atof ('d', litP, sizeP, false);
4143 }
4144
4145 #ifdef TARGET_USE_CFIPOP
4146 /* Initialize the DWARF-2 unwind information for this procedure. */
4147 void
4148 z80_tc_frame_initial_instructions (void)
4149 {
4150 static int sp_regno = -1;
4151
4152 if (sp_regno < 0)
4153 sp_regno = z80_tc_regname_to_dw2regnum ("sp");
4154
4155 cfi_add_CFA_def_cfa (sp_regno, 0);
4156 }
4157
4158 int
4159 z80_tc_regname_to_dw2regnum (const char *regname)
4160 {
4161 static const char *regs[] =
4162 { /* same registers as for GDB */
4163 "af", "bc", "de", "hl",
4164 "sp", "pc", "ix", "iy",
4165 "af_", "bc_", "de_", "hl_",
4166 "ir"
4167 };
4168 unsigned i;
4169
4170 for (i = 0; i < ARRAY_SIZE(regs); ++i)
4171 if (!strcasecmp (regs[i], regname))
4172 return i;
4173
4174 return -1;
4175 }
4176 #endif
4177
4178 /* Implement DWARF2_ADDR_SIZE. */
4179 int
4180 z80_dwarf2_addr_size (const bfd *abfd)
4181 {
4182 switch (bfd_get_mach (abfd))
4183 {
4184 case bfd_mach_ez80_adl:
4185 return 3;
4186 default:
4187 return 2;
4188 }
4189 }
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