1 @c Copyright (C) 1996-2021 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
144 @code{cortex-r52plus},
153 @code{cortex-m0plus},
157 @code{marvell-whitney},
163 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
164 @code{i80200} (Intel XScale processor)
165 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
168 The special name @code{all} may be used to allow the
169 assembler to accept instructions valid for any ARM processor.
171 In addition to the basic instruction set, the assembler can be told to
172 accept various extension mnemonics that extend the processor using the
173 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
174 is equivalent to specifying @code{-mcpu=ep9312}.
176 Multiple extensions may be specified, separated by a @code{+}. The
177 extensions should be specified in ascending alphabetical order.
179 Some extensions may be restricted to particular architectures; this is
180 documented in the list of extensions below.
182 Extension mnemonics may also be removed from those the assembler accepts.
183 This is done be prepending @code{no} to the option that adds the extension.
184 Extensions that are removed should be listed after all extensions which have
185 been added, again in ascending alphabetical order. For example,
186 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
189 The following extensions are currently supported:
190 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
191 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
193 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
194 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
195 @code{fp} (Floating Point Extensions for v8-A architecture),
196 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
197 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
198 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
203 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
205 @code{os} (Operating System for v6M architecture),
206 @code{predres} (Execution and Data Prediction Restriction Instruction for
207 v8-A architectures, added by default from v8.5-A),
208 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
209 default from v8.5-A),
210 @code{sec} (Security Extensions for v6K and v7-A architectures),
211 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
212 @code{virt} (Virtualization Extensions for v7-A architecture, implies
214 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
215 @code{ras} (Reliability, Availability and Serviceability extensions
216 for v8-A architecture),
217 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
222 @cindex @code{-march=} command-line option, ARM
223 @item -march=@var{architecture}[+@var{extension}@dots{}]
224 This option specifies the target architecture. The assembler will issue
225 an error message if an attempt is made to assemble an instruction which
226 will not execute on the target architecture. The following architecture
227 names are recognized:
265 @code{armv8.1-m.main},
272 If both @code{-mcpu} and
273 @code{-march} are specified, the assembler will use
274 the setting for @code{-mcpu}.
276 The architecture option can be extended with a set extension options. These
277 extensions are context sensitive, i.e. the same extension may mean different
278 things when used with different architectures. When used together with a
279 @code{-mfpu} option, the union of both feature enablement is taken.
280 See their availability and meaning below:
282 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
284 @code{+fp}: Enables VFPv2 instructions.
285 @code{+nofp}: Disables all FPU instrunctions.
289 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
290 @code{+nofp}: Disables all FPU instructions.
294 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
295 @code{+vfpv3-d16}: Alias for @code{+fp}.
296 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
297 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
298 conversion instructions and 16 double-word registers.
299 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
300 instructions and 32 double-word registers.
301 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
302 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
303 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
305 @code{+neon}: Alias for @code{+simd}.
306 @code{+neon-vfpv3}: Alias for @code{+simd}.
307 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
308 NEONv1 instructions with 32 double-word registers.
309 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
310 double-word registers.
311 @code{+mp}: Enables Multiprocessing Extensions.
312 @code{+sec}: Enables Security Extensions.
313 @code{+nofp}: Disables all FPU and NEON instructions.
314 @code{+nosimd}: Disables all NEON instructions.
318 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
319 @code{+vfpv4-d16}: Alias for @code{+fp}.
320 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
321 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
322 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
323 conversion instructions and 16 double-word registers.
324 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
325 instructions and 32 double-word registers.
326 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
327 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
328 double-word registers.
329 @code{+neon-vfpv4}: Alias for @code{+simd}.
330 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
332 @code{+neon-vfpv3}: Alias for @code{+neon}.
333 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
334 NEONv1 instructions with 32 double-word registers.
335 double-word registers.
336 @code{+nofp}: Disables all FPU and NEON instructions.
337 @code{+nosimd}: Disables all NEON instructions.
341 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
342 double-word registers.
343 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
344 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
345 @code{+vfpv3-d16}: Alias for @code{+fp}.
346 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
347 floating-point conversion instructions with 16 double-word registers.
348 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
349 conversion instructions with 16 double-word registers.
350 @code{+idiv}: Enables integer division instructions in ARM mode.
351 @code{+nofp}: Disables all FPU instructions.
355 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
356 double-word registers.
357 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
358 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
359 double-word registers.
360 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
361 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
362 @code{+nofp}: Disables all FPU instructions.
364 For @code{armv8-m.main}:
366 @code{+dsp}: Enables DSP Extension.
367 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
368 double-word registers.
369 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
370 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
371 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
372 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
373 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
374 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
375 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
376 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
377 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
378 @code{+nofp}: Disables all FPU instructions.
379 @code{+nodsp}: Disables DSP Extension.
381 For @code{armv8.1-m.main}:
383 @code{+dsp}: Enables DSP Extension.
384 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
385 for Armv8.1-M Mainline with 16 double-word registers.
386 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
387 Armv8.1-M Mainline, implies @code{+fp}.
388 @code{+mve}: Enables integer only M-profile Vector Extension for
389 Armv8.1-M Mainline, implies @code{+dsp}.
390 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
391 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
392 @code{+nofp}: Disables all FPU instructions.
393 @code{+nodsp}: Disables DSP Extension.
394 @code{+nomve}: Disables all M-profile Vector Extensions.
398 @code{+crc}: Enables CRC32 Extension.
399 @code{+simd}: Enables VFP and NEON for Armv8-A.
400 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
402 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
403 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
405 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
406 @code{+nocrypto}: Disables Cryptography Extensions.
408 For @code{armv8.1-a}:
410 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
411 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
413 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
414 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
416 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
417 @code{+nocrypto}: Disables Cryptography Extensions.
419 For @code{armv8.2-a} and @code{armv8.3-a}:
421 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
422 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
423 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
424 for Armv8.2-A, implies @code{+fp16}.
425 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
427 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
429 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
430 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
432 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
433 @code{+nocrypto}: Disables Cryptography Extensions.
435 For @code{armv8.4-a}:
437 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
439 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
440 Variant Extensions for Armv8.2-A, implies @code{+simd}.
441 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
443 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
444 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
446 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
447 @code{+nocryptp}: Disables Cryptography Extensions.
449 For @code{armv8.5-a}:
451 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
453 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
454 Variant Extensions for Armv8.2-A, implies @code{+simd}.
455 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
457 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
458 @code{+nocryptp}: Disables Cryptography Extensions.
461 @cindex @code{-mfpu=} command-line option, ARM
462 @item -mfpu=@var{floating-point-format}
464 This option specifies the floating point format to assemble for. The
465 assembler will issue an error message if an attempt is made to assemble
466 an instruction which will not execute on the target floating point unit.
467 The following format options are recognized:
487 @code{vfpv3-d16-fp16},
504 @code{neon-fp-armv8},
505 @code{crypto-neon-fp-armv8},
506 @code{neon-fp-armv8.1}
508 @code{crypto-neon-fp-armv8.1}.
510 In addition to determining which instructions are assembled, this option
511 also affects the way in which the @code{.double} assembler directive behaves
512 when assembling little-endian code.
514 The default is dependent on the processor selected. For Architecture 5 or
515 later, the default is to assemble for VFP instructions; for earlier
516 architectures the default is to assemble for FPA instructions.
518 @cindex @code{-mfp16-format=} command-line option
519 @item -mfp16-format=@var{format}
520 This option specifies the half-precision floating point format to use
521 when assembling floating point numbers emitted by the @code{.float16}
523 The following format options are recognized:
526 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
527 point format is used, if @code{alternative} is specified then the Arm
528 alternative half-precision format is used. If this option is set on the
529 command line then the format is fixed and cannot be changed with
530 the @code{float16_format} directive. If this value is not set then
531 the IEEE 754-2008 format is used until the format is explicitly set with
532 the @code{float16_format} directive.
534 @cindex @code{-mthumb} command-line option, ARM
536 This option specifies that the assembler should start assembling Thumb
537 instructions; that is, it should behave as though the file starts with a
538 @code{.code 16} directive.
540 @cindex @code{-mthumb-interwork} command-line option, ARM
541 @item -mthumb-interwork
542 This option specifies that the output generated by the assembler should
543 be marked as supporting interworking. It also affects the behaviour
544 of the @code{ADR} and @code{ADRL} pseudo opcodes.
546 @cindex @code{-mimplicit-it} command-line option, ARM
547 @item -mimplicit-it=never
548 @itemx -mimplicit-it=always
549 @itemx -mimplicit-it=arm
550 @itemx -mimplicit-it=thumb
551 The @code{-mimplicit-it} option controls the behavior of the assembler when
552 conditional instructions are not enclosed in IT blocks.
553 There are four possible behaviors.
554 If @code{never} is specified, such constructs cause a warning in ARM
555 code and an error in Thumb-2 code.
556 If @code{always} is specified, such constructs are accepted in both
557 ARM and Thumb-2 code, where the IT instruction is added implicitly.
558 If @code{arm} is specified, such constructs are accepted in ARM code
559 and cause an error in Thumb-2 code.
560 If @code{thumb} is specified, such constructs cause a warning in ARM
561 code and are accepted in Thumb-2 code. If you omit this option, the
562 behavior is equivalent to @code{-mimplicit-it=arm}.
564 @cindex @code{-mapcs-26} command-line option, ARM
565 @cindex @code{-mapcs-32} command-line option, ARM
568 These options specify that the output generated by the assembler should
569 be marked as supporting the indicated version of the Arm Procedure.
572 @cindex @code{-matpcs} command-line option, ARM
574 This option specifies that the output generated by the assembler should
575 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
576 enabled this option will cause the assembler to create an empty
577 debugging section in the object file called .arm.atpcs. Debuggers can
578 use this to determine the ABI being used by.
580 @cindex @code{-mapcs-float} command-line option, ARM
582 This indicates the floating point variant of the APCS should be
583 used. In this variant floating point arguments are passed in FP
584 registers rather than integer registers.
586 @cindex @code{-mapcs-reentrant} command-line option, ARM
587 @item -mapcs-reentrant
588 This indicates that the reentrant variant of the APCS should be used.
589 This variant supports position independent code.
591 @cindex @code{-mfloat-abi=} command-line option, ARM
592 @item -mfloat-abi=@var{abi}
593 This option specifies that the output generated by the assembler should be
594 marked as using specified floating point ABI.
595 The following values are recognized:
601 @cindex @code{-eabi=} command-line option, ARM
602 @item -meabi=@var{ver}
603 This option specifies which EABI version the produced object files should
605 The following values are recognized:
611 @cindex @code{-EB} command-line option, ARM
613 This option specifies that the output generated by the assembler should
614 be marked as being encoded for a big-endian processor.
616 Note: If a program is being built for a system with big-endian data
617 and little-endian instructions then it should be assembled with the
618 @option{-EB} option, (all of it, code and data) and then linked with
619 the @option{--be8} option. This will reverse the endianness of the
620 instructions back to little-endian, but leave the data as big-endian.
622 @cindex @code{-EL} command-line option, ARM
624 This option specifies that the output generated by the assembler should
625 be marked as being encoded for a little-endian processor.
627 @cindex @code{-k} command-line option, ARM
628 @cindex PIC code generation for ARM
630 This option specifies that the output of the assembler should be marked
631 as position-independent code (PIC).
633 @cindex @code{--fix-v4bx} command-line option, ARM
635 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
636 the linker option of the same name.
638 @cindex @code{-mwarn-deprecated} command-line option, ARM
639 @item -mwarn-deprecated
640 @itemx -mno-warn-deprecated
641 Enable or disable warnings about using deprecated options or
642 features. The default is to warn.
644 @cindex @code{-mccs} command-line option, ARM
646 Turns on CodeComposer Studio assembly syntax compatibility mode.
648 @cindex @code{-mwarn-syms} command-line option, ARM
650 @itemx -mno-warn-syms
651 Enable or disable warnings about symbols that match the names of ARM
652 instructions. The default is to warn.
660 * ARM-Instruction-Set:: Instruction Set
661 * ARM-Chars:: Special Characters
662 * ARM-Regs:: Register Names
663 * ARM-Relocations:: Relocations
664 * ARM-Neon-Alignment:: NEON Alignment Specifiers
667 @node ARM-Instruction-Set
668 @subsection Instruction Set Syntax
669 Two slightly different syntaxes are support for ARM and THUMB
670 instructions. The default, @code{divided}, uses the old style where
671 ARM and THUMB instructions had their own, separate syntaxes. The new,
672 @code{unified} syntax, which can be selected via the @code{.syntax}
673 directive, and has the following main features:
677 Immediate operands do not require a @code{#} prefix.
680 The @code{IT} instruction may appear, and if it does it is validated
681 against subsequent conditional affixes. In ARM mode it does not
682 generate machine code, in THUMB mode it does.
685 For ARM instructions the conditional affixes always appear at the end
686 of the instruction. For THUMB instructions conditional affixes can be
687 used, but only inside the scope of an @code{IT} instruction.
690 All of the instructions new to the V6T2 architecture (and later) are
691 available. (Only a few such instructions can be written in the
692 @code{divided} syntax).
695 The @code{.N} and @code{.W} suffixes are recognized and honored.
698 All instructions set the flags if and only if they have an @code{s}
703 @subsection Special Characters
705 @cindex line comment character, ARM
706 @cindex ARM line comment character
707 The presence of a @samp{@@} anywhere on a line indicates the start of
708 a comment that extends to the end of that line.
710 If a @samp{#} appears as the first character of a line then the whole
711 line is treated as a comment, but in this case the line could also be
712 a logical line number directive (@pxref{Comments}) or a preprocessor
713 control command (@pxref{Preprocessing}).
715 @cindex line separator, ARM
716 @cindex statement separator, ARM
717 @cindex ARM line separator
718 The @samp{;} character can be used instead of a newline to separate
721 @cindex immediate character, ARM
722 @cindex ARM immediate character
723 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
725 @cindex identifiers, ARM
726 @cindex ARM identifiers
727 *TODO* Explain about /data modifier on symbols.
730 @subsection Register Names
732 @cindex ARM register names
733 @cindex register names, ARM
734 *TODO* Explain about ARM register naming, and the predefined names.
736 @node ARM-Relocations
737 @subsection ARM relocation generation
739 @cindex data relocations, ARM
740 @cindex ARM data relocations
741 Specific data relocations can be generated by putting the relocation name
742 in parentheses after the symbol name. For example:
748 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
750 The following relocations are supported:
766 For compatibility with older toolchains the assembler also accepts
767 @code{(PLT)} after branch targets. On legacy targets this will
768 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
769 targets it will encode either the @samp{R_ARM_CALL} or
770 @samp{R_ARM_JUMP24} relocation, as appropriate.
772 @cindex MOVW and MOVT relocations, ARM
773 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
774 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
775 respectively. For example to load the 32-bit address of foo into r0:
778 MOVW r0, #:lower16:foo
779 MOVT r0, #:upper16:foo
782 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
783 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
784 generated by prefixing the value with @samp{#:lower0_7:#},
785 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
786 respectively. For example to load the 32-bit address of foo into r0:
789 MOVS r0, #:upper8_15:#foo
791 ADDS r0, #:upper0_7:#foo
793 ADDS r0, #:lower8_15:#foo
795 ADDS r0, #:lower0_7:#foo
798 @node ARM-Neon-Alignment
799 @subsection NEON Alignment Specifiers
801 @cindex alignment for NEON instructions
802 Some NEON load/store instructions allow an optional address
804 The ARM documentation specifies that this is indicated by
805 @samp{@@ @var{align}}. However GAS already interprets
806 the @samp{@@} character as a "line comment" start,
807 so @samp{: @var{align}} is used instead. For example:
810 vld1.8 @{q0@}, [r0, :128]
813 @node ARM Floating Point
814 @section Floating Point
816 @cindex floating point, ARM (@sc{ieee})
817 @cindex ARM floating point (@sc{ieee})
818 The ARM family uses @sc{ieee} floating-point numbers.
821 @section ARM Machine Directives
823 @cindex machine directives, ARM
824 @cindex ARM machine directives
827 @c AAAAAAAAAAAAAAAAAAAAAAAAA
830 @cindex @code{.2byte} directive, ARM
831 @cindex @code{.4byte} directive, ARM
832 @cindex @code{.8byte} directive, ARM
833 @item .2byte @var{expression} [, @var{expression}]*
834 @itemx .4byte @var{expression} [, @var{expression}]*
835 @itemx .8byte @var{expression} [, @var{expression}]*
836 These directives write 2, 4 or 8 byte values to the output section.
839 @cindex @code{.align} directive, ARM
840 @item .align @var{expression} [, @var{expression}]
841 This is the generic @var{.align} directive. For the ARM however if the
842 first argument is zero (ie no alignment is needed) the assembler will
843 behave as if the argument had been 2 (ie pad to the next four byte
844 boundary). This is for compatibility with ARM's own assembler.
846 @cindex @code{.arch} directive, ARM
847 @item .arch @var{name}
848 Select the target architecture. Valid values for @var{name} are the same as
849 for the @option{-march} command-line option without the instruction set
852 Specifying @code{.arch} clears any previously selected architecture
855 @cindex @code{.arch_extension} directive, ARM
856 @item .arch_extension @var{name}
857 Add or remove an architecture extension to the target architecture. Valid
858 values for @var{name} are the same as those accepted as architectural
859 extensions by the @option{-mcpu} and @option{-march} command-line options.
861 @code{.arch_extension} may be used multiple times to add or remove extensions
862 incrementally to the architecture being compiled for.
864 @cindex @code{.arm} directive, ARM
866 This performs the same action as @var{.code 32}.
868 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
870 @cindex @code{.bss} directive, ARM
872 This directive switches to the @code{.bss} section.
874 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
876 @cindex @code{.cantunwind} directive, ARM
878 Prevents unwinding through the current function. No personality routine
879 or exception table data is required or permitted.
881 @cindex @code{.code} directive, ARM
882 @item .code @code{[16|32]}
883 This directive selects the instruction set being generated. The value 16
884 selects Thumb, with the value 32 selecting ARM.
886 @cindex @code{.cpu} directive, ARM
887 @item .cpu @var{name}
888 Select the target processor. Valid values for @var{name} are the same as
889 for the @option{-mcpu} command-line option without the instruction set
892 Specifying @code{.cpu} clears any previously selected architecture
895 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
897 @cindex @code{.dn} and @code{.qn} directives, ARM
898 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
899 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
901 The @code{dn} and @code{qn} directives are used to create typed
902 and/or indexed register aliases for use in Advanced SIMD Extension
903 (Neon) instructions. The former should be used to create aliases
904 of double-precision registers, and the latter to create aliases of
905 quad-precision registers.
907 If these directives are used to create typed aliases, those aliases can
908 be used in Neon instructions instead of writing types after the mnemonic
909 or after each operand. For example:
918 This is equivalent to writing the following:
924 Aliases created using @code{dn} or @code{qn} can be destroyed using
927 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
929 @cindex @code{.eabi_attribute} directive, ARM
930 @item .eabi_attribute @var{tag}, @var{value}
931 Set the EABI object attribute @var{tag} to @var{value}.
933 The @var{tag} is either an attribute number, or one of the following:
934 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
935 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
936 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
937 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
938 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
939 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
940 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
941 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
942 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
943 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
944 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
945 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
946 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
947 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
948 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
949 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
950 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
951 @code{Tag_conformance}, @code{Tag_T2EE_use},
952 @code{Tag_Virtualization_use}
954 The @var{value} is either a @code{number}, @code{"string"}, or
955 @code{number, "string"} depending on the tag.
957 Note - the following legacy values are also accepted by @var{tag}:
958 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
959 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
961 @cindex @code{.even} directive, ARM
963 This directive aligns to an even-numbered address.
965 @cindex @code{.extend} directive, ARM
966 @cindex @code{.ldouble} directive, ARM
967 @item .extend @var{expression} [, @var{expression}]*
968 @itemx .ldouble @var{expression} [, @var{expression}]*
969 These directives write 12byte long double floating-point values to the
970 output section. These are not compatible with current ARM processors
973 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
975 @cindex @code{.float16} directive, ARM
976 @item .float16 @var{value [,...,value_n]}
977 Place the half precision floating point representation of one or more
978 floating-point values into the current section. The exact format of the
979 encoding is specified by @code{.float16_format}. If the format has not
980 been explicitly set yet (either via the @code{.float16_format} directive or
981 the command line option) then the IEEE 754-2008 format is used.
983 @cindex @code{.float16_format} directive, ARM
984 @item .float16_format @var{format}
985 Set the format to use when encoding float16 values emitted by
986 the @code{.float16} directive.
987 Once the format has been set it cannot be changed.
988 @code{format} should be one of the following: @code{ieee} (encode in
989 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
990 the Arm alternative half precision format).
993 @cindex @code{.fnend} directive, ARM
995 Marks the end of a function with an unwind table entry. The unwind index
996 table entry is created when this directive is processed.
998 If no personality routine has been specified then standard personality
999 routine 0 or 1 will be used, depending on the number of unwind opcodes
1002 @anchor{arm_fnstart}
1003 @cindex @code{.fnstart} directive, ARM
1005 Marks the start of a function with an unwind table entry.
1007 @cindex @code{.force_thumb} directive, ARM
1009 This directive forces the selection of Thumb instructions, even if the
1010 target processor does not support those instructions
1012 @cindex @code{.fpu} directive, ARM
1013 @item .fpu @var{name}
1014 Select the floating-point unit to assemble for. Valid values for @var{name}
1015 are the same as for the @option{-mfpu} command-line option.
1017 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
1018 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1020 @cindex @code{.handlerdata} directive, ARM
1022 Marks the end of the current function, and the start of the exception table
1023 entry for that function. Anything between this directive and the
1024 @code{.fnend} directive will be added to the exception table entry.
1026 Must be preceded by a @code{.personality} or @code{.personalityindex}
1029 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1031 @cindex @code{.inst} directive, ARM
1032 @item .inst @var{opcode} [ , @dots{} ]
1033 @itemx .inst.n @var{opcode} [ , @dots{} ]
1034 @itemx .inst.w @var{opcode} [ , @dots{} ]
1035 Generates the instruction corresponding to the numerical value @var{opcode}.
1036 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1037 specified explicitly, overriding the normal encoding rules.
1039 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1040 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1041 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1043 @item .ldouble @var{expression} [, @var{expression}]*
1046 @cindex @code{.ltorg} directive, ARM
1048 This directive causes the current contents of the literal pool to be
1049 dumped into the current section (which is assumed to be the .text
1050 section) at the current location (aligned to a word boundary).
1051 @code{GAS} maintains a separate literal pool for each section and each
1052 sub-section. The @code{.ltorg} directive will only affect the literal
1053 pool of the current section and sub-section. At the end of assembly
1054 all remaining, un-empty literal pools will automatically be dumped.
1056 Note - older versions of @code{GAS} would dump the current literal
1057 pool any time a section change occurred. This is no longer done, since
1058 it prevents accurate control of the placement of literal pools.
1060 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1062 @cindex @code{.movsp} directive, ARM
1063 @item .movsp @var{reg} [, #@var{offset}]
1064 Tell the unwinder that @var{reg} contains an offset from the current
1065 stack pointer. If @var{offset} is not specified then it is assumed to be
1068 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1069 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1071 @cindex @code{.object_arch} directive, ARM
1072 @item .object_arch @var{name}
1073 Override the architecture recorded in the EABI object attribute section.
1074 Valid values for @var{name} are the same as for the @code{.arch} directive.
1075 Typically this is useful when code uses runtime detection of CPU features.
1077 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1079 @cindex @code{.packed} directive, ARM
1080 @item .packed @var{expression} [, @var{expression}]*
1081 This directive writes 12-byte packed floating-point values to the
1082 output section. These are not compatible with current ARM processors
1086 @cindex @code{.pad} directive, ARM
1087 @item .pad #@var{count}
1088 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1089 A positive value indicates the function prologue allocated stack space by
1090 decrementing the stack pointer.
1092 @cindex @code{.personality} directive, ARM
1093 @item .personality @var{name}
1094 Sets the personality routine for the current function to @var{name}.
1096 @cindex @code{.personalityindex} directive, ARM
1097 @item .personalityindex @var{index}
1098 Sets the personality routine for the current function to the EABI standard
1099 routine number @var{index}
1101 @cindex @code{.pool} directive, ARM
1103 This is a synonym for .ltorg.
1105 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1106 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1108 @cindex @code{.req} directive, ARM
1109 @item @var{name} .req @var{register name}
1110 This creates an alias for @var{register name} called @var{name}. For
1117 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1120 @cindex @code{.save} directive, ARM
1121 @item .save @var{reglist}
1122 Generate unwinder annotations to restore the registers in @var{reglist}.
1123 The format of @var{reglist} is the same as the corresponding store-multiple
1127 @exdent @emph{core registers}
1128 .save @{r4, r5, r6, lr@}
1129 stmfd sp!, @{r4, r5, r6, lr@}
1130 @exdent @emph{FPA registers}
1133 @exdent @emph{VFP registers}
1134 .save @{d8, d9, d10@}
1135 fstmdx sp!, @{d8, d9, d10@}
1136 @exdent @emph{iWMMXt registers}
1137 .save @{wr10, wr11@}
1138 wstrd wr11, [sp, #-8]!
1139 wstrd wr10, [sp, #-8]!
1142 wstrd wr11, [sp, #-8]!
1144 wstrd wr10, [sp, #-8]!
1148 @cindex @code{.setfp} directive, ARM
1149 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1150 Make all unwinder annotations relative to a frame pointer. Without this
1151 the unwinder will use offsets from the stack pointer.
1153 The syntax of this directive is the same as the @code{add} or @code{mov}
1154 instruction used to set the frame pointer. @var{spreg} must be either
1155 @code{sp} or mentioned in a previous @code{.movsp} directive.
1165 @cindex @code{.secrel32} directive, ARM
1166 @item .secrel32 @var{expression} [, @var{expression}]*
1167 This directive emits relocations that evaluate to the section-relative
1168 offset of each expression's symbol. This directive is only supported
1171 @cindex @code{.syntax} directive, ARM
1172 @item .syntax [@code{unified} | @code{divided}]
1173 This directive sets the Instruction Set Syntax as described in the
1174 @ref{ARM-Instruction-Set} section.
1176 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1178 @cindex @code{.thumb} directive, ARM
1180 This performs the same action as @var{.code 16}.
1182 @cindex @code{.thumb_func} directive, ARM
1184 This directive specifies that the following symbol is the name of a
1185 Thumb encoded function. This information is necessary in order to allow
1186 the assembler and linker to generate correct code for interworking
1187 between Arm and Thumb instructions and should be used even if
1188 interworking is not going to be performed. The presence of this
1189 directive also implies @code{.thumb}
1191 This directive is not necessary when generating EABI objects. On these
1192 targets the encoding is implicit when generating Thumb code.
1194 @cindex @code{.thumb_set} directive, ARM
1196 This performs the equivalent of a @code{.set} directive in that it
1197 creates a symbol which is an alias for another symbol (possibly not yet
1198 defined). This directive also has the added property in that it marks
1199 the aliased symbol as being a thumb function entry point, in the same
1200 way that the @code{.thumb_func} directive does.
1202 @cindex @code{.tlsdescseq} directive, ARM
1203 @item .tlsdescseq @var{tls-variable}
1204 This directive is used to annotate parts of an inlined TLS descriptor
1205 trampoline. Normally the trampoline is provided by the linker, and
1206 this directive is not needed.
1208 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1210 @cindex @code{.unreq} directive, ARM
1211 @item .unreq @var{alias-name}
1212 This undefines a register alias which was previously defined using the
1213 @code{req}, @code{dn} or @code{qn} directives. For example:
1220 An error occurs if the name is undefined. Note - this pseudo op can
1221 be used to delete builtin in register name aliases (eg 'r0'). This
1222 should only be done if it is really necessary.
1224 @cindex @code{.unwind_raw} directive, ARM
1225 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1226 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1227 the stack pointer by @var{offset} bytes.
1229 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1232 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1234 @cindex @code{.vsave} directive, ARM
1235 @item .vsave @var{vfp-reglist}
1236 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1237 using FLDMD. Also works for VFPv3 registers
1238 that are to be restored using VLDM.
1239 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1243 @exdent @emph{VFP registers}
1244 .vsave @{d8, d9, d10@}
1245 fstmdd sp!, @{d8, d9, d10@}
1246 @exdent @emph{VFPv3 registers}
1247 .vsave @{d15, d16, d17@}
1248 vstm sp!, @{d15, d16, d17@}
1251 Since FLDMX and FSTMX are now deprecated, this directive should be
1252 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1254 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1255 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1256 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1257 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1265 @cindex opcodes for ARM
1266 @code{@value{AS}} implements all the standard ARM opcodes. It also
1267 implements several pseudo opcodes, including several synthetic load
1272 @cindex @code{NOP} pseudo op, ARM
1278 This pseudo op will always evaluate to a legal ARM instruction that does
1279 nothing. Currently it will evaluate to MOV r0, r0.
1281 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1284 ldr <register> , = <expression>
1287 If expression evaluates to a numeric constant then a MOV or MVN
1288 instruction will be used in place of the LDR instruction, if the
1289 constant can be generated by either of these instructions. Otherwise
1290 the constant will be placed into the nearest literal pool (if it not
1291 already there) and a PC relative LDR instruction will be generated.
1293 @cindex @code{ADR reg,<label>} pseudo op, ARM
1296 adr <register> <label>
1299 This instruction will load the address of @var{label} into the indicated
1300 register. The instruction will evaluate to a PC relative ADD or SUB
1301 instruction depending upon where the label is located. If the label is
1302 out of range, or if it is not defined in the same file (and section) as
1303 the ADR instruction, then an error will be generated. This instruction
1304 will not make use of the literal pool.
1306 If @var{label} is a thumb function symbol, and thumb interworking has
1307 been enabled via the @option{-mthumb-interwork} option then the bottom
1308 bit of the value stored into @var{register} will be set. This allows
1309 the following sequence to work as expected:
1312 adr r0, thumb_function
1316 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1319 adrl <register> <label>
1322 This instruction will load the address of @var{label} into the indicated
1323 register. The instruction will evaluate to one or two PC relative ADD
1324 or SUB instructions depending upon where the label is located. If a
1325 second instruction is not needed a NOP instruction will be generated in
1326 its place, so that this instruction is always 8 bytes long.
1328 If the label is out of range, or if it is not defined in the same file
1329 (and section) as the ADRL instruction, then an error will be generated.
1330 This instruction will not make use of the literal pool.
1332 If @var{label} is a thumb function symbol, and thumb interworking has
1333 been enabled via the @option{-mthumb-interwork} option then the bottom
1334 bit of the value stored into @var{register} will be set.
1338 For information on the ARM or Thumb instruction sets, see @cite{ARM
1339 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1342 @node ARM Mapping Symbols
1343 @section Mapping Symbols
1345 The ARM ELF specification requires that special symbols be inserted
1346 into object files to mark certain features:
1352 At the start of a region of code containing ARM instructions.
1356 At the start of a region of code containing THUMB instructions.
1360 At the start of a region of data.
1364 The assembler will automatically insert these symbols for you - there
1365 is no need to code them yourself. Support for tagging symbols ($b,
1366 $f, $p and $m) which is also mentioned in the current ARM ELF
1367 specification is not implemented. This is because they have been
1368 dropped from the new EABI and so tools cannot rely upon their
1371 @node ARM Unwinding Tutorial
1374 The ABI for the ARM Architecture specifies a standard format for
1375 exception unwind information. This information is used when an
1376 exception is thrown to determine where control should be transferred.
1377 In particular, the unwind information is used to determine which
1378 function called the function that threw the exception, and which
1379 function called that one, and so forth. This information is also used
1380 to restore the values of callee-saved registers in the function
1381 catching the exception.
1383 If you are writing functions in assembly code, and those functions
1384 call other functions that throw exceptions, you must use assembly
1385 pseudo ops to ensure that appropriate exception unwind information is
1386 generated. Otherwise, if one of the functions called by your assembly
1387 code throws an exception, the run-time library will be unable to
1388 unwind the stack through your assembly code and your program will not
1391 To illustrate the use of these pseudo ops, we will examine the code
1392 that G++ generates for the following C++ input:
1395 void callee (int *);
1406 This example does not show how to throw or catch an exception from
1407 assembly code. That is a much more complex operation and should
1408 always be done in a high-level language, such as C++, that directly
1409 supports exceptions.
1411 The code generated by one particular version of G++ when compiling the
1418 @ Function supports interworking.
1419 @ args = 0, pretend = 0, frame = 8
1420 @ frame_needed = 1, uses_anonymous_args = 0
1442 Of course, the sequence of instructions varies based on the options
1443 you pass to GCC and on the version of GCC in use. The exact
1444 instructions are not important since we are focusing on the pseudo ops
1445 that are used to generate unwind information.
1447 An important assumption made by the unwinder is that the stack frame
1448 does not change during the body of the function. In particular, since
1449 we assume that the assembly code does not itself throw an exception,
1450 the only point where an exception can be thrown is from a call, such
1451 as the @code{bl} instruction above. At each call site, the same saved
1452 registers (including @code{lr}, which indicates the return address)
1453 must be located in the same locations relative to the frame pointer.
1455 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1456 op appears immediately before the first instruction of the function
1457 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1458 op appears immediately after the last instruction of the function.
1459 These pseudo ops specify the range of the function.
1461 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1462 @code{.pad}) matters; their exact locations are irrelevant. In the
1463 example above, the compiler emits the pseudo ops with particular
1464 instructions. That makes it easier to understand the code, but it is
1465 not required for correctness. It would work just as well to emit all
1466 of the pseudo ops other than @code{.fnend} in the same order, but
1467 immediately after @code{.fnstart}.
1469 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1470 indicates registers that have been saved to the stack so that they can
1471 be restored before the function returns. The argument to the
1472 @code{.save} pseudo op is a list of registers to save. If a register
1473 is ``callee-saved'' (as specified by the ABI) and is modified by the
1474 function you are writing, then your code must save the value before it
1475 is modified and restore the original value before the function
1476 returns. If an exception is thrown, the run-time library restores the
1477 values of these registers from their locations on the stack before
1478 returning control to the exception handler. (Of course, if an
1479 exception is not thrown, the function that contains the @code{.save}
1480 pseudo op restores these registers in the function epilogue, as is
1481 done with the @code{ldmfd} instruction above.)
1483 You do not have to save callee-saved registers at the very beginning
1484 of the function and you do not need to use the @code{.save} pseudo op
1485 immediately following the point at which the registers are saved.
1486 However, if you modify a callee-saved register, you must save it on
1487 the stack before modifying it and before calling any functions which
1488 might throw an exception. And, you must use the @code{.save} pseudo
1489 op to indicate that you have done so.
1491 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1492 modification of the stack pointer that does not save any registers.
1493 The argument is the number of bytes (in decimal) that are subtracted
1494 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1495 subtracting from the stack pointer increases the size of the stack.)
1497 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1498 indicates the register that contains the frame pointer. The first
1499 argument is the register that is set, which is typically @code{fp}.
1500 The second argument indicates the register from which the frame
1501 pointer takes its value. The third argument, if present, is the value
1502 (in decimal) added to the register specified by the second argument to
1503 compute the value of the frame pointer. You should not modify the
1504 frame pointer in the body of the function.
1506 If you do not use a frame pointer, then you should not use the
1507 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1508 should avoid modifying the stack pointer outside of the function
1509 prologue. Otherwise, the run-time library will be unable to find
1510 saved registers when it is unwinding the stack.
1512 The pseudo ops described above are sufficient for writing assembly
1513 code that calls functions which may throw exceptions. If you need to
1514 know more about the object-file format used to represent unwind
1515 information, you may consult the @cite{Exception Handling ABI for the
1516 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / thirdparty / binutils-gdb.git / blob