1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa606te} (Faraday FA606TE processor),
106 @code{fa616te} (Faraday FA616TE processor),
107 @code{fa626te} (Faraday FA626TE processor),
108 @code{fmp626} (Faraday FMP626 processor),
109 @code{fa726te} (Faraday FA726TE processor),
128 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
129 @code{i80200} (Intel XScale processor)
130 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
133 The special name @code{all} may be used to allow the
134 assembler to accept instructions valid for any ARM processor.
136 In addition to the basic instruction set, the assembler can be told to
137 accept various extension mnemonics that extend the processor using the
138 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
139 is equivalent to specifying @code{-mcpu=ep9312}.
141 Multiple extensions may be specified, separated by a @code{+}. The
142 extensions should be specified in ascending alphabetical order.
144 Some extensions may be restricted to particular architectures; this is
145 documented in the list of extensions below.
147 Extension mnemonics may also be removed from those the assembler accepts.
148 This is done be prepending @code{no} to the option that adds the extension.
149 Extensions that are removed should be listed after all extensions which have
150 been added, again in ascending alphabetical order. For example,
151 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
154 The following extensions are currently supported:
155 @code{idiv}, (Integer Divide Extensions for v7-A and v7-R architectures),
159 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
160 @code{os} (Operating System for v6M architecture),
161 @code{sec} (Security Extensions for v6K and v7-A architectures),
162 @code{virt} (Virtualization Extensions for v7-A architecture, implies
167 @cindex @code{-march=} command line option, ARM
168 @item -march=@var{architecture}[+@var{extension}@dots{}]
169 This option specifies the target architecture. The assembler will issue
170 an error message if an attempt is made to assemble an instruction which
171 will not execute on the target architecture. The following architecture
172 names are recognized:
203 If both @code{-mcpu} and
204 @code{-march} are specified, the assembler will use
205 the setting for @code{-mcpu}.
207 The architecture option can be extended with the same instruction set
208 extension options as the @code{-mcpu} option.
210 @cindex @code{-mfpu=} command line option, ARM
211 @item -mfpu=@var{floating-point-format}
213 This option specifies the floating point format to assemble for. The
214 assembler will issue an error message if an attempt is made to assemble
215 an instruction which will not execute on the target floating point unit.
216 The following format options are recognized:
236 @code{vfpv3-d16-fp16},
250 In addition to determining which instructions are assembled, this option
251 also affects the way in which the @code{.double} assembler directive behaves
252 when assembling little-endian code.
254 The default is dependent on the processor selected. For Architecture 5 or
255 later, the default is to assembler for VFP instructions; for earlier
256 architectures the default is to assemble for FPA instructions.
258 @cindex @code{-mthumb} command line option, ARM
260 This option specifies that the assembler should start assembling Thumb
261 instructions; that is, it should behave as though the file starts with a
262 @code{.code 16} directive.
264 @cindex @code{-mthumb-interwork} command line option, ARM
265 @item -mthumb-interwork
266 This option specifies that the output generated by the assembler should
267 be marked as supporting interworking.
269 @cindex @code{-mimplicit-it} command line option, ARM
270 @item -mimplicit-it=never
271 @itemx -mimplicit-it=always
272 @itemx -mimplicit-it=arm
273 @itemx -mimplicit-it=thumb
274 The @code{-mimplicit-it} option controls the behavior of the assembler when
275 conditional instructions are not enclosed in IT blocks.
276 There are four possible behaviors.
277 If @code{never} is specified, such constructs cause a warning in ARM
278 code and an error in Thumb-2 code.
279 If @code{always} is specified, such constructs are accepted in both
280 ARM and Thumb-2 code, where the IT instruction is added implicitly.
281 If @code{arm} is specified, such constructs are accepted in ARM code
282 and cause an error in Thumb-2 code.
283 If @code{thumb} is specified, such constructs cause a warning in ARM
284 code and are accepted in Thumb-2 code. If you omit this option, the
285 behavior is equivalent to @code{-mimplicit-it=arm}.
287 @cindex @code{-mapcs-26} command line option, ARM
288 @cindex @code{-mapcs-32} command line option, ARM
291 These options specify that the output generated by the assembler should
292 be marked as supporting the indicated version of the Arm Procedure.
295 @cindex @code{-matpcs} command line option, ARM
297 This option specifies that the output generated by the assembler should
298 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
299 enabled this option will cause the assembler to create an empty
300 debugging section in the object file called .arm.atpcs. Debuggers can
301 use this to determine the ABI being used by.
303 @cindex @code{-mapcs-float} command line option, ARM
305 This indicates the floating point variant of the APCS should be
306 used. In this variant floating point arguments are passed in FP
307 registers rather than integer registers.
309 @cindex @code{-mapcs-reentrant} command line option, ARM
310 @item -mapcs-reentrant
311 This indicates that the reentrant variant of the APCS should be used.
312 This variant supports position independent code.
314 @cindex @code{-mfloat-abi=} command line option, ARM
315 @item -mfloat-abi=@var{abi}
316 This option specifies that the output generated by the assembler should be
317 marked as using specified floating point ABI.
318 The following values are recognized:
324 @cindex @code{-eabi=} command line option, ARM
325 @item -meabi=@var{ver}
326 This option specifies which EABI version the produced object files should
328 The following values are recognized:
334 @cindex @code{-EB} command line option, ARM
336 This option specifies that the output generated by the assembler should
337 be marked as being encoded for a big-endian processor.
339 @cindex @code{-EL} command line option, ARM
341 This option specifies that the output generated by the assembler should
342 be marked as being encoded for a little-endian processor.
344 @cindex @code{-k} command line option, ARM
345 @cindex PIC code generation for ARM
347 This option specifies that the output of the assembler should be marked
348 as position-independent code (PIC).
350 @cindex @code{--fix-v4bx} command line option, ARM
352 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
353 the linker option of the same name.
355 @cindex @code{-mwarn-deprecated} command line option, ARM
356 @item -mwarn-deprecated
357 @itemx -mno-warn-deprecated
358 Enable or disable warnings about using deprecated options or
359 features. The default is to warn.
367 * ARM-Instruction-Set:: Instruction Set
368 * ARM-Chars:: Special Characters
369 * ARM-Regs:: Register Names
370 * ARM-Relocations:: Relocations
371 * ARM-Neon-Alignment:: NEON Alignment Specifiers
374 @node ARM-Instruction-Set
375 @subsection Instruction Set Syntax
376 Two slightly different syntaxes are support for ARM and THUMB
377 instructions. The default, @code{divided}, uses the old style where
378 ARM and THUMB instructions had their own, separate syntaxes. The new,
379 @code{unified} syntax, which can be selected via the @code{.syntax}
380 directive, and has the following main features:
384 Immediate operands do not require a @code{#} prefix.
387 The @code{IT} instruction may appear, and if it does it is validated
388 against subsequent conditional affixes. In ARM mode it does not
389 generate machine code, in THUMB mode it does.
392 For ARM instructions the conditional affixes always appear at the end
393 of the instruction. For THUMB instructions conditional affixes can be
394 used, but only inside the scope of an @code{IT} instruction.
397 All of the instructions new to the V6T2 architecture (and later) are
398 available. (Only a few such instructions can be written in the
399 @code{divided} syntax).
402 The @code{.N} and @code{.W} suffixes are recognized and honored.
405 All instructions set the flags if and only if they have an @code{s}
410 @subsection Special Characters
412 @cindex line comment character, ARM
413 @cindex ARM line comment character
414 The presence of a @samp{@@} anywhere on a line indicates the start of
415 a comment that extends to the end of that line.
417 If a @samp{#} appears as the first character of a line then the whole
418 line is treated as a comment, but in this case the line could also be
419 a logical line number directive (@pxref{Comments}) or a preprocessor
420 control command (@pxref{Preprocessing}).
422 @cindex line separator, ARM
423 @cindex statement separator, ARM
424 @cindex ARM line separator
425 The @samp{;} character can be used instead of a newline to separate
428 @cindex immediate character, ARM
429 @cindex ARM immediate character
430 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
432 @cindex identifiers, ARM
433 @cindex ARM identifiers
434 *TODO* Explain about /data modifier on symbols.
437 @subsection Register Names
439 @cindex ARM register names
440 @cindex register names, ARM
441 *TODO* Explain about ARM register naming, and the predefined names.
443 @node ARM-Neon-Alignment
444 @subsection NEON Alignment Specifiers
446 @cindex alignment for NEON instructions
447 Some NEON load/store instructions allow an optional address
449 The ARM documentation specifies that this is indicated by
450 @samp{@@ @var{align}}. However GAS already interprets
451 the @samp{@@} character as a "line comment" start,
452 so @samp{: @var{align}} is used instead. For example:
455 vld1.8 @{q0@}, [r0, :128]
458 @node ARM Floating Point
459 @section Floating Point
461 @cindex floating point, ARM (@sc{ieee})
462 @cindex ARM floating point (@sc{ieee})
463 The ARM family uses @sc{ieee} floating-point numbers.
465 @node ARM-Relocations
466 @subsection ARM relocation generation
468 @cindex data relocations, ARM
469 @cindex ARM data relocations
470 Specific data relocations can be generated by putting the relocation name
471 in parentheses after the symbol name. For example:
477 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
479 The following relocations are supported:
495 For compatibility with older toolchains the assembler also accepts
496 @code{(PLT)} after branch targets. On legacy targets this will
497 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
498 targets it will encode either the @samp{R_ARM_CALL} or
499 @samp{R_ARM_JUMP24} relocation, as appropriate.
501 @cindex MOVW and MOVT relocations, ARM
502 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
503 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
504 respectively. For example to load the 32-bit address of foo into r0:
507 MOVW r0, #:lower16:foo
508 MOVT r0, #:upper16:foo
512 @section ARM Machine Directives
514 @cindex machine directives, ARM
515 @cindex ARM machine directives
518 @c AAAAAAAAAAAAAAAAAAAAAAAAA
520 @cindex @code{.2byte} directive, ARM
521 @cindex @code{.4byte} directive, ARM
522 @cindex @code{.8byte} directive, ARM
523 @item .2byte @var{expression} [, @var{expression}]*
524 @itemx .4byte @var{expression} [, @var{expression}]*
525 @itemx .8byte @var{expression} [, @var{expression}]*
526 These directives write 2, 4 or 8 byte values to the output section.
528 @cindex @code{.align} directive, ARM
529 @item .align @var{expression} [, @var{expression}]
530 This is the generic @var{.align} directive. For the ARM however if the
531 first argument is zero (ie no alignment is needed) the assembler will
532 behave as if the argument had been 2 (ie pad to the next four byte
533 boundary). This is for compatibility with ARM's own assembler.
535 @cindex @code{.arch} directive, ARM
536 @item .arch @var{name}
537 Select the target architecture. Valid values for @var{name} are the same as
538 for the @option{-march} commandline option.
540 Specifying @code{.arch} clears any previously selected architecture
543 @cindex @code{.arch_extension} directive, ARM
544 @item .arch_extension @var{name}
545 Add or remove an architecture extension to the target architecture. Valid
546 values for @var{name} are the same as those accepted as architectural
547 extensions by the @option{-mcpu} commandline option.
549 @code{.arch_extension} may be used multiple times to add or remove extensions
550 incrementally to the architecture being compiled for.
552 @cindex @code{.arm} directive, ARM
554 This performs the same action as @var{.code 32}.
557 @cindex @code{.pad} directive, ARM
558 @item .pad #@var{count}
559 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
560 A positive value indicates the function prologue allocated stack space by
561 decrementing the stack pointer.
563 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
565 @cindex @code{.bss} directive, ARM
567 This directive switches to the @code{.bss} section.
569 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
571 @cindex @code{.cantunwind} directive, ARM
573 Prevents unwinding through the current function. No personality routine
574 or exception table data is required or permitted.
576 @cindex @code{.code} directive, ARM
577 @item .code @code{[16|32]}
578 This directive selects the instruction set being generated. The value 16
579 selects Thumb, with the value 32 selecting ARM.
581 @cindex @code{.cpu} directive, ARM
582 @item .cpu @var{name}
583 Select the target processor. Valid values for @var{name} are the same as
584 for the @option{-mcpu} commandline option.
586 Specifying @code{.cpu} clears any previously selected architecture
589 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
591 @cindex @code{.dn} and @code{.qn} directives, ARM
592 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
593 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
595 The @code{dn} and @code{qn} directives are used to create typed
596 and/or indexed register aliases for use in Advanced SIMD Extension
597 (Neon) instructions. The former should be used to create aliases
598 of double-precision registers, and the latter to create aliases of
599 quad-precision registers.
601 If these directives are used to create typed aliases, those aliases can
602 be used in Neon instructions instead of writing types after the mnemonic
603 or after each operand. For example:
612 This is equivalent to writing the following:
618 Aliases created using @code{dn} or @code{qn} can be destroyed using
621 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
623 @cindex @code{.eabi_attribute} directive, ARM
624 @item .eabi_attribute @var{tag}, @var{value}
625 Set the EABI object attribute @var{tag} to @var{value}.
627 The @var{tag} is either an attribute number, or one of the following:
628 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
629 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
630 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
631 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
632 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
633 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
634 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
635 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
636 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
637 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
638 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
639 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
640 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
641 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
642 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
643 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
644 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
645 @code{Tag_conformance}, @code{Tag_T2EE_use},
646 @code{Tag_Virtualization_use}
648 The @var{value} is either a @code{number}, @code{"string"}, or
649 @code{number, "string"} depending on the tag.
651 Note - the following legacy values are also accepted by @var{tag}:
652 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
653 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
655 @cindex @code{.even} directive, ARM
657 This directive aligns to an even-numbered address.
659 @cindex @code{.extend} directive, ARM
660 @cindex @code{.ldouble} directive, ARM
661 @item .extend @var{expression} [, @var{expression}]*
662 @itemx .ldouble @var{expression} [, @var{expression}]*
663 These directives write 12byte long double floating-point values to the
664 output section. These are not compatible with current ARM processors
667 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
670 @cindex @code{.fnend} directive, ARM
672 Marks the end of a function with an unwind table entry. The unwind index
673 table entry is created when this directive is processed.
675 If no personality routine has been specified then standard personality
676 routine 0 or 1 will be used, depending on the number of unwind opcodes
680 @cindex @code{.fnstart} directive, ARM
682 Marks the start of a function with an unwind table entry.
684 @cindex @code{.force_thumb} directive, ARM
686 This directive forces the selection of Thumb instructions, even if the
687 target processor does not support those instructions
689 @cindex @code{.fpu} directive, ARM
690 @item .fpu @var{name}
691 Select the floating-point unit to assemble for. Valid values for @var{name}
692 are the same as for the @option{-mfpu} commandline option.
694 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
695 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
697 @cindex @code{.handlerdata} directive, ARM
699 Marks the end of the current function, and the start of the exception table
700 entry for that function. Anything between this directive and the
701 @code{.fnend} directive will be added to the exception table entry.
703 Must be preceded by a @code{.personality} or @code{.personalityindex}
706 @c IIIIIIIIIIIIIIIIIIIIIIIIII
708 @cindex @code{.inst} directive, ARM
709 @item .inst @var{opcode} [ , @dots{} ]
710 @itemx .inst.n @var{opcode} [ , @dots{} ]
711 @itemx .inst.w @var{opcode} [ , @dots{} ]
712 Generates the instruction corresponding to the numerical value @var{opcode}.
713 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
714 specified explicitly, overriding the normal encoding rules.
716 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
717 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
718 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
720 @item .ldouble @var{expression} [, @var{expression}]*
723 @cindex @code{.ltorg} directive, ARM
725 This directive causes the current contents of the literal pool to be
726 dumped into the current section (which is assumed to be the .text
727 section) at the current location (aligned to a word boundary).
728 @code{GAS} maintains a separate literal pool for each section and each
729 sub-section. The @code{.ltorg} directive will only affect the literal
730 pool of the current section and sub-section. At the end of assembly
731 all remaining, un-empty literal pools will automatically be dumped.
733 Note - older versions of @code{GAS} would dump the current literal
734 pool any time a section change occurred. This is no longer done, since
735 it prevents accurate control of the placement of literal pools.
737 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
739 @cindex @code{.movsp} directive, ARM
740 @item .movsp @var{reg} [, #@var{offset}]
741 Tell the unwinder that @var{reg} contains an offset from the current
742 stack pointer. If @var{offset} is not specified then it is assumed to be
745 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
746 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
748 @cindex @code{.object_arch} directive, ARM
749 @item .object_arch @var{name}
750 Override the architecture recorded in the EABI object attribute section.
751 Valid values for @var{name} are the same as for the @code{.arch} directive.
752 Typically this is useful when code uses runtime detection of CPU features.
754 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
756 @cindex @code{.packed} directive, ARM
757 @item .packed @var{expression} [, @var{expression}]*
758 This directive writes 12-byte packed floating-point values to the
759 output section. These are not compatible with current ARM processors
762 @cindex @code{.pad} directive, ARM
763 @item .pad #@var{count}
764 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
765 A positive value indicates the function prologue allocated stack space by
766 decrementing the stack pointer.
768 @cindex @code{.personality} directive, ARM
769 @item .personality @var{name}
770 Sets the personality routine for the current function to @var{name}.
772 @cindex @code{.personalityindex} directive, ARM
773 @item .personalityindex @var{index}
774 Sets the personality routine for the current function to the EABI standard
775 routine number @var{index}
777 @cindex @code{.pool} directive, ARM
779 This is a synonym for .ltorg.
781 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
782 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
784 @cindex @code{.req} directive, ARM
785 @item @var{name} .req @var{register name}
786 This creates an alias for @var{register name} called @var{name}. For
793 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
796 @cindex @code{.save} directive, ARM
797 @item .save @var{reglist}
798 Generate unwinder annotations to restore the registers in @var{reglist}.
799 The format of @var{reglist} is the same as the corresponding store-multiple
803 @exdent @emph{core registers}
804 .save @{r4, r5, r6, lr@}
805 stmfd sp!, @{r4, r5, r6, lr@}
806 @exdent @emph{FPA registers}
809 @exdent @emph{VFP registers}
810 .save @{d8, d9, d10@}
811 fstmdx sp!, @{d8, d9, d10@}
812 @exdent @emph{iWMMXt registers}
814 wstrd wr11, [sp, #-8]!
815 wstrd wr10, [sp, #-8]!
818 wstrd wr11, [sp, #-8]!
820 wstrd wr10, [sp, #-8]!
824 @cindex @code{.setfp} directive, ARM
825 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
826 Make all unwinder annotations relative to a frame pointer. Without this
827 the unwinder will use offsets from the stack pointer.
829 The syntax of this directive is the same as the @code{add} or @code{mov}
830 instruction used to set the frame pointer. @var{spreg} must be either
831 @code{sp} or mentioned in a previous @code{.movsp} directive.
841 @cindex @code{.secrel32} directive, ARM
842 @item .secrel32 @var{expression} [, @var{expression}]*
843 This directive emits relocations that evaluate to the section-relative
844 offset of each expression's symbol. This directive is only supported
847 @cindex @code{.syntax} directive, ARM
848 @item .syntax [@code{unified} | @code{divided}]
849 This directive sets the Instruction Set Syntax as described in the
850 @ref{ARM-Instruction-Set} section.
852 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
854 @cindex @code{.thumb} directive, ARM
856 This performs the same action as @var{.code 16}.
858 @cindex @code{.thumb_func} directive, ARM
860 This directive specifies that the following symbol is the name of a
861 Thumb encoded function. This information is necessary in order to allow
862 the assembler and linker to generate correct code for interworking
863 between Arm and Thumb instructions and should be used even if
864 interworking is not going to be performed. The presence of this
865 directive also implies @code{.thumb}
867 This directive is not neccessary when generating EABI objects. On these
868 targets the encoding is implicit when generating Thumb code.
870 @cindex @code{.thumb_set} directive, ARM
872 This performs the equivalent of a @code{.set} directive in that it
873 creates a symbol which is an alias for another symbol (possibly not yet
874 defined). This directive also has the added property in that it marks
875 the aliased symbol as being a thumb function entry point, in the same
876 way that the @code{.thumb_func} directive does.
878 @cindex @code{.tlsdescseq} directive, ARM
879 @item .tlsdescseq @var{tls-variable}
880 This directive is used to annotate parts of an inlined TLS descriptor
881 trampoline. Normally the trampoline is provided by the linker, and
882 this directive is not needed.
884 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
886 @cindex @code{.unreq} directive, ARM
887 @item .unreq @var{alias-name}
888 This undefines a register alias which was previously defined using the
889 @code{req}, @code{dn} or @code{qn} directives. For example:
896 An error occurs if the name is undefined. Note - this pseudo op can
897 be used to delete builtin in register name aliases (eg 'r0'). This
898 should only be done if it is really necessary.
900 @cindex @code{.unwind_raw} directive, ARM
901 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
902 Insert one of more arbitary unwind opcode bytes, which are known to adjust
903 the stack pointer by @var{offset} bytes.
905 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
908 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
910 @cindex @code{.vsave} directive, ARM
911 @item .vsave @var{vfp-reglist}
912 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
913 using FLDMD. Also works for VFPv3 registers
914 that are to be restored using VLDM.
915 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
919 @exdent @emph{VFP registers}
920 .vsave @{d8, d9, d10@}
921 fstmdd sp!, @{d8, d9, d10@}
922 @exdent @emph{VFPv3 registers}
923 .vsave @{d15, d16, d17@}
924 vstm sp!, @{d15, d16, d17@}
927 Since FLDMX and FSTMX are now deprecated, this directive should be
928 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
930 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
931 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
932 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
933 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
941 @cindex opcodes for ARM
942 @code{@value{AS}} implements all the standard ARM opcodes. It also
943 implements several pseudo opcodes, including several synthetic load
948 @cindex @code{NOP} pseudo op, ARM
954 This pseudo op will always evaluate to a legal ARM instruction that does
955 nothing. Currently it will evaluate to MOV r0, r0.
957 @cindex @code{LDR reg,=<label>} pseudo op, ARM
960 ldr <register> , = <expression>
963 If expression evaluates to a numeric constant then a MOV or MVN
964 instruction will be used in place of the LDR instruction, if the
965 constant can be generated by either of these instructions. Otherwise
966 the constant will be placed into the nearest literal pool (if it not
967 already there) and a PC relative LDR instruction will be generated.
969 @cindex @code{ADR reg,<label>} pseudo op, ARM
972 adr <register> <label>
975 This instruction will load the address of @var{label} into the indicated
976 register. The instruction will evaluate to a PC relative ADD or SUB
977 instruction depending upon where the label is located. If the label is
978 out of range, or if it is not defined in the same file (and section) as
979 the ADR instruction, then an error will be generated. This instruction
980 will not make use of the literal pool.
982 @cindex @code{ADRL reg,<label>} pseudo op, ARM
985 adrl <register> <label>
988 This instruction will load the address of @var{label} into the indicated
989 register. The instruction will evaluate to one or two PC relative ADD
990 or SUB instructions depending upon where the label is located. If a
991 second instruction is not needed a NOP instruction will be generated in
992 its place, so that this instruction is always 8 bytes long.
994 If the label is out of range, or if it is not defined in the same file
995 (and section) as the ADRL instruction, then an error will be generated.
996 This instruction will not make use of the literal pool.
1000 For information on the ARM or Thumb instruction sets, see @cite{ARM
1001 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1004 @node ARM Mapping Symbols
1005 @section Mapping Symbols
1007 The ARM ELF specification requires that special symbols be inserted
1008 into object files to mark certain features:
1014 At the start of a region of code containing ARM instructions.
1018 At the start of a region of code containing THUMB instructions.
1022 At the start of a region of data.
1026 The assembler will automatically insert these symbols for you - there
1027 is no need to code them yourself. Support for tagging symbols ($b,
1028 $f, $p and $m) which is also mentioned in the current ARM ELF
1029 specification is not implemented. This is because they have been
1030 dropped from the new EABI and so tools cannot rely upon their
1033 @node ARM Unwinding Tutorial
1036 The ABI for the ARM Architecture specifies a standard format for
1037 exception unwind information. This information is used when an
1038 exception is thrown to determine where control should be transferred.
1039 In particular, the unwind information is used to determine which
1040 function called the function that threw the exception, and which
1041 function called that one, and so forth. This information is also used
1042 to restore the values of callee-saved registers in the function
1043 catching the exception.
1045 If you are writing functions in assembly code, and those functions
1046 call other functions that throw exceptions, you must use assembly
1047 pseudo ops to ensure that appropriate exception unwind information is
1048 generated. Otherwise, if one of the functions called by your assembly
1049 code throws an exception, the run-time library will be unable to
1050 unwind the stack through your assembly code and your program will not
1053 To illustrate the use of these pseudo ops, we will examine the code
1054 that G++ generates for the following C++ input:
1057 void callee (int *);
1068 This example does not show how to throw or catch an exception from
1069 assembly code. That is a much more complex operation and should
1070 always be done in a high-level language, such as C++, that directly
1071 supports exceptions.
1073 The code generated by one particular version of G++ when compiling the
1080 @ Function supports interworking.
1081 @ args = 0, pretend = 0, frame = 8
1082 @ frame_needed = 1, uses_anonymous_args = 0
1104 Of course, the sequence of instructions varies based on the options
1105 you pass to GCC and on the version of GCC in use. The exact
1106 instructions are not important since we are focusing on the pseudo ops
1107 that are used to generate unwind information.
1109 An important assumption made by the unwinder is that the stack frame
1110 does not change during the body of the function. In particular, since
1111 we assume that the assembly code does not itself throw an exception,
1112 the only point where an exception can be thrown is from a call, such
1113 as the @code{bl} instruction above. At each call site, the same saved
1114 registers (including @code{lr}, which indicates the return address)
1115 must be located in the same locations relative to the frame pointer.
1117 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1118 op appears immediately before the first instruction of the function
1119 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1120 op appears immediately after the last instruction of the function.
1121 These pseudo ops specify the range of the function.
1123 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1124 @code{.pad}) matters; their exact locations are irrelevant. In the
1125 example above, the compiler emits the pseudo ops with particular
1126 instructions. That makes it easier to understand the code, but it is
1127 not required for correctness. It would work just as well to emit all
1128 of the pseudo ops other than @code{.fnend} in the same order, but
1129 immediately after @code{.fnstart}.
1131 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1132 indicates registers that have been saved to the stack so that they can
1133 be restored before the function returns. The argument to the
1134 @code{.save} pseudo op is a list of registers to save. If a register
1135 is ``callee-saved'' (as specified by the ABI) and is modified by the
1136 function you are writing, then your code must save the value before it
1137 is modified and restore the original value before the function
1138 returns. If an exception is thrown, the run-time library restores the
1139 values of these registers from their locations on the stack before
1140 returning control to the exception handler. (Of course, if an
1141 exception is not thrown, the function that contains the @code{.save}
1142 pseudo op restores these registers in the function epilogue, as is
1143 done with the @code{ldmfd} instruction above.)
1145 You do not have to save callee-saved registers at the very beginning
1146 of the function and you do not need to use the @code{.save} pseudo op
1147 immediately following the point at which the registers are saved.
1148 However, if you modify a callee-saved register, you must save it on
1149 the stack before modifying it and before calling any functions which
1150 might throw an exception. And, you must use the @code{.save} pseudo
1151 op to indicate that you have done so.
1153 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1154 modification of the stack pointer that does not save any registers.
1155 The argument is the number of bytes (in decimal) that are subtracted
1156 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1157 subtracting from the stack pointer increases the size of the stack.)
1159 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1160 indicates the register that contains the frame pointer. The first
1161 argument is the register that is set, which is typically @code{fp}.
1162 The second argument indicates the register from which the frame
1163 pointer takes its value. The third argument, if present, is the value
1164 (in decimal) added to the register specified by the second argument to
1165 compute the value of the frame pointer. You should not modify the
1166 frame pointer in the body of the function.
1168 If you do not use a frame pointer, then you should not use the
1169 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1170 should avoid modifying the stack pointer outside of the function
1171 prologue. Otherwise, the run-time library will be unable to find
1172 saved registers when it is unwinding the stack.
1174 The pseudo ops described above are sufficient for writing assembly
1175 code that calls functions which may throw exceptions. If you need to
1176 know more about the object-file format used to represent unwind
1177 information, you may consult the @cite{Exception Handling ABI for the
1178 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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