gas/doc/c-m32r.texi

   1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @ifset GENERIC
   6 @page
   7 @node M32R-Dependent
   8 @chapter M32R Dependent Features
   9 @end ifset
  10 @ifclear GENERIC
  11 @node Machine Dependencies
  12 @chapter M32R Dependent Features
  13 @end ifclear
  14
  15 @cindex M32R support
  16 @menu
  17 * M32R-Opts::                   M32R Options
  18 * M32R-Warnings::               M32R Warnings
  19 @end menu
  20
  21 @node M32R-Opts
  22 @section M32R Options
  23
  24 @cindex options, M32R
  25 @cindex M32R options
  26
  27 The Mitsubishi M32R version of @code{@value{AS}} has a few machine
  28 dependent options:
  29
  30 @table @code
  31 @item -m32rx
  32 @cindex @samp{-m32rx} option, M32RX
  33 @cindex architecture options, M32RX
  34 @cindex M32R architecture options
  35 @code{@value{AS}} can assemble code for several different members of the
  36 Mitsubishi M32R family.  Normally the default is to assemble code for
  37 the M32R microprocessor.  This option may be used to change the default
  38 to the M32RX microprocessor, which adds some more instructions to the
  39 basic M32R instruction set, and some additional parameters to some of
  40 the original instructions.
  41
  42 @item -m32r
  43 @cindex @samp{-m32r} option, M32R
  44 @cindex architecture options, M32R
  45 @cindex M32R architecture options
  46 This option can be used to restore the assembler's default behaviour of
  47 assembling for the M32R microprocessor.  This can be useful if the
  48 default has been changed by a previous command line option.
  49
  50 @item -warn-explicit-parallel-conflicts
  51 @cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX
  52 Instructs @code{@value{AS}} to produce warning messages when
  53 questionable parallel instructions are encountered.  This option is
  54 enabled by default, but @code{@value{GCC}} disables it when it invokes
  55 @code{@value{AS}} directly.  Questionable instructions are those whoes
  56 behaviour would be different if they were executed sequentially.  For
  57 example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
  58 different result from @samp{mv r1, r2 \n mv r3, r1} since the former
  59 moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
  60 and r3.
  61
  62 @item -Wp
  63 @cindex @samp{-Wp} option, M32RX
  64 This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts}
  65 option.
  66
  67 @item -no-warn-explicit-parallel-conflicts
  68 @cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX
  69 Instructs @code{@value{AS}} not to produce warning messages when
  70 questionable parallel instructions are encountered.
  71
  72 @item -Wnp
  73 @cindex @samp{-Wnp} option, M32RX
  74 This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts}
  75 option.
  76
  77 @end table
  78
  79 @node M32R-Warnings
  80 @section M32R Warnings
  81
  82 @cindex warnings, M32R
  83 @cindex M32R warnings
  84
  85 There are several warning and error messages that can be produced by
  86 @code{@value{AS}} which are specific to the M32R:
  87
  88 @table @code
  89
  90 @item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
  91 This message is only produced if warnings for explicit parallel
  92 conflicts have been enabled.  It indicates that the assembler has
  93 encountered a parallel instruction in which the destination register of
  94 the left hand instruction is used as an input register in the right hand
  95 instruction.  For example in this code fragment
  96 @samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
  97 move instruction and the input to the neg instruction.
  98
  99 @item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
 100 This message is only produced if warnings for explicit parallel
 101 conflicts have been enabled.  It indicates that the assembler has
 102 encountered a parallel instruction in which the destination register of
 103 the right hand instruction is used as an input register in the left hand
 104 instruction.  For example in this code fragment
 105 @samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
 106 neg instruction and the input to the move instruction.
 107
 108 @item instruction @samp{...} is for the M32RX only
 109 This message is produced when the assembler encounters an instruction
 110 which is only supported by the M32Rx processor, and the @samp{-m32rx}
 111 command line flag has not been specified to allow assembly of such
 112 instructions.
 113
 114 @item unknown instruction @samp{...}
 115 This message is produced when the assembler encounters an instruction
 116 which it doe snot recognise.
 117
 118 @item only the NOP instruction can be issued in parallel on the m32r
 119 This message is produced when the assembler encounters a parallel
 120 instruction which does not involve a NOP instruction and the
 121 @samp{-m32rx} command line flag has not been specified.  Only the M32Rx
 122 processor is able to execute two instructions in parallel.
 123
 124 @item instruction @samp{...} cannot be executed in parallel.
 125 This message is produced when the assembler encounters a parallel
 126 instruction which is made up of one or two instructions which cannot be
 127 executed in parallel.
 128
 129 @item Instructions share the same execution pipeline
 130 This message is produced when the assembler encounters a parallel
 131 instruction whoes components both use the same execution pipeline.
 132
 133 @item Instructions write to the same destination register.
 134 This message is produced when the assembler encounters a parallel
 135 instruction where both components attempt to modify the same register.
 136 For example these code fragments will produce this message:
 137 @samp{mv r1, r2 || neg r1, r3}
 138 @samp{jl r0 || mv r14, r1}
 139 @samp{st r2, @@-r1 || mv r1, r3}
 140 @samp{mv r1, r2 || ld r0, @@r1+}
 141 @samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
 142
 143 @end table