gas/doc/c-m32r.texi

   1 @c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node M32R-Dependent
   7 @chapter M32R Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter M32R Dependent Features
  12 @end ifclear
  13
  14 @c start-sanitize-m32rx
  15
  16 @cindex M32R support
  17 @menu
  18 * M32R-Opts::                   M32R Options
  19 * M32R-Warnings::               M32R Warnings
  20 @end menu
  21
  22 @node M32R-Opts
  23 @section M32R Options
  24
  25 @cindex options, M32R
  26 @cindex M32R options
  27
  28 The Mitsubishi M32R version of @code{@value{AS}} has a few machine
  29 dependent options:
  30
  31 @table @code
  32 @item --m32rx
  33 @cindex @samp{--m32rx} option, M32RX
  34 @cindex architecture options, M32RX
  35 @cindex M32R architecture options
  36 @code{@value{AS}} can assemble code for several different members of the
  37 Mitsubishi M32R family.  Normally the default is to assemble code for
  38 the M32R microprocessor.  This option may be used to change the default
  39 to the M32RX microprocessor, which adds some more instructions to the
  40 basic M32R instruction set, and some additional parameters to some of
  41 the original instructions.
  42
  43 @item --warn-explicit-parallel-conflicts
  44 @cindex @samp{--warn-explicit-parallel-conflicts} option, M32RX
  45 Instructs @code{@value{AS}} to produce warning messages when
  46 questionable parallel instructions are encountered.  This option is
  47 enabled by default, but @code{@value{GCC}} disables it when it invokes
  48 @code{@value{AS}} directly.  Questionable instructions are those whoes
  49 behaviour would be different if they were executed sequentially.  For
  50 example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
  51 different result from @samp{mv r1, r2 \n mv r3, r1} since the former
  52 moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
  53 and r3.
  54
  55 @item --no-warn-explicit-parallel-conflicts
  56 @cindex @samp{--no-warn-explicit-parallel-conflicts} option, M32RX
  57 Instructs @code{@value{AS}} not to produce warning messages when
  58 questionable parallel instructions are encountered.
  59
  60 @end table
  61
  62 @node M32R-Warnings
  63 @section M32R Warnings
  64
  65 @cindex warnings, M32R
  66 @cindex M32R warnings
  67
  68 There are several warning and error messages that can be produced by
  69 @code{@value{AS}} which are specific to the M32R:
  70
  71 @table @code
  72
  73 @item output of first instruction is the same as the input of second instruction - is this intentional ?
  74 This message is only produced if warnings for explicit parallel
  75 conflicts have been enabled.  It indicates that the assembler has
  76 encountered a parallel instruction in which the destination register of
  77 the left hand instruction is used as an input register in the right hand
  78 instruction.  For example in this code fragment
  79 @samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
  80 move instruction and the input to the neg instruction.
  81
  82 @item output of second instruction is the same as the input of first instruction - is this intentional ?
  83 This message is only produced if warnings for explicit parallel
  84 conflicts have been enabled.  It indicates that the assembler has
  85 encountered a parallel instruction in which the destination register of
  86 the right hand instruction is used as an input register in the left hand
  87 instruction.  For example in this code fragment
  88 @samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
  89 neg instruction and the input to the move instruction.
  90
  91 @item instruction @samp{...} is for the M32RX only
  92 This message is produced when the assembler encounters an instruction
  93 which is only supported by the M32Rx processor, and the @samp{--m32rx}
  94 command line flag has not been specified to allow assembly of such
  95 instructions.
  96
  97 @item only the NOP instruction can be issued in parallel on the m32r
  98 This message is produced when the assembler encounters a parallel
  99 instruction which does not involve a NOP instruction and the
 100 @samp{--m32rx} command line flag has not been specified.  Only the M32Rx
 101 processor is able to execute two instructions in parallel.
 102
 103 @item instruction @samp{...} cannot be executed in parallel.
 104 This message is produced when the assembler encounters a parallel
 105 instruction which is made up of one or two instructions which cannot be
 106 executed in parallel.
 107
 108 @item Instructions share the same execution pipeline
 109 This message is produced when the assembler encounters a parallel
 110 instruction whoes components both use the same execution pipeline.
 111
 112 @item Both instructions write to the link register
 113 This message is produced when the assembler encounters a parallel
 114 instruction whoes components both write to the link register, one of
 115 them as a side effect.  For example this code fragment will produce this
 116 message:  @samp{jl r0 || mv r14, r1}
 117
 118 @item Destination of first instruction written to by side effect of second instruction.
 119 This message is produced when the assembler encounters a parallel
 120 instruction whoes right hand component has a side effect which modifes a
 121 register used as the destination by the left hand component.  For
 122 example this code fragment will produce this message:
 123 @samp{mv r1, r2 || ld r0, @@r1+}
 124
 125 @item Destination of second instruction written to by side effect of first instruction.
 126 This message is produced when the assembler encounters a parallel
 127 instruction whoes left hand component has a side effect which modifes a
 128 register used as the destination by the right hand component.  For
 129 example this code fragment will produce this message:
 130 @samp{st r2, @@-r1 || mv r1, r3}
 131
 132 @item Instructions write to the same destination register.
 133 This message is produced when the assembler encounters a parallel
 134 instruction where both components attempt to modify the same register.
 135 For example this code fragment will produce this message:
 136 @samp{mv r1, r2 || neg r1, r3}
 137
 138 @end table
 139 @c end-sanitize-m32rx