1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
18 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the @sc{mips} instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Opts:: Assembler options
26 * MIPS Object:: ECOFF object code
27 * MIPS Stabs:: Directives for debugging information
28 * MIPS ISA:: Directives to override the ISA level
29 * MIPS symbol sizes:: Directives to override the size of symbols
30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
31 * MIPS insn:: Directive to mark data as an instruction
32 * MIPS option stack:: Directives to save and restore options
33 * MIPS ASE instruction generation overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS floating-point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 This option sets the largest size of an object that can be referenced
49 implicitly with the @code{gp} register. It is only accepted for targets
50 that use @sc{ecoff} format. The default value is 8.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
87 Generate code for a particular MIPS Instruction Set Architecture level.
88 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
89 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
90 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
91 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
92 @samp{-mips64}, and @samp{-mips64r2}
94 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
95 and @sc{MIPS64 Release 2}
96 ISA processors, respectively. You can also switch
97 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
98 override the ISA level}.
102 Some macros have different expansions for 32-bit and 64-bit registers.
103 The register sizes are normally inferred from the ISA and ABI, but these
104 flags force a certain group of registers to be treated as 32 bits wide at
105 all times. @samp{-mgp32} controls the size of general-purpose registers
106 and @samp{-mfp32} controls the size of floating-point registers.
108 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
109 of registers to be changed for parts of an object. The default value is
110 restored by @code{.set gp=default} and @code{.set fp=default}.
112 On some MIPS variants there is a 32-bit mode flag; when this flag is
113 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
114 save the 32-bit registers on a context switch, so it is essential never
115 to use the 64-bit registers.
119 Assume that 64-bit registers are available. This is provided in the
120 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
122 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
123 of registers to be changed for parts of an object. The default value is
124 restored by @code{.set gp=default} and @code{.set fp=default}.
128 Generate code for the MIPS 16 processor. This is equivalent to putting
129 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
130 turns off this option.
133 @itemx -mno-micromips
134 Generate code for the microMIPS processor. This is equivalent to putting
135 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
136 turns off this option. This is equivalent to putting @code{.set nomicromips}
137 at the start of the assembly file.
140 @itemx -mno-smartmips
141 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
142 provides a number of new instructions which target smartcard and
143 cryptographic applications. This is equivalent to putting
144 @code{.set smartmips} at the start of the assembly file.
145 @samp{-mno-smartmips} turns off this option.
149 Generate code for the MIPS-3D Application Specific Extension.
150 This tells the assembler to accept MIPS-3D instructions.
151 @samp{-no-mips3d} turns off this option.
155 Generate code for the MDMX Application Specific Extension.
156 This tells the assembler to accept MDMX instructions.
157 @samp{-no-mdmx} turns off this option.
161 Generate code for the DSP Release 1 Application Specific Extension.
162 This tells the assembler to accept DSP Release 1 instructions.
163 @samp{-mno-dsp} turns off this option.
167 Generate code for the DSP Release 2 Application Specific Extension.
168 This option implies -mdsp.
169 This tells the assembler to accept DSP Release 2 instructions.
170 @samp{-mno-dspr2} turns off this option.
174 Generate code for the MT Application Specific Extension.
175 This tells the assembler to accept MT instructions.
176 @samp{-mno-mt} turns off this option.
180 Generate code for the MCU Application Specific Extension.
181 This tells the assembler to accept MCU instructions.
182 @samp{-mno-mcu} turns off this option.
186 Generate code for the Virtualization Application Specific Extension.
187 This tells the assembler to accept Virtualization instructions.
188 @samp{-mno-virt} turns off this option.
192 Cause nops to be inserted if the read of the destination register
193 of an mfhi or mflo instruction occurs in the following two instructions.
195 @item -mfix-loongson2f-jump
196 @itemx -mno-fix-loongson2f-jump
197 Eliminate instruction fetch from outside 256M region to work around the
198 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
199 the kernel may crash. The issue has been solved in latest processor
200 batches, but this fix has no side effect to them.
202 @item -mfix-loongson2f-nop
203 @itemx -mno-fix-loongson2f-nop
204 Replace nops by @code{or at,at,zero} to work around the Loongson2F
205 @samp{nop} errata. Without it, under extreme cases, cpu might
206 deadlock. The issue has been solved in latest loongson2f batches, but
207 this fix has no side effect to them.
210 @itemx -mno-fix-vr4120
211 Insert nops to work around certain VR4120 errata. This option is
212 intended to be used on GCC-generated code: it is not designed to catch
213 all problems in hand-written assembler code.
216 @itemx -mno-fix-vr4130
217 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
221 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
224 @itemx -mno-fix-cn63xxp1
225 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
226 certain CN63XXP1 errata.
230 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
231 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
232 etc.), and to not schedule @samp{nop} instructions around accesses to
233 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
238 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
239 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
240 instructions around accesses to the @samp{HI} and @samp{LO} registers.
241 @samp{-no-m4650} turns off this option.
247 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
248 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
249 specific to that chip, and to schedule for that chip's hazards.
251 @item -march=@var{cpu}
252 Generate code for a particular MIPS cpu. It is exactly equivalent to
253 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
254 understood. Valid @var{cpu} value are:
339 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
340 accepted as synonyms for @samp{@var{n}f1_1}. These values are
343 @item -mtune=@var{cpu}
344 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
345 identical to @samp{-march=@var{cpu}}.
347 @item -mabi=@var{abi}
348 Record which ABI the source code uses. The recognized arguments
349 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
355 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
356 the beginning of the assembler input. @xref{MIPS symbol sizes}.
358 @cindex @code{-nocpp} ignored (MIPS)
360 This option is ignored. It is accepted for command-line compatibility with
361 other assemblers, which use it to turn off C style preprocessing. With
362 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
363 @sc{gnu} assembler itself never runs the C preprocessor.
367 Disable or enable floating-point instructions. Note that by default
368 floating-point instructions are always allowed even with CPU targets
369 that don't have support for these instructions.
372 @itemx -mdouble-float
373 Disable or enable double-precision floating-point operations. Note
374 that by default double-precision floating-point operations are always
375 allowed even with CPU targets that don't have support for these
378 @item --construct-floats
379 @itemx --no-construct-floats
380 The @code{--no-construct-floats} option disables the construction of
381 double width floating point constants by loading the two halves of the
382 value into the two single width floating point registers that make up
383 the double width register. This feature is useful if the processor
384 support the FR bit in its status register, and this bit is known (by
385 the programmer) to be set. This bit prevents the aliasing of the double
386 width register by the single width registers.
388 By default @code{--construct-floats} is selected, allowing construction
389 of these floating point constants.
393 @c FIXME! (1) reflect these options (next item too) in option summaries;
394 @c (2) stop teasing, say _which_ instructions expanded _how_.
395 @code{@value{AS}} automatically macro expands certain division and
396 multiplication instructions to check for overflow and division by zero. This
397 option causes @code{@value{AS}} to generate code to take a trap exception
398 rather than a break exception when an error is detected. The trap instructions
399 are only supported at Instruction Set Architecture level 2 and higher.
403 Generate code to take a break exception rather than a trap exception when an
404 error is detected. This is the default.
408 Control generation of @code{.pdr} sections. Off by default on IRIX, on
413 When generating code using the Unix calling conventions (selected by
414 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
415 which can go into a shared library. The @samp{-mno-shared} option
416 tells gas to generate code which uses the calling convention, but can
417 not go into a shared library. The resulting code is slightly more
418 efficient. This option only affects the handling of the
419 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
423 @section MIPS ECOFF object code
425 @cindex ECOFF sections
426 @cindex MIPS ECOFF sections
427 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
428 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
429 additional sections are @code{.rdata}, used for read-only data,
430 @code{.sdata}, used for small data, and @code{.sbss}, used for small
433 @cindex small objects, MIPS ECOFF
434 @cindex @code{gp} register, MIPS
435 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
436 register to form the address of a ``small object''. Any object in the
437 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
438 For external objects, or for objects in the @code{.bss} section, you can use
439 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
440 @code{$gp}; the default value is 8, meaning that a reference to any object
441 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
442 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
443 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
444 or @code{sbss} in any case). The size of an object in the @code{.bss} section
445 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
446 size of an external object may be set with the @code{.extern} directive. For
447 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
448 in length, whie leaving @code{sym} otherwise undefined.
450 Using small @sc{ecoff} objects requires linker support, and assumes that the
451 @code{$gp} register is correctly initialized (normally done automatically by
452 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
456 @section Directives for debugging information
458 @cindex MIPS debugging directives
459 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
460 generating debugging information which are not support by traditional @sc{mips}
461 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
462 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
463 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
464 generated by the three @code{.stab} directives can only be read by @sc{gdb},
465 not by traditional @sc{mips} debuggers (this enhancement is required to fully
466 support C++ debugging). These directives are primarily used by compilers, not
467 assembly language programmers!
469 @node MIPS symbol sizes
470 @section Directives to override the size of symbols
472 @cindex @code{.set sym32}
473 @cindex @code{.set nosym32}
474 The n64 ABI allows symbols to have any 64-bit value. Although this
475 provides a great deal of flexibility, it means that some macros have
476 much longer expansions than their 32-bit counterparts. For example,
477 the non-PIC expansion of @samp{dla $4,sym} is usually:
482 daddiu $4,$4,%higher(sym)
483 daddiu $1,$1,%lo(sym)
488 whereas the 32-bit expansion is simply:
492 daddiu $4,$4,%lo(sym)
495 n64 code is sometimes constructed in such a way that all symbolic
496 constants are known to have 32-bit values, and in such cases, it's
497 preferable to use the 32-bit expansion instead of the 64-bit
500 You can use the @code{.set sym32} directive to tell the assembler
501 that, from this point on, all expressions of the form
502 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
503 have 32-bit values. For example:
512 will cause the assembler to treat @samp{sym}, @code{sym+16} and
513 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
514 addresses is not affected.
516 The directive @code{.set nosym32} ends a @code{.set sym32} block and
517 reverts to the normal behavior. It is also possible to change the
518 symbol size using the command-line options @option{-msym32} and
521 These options and directives are always accepted, but at present,
522 they have no effect for anything other than n64.
525 @section Directives to override the ISA level
527 @cindex MIPS ISA override
528 @kindex @code{.set mips@var{n}}
529 @sc{gnu} @code{@value{AS}} supports an additional directive to change
530 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
531 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
533 The values other than 0 make the assembler accept instructions
534 for the corresponding @sc{isa} level, from that point on in the
535 assembly. @code{.set mips@var{n}} affects not only which instructions
536 are permitted, but also how certain macros are expanded. @code{.set
537 mips0} restores the @sc{isa} level to its original level: either the
538 level you selected with command line options, or the default for your
539 configuration. You can use this feature to permit specific @sc{mips3}
540 instructions while assembling in 32 bit mode. Use this directive with
543 @cindex MIPS CPU override
544 @kindex @code{.set arch=@var{cpu}}
545 The @code{.set arch=@var{cpu}} directive provides even finer control.
546 It changes the effective CPU target and allows the assembler to use
547 instructions specific to a particular CPU. All CPUs supported by the
548 @samp{-march} command line option are also selectable by this directive.
549 The original value is restored by @code{.set arch=default}.
551 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
552 in which it will assemble instructions for the MIPS 16 processor. Use
553 @code{.set nomips16} to return to normal 32 bit mode.
555 Traditional @sc{mips} assemblers do not support this directive.
557 The directive @code{.set micromips} puts the assembler into microMIPS mode,
558 in which it will assemble instructions for the microMIPS processor. Use
559 @code{.set nomicromips} to return to normal 32 bit mode.
561 Traditional @sc{mips} assemblers do not support this directive.
563 @node MIPS autoextend
564 @section Directives for extending MIPS 16 bit instructions
566 @kindex @code{.set autoextend}
567 @kindex @code{.set noautoextend}
568 By default, MIPS 16 instructions are automatically extended to 32 bits
569 when necessary. The directive @code{.set noautoextend} will turn this
570 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
571 must be explicitly extended with the @code{.e} modifier (e.g.,
572 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
573 to once again automatically extend instructions when necessary.
575 This directive is only meaningful when in MIPS 16 mode. Traditional
576 @sc{mips} assemblers do not support this directive.
579 @section Directive to mark data as an instruction
582 The @code{.insn} directive tells @code{@value{AS}} that the following
583 data is actually instructions. This makes a difference in MIPS 16 and
584 microMIPS modes: when loading the address of a label which precedes
585 instructions, @code{@value{AS}} automatically adds 1 to the value, so
586 that jumping to the loaded address will do the right thing.
588 @kindex @code{.global}
589 The @code{.global} and @code{.globl} directives supported by
590 @code{@value{AS}} will by default mark the symbol as pointing to a
591 region of data not code. This means that, for example, any
592 instructions following such a symbol will not be disassembled by
593 @code{objdump} as it will regard them as data. To change this
594 behaviour an optional section name can be placed after the symbol name
595 in the @code{.global} directive. If this section exists and is known
596 to be a code section, then the symbol will be marked as poiting at
597 code not data. Ie the syntax for the directive is:
599 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
601 Here is a short example:
604 .global foo .text, bar, baz .data
614 @node MIPS option stack
615 @section Directives to save and restore options
617 @cindex MIPS option stack
618 @kindex @code{.set push}
619 @kindex @code{.set pop}
620 The directives @code{.set push} and @code{.set pop} may be used to save
621 and restore the current settings for all the options which are
622 controlled by @code{.set}. The @code{.set push} directive saves the
623 current settings on a stack. The @code{.set pop} directive pops the
624 stack and restores the settings.
626 These directives can be useful inside an macro which must change an
627 option such as the ISA level or instruction reordering but does not want
628 to change the state of the code which invoked the macro.
630 Traditional @sc{mips} assemblers do not support these directives.
632 @node MIPS ASE instruction generation overrides
633 @section Directives to control generation of MIPS ASE instructions
635 @cindex MIPS MIPS-3D instruction generation override
636 @kindex @code{.set mips3d}
637 @kindex @code{.set nomips3d}
638 The directive @code{.set mips3d} makes the assembler accept instructions
639 from the MIPS-3D Application Specific Extension from that point on
640 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
641 instructions from being accepted.
643 @cindex SmartMIPS instruction generation override
644 @kindex @code{.set smartmips}
645 @kindex @code{.set nosmartmips}
646 The directive @code{.set smartmips} makes the assembler accept
647 instructions from the SmartMIPS Application Specific Extension to the
648 MIPS32 @sc{isa} from that point on in the assembly. The
649 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
652 @cindex MIPS MDMX instruction generation override
653 @kindex @code{.set mdmx}
654 @kindex @code{.set nomdmx}
655 The directive @code{.set mdmx} makes the assembler accept instructions
656 from the MDMX Application Specific Extension from that point on
657 in the assembly. The @code{.set nomdmx} directive prevents MDMX
658 instructions from being accepted.
660 @cindex MIPS DSP Release 1 instruction generation override
661 @kindex @code{.set dsp}
662 @kindex @code{.set nodsp}
663 The directive @code{.set dsp} makes the assembler accept instructions
664 from the DSP Release 1 Application Specific Extension from that point
665 on in the assembly. The @code{.set nodsp} directive prevents DSP
666 Release 1 instructions from being accepted.
668 @cindex MIPS DSP Release 2 instruction generation override
669 @kindex @code{.set dspr2}
670 @kindex @code{.set nodspr2}
671 The directive @code{.set dspr2} makes the assembler accept instructions
672 from the DSP Release 2 Application Specific Extension from that point
673 on in the assembly. This dirctive implies @code{.set dsp}. The
674 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
677 @cindex MIPS MT instruction generation override
678 @kindex @code{.set mt}
679 @kindex @code{.set nomt}
680 The directive @code{.set mt} makes the assembler accept instructions
681 from the MT Application Specific Extension from that point on
682 in the assembly. The @code{.set nomt} directive prevents MT
683 instructions from being accepted.
685 @cindex MIPS MCU instruction generation override
686 @kindex @code{.set mcu}
687 @kindex @code{.set nomcu}
688 The directive @code{.set mcu} makes the assembler accept instructions
689 from the MCU Application Specific Extension from that point on
690 in the assembly. The @code{.set nomcu} directive prevents MCU
691 instructions from being accepted.
693 @cindex Virtualization instruction generation override
694 @kindex @code{.set virt}
695 @kindex @code{.set novirt}
696 The directive @code{.set virt} makes the assembler accept instructions
697 from the Virtualization Application Specific Extension from that point
698 on in the assembly. The @code{.set novirt} directive prevents Virtualization
699 instructions from being accepted.
701 Traditional @sc{mips} assemblers do not support these directives.
703 @node MIPS floating-point
704 @section Directives to override floating-point options
706 @cindex Disable floating-point instructions
707 @kindex @code{.set softfloat}
708 @kindex @code{.set hardfloat}
709 The directives @code{.set softfloat} and @code{.set hardfloat} provide
710 finer control of disabling and enabling float-point instructions.
711 These directives always override the default (that hard-float
712 instructions are accepted) or the command-line options
713 (@samp{-msoft-float} and @samp{-mhard-float}).
715 @cindex Disable single-precision floating-point operations
716 @kindex @code{.set singlefloat}
717 @kindex @code{.set doublefloat}
718 The directives @code{.set singlefloat} and @code{.set doublefloat}
719 provide finer control of disabling and enabling double-precision
720 float-point operations. These directives always override the default
721 (that double-precision operations are accepted) or the command-line
722 options (@samp{-msingle-float} and @samp{-mdouble-float}).
724 Traditional @sc{mips} assemblers do not support these directives.
727 @section Syntactical considerations for the MIPS assembler
729 * MIPS-Chars:: Special Characters
733 @subsection Special Characters
735 @cindex line comment character, MIPS
736 @cindex MIPS line comment character
737 The presence of a @samp{#} on a line indicates the start of a comment
738 that extends to the end of the current line.
740 If a @samp{#} appears as the first character of a line, the whole line
741 is treated as a comment, but in this case the line can also be a
742 logical line number directive (@pxref{Comments}) or a
743 preprocessor control command (@pxref{Preprocessing}).
745 @cindex line separator, MIPS
746 @cindex statement separator, MIPS
747 @cindex MIPS line separator
748 The @samp{;} character can be used to separate statements on the same