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1 /* IA-32 common hooks.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512DQ_SET \
68 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512BW_SET \
70 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512VL_SET \
72 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512IFMA_SET \
74 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
76 #define OPTION_MASK_ISA_AVX512VBMI_SET \
77 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
78 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
79 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
80 #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
81 #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
82 #define OPTION_MASK_ISA_AVX512VNNI_SET \
83 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
84 #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
85 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
86 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512BITALG_SET \
88 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
89 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
90 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
91 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
92 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
93 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
94 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
95 #define OPTION_MASK_ISA_XSAVES_SET \
96 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
97 #define OPTION_MASK_ISA_XSAVEC_SET \
98 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
99 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
100 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
101 #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
102 #define OPTION_MASK_ISA2_AMX_INT8_SET \
103 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
104 #define OPTION_MASK_ISA2_AMX_BF16_SET \
105 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
106 #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
107 #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
108 #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
109 #define OPTION_MASK_ISA2_AMX_FP16_SET \
110 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
111 #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
112 #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
113 #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
114 (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
115 #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
116 #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
117 #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
118 #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
119 #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
120 #define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
121 #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
122 #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
123 #define OPTION_MASK_ISA2_AVX10_1_512_SET \
124 (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
125
126 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
127 as -msse4.2. */
128 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
129
130 #define OPTION_MASK_ISA_SSE4A_SET \
131 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
132 #define OPTION_MASK_ISA_FMA4_SET \
133 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
134 | OPTION_MASK_ISA_AVX_SET)
135 #define OPTION_MASK_ISA_XOP_SET \
136 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
137 #define OPTION_MASK_ISA_LWP_SET \
138 OPTION_MASK_ISA_LWP
139
140 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
141 #define OPTION_MASK_ISA_AES_SET \
142 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
143 #define OPTION_MASK_ISA_SHA_SET \
144 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
145 #define OPTION_MASK_ISA_PCLMUL_SET \
146 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
147
148 #define OPTION_MASK_ISA_ABM_SET \
149 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
150
151 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
152 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
153 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
154 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
155 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
156 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
157 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
158 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
159 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
160 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
161 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
162 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
163
164 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
165 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
166 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
167 #define OPTION_MASK_ISA_F16C_SET \
168 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
169 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
170 #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
171 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
172 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
173 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
174 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
175 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
176 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
177 #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
178 (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
179 | OPTION_MASK_ISA_AVX_SET)
180 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
181 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
182 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
183 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
184 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
185 #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
186 #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
187 #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
188 #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
189 #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
190 #define OPTION_MASK_ISA2_WIDEKL_SET \
191 (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
192
193 /* Define a set of ISAs which aren't available when a given ISA is
194 disabled. MMX and SSE ISAs are handled separately. */
195
196 #define OPTION_MASK_ISA_MMX_UNSET \
197 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
198 #define OPTION_MASK_ISA_3DNOW_UNSET \
199 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
200 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
201
202 #define OPTION_MASK_ISA_SSE_UNSET \
203 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
204 #define OPTION_MASK_ISA_SSE2_UNSET \
205 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
206 #define OPTION_MASK_ISA_SSE3_UNSET \
207 (OPTION_MASK_ISA_SSE3 \
208 | OPTION_MASK_ISA_SSSE3_UNSET \
209 | OPTION_MASK_ISA_SSE4A_UNSET )
210 #define OPTION_MASK_ISA_SSSE3_UNSET \
211 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
212 #define OPTION_MASK_ISA_SSE4_1_UNSET \
213 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
214 #define OPTION_MASK_ISA_SSE4_2_UNSET \
215 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
216 #define OPTION_MASK_ISA_AVX_UNSET \
217 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
218 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
219 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
220 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
221 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
222 #define OPTION_MASK_ISA_XSAVE_UNSET \
223 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
224 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
225 | OPTION_MASK_ISA_AVX_UNSET)
226 #define OPTION_MASK_ISA2_XSAVE_UNSET \
227 (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
228 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
229 #define OPTION_MASK_ISA_AVX2_UNSET \
230 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
231 #define OPTION_MASK_ISA2_AVX2_UNSET \
232 (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
233 | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
234 | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
235 | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
236 #define OPTION_MASK_ISA_AVX512F_UNSET \
237 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
238 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
239 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
240 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
241 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
242 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
243 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
244 #define OPTION_MASK_ISA_AVX512BW_UNSET \
245 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
246 | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
247 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
248 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
249 #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
250 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
251 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
252 #define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET
253 #define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16
254 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
255 #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
256 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
257 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
258 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
259 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
260 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
261 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
262 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
263 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
264 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
265 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
266 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
267 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
268 #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
269 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
270 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
271 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
272 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
273 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
274 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
275 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
276 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
277 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
278 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
279 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
280 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
281 #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
282 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
283 #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
284 #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
285 (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
286 | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
287 | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET)
288 #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
289 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
290 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
291 #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
292 #define OPTION_MASK_ISA2_KL_UNSET \
293 (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
294 #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
295 #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
296 #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
297 #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
298 #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
299 #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
300 #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
301 #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
302 #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
303 #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
304 #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
305 #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
306 #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
307 #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
308 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
309 #define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
310 (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
311 #define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
312
313 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
314 as -mno-sse4.1. */
315 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
316
317 #define OPTION_MASK_ISA_SSE4A_UNSET \
318 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
319
320 #define OPTION_MASK_ISA_FMA4_UNSET \
321 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
322 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
323 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
324
325 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
326 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
327 #define OPTION_MASK_ISA_PCLMUL_UNSET \
328 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
329 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
330 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
331 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
332 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
333 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
334 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
335 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
336 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
337 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
338 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
339 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
340 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
341 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
342
343 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
344 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
345 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
346 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
347
348 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
349 (OPTION_MASK_ISA_MMX_UNSET \
350 | OPTION_MASK_ISA_SSE_UNSET)
351
352 #define OPTION_MASK_ISA2_AVX512F_UNSET \
353 (OPTION_MASK_ISA2_AVX512BW_UNSET \
354 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
355 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
356 OPTION_MASK_ISA2_SSE_UNSET
357 #define OPTION_MASK_ISA2_AVX_UNSET \
358 (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
359 | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
360 | OPTION_MASK_ISA2_SM4_UNSET)
361 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
362 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
363 #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
364 #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
365 #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
366 #define OPTION_MASK_ISA2_SSE2_UNSET \
367 (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
368 #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
369
370 #define OPTION_MASK_ISA2_AVX512BW_UNSET \
371 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
372 | OPTION_MASK_ISA2_AVX512FP16_UNSET)
373
374 /* Set 1 << value as value of -malign-FLAG option. */
375
376 static void
377 set_malign_value (const char **flag, unsigned value)
378 {
379 char *r = XNEWVEC (char, 6);
380 sprintf (r, "%d", 1 << value);
381 *flag = r;
382 }
383
384 /* Implement TARGET_HANDLE_OPTION. */
385
386 bool
387 ix86_handle_option (struct gcc_options *opts,
388 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
389 const struct cl_decoded_option *decoded,
390 location_t loc)
391 {
392 size_t code = decoded->opt_index;
393 int value = decoded->value;
394
395 switch (code)
396 {
397 case OPT_mgeneral_regs_only:
398 if (value)
399 {
400 HOST_WIDE_INT general_regs_only_flags = 0;
401 HOST_WIDE_INT general_regs_only_flags2 = 0;
402
403 /* NB: Enable the GPR only instructions which are enabled
404 implicitly by SSE ISAs unless they have been disabled
405 explicitly. */
406 if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
407 {
408 if (!TARGET_EXPLICIT_CRC32_P (opts))
409 general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
410 if (!TARGET_EXPLICIT_POPCNT_P (opts))
411 general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
412 }
413 if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
414 {
415 if (!TARGET_EXPLICIT_MWAIT_P (opts))
416 general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
417 }
418
419 /* Disable MMX, SSE and x87 instructions if only
420 general registers are allowed. */
421 opts->x_ix86_isa_flags
422 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
423 opts->x_ix86_isa_flags2
424 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
425 opts->x_ix86_isa_flags |= general_regs_only_flags;
426 opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
427 opts->x_ix86_isa_flags_explicit
428 |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
429 | general_regs_only_flags);
430 opts->x_ix86_isa_flags2_explicit
431 |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
432 | general_regs_only_flags2);
433
434 opts->x_target_flags &= ~MASK_80387;
435 }
436 else
437 gcc_unreachable ();
438 return true;
439
440 case OPT_mmmx:
441 if (value)
442 {
443 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
444 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
445 }
446 else
447 {
448 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
449 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
450 }
451 return true;
452
453 case OPT_m3dnow:
454 if (value)
455 {
456 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
457 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
458 }
459 else
460 {
461 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
462 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
463 }
464 return true;
465
466 case OPT_m3dnowa:
467 if (value)
468 {
469 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
470 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
471 }
472 else
473 {
474 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
475 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
476 }
477 return true;
478
479 case OPT_msse:
480 if (value)
481 {
482 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
483 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
484 }
485 else
486 {
487 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
488 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
489 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
490 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
491 }
492 return true;
493
494 case OPT_msse2:
495 if (value)
496 {
497 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
498 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
499 }
500 else
501 {
502 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
503 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
504 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
505 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
506 }
507 return true;
508
509 case OPT_msse3:
510 if (value)
511 {
512 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
513 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
514 }
515 else
516 {
517 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
518 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
519 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
520 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
521 }
522 return true;
523
524 case OPT_mssse3:
525 if (value)
526 {
527 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
529 }
530 else
531 {
532 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
533 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
534 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
535 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
536 }
537 return true;
538
539 case OPT_msse4_1:
540 if (value)
541 {
542 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
543 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
544 }
545 else
546 {
547 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
548 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
549 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
550 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
551 }
552 return true;
553
554 case OPT_msse4_2:
555 if (value)
556 {
557 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
558 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
559 }
560 else
561 {
562 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
563 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
564 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
565 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
566 }
567 return true;
568
569 case OPT_mavx:
570 if (value)
571 {
572 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
573 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
574 }
575 else
576 {
577 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
578 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
579 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
580 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
581 }
582 return true;
583
584 case OPT_mavx2:
585 if (value)
586 {
587 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
588 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
589 }
590 else
591 {
592 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
593 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
594 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
595 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
596 }
597 return true;
598
599 case OPT_mavx512f:
600 if (value)
601 {
602 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
603 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
604 }
605 else
606 {
607 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
608 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
609 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
610 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
611 opts->x_ix86_no_avx512_explicit = 1;
612 }
613 return true;
614
615 case OPT_mavx512cd:
616 if (value)
617 {
618 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
619 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
620 }
621 else
622 {
623 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
624 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
625 opts->x_ix86_no_avx512_explicit = 1;
626 }
627 return true;
628
629 case OPT_mrdpid:
630 if (value)
631 {
632 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
633 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
634 }
635 else
636 {
637 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
638 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
639 }
640 return true;
641
642 case OPT_mgfni:
643 if (value)
644 {
645 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
646 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
647 }
648 else
649 {
650 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
651 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
652 }
653 return true;
654
655 case OPT_mshstk:
656 if (value)
657 {
658 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
659 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
660 }
661 else
662 {
663 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
664 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
665 }
666 return true;
667
668 case OPT_mvaes:
669 if (value)
670 {
671 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
672 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
673 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
674 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
675 }
676 else
677 {
678 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
679 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
680 }
681 return true;
682
683 case OPT_mvpclmulqdq:
684 if (value)
685 {
686 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
687 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
688 }
689 else
690 {
691 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
692 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
693 }
694 return true;
695
696 case OPT_mmovdiri:
697 if (value)
698 {
699 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
700 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
701 }
702 else
703 {
704 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
705 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
706 }
707 return true;
708
709 case OPT_mmovdir64b:
710 if (value)
711 {
712 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
713 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
714 }
715 else
716 {
717 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
718 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
719 }
720 return true;
721
722 case OPT_mcldemote:
723 if (value)
724 {
725 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
726 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
727 }
728 else
729 {
730 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
731 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
732 }
733 return true;
734
735 case OPT_mwaitpkg:
736 if (value)
737 {
738 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
739 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
740 }
741 else
742 {
743 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
744 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
745 }
746 return true;
747
748 case OPT_menqcmd:
749 if (value)
750 {
751 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
752 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
753 }
754 else
755 {
756 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
757 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
758 }
759 return true;
760
761 case OPT_mkl:
762 if (value)
763 {
764 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
765 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
766
767 /* The Keylocker instructions need XMM registers from SSE2. */
768 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
769 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
770 }
771 else
772 {
773 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
774 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
775 }
776 return true;
777
778 case OPT_mwidekl:
779 if (value)
780 {
781 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
782 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
783
784 /* The Widekl instructions need XMM registers from SSE2. */
785 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
786 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
787 }
788 else
789 {
790 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
791 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
792 }
793 return true;
794
795 case OPT_mserialize:
796 if (value)
797 {
798 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
799 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
800 }
801 else
802 {
803 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
804 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
805 }
806 return true;
807
808 case OPT_muintr:
809 if (value)
810 {
811 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
812 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
813 }
814 else
815 {
816 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
817 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
818 }
819 return true;
820
821 case OPT_mhreset:
822 if (value)
823 {
824 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
825 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
826 }
827 else
828 {
829 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
830 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
831 }
832 return true;
833
834 case OPT_mavx512vbmi2:
835 if (value)
836 {
837 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
838 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
839 }
840 else
841 {
842 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
843 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
844 opts->x_ix86_no_avx512_explicit = 1;
845 }
846 return true;
847
848 case OPT_mavx512fp16:
849 if (value)
850 {
851 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
852 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
853 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
854 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
855 }
856 else
857 {
858 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
859 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
860 opts->x_ix86_no_avx512_explicit = 1;
861 }
862 return true;
863
864 case OPT_mavx512vnni:
865 if (value)
866 {
867 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
868 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
869 }
870 else
871 {
872 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
873 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
874 opts->x_ix86_no_avx512_explicit = 1;
875 }
876 return true;
877
878 case OPT_mavx512vpopcntdq:
879 if (value)
880 {
881 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
882 opts->x_ix86_isa_flags_explicit
883 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
884 }
885 else
886 {
887 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
888 opts->x_ix86_isa_flags_explicit
889 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
890 opts->x_ix86_no_avx512_explicit = 1;
891 }
892 return true;
893
894 case OPT_mavx512bitalg:
895 if (value)
896 {
897 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
898 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
899 }
900 else
901 {
902 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
903 opts->x_ix86_isa_flags_explicit
904 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
905 opts->x_ix86_no_avx512_explicit = 1;
906 }
907 return true;
908
909 case OPT_mavx512bf16:
910 if (value)
911 {
912 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
913 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
914 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
915 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
916 }
917 else
918 {
919 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
920 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
921 opts->x_ix86_no_avx512_explicit = 1;
922 }
923 return true;
924
925 case OPT_mavxvnni:
926 if (value)
927 {
928 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
929 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
930 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
931 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
932 }
933 else
934 {
935 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
936 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
937 }
938 return true;
939
940 case OPT_msgx:
941 if (value)
942 {
943 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
944 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
945 }
946 else
947 {
948 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
949 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
950 }
951 return true;
952
953 case OPT_mpconfig:
954 if (value)
955 {
956 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
957 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
958 }
959 else
960 {
961 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
962 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
963 }
964 return true;
965
966 case OPT_mwbnoinvd:
967 if (value)
968 {
969 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
970 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
971 }
972 else
973 {
974 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
975 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
976 }
977 return true;
978
979 case OPT_mavx512dq:
980 if (value)
981 {
982 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
983 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
984 }
985 else
986 {
987 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
988 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
989 opts->x_ix86_no_avx512_explicit = 1;
990 }
991 return true;
992
993 case OPT_mavx512bw:
994 if (value)
995 {
996 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
997 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
998 }
999 else
1000 {
1001 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1002 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1003 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1004 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1005 opts->x_ix86_no_avx512_explicit = 1;
1006 }
1007 return true;
1008
1009 case OPT_mavx512vl:
1010 if (value)
1011 {
1012 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1013 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1014 }
1015 else
1016 {
1017 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1018 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1019 opts->x_ix86_no_avx512_explicit = 1;
1020 }
1021 return true;
1022
1023 case OPT_mavx512ifma:
1024 if (value)
1025 {
1026 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1027 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1028 }
1029 else
1030 {
1031 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1032 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1033 opts->x_ix86_no_avx512_explicit = 1;
1034 }
1035 return true;
1036
1037 case OPT_mavx512vbmi:
1038 if (value)
1039 {
1040 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1041 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1042 }
1043 else
1044 {
1045 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1046 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1047 opts->x_ix86_no_avx512_explicit = 1;
1048 }
1049 return true;
1050
1051 case OPT_mavx512vp2intersect:
1052 if (value)
1053 {
1054 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1055 opts->x_ix86_isa_flags2_explicit |=
1056 OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1057 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1058 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1059 }
1060 else
1061 {
1062 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1063 opts->x_ix86_isa_flags2_explicit |=
1064 OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1065 }
1066 return true;
1067
1068 case OPT_mtsxldtrk:
1069 if (value)
1070 {
1071 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1072 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1073 }
1074 else
1075 {
1076 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1077 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1078 }
1079 return true;
1080
1081 case OPT_mamx_tile:
1082 if (value)
1083 {
1084 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1085 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1086 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1087 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1088 }
1089 else
1090 {
1091 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1092 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1093 }
1094 return true;
1095
1096 case OPT_mamx_int8:
1097 if (value)
1098 {
1099 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1100 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1101 }
1102 else
1103 {
1104 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1105 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1106 }
1107 return true;
1108
1109 case OPT_mamx_bf16:
1110 if (value)
1111 {
1112 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1113 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1114 }
1115 else
1116 {
1117 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1118 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1119 }
1120 return true;
1121
1122 case OPT_mavxifma:
1123 if (value)
1124 {
1125 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1126 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1127 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1128 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1129 }
1130 else
1131 {
1132 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1133 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1134 }
1135 return true;
1136
1137 case OPT_mavxvnniint8:
1138 if (value)
1139 {
1140 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1141 opts->x_ix86_isa_flags2_explicit |=
1142 OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1143 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1144 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1145 }
1146 else
1147 {
1148 opts->x_ix86_isa_flags2 &=
1149 ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1150 opts->x_ix86_isa_flags2_explicit |=
1151 OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1152 }
1153 return true;
1154
1155 case OPT_mavxneconvert:
1156 if (value)
1157 {
1158 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1159 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1160 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1161 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1162 }
1163 else
1164 {
1165 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1166 opts->x_ix86_isa_flags2_explicit
1167 |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1168 }
1169 return true;
1170
1171 case OPT_mcmpccxadd:
1172 if (value)
1173 {
1174 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1175 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1176 }
1177 else
1178 {
1179 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1180 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1181 }
1182 return true;
1183
1184 case OPT_mamx_fp16:
1185 if (value)
1186 {
1187 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1188 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1189 }
1190 else
1191 {
1192 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1193 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1194 }
1195 return true;
1196
1197 case OPT_mprefetchi:
1198 if (value)
1199 {
1200 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1201 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1202 }
1203 else
1204 {
1205 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1206 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1207 }
1208 return true;
1209
1210 case OPT_mraoint:
1211 if (value)
1212 {
1213 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1214 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1215 }
1216 else
1217 {
1218 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1219 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1220 }
1221 return true;
1222
1223 case OPT_mamx_complex:
1224 if (value)
1225 {
1226 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1227 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1228 }
1229 else
1230 {
1231 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1232 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1233 }
1234 return true;
1235
1236 case OPT_mavxvnniint16:
1237 if (value)
1238 {
1239 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1240 opts->x_ix86_isa_flags2_explicit |=
1241 OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1242 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1243 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1244 }
1245 else
1246 {
1247 opts->x_ix86_isa_flags2 &=
1248 ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1249 opts->x_ix86_isa_flags2_explicit |=
1250 OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1251 }
1252 return true;
1253
1254 case OPT_msm3:
1255 if (value)
1256 {
1257 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
1258 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
1259 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1260 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1261 }
1262 else
1263 {
1264 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
1265 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
1266 }
1267 return true;
1268
1269 case OPT_msha512:
1270 if (value)
1271 {
1272 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
1273 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
1274 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1275 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1276 }
1277 else
1278 {
1279 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
1280 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
1281 }
1282 return true;
1283
1284 case OPT_msm4:
1285 if (value)
1286 {
1287 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET;
1288 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET;
1289 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1290 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1291 }
1292 else
1293 {
1294 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET;
1295 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET;
1296 }
1297 return true;
1298
1299 case OPT_mapxf:
1300 if (value)
1301 {
1302 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
1303 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
1304 opts->x_ix86_apx_features = apx_all;
1305 }
1306 else
1307 {
1308 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
1309 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
1310 opts->x_ix86_apx_features = apx_none;
1311 }
1312 return true;
1313
1314 case OPT_mevex512:
1315 if (value)
1316 {
1317 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512_SET;
1318 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_SET;
1319 }
1320 else
1321 {
1322 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET;
1323 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET;
1324 opts->x_ix86_no_avx512_explicit = 1;
1325 }
1326 return true;
1327
1328 case OPT_musermsr:
1329 if (value)
1330 {
1331 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET;
1332 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET;
1333 }
1334 else
1335 {
1336 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET;
1337 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET;
1338 }
1339 return true;
1340
1341 case OPT_mavx10_1_256:
1342 if (value)
1343 {
1344 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET;
1345 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET;
1346 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1347 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1348 }
1349 else
1350 {
1351 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
1352 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
1353 opts->x_ix86_no_avx10_1_explicit = 1;
1354 }
1355 return true;
1356
1357 case OPT_mavx10_1_512:
1358 if (value)
1359 {
1360 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET;
1361 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET;
1362 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1363 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1364 }
1365 else
1366 {
1367 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
1368 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
1369 opts->x_ix86_no_avx10_1_explicit = 1;
1370 }
1371 return true;
1372
1373 case OPT_mfma:
1374 if (value)
1375 {
1376 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1377 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1378 }
1379 else
1380 {
1381 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1382 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1383 }
1384 return true;
1385
1386 case OPT_mrtm:
1387 if (value)
1388 {
1389 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1390 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1391 }
1392 else
1393 {
1394 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1395 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1396 }
1397 return true;
1398
1399 case OPT_msse4:
1400 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1401 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1402 return true;
1403
1404 case OPT_mno_sse4:
1405 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1406 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1407 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1408 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1409 return true;
1410
1411 case OPT_msse4a:
1412 if (value)
1413 {
1414 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1415 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1416 }
1417 else
1418 {
1419 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1420 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1421 }
1422 return true;
1423
1424 case OPT_mfma4:
1425 if (value)
1426 {
1427 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1428 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1429 }
1430 else
1431 {
1432 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1433 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1434 }
1435 return true;
1436
1437 case OPT_mxop:
1438 if (value)
1439 {
1440 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1441 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1442 }
1443 else
1444 {
1445 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1446 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1447 }
1448 return true;
1449
1450 case OPT_mlwp:
1451 if (value)
1452 {
1453 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1454 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1455 }
1456 else
1457 {
1458 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1459 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1460 }
1461 return true;
1462
1463 case OPT_mabm:
1464 if (value)
1465 {
1466 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1467 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1468 }
1469 else
1470 {
1471 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1472 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1473 }
1474 return true;
1475
1476 case OPT_mbmi:
1477 if (value)
1478 {
1479 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1480 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1481 }
1482 else
1483 {
1484 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1485 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1486 }
1487 return true;
1488
1489 case OPT_mbmi2:
1490 if (value)
1491 {
1492 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1493 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1494 }
1495 else
1496 {
1497 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1498 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1499 }
1500 return true;
1501
1502 case OPT_mlzcnt:
1503 if (value)
1504 {
1505 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1506 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1507 }
1508 else
1509 {
1510 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1511 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1512 }
1513 return true;
1514
1515 case OPT_mtbm:
1516 if (value)
1517 {
1518 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1519 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1520 }
1521 else
1522 {
1523 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1524 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1525 }
1526 return true;
1527
1528 case OPT_mpopcnt:
1529 if (value)
1530 {
1531 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1532 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1533 }
1534 else
1535 {
1536 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1537 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1538 }
1539 return true;
1540
1541 case OPT_msahf:
1542 if (value)
1543 {
1544 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1545 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1546 }
1547 else
1548 {
1549 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1550 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1551 }
1552 return true;
1553
1554 case OPT_mcx16:
1555 if (value)
1556 {
1557 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1558 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1559 }
1560 else
1561 {
1562 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1563 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1564 }
1565 return true;
1566
1567 case OPT_mmovbe:
1568 if (value)
1569 {
1570 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1571 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1572 }
1573 else
1574 {
1575 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1576 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1577 }
1578 return true;
1579
1580 case OPT_mcrc32:
1581 if (value)
1582 {
1583 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1584 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1585 }
1586 else
1587 {
1588 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1589 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1590 }
1591 return true;
1592
1593 case OPT_maes:
1594 if (value)
1595 {
1596 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1597 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1598 }
1599 else
1600 {
1601 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1602 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1603 }
1604 return true;
1605
1606 case OPT_msha:
1607 if (value)
1608 {
1609 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1610 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1611 }
1612 else
1613 {
1614 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1615 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1616 }
1617 return true;
1618
1619 case OPT_mpclmul:
1620 if (value)
1621 {
1622 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1623 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1624 }
1625 else
1626 {
1627 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1628 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1629 }
1630 return true;
1631
1632 case OPT_mfsgsbase:
1633 if (value)
1634 {
1635 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1636 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1637 }
1638 else
1639 {
1640 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1641 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1642 }
1643 return true;
1644
1645 case OPT_mrdrnd:
1646 if (value)
1647 {
1648 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1649 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1650 }
1651 else
1652 {
1653 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1654 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1655 }
1656 return true;
1657
1658 case OPT_mptwrite:
1659 if (value)
1660 {
1661 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1662 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1663 }
1664 else
1665 {
1666 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1667 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1668 }
1669 return true;
1670
1671 case OPT_mf16c:
1672 if (value)
1673 {
1674 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1675 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1676 }
1677 else
1678 {
1679 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1680 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1681 }
1682 return true;
1683
1684 case OPT_mfxsr:
1685 if (value)
1686 {
1687 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1688 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1689 }
1690 else
1691 {
1692 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1693 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1694 }
1695 return true;
1696
1697 case OPT_mxsave:
1698 if (value)
1699 {
1700 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1701 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1702 }
1703 else
1704 {
1705 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1706 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1707 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1708 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1709 }
1710 return true;
1711
1712 case OPT_mxsaveopt:
1713 if (value)
1714 {
1715 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1716 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1717 }
1718 else
1719 {
1720 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1721 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1722 }
1723 return true;
1724
1725 case OPT_mxsavec:
1726 if (value)
1727 {
1728 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1729 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1730 }
1731 else
1732 {
1733 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1734 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1735 }
1736 return true;
1737
1738 case OPT_mxsaves:
1739 if (value)
1740 {
1741 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1742 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1743 }
1744 else
1745 {
1746 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1747 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1748 }
1749 return true;
1750
1751 case OPT_mrdseed:
1752 if (value)
1753 {
1754 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1755 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1756 }
1757 else
1758 {
1759 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1760 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1761 }
1762 return true;
1763
1764 case OPT_mprfchw:
1765 if (value)
1766 {
1767 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1768 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1769 }
1770 else
1771 {
1772 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1773 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1774 }
1775 return true;
1776
1777 case OPT_madx:
1778 if (value)
1779 {
1780 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1781 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1782 }
1783 else
1784 {
1785 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1786 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1787 }
1788 return true;
1789
1790 case OPT_mclflushopt:
1791 if (value)
1792 {
1793 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1794 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1795 }
1796 else
1797 {
1798 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1799 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1800 }
1801 return true;
1802
1803 case OPT_mclwb:
1804 if (value)
1805 {
1806 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1807 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1808 }
1809 else
1810 {
1811 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1812 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1813 }
1814 return true;
1815
1816 case OPT_mmwaitx:
1817 if (value)
1818 {
1819 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1820 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1821 }
1822 else
1823 {
1824 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1825 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1826 }
1827 return true;
1828
1829 case OPT_mmwait:
1830 if (value)
1831 {
1832 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1833 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1834 }
1835 else
1836 {
1837 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1838 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1839 }
1840 return true;
1841
1842 case OPT_mclzero:
1843 if (value)
1844 {
1845 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1846 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1847 }
1848 else
1849 {
1850 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1851 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1852 }
1853 return true;
1854
1855 case OPT_mpku:
1856 if (value)
1857 {
1858 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1859 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1860 }
1861 else
1862 {
1863 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1864 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1865 }
1866 return true;
1867
1868
1869 case OPT_malign_loops_:
1870 warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1871 "use %<-falign-loops%>");
1872 if (value > MAX_CODE_ALIGN)
1873 error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1874 value, MAX_CODE_ALIGN);
1875 else
1876 set_malign_value (&opts->x_str_align_loops, value);
1877 return true;
1878
1879 case OPT_malign_jumps_:
1880 warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1881 "use %<-falign-jumps%>");
1882 if (value > MAX_CODE_ALIGN)
1883 error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1884 value, MAX_CODE_ALIGN);
1885 else
1886 set_malign_value (&opts->x_str_align_jumps, value);
1887 return true;
1888
1889 case OPT_malign_functions_:
1890 warning_at (loc, 0,
1891 "%<-malign-functions%> is obsolete, "
1892 "use %<-falign-functions%>");
1893 if (value > MAX_CODE_ALIGN)
1894 error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1895 value, MAX_CODE_ALIGN);
1896 else
1897 set_malign_value (&opts->x_str_align_functions, value);
1898 return true;
1899
1900 case OPT_mbranch_cost_:
1901 if (value > 5)
1902 {
1903 error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
1904 opts->x_ix86_branch_cost = 5;
1905 }
1906 return true;
1907
1908 default:
1909 return true;
1910 }
1911 }
1912
1913 static const struct default_options ix86_option_optimization_table[] =
1914 {
1915 /* Enable redundant extension instructions removal at -O2 and higher. */
1916 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1917 /* Enable function splitting at -O2 and higher. */
1918 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1919 /* The STC algorithm produces the smallest code at -Os, for x86. */
1920 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1921 REORDER_BLOCKS_ALGORITHM_STC },
1922
1923 /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
1924 loop unrolling at -O2. */
1925 { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
1926 { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
1927 /* Turns off -frename-registers and -fweb which are enabled by
1928 funroll-loops. */
1929 { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
1930 { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
1931 /* Turn off -fschedule-insns by default. It tends to make the
1932 problem with not enough registers even worse. */
1933 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1934
1935 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1936 SUBTARGET_OPTIMIZATION_OPTIONS,
1937 #endif
1938 { OPT_LEVELS_NONE, 0, NULL, 0 }
1939 };
1940
1941 /* Implement TARGET_OPTION_INIT_STRUCT. */
1942
1943 static void
1944 ix86_option_init_struct (struct gcc_options *opts)
1945 {
1946 if (TARGET_MACHO)
1947 /* The Darwin libraries never set errno, so we might as well
1948 avoid calling them when that's the only reason we would. */
1949 opts->x_flag_errno_math = 0;
1950
1951 opts->x_flag_pcc_struct_return = 2;
1952 opts->x_flag_asynchronous_unwind_tables = 2;
1953 }
1954
1955 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1956 field in the TCB, so they cannot be used together. */
1957
1958 static bool
1959 ix86_supports_split_stack (bool report,
1960 struct gcc_options *opts ATTRIBUTE_UNUSED)
1961 {
1962 #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
1963 if (!OPTION_GLIBC_P (opts))
1964 #endif
1965 {
1966 if (report)
1967 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1968 return false;
1969 }
1970
1971 bool ret = true;
1972
1973 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
1974 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1975 {
1976 if (report)
1977 error ("%<-fsplit-stack%> requires "
1978 "assembler support for CFI directives");
1979 ret = false;
1980 }
1981 #endif
1982
1983 return ret;
1984 }
1985
1986 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1987
1988 static enum unwind_info_type
1989 i386_except_unwind_info (struct gcc_options *opts)
1990 {
1991 /* Honor the --enable-sjlj-exceptions configure switch. */
1992 #ifdef CONFIG_SJLJ_EXCEPTIONS
1993 if (CONFIG_SJLJ_EXCEPTIONS)
1994 return UI_SJLJ;
1995 #endif
1996
1997 /* On windows 64, prefer SEH exceptions over anything else. */
1998 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1999 return UI_SEH;
2000
2001 if (DWARF2_UNWIND_INFO)
2002 return UI_DWARF2;
2003
2004 return UI_SJLJ;
2005 }
2006
2007 #undef TARGET_EXCEPT_UNWIND_INFO
2008 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2009
2010 #undef TARGET_DEFAULT_TARGET_FLAGS
2011 #define TARGET_DEFAULT_TARGET_FLAGS \
2012 (TARGET_DEFAULT \
2013 | TARGET_SUBTARGET_DEFAULT \
2014 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2015
2016 #undef TARGET_HANDLE_OPTION
2017 #define TARGET_HANDLE_OPTION ix86_handle_option
2018
2019 #undef TARGET_OPTION_OPTIMIZATION_TABLE
2020 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2021 #undef TARGET_OPTION_INIT_STRUCT
2022 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2023
2024 #undef TARGET_SUPPORTS_SPLIT_STACK
2025 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2026
2027 /* This table must be in sync with enum processor_type in i386.h. */
2028 const char *const processor_names[] =
2029 {
2030 "generic",
2031 "i386",
2032 "i486",
2033 "pentium",
2034 "lakemont",
2035 "pentiumpro",
2036 "pentium4",
2037 "nocona",
2038 "core2",
2039 "nehalem",
2040 "sandybridge",
2041 "haswell",
2042 "bonnell",
2043 "silvermont",
2044 "goldmont",
2045 "goldmont-plus",
2046 "tremont",
2047 "sierraforest",
2048 "grandridge",
2049 "clearwaterforest",
2050 "skylake",
2051 "skylake-avx512",
2052 "cannonlake",
2053 "icelake-client",
2054 "icelake-server",
2055 "cascadelake",
2056 "tigerlake",
2057 "cooperlake",
2058 "sapphirerapids",
2059 "alderlake",
2060 "rocketlake",
2061 "graniterapids",
2062 "graniterapids-d",
2063 "arrowlake",
2064 "arrowlake-s",
2065 "pantherlake",
2066 "intel",
2067 "lujiazui",
2068 "yongfeng",
2069 "shijidadao",
2070 "geode",
2071 "k6",
2072 "athlon",
2073 "k8",
2074 "amdfam10",
2075 "bdver1",
2076 "bdver2",
2077 "bdver3",
2078 "bdver4",
2079 "btver1",
2080 "btver2",
2081 "znver1",
2082 "znver2",
2083 "znver3",
2084 "znver4",
2085 "znver5"
2086 };
2087
2088 /* Guarantee that the array is aligned with enum processor_type. */
2089 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
2090
2091 const pta processor_alias_table[] =
2092 {
2093 {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
2094 {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
2095 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2096 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2097 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
2098 0, P_NONE},
2099 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
2100 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
2101 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2102 0, P_NONE},
2103 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2104 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2105 0, P_NONE},
2106 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2107 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2108 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2109 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2110 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2111 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2112 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2113 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2114 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2115 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2116 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2117 0, P_NONE},
2118 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2119 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2120 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2121 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2122 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2123 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2124 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2125 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2126 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2127 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2128 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2129 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2130 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2131 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2132 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2133 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2134 M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2135 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2136 M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2137 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2138 M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2139 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2140 M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2141 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2142 PTA_SANDYBRIDGE,
2143 M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2144 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2145 PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2146 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2147 PTA_IVYBRIDGE,
2148 M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2149 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2150 PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2151 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2152 M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2153 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2154 0, P_PROC_DYNAMIC},
2155 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2156 M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2157 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2158 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2159 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2160 PTA_SKYLAKE_AVX512,
2161 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2162 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2163 M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2164 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2165 PTA_ICELAKE_CLIENT,
2166 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2167 {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2168 PTA_ROCKETLAKE,
2169 M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2170 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2171 PTA_ICELAKE_SERVER,
2172 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2173 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2174 PTA_CASCADELAKE,
2175 M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2176 {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2177 M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2178 {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2179 M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2180 {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2181 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2182 {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2183 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2184 {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2185 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2186 {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2187 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2188 {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2189 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2190 {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2191 M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1_512},
2192 {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
2193 PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
2194 P_PROC_AVX10_1_512},
2195 {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
2196 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
2197 {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2198 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2199 {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2200 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2201 {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2202 M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2203 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2204 M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2205 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2206 M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2207 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2208 M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2209 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2210 M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2211 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2212 M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2213 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2214 M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2215 {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2216 M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2217 {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2218 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2219 {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2220 M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2221 {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2222 M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2223 {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
2224 PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2},
2225 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM,
2226 M_VENDOR (VENDOR_INTEL), P_NONE},
2227 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2228 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2229 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2230 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2231 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2232 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2233 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2234 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2235 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2236 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2237 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2238 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2239 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2240 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2241 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2242 {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2243 {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2244 0, P_NONE},
2245 {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2246 0, P_NONE},
2247 {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2248 0, P_NONE},
2249 {"eden-x2", PROCESSOR_K8, CPU_K8,
2250 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2251 0, P_NONE},
2252 {"nano", PROCESSOR_K8, CPU_K8,
2253 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2254 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2255 {"nano-1000", PROCESSOR_K8, CPU_K8,
2256 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2257 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2258 {"nano-2000", PROCESSOR_K8, CPU_K8,
2259 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2260 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2261 {"nano-3000", PROCESSOR_K8, CPU_K8,
2262 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2263 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2264 {"nano-x2", PROCESSOR_K8, CPU_K8,
2265 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2266 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2267 {"eden-x4", PROCESSOR_K8, CPU_K8,
2268 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2269 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2270 {"nano-x4", PROCESSOR_K8, CPU_K8,
2271 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2272 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2273 {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2274 PTA_LUJIAZUI,
2275 M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
2276 {"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
2277 PTA_YONGFENG,
2278 M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
2279 {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
2280 PTA_YONGFENG,
2281 M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
2282 {"k8", PROCESSOR_K8, CPU_K8,
2283 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2284 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2285 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2286 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2287 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2288 {"opteron", PROCESSOR_K8, CPU_K8,
2289 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2290 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2291 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2292 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2293 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2294 {"athlon64", PROCESSOR_K8, CPU_K8,
2295 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2296 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2297 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2298 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2299 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2300 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2301 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2302 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2303 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2304 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2305 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2306 0, P_PROC_DYNAMIC},
2307 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2308 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2309 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2310 M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2311 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2312 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2313 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2314 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2315 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
2316 M_CPU_TYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2317 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2318 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2319 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2320 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2321 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
2322 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
2323 M_CPU_TYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2324 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2325 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2326 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2327 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2328 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
2329 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
2330 | PTA_XSAVEOPT | PTA_FSGSBASE,
2331 M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2332 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2333 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2334 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2335 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
2336 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
2337 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
2338 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
2339 | PTA_MOVBE | PTA_MWAITX,
2340 M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2341 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2342 PTA_ZNVER1,
2343 M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2344 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2345 PTA_ZNVER2,
2346 M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2347 {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2348 PTA_ZNVER3,
2349 M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2350 {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2351 PTA_ZNVER4,
2352 M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2353 {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
2354 PTA_ZNVER5,
2355 M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
2356 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2357 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2358 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
2359 | PTA_FXSR | PTA_XSAVE,
2360 M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_SSE4_A},
2361 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2362 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2363 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
2364 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
2365 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
2366 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT,
2367 M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2368
2369 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2370 PTA_64BIT
2371 | PTA_HLE /* flags are only used for -march switch. */,
2372 0, P_NONE},
2373
2374 {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2375 M_VENDOR (VENDOR_AMD), P_NONE},
2376 {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2377 M_CPU_TYPE (AMDFAM10H), P_NONE},
2378 {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2379 M_CPU_TYPE (AMDFAM15H), P_NONE},
2380 {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2381 M_CPU_TYPE (AMDFAM17H), P_NONE},
2382 {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2383 M_CPU_TYPE (AMDFAM19H), P_NONE},
2384 {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2385 M_CPU_TYPE (AMDFAM10H_SHANGHAI), P_NONE},
2386 {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2387 M_CPU_TYPE (AMDFAM10H_ISTANBUL), P_NONE},
2388 };
2389
2390 /* NB: processor_alias_table stops at the "generic" entry. */
2391 unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
2392 unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2393
2394 /* Provide valid option values for -march and -mtune options. */
2395
2396 vec<const char *>
2397 ix86_get_valid_option_values (int option_code,
2398 const char *prefix ATTRIBUTE_UNUSED)
2399 {
2400 vec<const char *> v;
2401 v.create (0);
2402 opt_code opt = (opt_code) option_code;
2403
2404 switch (opt)
2405 {
2406 case OPT_march_:
2407 for (unsigned i = 0; i < pta_size; i++)
2408 {
2409 const char *name = processor_alias_table[i].name;
2410 gcc_checking_assert (name != NULL);
2411 v.safe_push (name);
2412 }
2413 #ifdef HAVE_LOCAL_CPU_DETECT
2414 /* Add also "native" as possible value. */
2415 v.safe_push ("native");
2416 #endif
2417
2418 break;
2419 case OPT_mtune_:
2420 for (unsigned i = 0; i < PROCESSOR_max; i++)
2421 {
2422 const char *name = processor_names[i];
2423 gcc_checking_assert (name != NULL);
2424 v.safe_push (name);
2425 }
2426 break;
2427 default:
2428 break;
2429 }
2430
2431 return v;
2432 }
2433
2434 #undef TARGET_GET_VALID_OPTION_VALUES
2435 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2436
2437 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git