gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2024 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target
  42 Same as -mA6.
  43
  44 mARC601
  45 Target
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target
  54 Same as -mA7.
  55
  56 mjli-always
  57 Target Mask(JLI_ALWAYS)
  58 Force all calls to be made via a jli instruction.
  59
  60 mmpy-option=
  61 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
  62 -mmpy-option=MPY        Compile ARCv2 code with a multiplier design option.
  63
  64 Enum
  65 Name(arc_mpy) Type(int)
  66
  67 EnumValue
  68 Enum(arc_mpy) String(0) Value(0)
  69
  70 EnumValue
  71 Enum(arc_mpy) String(none) Value(0) Canonical
  72
  73 EnumValue
  74 Enum(arc_mpy) String(1) Value(1)
  75
  76 EnumValue
  77 Enum(arc_mpy) String(w) Value(1) Canonical
  78
  79 EnumValue
  80 Enum(arc_mpy) String(2) Value(2)
  81
  82 EnumValue
  83 Enum(arc_mpy) String(mpy) Value(2)
  84
  85 EnumValue
  86 Enum(arc_mpy) String(wlh1) Value(2) Canonical
  87
  88 EnumValue
  89 Enum(arc_mpy) String(3) Value(3)
  90
  91 EnumValue
  92 Enum(arc_mpy) String(wlh2) Value(3) Canonical
  93
  94 EnumValue
  95 Enum(arc_mpy) String(4) Value(4)
  96
  97 EnumValue
  98 Enum(arc_mpy) String(wlh3) Value(4) Canonical
  99
 100 EnumValue
 101 Enum(arc_mpy) String(5) Value(5)
 102
 103 EnumValue
 104 Enum(arc_mpy) String(wlh4) Value(5) Canonical
 105
 106 EnumValue
 107 Enum(arc_mpy) String(6) Value(6)
 108
 109 EnumValue
 110 Enum(arc_mpy) String(wlh5) Value(6) Canonical
 111
 112 EnumValue
 113 Enum(arc_mpy) String(7) Value(7)
 114
 115 EnumValue
 116 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
 117
 118 EnumValue
 119 Enum(arc_mpy) String(8) Value(8)
 120
 121 EnumValue
 122 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
 123
 124 EnumValue
 125 Enum(arc_mpy) String(9) Value(9)
 126
 127 EnumValue
 128 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
 129
 130 mdiv-rem
 131 Target Mask(DIVREM)
 132 Enable DIV-REM instructions for ARCv2.
 133
 134 mcode-density
 135 Target Mask(CODE_DENSITY)
 136 Enable code density instructions for ARCv2.
 137
 138 mmixed-code
 139 Target Ignore
 140 Does nothing.  Preserved for backward compatibility.
 141
 142 ; We use an explict definition for the negative form because that is the
 143 ; actually interesting option, and we want that to have its own comment.
 144 mvolatile-cache
 145 Target RejectNegative Mask(VOLATILE_CACHE_SET)
 146 Use ordinarily cached memory accesses for volatile references.
 147
 148 mno-volatile-cache
 149 Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
 150 Enable cache bypass for volatile references.
 151
 152 mbarrel-shifter
 153 Target Mask(BARREL_SHIFTER)
 154 Generate instructions supported by barrel shifter.
 155
 156 mnorm
 157 Target Mask(NORM_SET)
 158 Generate norm instruction.
 159
 160 mswap
 161 Target Mask(SWAP_SET)
 162 Generate swap instruction.
 163
 164 mmul64
 165 Target Mask(MUL64_SET)
 166 Generate mul64 and mulu64 instructions.
 167
 168 mno-mpy
 169 Target Mask(NOMPY_SET) Warn(%qs is deprecated)
 170 Do not generate mpy instructions for ARC700.
 171
 172 mea
 173 Target Mask(EA_SET)
 174 Generate extended arithmetic instructions, only valid for ARC700.
 175
 176 msoft-float
 177 Target Mask(0)
 178 Dummy flag. This is the default unless FPX switches are provided explicitly.
 179
 180 mlong-calls
 181 Target Mask(LONG_CALLS_SET)
 182 Generate call insns as register indirect calls.
 183
 184 mno-brcc
 185 Target Mask(NO_BRCC_SET)
 186 Do no generate BRcc instructions in arc_reorg.
 187
 188 msdata
 189 Target InverseMask(NO_SDATA_SET)
 190 Generate sdata references.  This is the default, unless you compile for PIC.
 191
 192 mmillicode
 193 Target Mask(MILLICODE_THUNK_SET)
 194 Generate millicode thunks.
 195
 196 mspfp
 197 Target Mask(SPFP_COMPACT_SET)
 198 FPX: Generate Single Precision FPX (compact) instructions.
 199
 200 mspfp-compact
 201 Target Mask(SPFP_COMPACT_SET) MaskExists
 202 FPX: Generate Single Precision FPX (compact) instructions.
 203
 204 mspfp-fast
 205 Target Mask(SPFP_FAST_SET)
 206 FPX: Generate Single Precision FPX (fast) instructions.
 207
 208 margonaut
 209 Target Mask(ARGONAUT_SET)
 210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 211
 212 mdpfp
 213 Target Mask(DPFP_COMPACT_SET)
 214 FPX: Generate Double Precision FPX (compact) instructions.
 215
 216 mdpfp-compact
 217 Target Mask(DPFP_COMPACT_SET) MaskExists
 218 FPX: Generate Double Precision FPX (compact) instructions.
 219
 220 mdpfp-fast
 221 Target Mask(DPFP_FAST_SET)
 222 FPX: Generate Double Precision FPX (fast) instructions.
 223
 224 mno-dpfp-lrsr
 225 Target Mask(DPFP_DISABLE_LRSR)
 226 Disable LR and SR instructions from using FPX extension aux registers.
 227
 228 msimd
 229 Target Mask(SIMD_SET)
 230 Enable generation of ARC SIMD instructions via target-specific builtins.
 231
 232 mcpu=
 233 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 234 -mcpu=CPU       Compile code for ARC variant CPU.
 235
 236 msize-level=
 237 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 238 Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 239
 240 misize
 241 Target PchIgnore Var(TARGET_DUMPISIZE)
 242 Annotate assembler instructions with estimated addresses.
 243
 244 mmultcost=
 245 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 246 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 247
 248 mtune=
 249 Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
 250 -mtune=TUNE     Tune code for given ARC variant.
 251
 252 Enum
 253 Name(arc_tune_attr) Type(int)
 254
 255 EnumValue
 256 Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
 257
 258 EnumValue
 259 Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
 260
 261 EnumValue
 262 Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
 263
 264 EnumValue
 265 Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
 266
 267 EnumValue
 268 Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
 269
 270 EnumValue
 271 Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
 272
 273 EnumValue
 274 Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
 275
 276 EnumValue
 277 Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
 278
 279 EnumValue
 280 Enum(arc_tune_attr) String(release31a) Value(ARC_TUNE_ARCHS4X_REL31A)
 281
 282 mindexed-loads
 283 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
 284 Enable the use of indexed loads.
 285
 286 mauto-modify-reg
 287 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
 288 Enable the use of pre/post modify with register displacement.
 289
 290 mmul32x16
 291 Target Mask(MULMAC_32BY16_SET)
 292 Generate 32x16 multiply and mac instructions.
 293
 294 munalign-prob-threshold=
 295 Target Ignore
 296 Does nothing.  Preserved for backward compatibility.
 297
 298 mmedium-calls
 299 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 300 Don't use less than 25 bit addressing range for calls.
 301
 302 mannotate-align
 303 Target Ignore
 304 Does nothing.  Preserved for backward compatibility.
 305
 306 malign-call
 307 Target Ignore
 308 Does nothing.  Preserved for backward compatibility.
 309
 310 mRcq
 311 Target Ignore
 312 Does nothing.  Preserved for backward compatibility.
 313
 314
 315 mRcw
 316 Target Ignore
 317 Does nothing.  Preserved for backward compatibility.
 318
 319
 320 mearly-cbranchsi
 321 Target Var(TARGET_EARLY_CBRANCHSI)
 322 Enable pre-reload use of cbranchsi pattern.
 323
 324 mbbit-peephole
 325 Target Ignore
 326 Does nothing.  Preserved for backward compatibility.
 327
 328 mcase-vector-pcrel
 329 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 330 Use pc-relative switch case tables - this enables case table shortening.
 331
 332 mcompact-casesi
 333 Target Warn(%qs is deprecated)
 334 Enable compact casesi pattern.
 335
 336 mq-class
 337 Target Warn(%qs is deprecated)
 338 Enable 'q' instruction alternatives.
 339
 340 mexpand-adddi
 341 Target Warn(%qs is deprecated)
 342 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 343
 344
 345 ; Flags used by the assembler, but for which we define preprocessor
 346 ; macro symbols as well.
 347 mcrc
 348 Target Warn(%qs is deprecated)
 349 Enable variable polynomial CRC extension.
 350
 351 mdsp-packa
 352 Target Warn(%qs is deprecated)
 353 Enable DSP 3.1 Pack A extensions.
 354
 355 mdvbf
 356 Target Warn(%qs is deprecated)
 357 Enable dual viterbi butterfly extension.
 358
 359 mmac-d16
 360 Target Undocumented Warn(%qs is deprecated)
 361
 362 mmac-24
 363 Target Undocumented Warn(%qs is deprecated)
 364
 365 mtelephony
 366 Target RejectNegative Warn(%qs is deprecated)
 367 Enable Dual and Single Operand Instructions for Telephony.
 368
 369 mxy
 370 Target
 371 Enable XY Memory extension (DSP version 3).
 372
 373 ; ARC700 4.10 extension instructions
 374 mlock
 375 Target
 376 Enable Locked Load/Store Conditional extension.
 377
 378 mswape
 379 Target
 380 Enable swap byte ordering extension instruction.
 381
 382 mrtsc
 383 Target Warn(%qs is deprecated)
 384 Enable 64-bit Time-Stamp Counter extension instruction.
 385
 386 EB
 387 Target
 388 Pass -EB option through to linker.
 389
 390 EL
 391 Target
 392 Pass -EL option through to linker.
 393
 394 marclinux
 395 Target
 396 Pass -marclinux option through to linker.
 397
 398 marclinux_prof
 399 Target
 400 Pass -marclinux_prof option through to linker.
 401
 402 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 403 mlra
 404 Target Var(arc_lra_flag) Init(1) Save
 405 Use LRA instead of reload.
 406
 407 mlra-priority-none
 408 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 409 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 410
 411 mlra-priority-compact
 412 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 413 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 414
 415 mlra-priority-noncompact
 416 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 417 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 418
 419 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 420
 421 mEA
 422 Target
 423
 424 multcost=
 425 Target RejectNegative Joined
 426
 427 matomic
 428 Target Mask(ATOMIC)
 429 Enable atomic instructions.
 430
 431 mll64
 432 Target Mask(LL64)
 433 Enable double load/store instructions for ARC HS.
 434
 435 mfpu=
 436 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
 437 Specify the name of the target floating point configuration.
 438
 439 Enum
 440 Name(arc_fpu) Type(int)
 441
 442 EnumValue
 443 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
 444
 445 EnumValue
 446 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
 447
 448 EnumValue
 449 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
 450
 451 EnumValue
 452 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
 453
 454 EnumValue
 455 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
 456
 457 EnumValue
 458 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
 459
 460 EnumValue
 461 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
 462
 463 EnumValue
 464 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
 465
 466 EnumValue
 467 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
 468
 469 EnumValue
 470 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
 471
 472 EnumValue
 473 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
 474
 475 EnumValue
 476 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
 477
 478 mtp-regno=
 479 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
 480 Specify thread pointer register number.
 481
 482 mtp-regno=none
 483 Target RejectNegative Var(arc_tp_regno,-1)
 484
 485 mbitops
 486 Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
 487 Enable use of NPS400 bit operations.
 488
 489 mcmem
 490 Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
 491 Enable use of NPS400 xld/xst extension.
 492
 493 munaligned-access
 494 Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
 495 Enable unaligned word and halfword accesses to packed data.
 496
 497 mirq-ctrl-saved=
 498 Target RejectNegative Joined Var(arc_deferred_options) Defer
 499 Specifies the registers that the processor saves on an interrupt entry and exit.
 500
 501 mrgf-banked-regs=
 502 Target RejectNegative Joined Var(arc_deferred_options) Defer
 503 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
 504
 505 mlpc-width=
 506 Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
 507 Sets LP_COUNT register width.  Possible values are 8, 16, 20, 24, 28, and 32.
 508
 509 Enum
 510 Name(arc_lpc) Type(int)
 511
 512 EnumValue
 513 Enum(arc_lpc) String(8) Value(8)
 514
 515 EnumValue
 516 Enum(arc_lpc) String(16) Value(16)
 517
 518 EnumValue
 519 Enum(arc_lpc) String(20) Value(20)
 520
 521 EnumValue
 522 Enum(arc_lpc) String(24) Value(24)
 523
 524 EnumValue
 525 Enum(arc_lpc) String(28) Value(28)
 526
 527 EnumValue
 528 Enum(arc_lpc) String(32) Value(32)
 529
 530 mrf16
 531 Target Mask(RF16)
 532 Enable 16-entry register file.
 533
 534 mbranch-index
 535 Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
 536 Enable use of BI/BIH instructions when available.
 537
 538 mcode-density-frame
 539 Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
 540 Enable ENTER_S and LEAVE_S opcodes for ARCv2.