1 ;; Machine description of Andes NDS32 cpu for GNU compiler
2 ;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
3 ;; Contributed by Andes Technology Corporation.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_expand "mov<mode>"
22 [(set (match_operand:VQIHI 0 "general_operand" "")
23 (match_operand:VQIHI 1 "general_operand" ""))]
26 /* Need to force register if mem <- !reg. */
27 if (MEM_P (operands[0]) && !REG_P (operands[1]))
28 operands[1] = force_reg (<MODE>mode, operands[1]);
30 /* If operands[1] is a large constant and cannot be performed
31 by a single instruction, we need to split it. */
32 if (GET_CODE (operands[1]) == CONST_VECTOR
33 && !satisfies_constraint_CVs2 (operands[1])
34 && !satisfies_constraint_CVhi (operands[1]))
36 HOST_WIDE_INT ival = const_vector_to_hwint (operands[1]);
39 tmp_rtx = can_create_pseudo_p ()
40 ? gen_reg_rtx (SImode)
41 : simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
43 emit_move_insn (tmp_rtx, gen_int_mode (ival, SImode));
44 convert_move (operands[0], tmp_rtx, false);
48 if (REG_P (operands[0]) && SYMBOLIC_CONST_P (operands[1]))
50 if (nds32_tls_referenced_p (operands [1]))
52 nds32_expand_tls_move (operands);
57 nds32_expand_pic_move (operands);
63 (define_insn "*mov<mode>"
64 [(set (match_operand:VQIHI 0 "nonimmediate_operand" "=r, r,$U45,$U33,$U37,$U45, m,$ l,$ l,$ l,$ d, d, r,$ d, r, r, r, *f, *f, r, *f, Q")
65 (match_operand:VQIHI 1 "nds32_vmove_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45,Ufe, m, CVp5, CVs5, CVs2, CVhi, *f, r, *f, Q, *f"))]
67 && (register_operand(operands[0], <MODE>mode)
68 || register_operand(operands[1], <MODE>mode))"
70 switch (which_alternative)
73 return "mov55\t%0, %1";
75 return "ori\t%0, %1, 0";
80 return nds32_output_16bit_store (operands, <byte>);
82 return nds32_output_32bit_store (operands, <byte>);
88 return nds32_output_16bit_load (operands, <byte>);
90 return nds32_output_32bit_load (operands, <byte>);
92 return "movpi45\t%0, %1";
94 return "movi55\t%0, %1";
96 return "movi\t%0, %1";
98 return "sethi\t%0, hi20(%1)";
100 if (TARGET_FPU_SINGLE)
101 return "fcpyss\t%0, %1, %1";
105 return "fmtsr\t%1, %0";
107 return "fmfsr\t%0, %1";
109 return nds32_output_float_load (operands);
111 return nds32_output_float_store (operands);
116 [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu,fcpy,fmtsr,fmfsr,fload,fstore")
117 (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4, 4, 4, 4, 4, 4")
118 (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v3m, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")])
120 (define_expand "movv2si"
121 [(set (match_operand:V2SI 0 "general_operand" "")
122 (match_operand:V2SI 1 "general_operand" ""))]
125 /* Need to force register if mem <- !reg. */
126 if (MEM_P (operands[0]) && !REG_P (operands[1]))
127 operands[1] = force_reg (V2SImode, operands[1]);
130 (define_insn "*movv2si"
131 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r, r, r, r, Da, m, f, Q, f, r, f")
132 (match_operand:V2SI 1 "general_operand" " r, i, Da, m, r, r, Q, f, f, f, r"))]
134 && (register_operand(operands[0], V2SImode)
135 || register_operand(operands[1], V2SImode))"
137 switch (which_alternative)
140 return "movd44\t%0, %1";
142 /* reg <- const_int, we ask gcc to split instruction. */
145 /* The memory format is (mem (reg)),
146 we can generate 'lmw.bi' instruction. */
147 return nds32_output_double (operands, true);
149 /* We haven't 64-bit load instruction,
150 we split this pattern to two SImode pattern. */
153 /* The memory format is (mem (reg)),
154 we can generate 'smw.bi' instruction. */
155 return nds32_output_double (operands, false);
157 /* We haven't 64-bit store instruction,
158 we split this pattern to two SImode pattern. */
161 return nds32_output_float_load (operands);
163 return nds32_output_float_store (operands);
165 return "fcpysd\t%0, %1, %1";
167 return "fmfdr\t%0, %1";
169 return "fmtdr\t%1, %0";
174 [(set_attr "type" "alu,alu,load,load,store,store,unknown,unknown,unknown,unknown,unknown")
175 (set_attr_alternative "length"
178 (if_then_else (match_test "!TARGET_16_BIT")
202 (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")])
204 (define_expand "movmisalign<mode>"
205 [(set (match_operand:VQIHI 0 "general_operand" "")
206 (match_operand:VQIHI 1 "general_operand" ""))]
210 if (MEM_P (operands[0]) && !REG_P (operands[1]))
211 operands[1] = force_reg (<MODE>mode, operands[1]);
213 if (MEM_P (operands[0]))
215 addr = force_reg (Pmode, XEXP (operands[0], 0));
216 emit_insn (gen_unaligned_store<mode> (addr, operands[1]));
220 addr = force_reg (Pmode, XEXP (operands[1], 0));
221 emit_insn (gen_unaligned_load<mode> (operands[0], addr));
226 (define_expand "unaligned_load<mode>"
227 [(set (match_operand:VQIHI 0 "register_operand" "=r")
228 (unspec:VQIHI [(mem:VQIHI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))]
232 nds32_expand_unaligned_load (operands, <MODE>mode);
234 emit_insn (gen_unaligned_load_w<mode> (operands[0], gen_rtx_MEM (<MODE>mode, operands[1])));
238 (define_insn "unaligned_load_w<mode>"
239 [(set (match_operand:VQIHI 0 "register_operand" "= r")
240 (unspec:VQIHI [(match_operand:VQIHI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))]
243 return nds32_output_lmw_single_word (operands);
245 [(set_attr "type" "load")
246 (set_attr "length" "4")]
249 (define_expand "unaligned_store<mode>"
250 [(set (mem:VQIHI (match_operand:SI 0 "register_operand" "r"))
251 (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" "r")] UNSPEC_UASTORE_W))]
255 nds32_expand_unaligned_store (operands, <MODE>mode);
257 emit_insn (gen_unaligned_store_w<mode> (gen_rtx_MEM (<MODE>mode, operands[0]), operands[1]));
261 (define_insn "unaligned_store_w<mode>"
262 [(set (match_operand:VQIHI 0 "nds32_lmw_smw_base_operand" "=Umw")
263 (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" " r")] UNSPEC_UASTORE_W))]
266 return nds32_output_smw_single_word (operands);
268 [(set_attr "type" "store")
269 (set_attr "length" "4")]
272 (define_insn "<uk>add<mode>3"
273 [(set (match_operand:VQIHI 0 "register_operand" "=r")
274 (all_plus:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
275 (match_operand:VQIHI 2 "register_operand" " r")))]
277 "<uk>add<bits> %0, %1, %2"
278 [(set_attr "type" "dalu")
279 (set_attr "length" "4")
280 (set_attr "feature" "v1")])
282 (define_insn "<uk>adddi3"
283 [(set (match_operand:DI 0 "register_operand" "=r")
284 (all_plus:DI (match_operand:DI 1 "register_operand" " r")
285 (match_operand:DI 2 "register_operand" " r")))]
287 "<uk>add64 %0, %1, %2"
288 [(set_attr "type" "dalu64")
289 (set_attr "length" "4")
290 (set_attr "feature" "v1")])
292 (define_insn "raddv4qi3"
293 [(set (match_operand:V4QI 0 "register_operand" "=r")
296 (plus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
297 (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
301 [(set_attr "type" "dalu")
302 (set_attr "length" "4")
303 (set_attr "feature" "v1")])
306 (define_insn "uraddv4qi3"
307 [(set (match_operand:V4QI 0 "register_operand" "=r")
310 (plus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
311 (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
315 [(set_attr "type" "dalu")
316 (set_attr "length" "4")
317 (set_attr "feature" "v1")])
319 (define_insn "raddv2hi3"
320 [(set (match_operand:V2HI 0 "register_operand" "=r")
323 (plus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
324 (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
328 [(set_attr "type" "dalu")
329 (set_attr "length" "4")
330 (set_attr "feature" "v1")])
332 (define_insn "uraddv2hi3"
333 [(set (match_operand:V2HI 0 "register_operand" "=r")
336 (plus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
337 (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
340 "uradd16\t%0, %1, %2"
341 [(set_attr "type" "dalu")
342 (set_attr "length" "4")
343 (set_attr "feature" "v1")])
345 (define_insn "radddi3"
346 [(set (match_operand:DI 0 "register_operand" "=r")
349 (plus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r"))
350 (sign_extend:TI (match_operand:DI 2 "register_operand" " r")))
354 [(set_attr "type" "dalu64")
355 (set_attr "length" "4")
356 (set_attr "feature" "v1")])
359 (define_insn "uradddi3"
360 [(set (match_operand:DI 0 "register_operand" "=r")
363 (plus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r"))
364 (zero_extend:TI (match_operand:DI 2 "register_operand" " r")))
367 "uradd64\t%0, %1, %2"
368 [(set_attr "type" "dalu64")
369 (set_attr "length" "4")
370 (set_attr "feature" "v1")])
372 (define_insn "<uk>sub<mode>3"
373 [(set (match_operand:VQIHI 0 "register_operand" "=r")
374 (all_minus:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
375 (match_operand:VQIHI 2 "register_operand" " r")))]
377 "<uk>sub<bits> %0, %1, %2"
378 [(set_attr "type" "dalu")
379 (set_attr "length" "4")
380 (set_attr "feature" "v1")])
382 (define_insn "<uk>subdi3"
383 [(set (match_operand:DI 0 "register_operand" "=r")
384 (all_minus:DI (match_operand:DI 1 "register_operand" " r")
385 (match_operand:DI 2 "register_operand" " r")))]
387 "<uk>sub64 %0, %1, %2"
388 [(set_attr "type" "dalu64")
389 (set_attr "length" "4")
390 (set_attr "feature" "v1")])
392 (define_insn "rsubv4qi3"
393 [(set (match_operand:V4QI 0 "register_operand" "=r")
396 (minus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
397 (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
401 [(set_attr "type" "dalu")
402 (set_attr "length" "4")])
404 (define_insn "ursubv4qi3"
405 [(set (match_operand:V4QI 0 "register_operand" "=r")
408 (minus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
409 (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
413 [(set_attr "type" "dalu")
414 (set_attr "length" "4")])
416 (define_insn "rsubv2hi3"
417 [(set (match_operand:V2HI 0 "register_operand" "=r")
420 (minus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
421 (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
425 [(set_attr "type" "dalu")
426 (set_attr "length" "4")])
428 (define_insn "ursubv2hi3"
429 [(set (match_operand:V2HI 0 "register_operand" "=r")
432 (minus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
433 (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
436 "ursub16\t%0, %1, %2"
437 [(set_attr "type" "dalu")
438 (set_attr "length" "4")])
440 (define_insn "rsubdi3"
441 [(set (match_operand:DI 0 "register_operand" "=r")
444 (minus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r"))
445 (sign_extend:TI (match_operand:DI 2 "register_operand" " r")))
449 [(set_attr "type" "dalu64")
450 (set_attr "length" "4")])
453 (define_insn "ursubdi3"
454 [(set (match_operand:DI 0 "register_operand" "=r")
457 (minus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r"))
458 (zero_extend:TI (match_operand:DI 2 "register_operand" " r")))
461 "ursub64\t%0, %1, %2"
462 [(set_attr "type" "dalu64")
463 (set_attr "length" "4")])
465 (define_expand "cras16_1"
466 [(match_operand:V2HI 0 "register_operand" "")
467 (match_operand:V2HI 1 "register_operand" "")
468 (match_operand:V2HI 2 "register_operand" "")]
471 if (TARGET_BIG_ENDIAN)
472 emit_insn (gen_cras16_1_be (operands[0], operands[1], operands[2]));
474 emit_insn (gen_cras16_1_le (operands[0], operands[1], operands[2]));
478 (define_insn "cras16_1_le"
479 [(set (match_operand:V2HI 0 "register_operand" "=r")
484 (match_operand:V2HI 1 "register_operand" " r")
485 (parallel [(const_int 0)]))
487 (match_operand:V2HI 2 "register_operand" " r")
488 (parallel [(const_int 1)]))))
493 (parallel [(const_int 0)]))
496 (parallel [(const_int 1)]))))
498 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
500 [(set_attr "type" "dalu")]
503 (define_insn "cras16_1_be"
504 [(set (match_operand:V2HI 0 "register_operand" "=r")
509 (match_operand:V2HI 1 "register_operand" " r")
510 (parallel [(const_int 1)]))
512 (match_operand:V2HI 2 "register_operand" " r")
513 (parallel [(const_int 0)]))))
518 (parallel [(const_int 1)]))
521 (parallel [(const_int 0)]))))
523 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
525 [(set_attr "type" "dalu")]
528 (define_expand "kcras16_1"
529 [(match_operand:V2HI 0 "register_operand" "")
530 (match_operand:V2HI 1 "register_operand" "")
531 (match_operand:V2HI 2 "register_operand" "")]
534 if (TARGET_BIG_ENDIAN)
535 emit_insn (gen_kcras16_1_be (operands[0], operands[1], operands[2]));
537 emit_insn (gen_kcras16_1_le (operands[0], operands[1], operands[2]));
541 (define_insn "kcras16_1_le"
542 [(set (match_operand:V2HI 0 "register_operand" "=r")
547 (match_operand:V2HI 1 "register_operand" " r")
548 (parallel [(const_int 0)]))
550 (match_operand:V2HI 2 "register_operand" " r")
551 (parallel [(const_int 1)]))))
556 (parallel [(const_int 0)]))
559 (parallel [(const_int 1)]))))
561 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
562 "kcras16\t%0, %1, %2"
563 [(set_attr "type" "dalu")]
566 (define_insn "kcras16_1_be"
567 [(set (match_operand:V2HI 0 "register_operand" "=r")
572 (match_operand:V2HI 1 "register_operand" " r")
573 (parallel [(const_int 1)]))
575 (match_operand:V2HI 2 "register_operand" " r")
576 (parallel [(const_int 0)]))))
581 (parallel [(const_int 1)]))
584 (parallel [(const_int 0)]))))
586 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
587 "kcras16\t%0, %1, %2"
588 [(set_attr "type" "dalu")]
591 (define_expand "ukcras16_1"
592 [(match_operand:V2HI 0 "register_operand" "")
593 (match_operand:V2HI 1 "register_operand" "")
594 (match_operand:V2HI 2 "register_operand" "")]
597 if (TARGET_BIG_ENDIAN)
598 emit_insn (gen_ukcras16_1_be (operands[0], operands[1], operands[2]));
600 emit_insn (gen_ukcras16_1_le (operands[0], operands[1], operands[2]));
604 (define_insn "ukcras16_1_le"
605 [(set (match_operand:V2HI 0 "register_operand" "=r")
610 (match_operand:V2HI 1 "register_operand" " r")
611 (parallel [(const_int 0)]))
613 (match_operand:V2HI 2 "register_operand" " r")
614 (parallel [(const_int 1)]))))
619 (parallel [(const_int 0)]))
622 (parallel [(const_int 1)]))))
624 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
625 "ukcras16\t%0, %1, %2"
626 [(set_attr "type" "dalu")]
629 (define_insn "ukcras16_1_be"
630 [(set (match_operand:V2HI 0 "register_operand" "=r")
635 (match_operand:V2HI 1 "register_operand" " r")
636 (parallel [(const_int 1)]))
638 (match_operand:V2HI 2 "register_operand" " r")
639 (parallel [(const_int 0)]))))
644 (parallel [(const_int 1)]))
647 (parallel [(const_int 0)]))))
649 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
650 "ukcras16\t%0, %1, %2"
651 [(set_attr "type" "dalu")]
654 (define_expand "crsa16_1"
655 [(match_operand:V2HI 0 "register_operand" "")
656 (match_operand:V2HI 1 "register_operand" "")
657 (match_operand:V2HI 2 "register_operand" "")]
660 if (TARGET_BIG_ENDIAN)
661 emit_insn (gen_crsa16_1_be (operands[0], operands[1], operands[2]));
663 emit_insn (gen_crsa16_1_le (operands[0], operands[1], operands[2]));
667 (define_insn "crsa16_1_le"
668 [(set (match_operand:V2HI 0 "register_operand" "=r")
673 (match_operand:V2HI 1 "register_operand" " r")
674 (parallel [(const_int 1)]))
676 (match_operand:V2HI 2 "register_operand" " r")
677 (parallel [(const_int 0)]))))
682 (parallel [(const_int 0)]))
685 (parallel [(const_int 1)]))))
687 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
689 [(set_attr "type" "dalu")]
692 (define_insn "crsa16_1_be"
693 [(set (match_operand:V2HI 0 "register_operand" "=r")
698 (match_operand:V2HI 1 "register_operand" " r")
699 (parallel [(const_int 0)]))
701 (match_operand:V2HI 2 "register_operand" " r")
702 (parallel [(const_int 1)]))))
707 (parallel [(const_int 1)]))
710 (parallel [(const_int 0)]))))
712 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
714 [(set_attr "type" "dalu")]
717 (define_expand "kcrsa16_1"
718 [(match_operand:V2HI 0 "register_operand" "")
719 (match_operand:V2HI 1 "register_operand" "")
720 (match_operand:V2HI 2 "register_operand" "")]
723 if (TARGET_BIG_ENDIAN)
724 emit_insn (gen_kcrsa16_1_be (operands[0], operands[1], operands[2]));
726 emit_insn (gen_kcrsa16_1_le (operands[0], operands[1], operands[2]));
730 (define_insn "kcrsa16_1_le"
731 [(set (match_operand:V2HI 0 "register_operand" "=r")
736 (match_operand:V2HI 1 "register_operand" " r")
737 (parallel [(const_int 1)]))
739 (match_operand:V2HI 2 "register_operand" " r")
740 (parallel [(const_int 0)]))))
745 (parallel [(const_int 0)]))
748 (parallel [(const_int 1)]))))
750 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
751 "kcrsa16\t%0, %1, %2"
752 [(set_attr "type" "dalu")]
755 (define_insn "kcrsa16_1_be"
756 [(set (match_operand:V2HI 0 "register_operand" "=r")
761 (match_operand:V2HI 1 "register_operand" " r")
762 (parallel [(const_int 0)]))
764 (match_operand:V2HI 2 "register_operand" " r")
765 (parallel [(const_int 1)]))))
770 (parallel [(const_int 1)]))
773 (parallel [(const_int 0)]))))
775 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
776 "kcrsa16\t%0, %1, %2"
777 [(set_attr "type" "dalu")]
780 (define_expand "ukcrsa16_1"
781 [(match_operand:V2HI 0 "register_operand" "")
782 (match_operand:V2HI 1 "register_operand" "")
783 (match_operand:V2HI 2 "register_operand" "")]
786 if (TARGET_BIG_ENDIAN)
787 emit_insn (gen_ukcrsa16_1_be (operands[0], operands[1], operands[2]));
789 emit_insn (gen_ukcrsa16_1_le (operands[0], operands[1], operands[2]));
793 (define_insn "ukcrsa16_1_le"
794 [(set (match_operand:V2HI 0 "register_operand" "=r")
799 (match_operand:V2HI 1 "register_operand" " r")
800 (parallel [(const_int 1)]))
802 (match_operand:V2HI 2 "register_operand" " r")
803 (parallel [(const_int 0)]))))
808 (parallel [(const_int 0)]))
811 (parallel [(const_int 1)]))))
813 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
814 "ukcrsa16\t%0, %1, %2"
815 [(set_attr "type" "dalu")]
818 (define_insn "ukcrsa16_1_be"
819 [(set (match_operand:V2HI 0 "register_operand" "=r")
824 (match_operand:V2HI 1 "register_operand" " r")
825 (parallel [(const_int 0)]))
827 (match_operand:V2HI 2 "register_operand" " r")
828 (parallel [(const_int 1)]))))
833 (parallel [(const_int 1)]))
836 (parallel [(const_int 0)]))))
838 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
839 "ukcrsa16\t%0, %1, %2"
840 [(set_attr "type" "dalu")]
843 (define_expand "rcras16_1"
844 [(match_operand:V2HI 0 "register_operand" "")
845 (match_operand:V2HI 1 "register_operand" "")
846 (match_operand:V2HI 2 "register_operand" "")]
849 if (TARGET_BIG_ENDIAN)
850 emit_insn (gen_rcras16_1_be (operands[0], operands[1], operands[2]));
852 emit_insn (gen_rcras16_1_le (operands[0], operands[1], operands[2]));
856 (define_insn "rcras16_1_le"
857 [(set (match_operand:V2HI 0 "register_operand" "=r")
865 (match_operand:V2HI 1 "register_operand" " r")
866 (parallel [(const_int 0)])))
869 (match_operand:V2HI 2 "register_operand" " r")
870 (parallel [(const_int 1)]))))
879 (parallel [(const_int 0)])))
883 (parallel [(const_int 1)]))))
886 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
887 "rcras16\t%0, %1, %2"
888 [(set_attr "type" "dalu")]
891 (define_insn "rcras16_1_be"
892 [(set (match_operand:V2HI 0 "register_operand" "=r")
900 (match_operand:V2HI 1 "register_operand" " r")
901 (parallel [(const_int 1)])))
904 (match_operand:V2HI 2 "register_operand" " r")
905 (parallel [(const_int 0)]))))
914 (parallel [(const_int 1)])))
918 (parallel [(const_int 0)]))))
921 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
922 "rcras16\t%0, %1, %2"
923 [(set_attr "type" "dalu")]
926 (define_expand "urcras16_1"
927 [(match_operand:V2HI 0 "register_operand" "")
928 (match_operand:V2HI 1 "register_operand" "")
929 (match_operand:V2HI 2 "register_operand" "")]
932 if (TARGET_BIG_ENDIAN)
933 emit_insn (gen_urcras16_1_be (operands[0], operands[1], operands[2]));
935 emit_insn (gen_urcras16_1_le (operands[0], operands[1], operands[2]));
939 (define_insn "urcras16_1_le"
940 [(set (match_operand:V2HI 0 "register_operand" "=r")
948 (match_operand:V2HI 1 "register_operand" " r")
949 (parallel [(const_int 0)])))
952 (match_operand:V2HI 2 "register_operand" " r")
953 (parallel [(const_int 1)]))))
962 (parallel [(const_int 0)])))
966 (parallel [(const_int 1)]))))
969 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
970 "urcras16\t%0, %1, %2"
971 [(set_attr "type" "dalu")]
974 (define_insn "urcras16_1_be"
975 [(set (match_operand:V2HI 0 "register_operand" "=r")
983 (match_operand:V2HI 1 "register_operand" " r")
984 (parallel [(const_int 1)])))
987 (match_operand:V2HI 2 "register_operand" " r")
988 (parallel [(const_int 0)]))))
997 (parallel [(const_int 1)])))
1001 (parallel [(const_int 0)]))))
1004 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
1005 "urcras16\t%0, %1, %2"
1006 [(set_attr "type" "dalu")]
1009 (define_expand "rcrsa16_1"
1010 [(match_operand:V2HI 0 "register_operand" "")
1011 (match_operand:V2HI 1 "register_operand" "")
1012 (match_operand:V2HI 2 "register_operand" "")]
1013 "NDS32_EXT_DSP_P ()"
1015 if (TARGET_BIG_ENDIAN)
1016 emit_insn (gen_rcrsa16_1_be (operands[0], operands[1], operands[2]));
1018 emit_insn (gen_rcrsa16_1_le (operands[0], operands[1], operands[2]));
1022 (define_insn "rcrsa16_1_le"
1023 [(set (match_operand:V2HI 0 "register_operand" "=r")
1031 (match_operand:V2HI 1 "register_operand" " r")
1032 (parallel [(const_int 1)])))
1035 (match_operand:V2HI 2 "register_operand" " r")
1036 (parallel [(const_int 0)]))))
1045 (parallel [(const_int 0)])))
1049 (parallel [(const_int 1)]))))
1052 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1053 "rcrsa16\t%0, %1, %2"
1054 [(set_attr "type" "dalu")]
1057 (define_insn "rcrsa16_1_be"
1058 [(set (match_operand:V2HI 0 "register_operand" "=r")
1066 (match_operand:V2HI 1 "register_operand" " r")
1067 (parallel [(const_int 0)])))
1070 (match_operand:V2HI 2 "register_operand" " r")
1071 (parallel [(const_int 1)]))))
1080 (parallel [(const_int 1)])))
1084 (parallel [(const_int 0)]))))
1087 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
1088 "rcrsa16\t%0, %1, %2"
1089 [(set_attr "type" "dalu")]
1092 (define_expand "urcrsa16_1"
1093 [(match_operand:V2HI 0 "register_operand" "")
1094 (match_operand:V2HI 1 "register_operand" "")
1095 (match_operand:V2HI 2 "register_operand" "")]
1096 "NDS32_EXT_DSP_P ()"
1098 if (TARGET_BIG_ENDIAN)
1099 emit_insn (gen_urcrsa16_1_be (operands[0], operands[1], operands[2]));
1101 emit_insn (gen_urcrsa16_1_le (operands[0], operands[1], operands[2]));
1105 (define_insn "urcrsa16_1_le"
1106 [(set (match_operand:V2HI 0 "register_operand" "=r")
1114 (match_operand:V2HI 1 "register_operand" " r")
1115 (parallel [(const_int 1)])))
1118 (match_operand:V2HI 2 "register_operand" " r")
1119 (parallel [(const_int 0)]))))
1128 (parallel [(const_int 0)])))
1132 (parallel [(const_int 1)]))))
1135 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1136 "urcrsa16\t%0, %1, %2"
1137 [(set_attr "type" "dalu")]
1140 (define_insn "urcrsa16_1_be"
1141 [(set (match_operand:V2HI 0 "register_operand" "=r")
1149 (match_operand:V2HI 1 "register_operand" " r")
1150 (parallel [(const_int 0)])))
1153 (match_operand:V2HI 2 "register_operand" " r")
1154 (parallel [(const_int 1)]))))
1163 (parallel [(const_int 1)])))
1167 (parallel [(const_int 0)]))))
1170 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
1171 "urcrsa16\t%0, %1, %2"
1172 [(set_attr "type" "dalu")]
1175 (define_expand "<shift>v2hi3"
1176 [(set (match_operand:V2HI 0 "register_operand" "")
1177 (shifts:V2HI (match_operand:V2HI 1 "register_operand" "")
1178 (match_operand:SI 2 "nds32_rimm4u_operand" "")))]
1179 "NDS32_EXT_DSP_P ()"
1181 if (operands[2] == const0_rtx)
1183 emit_move_insn (operands[0], operands[1]);
1188 (define_insn "*ashlv2hi3"
1189 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1190 (ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
1191 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
1192 "NDS32_EXT_DSP_P ()"
1196 [(set_attr "type" "dalu,dalu")
1197 (set_attr "length" " 4, 4")])
1199 (define_insn "kslli16"
1200 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1201 (ss_ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
1202 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
1203 "NDS32_EXT_DSP_P ()"
1207 [(set_attr "type" "dalu,dalu")
1208 (set_attr "length" " 4, 4")])
1210 (define_insn "*ashrv2hi3"
1211 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1212 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
1213 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
1214 "NDS32_EXT_DSP_P ()"
1218 [(set_attr "type" "dalu,dalu")
1219 (set_attr "length" " 4, 4")])
1221 (define_insn "sra16_round"
1222 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1223 (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
1224 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))]
1226 "NDS32_EXT_DSP_P ()"
1228 srai16.u\t%0, %1, %2
1229 sra16.u\t%0, %1, %2"
1230 [(set_attr "type" "daluround,daluround")
1231 (set_attr "length" " 4, 4")])
1233 (define_insn "*lshrv2hi3"
1234 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1235 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
1236 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
1237 "NDS32_EXT_DSP_P ()"
1241 [(set_attr "type" "dalu,dalu")
1242 (set_attr "length" " 4, 4")])
1244 (define_insn "srl16_round"
1245 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1246 (unspec:V2HI [(lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
1247 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))]
1249 "NDS32_EXT_DSP_P ()"
1251 srli16.u\t%0, %1, %2
1252 srl16.u\t%0, %1, %2"
1253 [(set_attr "type" "daluround,daluround")
1254 (set_attr "length" " 4, 4")])
1256 (define_insn "kslra16"
1257 [(set (match_operand:V2HI 0 "register_operand" "=r")
1259 (lt:SI (match_operand:SI 2 "register_operand" " r")
1261 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r")
1262 (neg:SI (match_dup 2)))
1263 (ashift:V2HI (match_dup 1)
1265 "NDS32_EXT_DSP_P ()"
1266 "kslra16\t%0, %1, %2"
1267 [(set_attr "type" "dalu")
1268 (set_attr "length" "4")])
1270 (define_insn "kslra16_round"
1271 [(set (match_operand:V2HI 0 "register_operand" "=r")
1273 (lt:SI (match_operand:SI 2 "register_operand" " r")
1275 (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r")
1276 (neg:SI (match_dup 2)))]
1278 (ashift:V2HI (match_dup 1)
1280 "NDS32_EXT_DSP_P ()"
1281 "kslra16.u\t%0, %1, %2"
1282 [(set_attr "type" "daluround")
1283 (set_attr "length" "4")])
1285 (define_insn "cmpeq<bits>"
1286 [(set (match_operand:SI 0 "register_operand" "=r")
1287 (unspec:SI [(eq:SI (match_operand:VQIHI 1 "register_operand" " r")
1288 (match_operand:VQIHI 2 "register_operand" " r"))]
1289 UNSPEC_VEC_COMPARE))]
1290 "NDS32_EXT_DSP_P ()"
1291 "cmpeq<bits>\t%0, %1, %2"
1292 [(set_attr "type" "dcmp")
1293 (set_attr "length" "4")])
1295 (define_insn "scmplt<bits>"
1296 [(set (match_operand:SI 0 "register_operand" "=r")
1297 (unspec:SI [(lt:SI (match_operand:VQIHI 1 "register_operand" " r")
1298 (match_operand:VQIHI 2 "register_operand" " r"))]
1299 UNSPEC_VEC_COMPARE))]
1300 "NDS32_EXT_DSP_P ()"
1301 "scmplt<bits>\t%0, %1, %2"
1302 [(set_attr "type" "dcmp")
1303 (set_attr "length" "4")])
1305 (define_insn "scmple<bits>"
1306 [(set (match_operand:SI 0 "register_operand" "=r")
1307 (unspec:SI [(le:SI (match_operand:VQIHI 1 "register_operand" " r")
1308 (match_operand:VQIHI 2 "register_operand" " r"))]
1309 UNSPEC_VEC_COMPARE))]
1310 "NDS32_EXT_DSP_P ()"
1311 "scmple<bits>\t%0, %1, %2"
1312 [(set_attr "type" "dcmp")
1313 (set_attr "length" "4")])
1315 (define_insn "ucmplt<bits>"
1316 [(set (match_operand:SI 0 "register_operand" "=r")
1317 (unspec:SI [(ltu:SI (match_operand:VQIHI 1 "register_operand" " r")
1318 (match_operand:VQIHI 2 "register_operand" " r"))]
1319 UNSPEC_VEC_COMPARE))]
1320 "NDS32_EXT_DSP_P ()"
1321 "ucmplt<bits>\t%0, %1, %2"
1322 [(set_attr "type" "dcmp")
1323 (set_attr "length" "4")])
1325 (define_insn "ucmple<bits>"
1326 [(set (match_operand:SI 0 "register_operand" "=r")
1327 (unspec:SI [(leu:SI (match_operand:VQIHI 1 "register_operand" " r")
1328 (match_operand:VQIHI 2 "register_operand" " r"))]
1329 UNSPEC_VEC_COMPARE))]
1330 "NDS32_EXT_DSP_P ()"
1331 "ucmple<bits>\t%0, %1, %2"
1332 [(set_attr "type" "dcmp")
1333 (set_attr "length" "4")])
1335 (define_insn "sclip16"
1336 [(set (match_operand:V2HI 0 "register_operand" "= r")
1337 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
1338 (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")]
1340 "NDS32_EXT_DSP_P ()"
1341 "sclip16\t%0, %1, %2"
1342 [(set_attr "type" "dclip")
1343 (set_attr "length" "4")])
1345 (define_insn "uclip16"
1346 [(set (match_operand:V2HI 0 "register_operand" "= r")
1347 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
1348 (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")]
1350 "NDS32_EXT_DSP_P ()"
1351 "uclip16\t%0, %1, %2"
1352 [(set_attr "type" "dclip")
1353 (set_attr "length" "4")])
1355 (define_insn "khm16"
1356 [(set (match_operand:V2HI 0 "register_operand" "=r")
1357 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
1358 (match_operand:V2HI 2 "register_operand" " r")]
1360 "NDS32_EXT_DSP_P ()"
1362 [(set_attr "type" "dmul")
1363 (set_attr "length" "4")])
1365 (define_insn "khmx16"
1366 [(set (match_operand:V2HI 0 "register_operand" "=r")
1367 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
1368 (match_operand:V2HI 2 "register_operand" " r")]
1370 "NDS32_EXT_DSP_P ()"
1371 "khmx16\t%0, %1, %2"
1372 [(set_attr "type" "dmul")
1373 (set_attr "length" "4")])
1375 (define_expand "vec_setv4qi"
1376 [(match_operand:V4QI 0 "register_operand" "")
1377 (match_operand:QI 1 "register_operand" "")
1378 (match_operand:SI 2 "immediate_operand" "")]
1379 "NDS32_EXT_DSP_P ()"
1381 HOST_WIDE_INT pos = INTVAL (operands[2]);
1384 HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos;
1385 emit_insn (gen_vec_setv4qi_internal (operands[0], operands[1],
1386 operands[0], GEN_INT (elem)));
1390 (define_expand "insb"
1391 [(match_operand:V4QI 0 "register_operand" "")
1392 (match_operand:V4QI 1 "register_operand" "")
1393 (match_operand:SI 2 "register_operand" "")
1394 (match_operand:SI 3 "const_int_operand" "")]
1395 "NDS32_EXT_DSP_P ()"
1397 if (INTVAL (operands[3]) > 3 || INTVAL (operands[3]) < 0)
1400 rtx src = gen_reg_rtx (QImode);
1402 convert_move (src, operands[2], false);
1404 HOST_WIDE_INT selector_index;
1405 /* Big endian need reverse index. */
1406 if (TARGET_BIG_ENDIAN)
1407 selector_index = 4 - INTVAL (operands[3]) - 1;
1409 selector_index = INTVAL (operands[3]);
1410 rtx selector = gen_int_mode (1 << selector_index, SImode);
1411 emit_insn (gen_vec_setv4qi_internal (operands[0], src,
1412 operands[1], selector));
1416 (define_expand "insvsi"
1417 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
1418 (match_operand:SI 1 "const_int_operand" "")
1419 (match_operand:SI 2 "nds32_insv_operand" ""))
1420 (match_operand:SI 3 "register_operand" ""))]
1421 "NDS32_EXT_DSP_P ()"
1423 if (INTVAL (operands[1]) != 8)
1426 [(set_attr "type" "dinsb")
1427 (set_attr "length" "4")])
1430 (define_insn "insvsi_internal"
1431 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1433 (match_operand:SI 1 "nds32_insv_operand" "i"))
1434 (match_operand:SI 2 "register_operand" "r"))]
1435 "NDS32_EXT_DSP_P ()"
1437 [(set_attr "type" "dinsb")
1438 (set_attr "length" "4")])
1440 (define_insn "insvsiqi_internal"
1441 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1443 (match_operand:SI 1 "nds32_insv_operand" "i"))
1444 (zero_extend:SI (match_operand:QI 2 "register_operand" "r")))]
1445 "NDS32_EXT_DSP_P ()"
1447 [(set_attr "type" "dinsb")
1448 (set_attr "length" "4")])
1450 ;; Intermedium pattern for synthetize insvsiqi_internal
1451 ;; v0 = ((v1 & 0xff) << 8)
1452 (define_insn_and_split "and0xff_s8"
1453 [(set (match_operand:SI 0 "register_operand" "=r")
1454 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1456 (const_int 65280)))]
1457 "NDS32_EXT_DSP_P () && !reload_completed"
1459 "NDS32_EXT_DSP_P () && !reload_completed"
1462 rtx tmp = gen_reg_rtx (SImode);
1463 emit_insn (gen_ashlsi3 (tmp, operands[1], gen_int_mode (8, SImode)));
1464 emit_insn (gen_andsi3 (operands[0], tmp, gen_int_mode (0xffff, SImode)));
1468 ;; v0 = (v1 & 0xff00ffff) | ((v2 << 16) | 0xff0000)
1469 (define_insn_and_split "insbsi2"
1470 [(set (match_operand:SI 0 "register_operand" "=r")
1471 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
1472 (const_int -16711681))
1473 (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1475 (const_int 16711680))))]
1476 "NDS32_EXT_DSP_P () && !reload_completed"
1478 "NDS32_EXT_DSP_P () && !reload_completed"
1481 rtx tmp = gen_reg_rtx (SImode);
1482 emit_move_insn (tmp, operands[1]);
1483 emit_insn (gen_insvsi_internal (tmp, gen_int_mode(16, SImode), operands[2]));
1484 emit_move_insn (operands[0], tmp);
1488 ;; v0 = (v1 & 0xff00ffff) | v2
1489 (define_insn_and_split "ior_and0xff00ffff_reg"
1490 [(set (match_operand:SI 0 "register_operand" "=r")
1491 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
1492 (const_int -16711681))
1493 (match_operand:SI 2 "register_operand" "r")))]
1494 "NDS32_EXT_DSP_P () && !reload_completed"
1496 "NDS32_EXT_DSP_P () && !reload_completed"
1499 rtx tmp = gen_reg_rtx (SImode);
1500 emit_insn (gen_andsi3 (tmp, operands[1], gen_int_mode (0xff00ffff, SImode)));
1501 emit_insn (gen_iorsi3 (operands[0], tmp, operands[2]));
1505 (define_insn "vec_setv4qi_internal"
1506 [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r")
1509 (match_operand:QI 1 "register_operand" " r, r, r, r"))
1510 (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0")
1511 (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))]
1512 "NDS32_EXT_DSP_P ()"
1514 if (TARGET_BIG_ENDIAN)
1516 const char *pats[] = { "insb\t%0, %1, 3",
1519 "insb\t%0, %1, 0" };
1520 return pats[which_alternative];
1524 const char *pats[] = { "insb\t%0, %1, 0",
1527 "insb\t%0, %1, 3" };
1528 return pats[which_alternative];
1531 [(set_attr "type" "dinsb")
1532 (set_attr "length" "4")])
1534 (define_insn "vec_setv4qi_internal_vec"
1535 [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r")
1539 (match_operand:V4QI 1 "register_operand" " r, r, r, r")
1540 (parallel [(const_int 0)])))
1541 (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0")
1542 (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))]
1543 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1549 [(set_attr "type" "dinsb")
1550 (set_attr "length" "4")])
1552 (define_insn "vec_mergev4qi_and_cv0_1"
1553 [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
1557 (match_operand:V4QI 1 "register_operand" " l,r")
1558 (parallel [(const_int 0)])))
1559 (const_vector:V4QI [
1565 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1569 [(set_attr "type" "alu,alu")
1570 (set_attr "length" " 2, 4")])
1572 (define_insn "vec_mergev4qi_and_cv0_2"
1573 [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
1575 (const_vector:V4QI [
1582 (match_operand:V4QI 1 "register_operand" " l,r")
1583 (parallel [(const_int 0)])))
1585 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1589 [(set_attr "type" "alu,alu")
1590 (set_attr "length" " 2, 4")])
1592 (define_insn "vec_mergeqi_and_cv0_1"
1593 [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
1595 (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r"))
1596 (const_vector:V4QI [
1602 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1606 [(set_attr "type" "alu,alu")
1607 (set_attr "length" " 2, 4")])
1609 (define_insn "vec_mergeqi_and_cv0_2"
1610 [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
1612 (const_vector:V4QI [
1617 (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r"))
1619 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1623 [(set_attr "type" "alu,alu")
1624 (set_attr "length" " 2, 4")])
1626 (define_expand "vec_setv2hi"
1627 [(match_operand:V2HI 0 "register_operand" "")
1628 (match_operand:HI 1 "register_operand" "")
1629 (match_operand:SI 2 "immediate_operand" "")]
1630 "NDS32_EXT_DSP_P ()"
1632 HOST_WIDE_INT pos = INTVAL (operands[2]);
1635 HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos;
1636 emit_insn (gen_vec_setv2hi_internal (operands[0], operands[1],
1637 operands[0], GEN_INT (elem)));
1641 (define_insn "vec_setv2hi_internal"
1642 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1645 (match_operand:HI 1 "register_operand" " r, r"))
1646 (match_operand:V2HI 2 "register_operand" " r, r")
1647 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))]
1648 "NDS32_EXT_DSP_P ()"
1650 if (TARGET_BIG_ENDIAN)
1652 const char *pats[] = { "pkbb16\t%0, %1, %2",
1653 "pktb16\t%0, %2, %1" };
1654 return pats[which_alternative];
1658 const char *pats[] = { "pktb16\t%0, %2, %1",
1659 "pkbb16\t%0, %1, %2" };
1660 return pats[which_alternative];
1663 [(set_attr "type" "dpack")
1664 (set_attr "length" "4")])
1666 (define_insn "vec_mergev2hi_and_cv0_1"
1667 [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
1671 (match_operand:V2HI 1 "register_operand" " l,r")
1672 (parallel [(const_int 0)])))
1673 (const_vector:V2HI [
1677 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1681 [(set_attr "type" "alu,alu")
1682 (set_attr "length" " 2, 4")])
1684 (define_insn "vec_mergev2hi_and_cv0_2"
1685 [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
1687 (const_vector:V2HI [
1692 (match_operand:V2HI 1 "register_operand" " l,r")
1693 (parallel [(const_int 0)])))
1695 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1699 [(set_attr "type" "alu,alu")
1700 (set_attr "length" " 2, 4")])
1702 (define_insn "vec_mergehi_and_cv0_1"
1703 [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
1705 (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r"))
1706 (const_vector:V2HI [
1710 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1714 [(set_attr "type" "alu,alu")
1715 (set_attr "length" " 2, 4")])
1717 (define_insn "vec_mergehi_and_cv0_2"
1718 [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
1720 (const_vector:V2HI [
1723 (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r"))
1725 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1729 [(set_attr "type" "alu,alu")
1730 (set_attr "length" " 2, 4")])
1732 (define_expand "pkbb"
1733 [(match_operand:V2HI 0 "register_operand")
1734 (match_operand:V2HI 1 "register_operand")
1735 (match_operand:V2HI 2 "register_operand")]
1736 "NDS32_EXT_DSP_P ()"
1738 if (TARGET_BIG_ENDIAN)
1740 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1741 GEN_INT (1), GEN_INT (1), GEN_INT (1)));
1745 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1746 GEN_INT (2), GEN_INT (0), GEN_INT (0)));
1751 (define_insn "pkbbsi_1"
1752 [(set (match_operand:SI 0 "register_operand" "=r")
1753 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
1755 (ashift:SI (match_operand:SI 2 "register_operand" "r")
1757 "NDS32_EXT_DSP_P ()"
1758 "pkbb16\t%0, %2, %1"
1759 [(set_attr "type" "dpack")
1760 (set_attr "length" "4")])
1762 (define_insn "pkbbsi_2"
1763 [(set (match_operand:SI 0 "register_operand" "=r")
1764 (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1766 (and:SI (match_operand:SI 1 "register_operand" "r")
1767 (const_int 65535))))]
1768 "NDS32_EXT_DSP_P ()"
1769 "pkbb16\t%0, %2, %1"
1770 [(set_attr "type" "dpack")
1771 (set_attr "length" "4")])
1773 (define_insn "pkbbsi_3"
1774 [(set (match_operand:SI 0 "register_operand" "=r")
1775 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
1776 (ashift:SI (match_operand:SI 2 "register_operand" "r")
1778 "NDS32_EXT_DSP_P ()"
1779 "pkbb16\t%0, %2, %1"
1780 [(set_attr "type" "dpack")
1781 (set_attr "length" "4")])
1783 (define_insn "pkbbsi_4"
1784 [(set (match_operand:SI 0 "register_operand" "=r")
1785 (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1787 (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))))]
1788 "NDS32_EXT_DSP_P ()"
1789 "pkbb16\t%0, %2, %1"
1790 [(set_attr "type" "dpack")
1791 (set_attr "length" "4")])
1793 ;; v0 = (v1 & 0xffff0000) | (v2 & 0xffff)
1794 (define_insn "pktbsi_1"
1795 [(set (match_operand:SI 0 "register_operand" "=r")
1796 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
1798 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1799 "NDS32_EXT_DSP_P ()"
1800 "pktb16\t%0, %1, %2"
1801 [(set_attr "type" "dpack")
1802 (set_attr "length" "4")])
1804 (define_insn "pktbsi_2"
1805 [(set (match_operand:SI 0 "register_operand" "=r")
1806 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
1808 (and:SI (match_operand:SI 2 "register_operand" "r")
1809 (const_int 65535))))]
1810 "NDS32_EXT_DSP_P ()"
1811 "pktb16\t%0, %1, %2"
1812 [(set_attr "type" "alu")
1813 (set_attr "length" "4")])
1815 (define_insn "pktbsi_3"
1816 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1819 (match_operand:SI 1 "register_operand" " r"))]
1820 "NDS32_EXT_DSP_P ()"
1821 "pktb16\t%0, %0, %1"
1822 [(set_attr "type" "dpack")
1823 (set_attr "length" "4")])
1825 (define_insn "pktbsi_4"
1826 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1829 (zero_extend:SI (match_operand:HI 1 "register_operand" " r")))]
1830 "NDS32_EXT_DSP_P ()"
1831 "pktb16\t%0, %0, %1"
1832 [(set_attr "type" "dpack")
1833 (set_attr "length" "4")])
1835 (define_insn "pkttsi"
1836 [(set (match_operand:SI 0 "register_operand" "=r")
1837 (ior:SI (and:SI (match_operand:SI 1 "register_operand" " r")
1839 (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
1841 "NDS32_EXT_DSP_P ()"
1842 "pktt16\t%0, %1, %2"
1843 [(set_attr "type" "dpack")
1844 (set_attr "length" "4")])
1846 (define_expand "pkbt"
1847 [(match_operand:V2HI 0 "register_operand")
1848 (match_operand:V2HI 1 "register_operand")
1849 (match_operand:V2HI 2 "register_operand")]
1850 "NDS32_EXT_DSP_P ()"
1852 if (TARGET_BIG_ENDIAN)
1854 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1855 GEN_INT (1), GEN_INT (1), GEN_INT (0)));
1859 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1860 GEN_INT (2), GEN_INT (0), GEN_INT (1)));
1865 (define_expand "pktt"
1866 [(match_operand:V2HI 0 "register_operand")
1867 (match_operand:V2HI 1 "register_operand")
1868 (match_operand:V2HI 2 "register_operand")]
1869 "NDS32_EXT_DSP_P ()"
1871 if (TARGET_BIG_ENDIAN)
1873 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1874 GEN_INT (1), GEN_INT (0), GEN_INT (0)));
1878 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1879 GEN_INT (2), GEN_INT (1), GEN_INT (1)));
1884 (define_expand "pktb"
1885 [(match_operand:V2HI 0 "register_operand")
1886 (match_operand:V2HI 1 "register_operand")
1887 (match_operand:V2HI 2 "register_operand")]
1888 "NDS32_EXT_DSP_P ()"
1890 if (TARGET_BIG_ENDIAN)
1892 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1893 GEN_INT (1), GEN_INT (0), GEN_INT (1)));
1897 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
1898 GEN_INT (2), GEN_INT (1), GEN_INT (0)));
1903 (define_insn "vec_mergerr"
1904 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1907 (match_operand:HI 1 "register_operand" " r, r"))
1909 (match_operand:HI 2 "register_operand" " r, r"))
1910 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))]
1911 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1915 [(set_attr "type" "dpack")
1916 (set_attr "length" "4")])
1919 (define_insn "vec_merge"
1920 [(set (match_operand:V2HI 0 "register_operand" "= r, r")
1922 (match_operand:V2HI 1 "register_operand" " r, r")
1923 (match_operand:V2HI 2 "register_operand" " r, r")
1924 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))]
1925 "NDS32_EXT_DSP_P ()"
1927 if (TARGET_BIG_ENDIAN)
1929 const char *pats[] = { "pktb16\t%0, %1, %2",
1930 "pktb16\t%0, %2, %1" };
1931 return pats[which_alternative];
1935 const char *pats[] = { "pktb16\t%0, %2, %1",
1936 "pktb16\t%0, %1, %2" };
1937 return pats[which_alternative];
1940 [(set_attr "type" "dpack")
1941 (set_attr "length" "4")])
1943 (define_insn "vec_mergerv"
1944 [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r")
1947 (match_operand:HI 1 "register_operand" " r, r, r, r"))
1950 (match_operand:V2HI 2 "register_operand" " r, r, r, r")
1951 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")])))
1952 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))]
1953 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1959 [(set_attr "type" "dpack")
1960 (set_attr "length" "4")])
1962 (define_insn "vec_mergevr"
1963 [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r")
1967 (match_operand:V2HI 1 "register_operand" " r, r, r, r")
1968 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")])))
1970 (match_operand:HI 2 "register_operand" " r, r, r, r"))
1971 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))]
1972 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
1978 [(set_attr "type" "dpack")
1979 (set_attr "length" "4")])
1981 (define_insn "vec_mergevv"
1982 [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r, r, r, r, r")
1986 (match_operand:V2HI 1 "register_operand" " r, r, r, r, r, r, r, r")
1987 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01")])))
1990 (match_operand:V2HI 2 "register_operand" " r, r, r, r, r, r, r, r")
1991 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01, Iv00")])))
1992 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv01, Iv01, Iv02, Iv02, Iv02, Iv02")))]
1993 "NDS32_EXT_DSP_P ()"
1995 if (TARGET_BIG_ENDIAN)
1997 const char *pats[] = { "pktt16\t%0, %1, %2",
1998 "pktb16\t%0, %1, %2",
1999 "pkbb16\t%0, %1, %2",
2000 "pkbt16\t%0, %1, %2",
2001 "pktt16\t%0, %2, %1",
2002 "pkbt16\t%0, %2, %1",
2003 "pkbb16\t%0, %2, %1",
2004 "pktb16\t%0, %2, %1" };
2005 return pats[which_alternative];
2009 const char *pats[] = { "pkbb16\t%0, %2, %1",
2010 "pktb16\t%0, %2, %1",
2011 "pktt16\t%0, %2, %1",
2012 "pkbt16\t%0, %2, %1",
2013 "pkbb16\t%0, %1, %2",
2014 "pkbt16\t%0, %1, %2",
2015 "pktt16\t%0, %1, %2",
2016 "pktb16\t%0, %1, %2" };
2017 return pats[which_alternative];
2020 [(set_attr "type" "dpack")
2021 (set_attr "length" "4")])
2023 (define_expand "vec_extractv4qi"
2024 [(set (match_operand:QI 0 "register_operand" "")
2026 (match_operand:V4QI 1 "nonimmediate_operand" "")
2027 (parallel [(match_operand:SI 2 "const_int_operand" "")])))]
2028 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2030 if (INTVAL (operands[2]) != 0
2031 && INTVAL (operands[2]) != 1
2032 && INTVAL (operands[2]) != 2
2033 && INTVAL (operands[2]) != 3)
2036 if (INTVAL (operands[2]) != 0 && MEM_P (operands[0]))
2040 (define_insn "vec_extractv4qi0"
2041 [(set (match_operand:QI 0 "register_operand" "=l,r,r")
2043 (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m")
2044 (parallel [(const_int 0)])))]
2045 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2047 switch (which_alternative)
2050 return "zeb33\t%0, %1";
2052 return "zeb\t%0, %1";
2054 return nds32_output_32bit_load (operands, 1);
2059 [(set_attr "type" "alu")
2060 (set_attr "length" "4")])
2062 (define_insn "vec_extractv4qi0_ze"
2063 [(set (match_operand:SI 0 "register_operand" "=l,r,r")
2066 (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m")
2067 (parallel [(const_int 0)]))))]
2068 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2070 switch (which_alternative)
2073 return "zeb33\t%0, %1";
2075 return "zeb\t%0, %1";
2077 return nds32_output_32bit_load (operands, 1);
2082 [(set_attr "type" "alu")
2083 (set_attr "length" "4")])
2085 (define_insn "vec_extractv4qi0_se"
2086 [(set (match_operand:SI 0 "register_operand" "=l,r,r")
2089 (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m")
2090 (parallel [(const_int 0)]))))]
2091 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2093 switch (which_alternative)
2096 return "seb33\t%0, %1";
2098 return "seb\t%0, %1";
2100 return nds32_output_32bit_load_s (operands, 1);
2105 [(set_attr "type" "alu")
2106 (set_attr "length" "4")])
2108 (define_insn_and_split "vec_extractv4qi1"
2109 [(set (match_operand:QI 0 "register_operand" "=r")
2111 (match_operand:V4QI 1 "register_operand" " r")
2112 (parallel [(const_int 1)])))]
2113 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2115 "NDS32_EXT_DSP_P () && !reload_completed"
2118 rtx tmp = gen_reg_rtx (V4QImode);
2119 emit_insn (gen_rotrv4qi_1 (tmp, operands[1]));
2120 emit_insn (gen_vec_extractv4qi0 (operands[0], tmp));
2123 [(set_attr "type" "alu")
2124 (set_attr "length" "4")])
2126 (define_insn_and_split "vec_extractv4qi2"
2127 [(set (match_operand:QI 0 "register_operand" "=r")
2129 (match_operand:V4QI 1 "register_operand" " r")
2130 (parallel [(const_int 2)])))]
2131 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2133 "NDS32_EXT_DSP_P () && !reload_completed"
2136 rtx tmp = gen_reg_rtx (V4QImode);
2137 emit_insn (gen_rotrv4qi_2 (tmp, operands[1]));
2138 emit_insn (gen_vec_extractv4qi0 (operands[0], tmp));
2141 [(set_attr "type" "alu")
2142 (set_attr "length" "4")])
2144 (define_insn_and_split "vec_extractv4qi3"
2145 [(set (match_operand:QI 0 "register_operand" "=r")
2147 (match_operand:V4QI 1 "register_operand" " r")
2148 (parallel [(const_int 3)])))]
2149 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2151 "NDS32_EXT_DSP_P () && !reload_completed"
2154 rtx tmp = gen_reg_rtx (V4QImode);
2155 emit_insn (gen_rotrv4qi_3 (tmp, operands[1]));
2156 emit_insn (gen_vec_extractv4qi0 (operands[0], tmp));
2159 [(set_attr "type" "alu")
2160 (set_attr "length" "4")])
2162 (define_insn "vec_extractv4qi3_se"
2163 [(set (match_operand:SI 0 "register_operand" "=$d,r")
2166 (match_operand:V4QI 1 "register_operand" " 0,r")
2167 (parallel [(const_int 3)]))))]
2168 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2172 [(set_attr "type" "alu,alu")
2173 (set_attr "length" " 2, 4")])
2175 (define_insn "vec_extractv4qi3_ze"
2176 [(set (match_operand:SI 0 "register_operand" "=$d,r")
2179 (match_operand:V4QI 1 "register_operand" " 0,r")
2180 (parallel [(const_int 3)]))))]
2181 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2185 [(set_attr "type" "alu,alu")
2186 (set_attr "length" " 2, 4")])
2188 (define_insn_and_split "vec_extractv4qihi0"
2189 [(set (match_operand:HI 0 "register_operand" "=r")
2192 (match_operand:V4QI 1 "register_operand" " r")
2193 (parallel [(const_int 0)]))))]
2194 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2196 "NDS32_EXT_DSP_P () && !reload_completed"
2199 rtx tmp = gen_reg_rtx (QImode);
2200 emit_insn (gen_vec_extractv4qi0 (tmp, operands[1]));
2201 emit_insn (gen_extendqihi2 (operands[0], tmp));
2204 [(set_attr "type" "alu")
2205 (set_attr "length" "4")])
2207 (define_insn_and_split "vec_extractv4qihi1"
2208 [(set (match_operand:HI 0 "register_operand" "=r")
2211 (match_operand:V4QI 1 "register_operand" " r")
2212 (parallel [(const_int 1)]))))]
2213 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2215 "NDS32_EXT_DSP_P () && !reload_completed"
2218 rtx tmp = gen_reg_rtx (QImode);
2219 emit_insn (gen_vec_extractv4qi1 (tmp, operands[1]));
2220 emit_insn (gen_extendqihi2 (operands[0], tmp));
2223 [(set_attr "type" "alu")
2224 (set_attr "length" "4")])
2226 (define_insn_and_split "vec_extractv4qihi2"
2227 [(set (match_operand:HI 0 "register_operand" "=r")
2230 (match_operand:V4QI 1 "register_operand" " r")
2231 (parallel [(const_int 2)]))))]
2232 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2234 "NDS32_EXT_DSP_P () && !reload_completed"
2237 rtx tmp = gen_reg_rtx (QImode);
2238 emit_insn (gen_vec_extractv4qi2 (tmp, operands[1]));
2239 emit_insn (gen_extendqihi2 (operands[0], tmp));
2242 [(set_attr "type" "alu")
2243 (set_attr "length" "4")])
2245 (define_insn_and_split "vec_extractv4qihi3"
2246 [(set (match_operand:HI 0 "register_operand" "=r")
2249 (match_operand:V4QI 1 "register_operand" " r")
2250 (parallel [(const_int 3)]))))]
2251 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
2253 "NDS32_EXT_DSP_P () && !reload_completed"
2256 rtx tmp = gen_reg_rtx (QImode);
2257 emit_insn (gen_vec_extractv4qi3 (tmp, operands[1]));
2258 emit_insn (gen_extendqihi2 (operands[0], tmp));
2261 [(set_attr "type" "alu")
2262 (set_attr "length" "4")])
2264 (define_expand "vec_extractv2hi"
2265 [(set (match_operand:HI 0 "register_operand" "")
2267 (match_operand:V2HI 1 "nonimmediate_operand" "")
2268 (parallel [(match_operand:SI 2 "const_int_operand" "")])))]
2269 "NDS32_EXT_DSP_P ()"
2271 if (INTVAL (operands[2]) != 0
2272 && INTVAL (operands[2]) != 1)
2275 if (INTVAL (operands[2]) != 0 && MEM_P (operands[0]))
2279 (define_insn "vec_extractv2hi0"
2280 [(set (match_operand:HI 0 "register_operand" "=$l,r,r")
2282 (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m")
2283 (parallel [(const_int 0)])))]
2284 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2286 switch (which_alternative)
2289 return "seh33\t%0, %1";
2291 return "seh\t%0, %1";
2293 return nds32_output_32bit_load_s (operands, 2);
2299 [(set_attr "type" "alu,alu,load")
2300 (set_attr "length" " 2, 4, 4")])
2302 (define_insn "vec_extractv2hi0_ze"
2303 [(set (match_operand:SI 0 "register_operand" "=$l, r,$ l, *r")
2306 (match_operand:V2HI 1 "nonimmediate_operand" " l, r, U33, m")
2307 (parallel [(const_int 0)]))))]
2308 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2310 switch (which_alternative)
2313 return "zeh33\t%0, %1";
2315 return "zeh\t%0, %1";
2317 return nds32_output_16bit_load (operands, 2);
2319 return nds32_output_32bit_load (operands, 2);
2325 [(set_attr "type" "alu,alu,load,load")
2326 (set_attr "length" " 2, 4, 2, 4")])
2328 (define_insn "vec_extractv2hi0_se"
2329 [(set (match_operand:SI 0 "register_operand" "=$l, r, r")
2332 (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m")
2333 (parallel [(const_int 0)]))))]
2334 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2336 switch (which_alternative)
2339 return "seh33\t%0, %1";
2341 return "seh\t%0, %1";
2343 return nds32_output_32bit_load_s (operands, 2);
2349 [(set_attr "type" "alu,alu,load")
2350 (set_attr "length" " 2, 4, 4")])
2352 (define_insn "vec_extractv2hi0_be"
2353 [(set (match_operand:HI 0 "register_operand" "=$d,r")
2355 (match_operand:V2HI 1 "register_operand" " 0,r")
2356 (parallel [(const_int 0)])))]
2357 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2361 [(set_attr "type" "alu,alu")
2362 (set_attr "length" " 2, 4")])
2364 (define_insn "vec_extractv2hi1"
2365 [(set (match_operand:HI 0 "register_operand" "=$d,r")
2367 (match_operand:V2HI 1 "register_operand" " 0,r")
2368 (parallel [(const_int 1)])))]
2369 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2373 [(set_attr "type" "alu,alu")
2374 (set_attr "length" " 2, 4")])
2376 (define_insn "vec_extractv2hi1_se"
2377 [(set (match_operand:SI 0 "register_operand" "=$d,r")
2380 (match_operand:V2HI 1 "register_operand" " 0,r")
2381 (parallel [(const_int 1)]))))]
2382 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2386 [(set_attr "type" "alu,alu")
2387 (set_attr "length" " 2, 4")])
2389 (define_insn "vec_extractv2hi1_ze"
2390 [(set (match_operand:SI 0 "register_operand" "=$d,r")
2393 (match_operand:V2HI 1 "register_operand" " 0,r")
2394 (parallel [(const_int 1)]))))]
2395 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2399 [(set_attr "type" "alu,alu")
2400 (set_attr "length" " 2, 4")])
2402 (define_insn "vec_extractv2hi1_be"
2403 [(set (match_operand:HI 0 "register_operand" "=$l,r,r")
2405 (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m")
2406 (parallel [(const_int 1)])))]
2407 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2409 switch (which_alternative)
2412 return "seh33\t%0, %1";
2414 return "seh\t%0, %1";
2416 return nds32_output_32bit_load_s (operands, 2);
2422 [(set_attr "type" "alu,alu,load")
2423 (set_attr "length" " 2, 4, 4")])
2425 (define_insn "<su>mul16"
2426 [(set (match_operand:V2SI 0 "register_operand" "=r")
2427 (mult:V2SI (extend:V2SI (match_operand:V2HI 1 "register_operand" "%r"))
2428 (extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))))]
2429 "NDS32_EXT_DSP_P ()"
2430 "<su>mul16\t%0, %1, %2"
2431 [(set_attr "type" "dmul")
2432 (set_attr "length" "4")])
2434 (define_insn "<su>mulx16"
2435 [(set (match_operand:V2SI 0 "register_operand" "=r")
2441 (match_operand:V2HI 1 "register_operand" " r")
2442 (parallel [(const_int 0)])))
2445 (match_operand:V2HI 2 "register_operand" " r")
2446 (parallel [(const_int 1)])))))
2452 (parallel [(const_int 1)])))
2456 (parallel [(const_int 0)])))))
2458 "NDS32_EXT_DSP_P ()"
2459 "<su>mulx16\t%0, %1, %2"
2460 [(set_attr "type" "dmul")
2461 (set_attr "length" "4")])
2463 (define_insn "rotrv2hi_1"
2464 [(set (match_operand:V2HI 0 "register_operand" "=r")
2466 (match_operand:V2HI 1 "register_operand" " r")
2467 (parallel [(const_int 1) (const_int 0)])))]
2468 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2470 [(set_attr "type" "alu")
2471 (set_attr "length" "4")])
2473 (define_insn "rotrv2hi_1_be"
2474 [(set (match_operand:V2HI 0 "register_operand" "=r")
2476 (match_operand:V2HI 1 "register_operand" " r")
2477 (parallel [(const_int 0) (const_int 1)])))]
2478 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2480 [(set_attr "type" "alu")
2481 (set_attr "length" "4")])
2483 (define_insn "rotrv4qi_1"
2484 [(set (match_operand:V4QI 0 "register_operand" "=r")
2486 (match_operand:V4QI 1 "register_operand" " r")
2487 (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 0)])))]
2488 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2490 [(set_attr "type" "alu")
2491 (set_attr "length" "4")])
2493 (define_insn "rotrv4qi_1_be"
2494 [(set (match_operand:V4QI 0 "register_operand" "=r")
2496 (match_operand:V4QI 1 "register_operand" " r")
2497 (parallel [(const_int 2) (const_int 1) (const_int 0) (const_int 3)])))]
2498 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2500 [(set_attr "type" "alu")
2501 (set_attr "length" "4")])
2503 (define_insn "rotrv4qi_2"
2504 [(set (match_operand:V4QI 0 "register_operand" "=r")
2506 (match_operand:V4QI 1 "register_operand" " r")
2507 (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))]
2508 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2510 [(set_attr "type" "alu")
2511 (set_attr "length" "4")])
2513 (define_insn "rotrv4qi_2_be"
2514 [(set (match_operand:V4QI 0 "register_operand" "=r")
2516 (match_operand:V4QI 1 "register_operand" " r")
2517 (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))]
2518 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2520 [(set_attr "type" "alu")
2521 (set_attr "length" "4")])
2523 (define_insn "rotrv4qi_3"
2524 [(set (match_operand:V4QI 0 "register_operand" "=r")
2526 (match_operand:V4QI 1 "register_operand" " r")
2527 (parallel [(const_int 3) (const_int 0) (const_int 1) (const_int 2)])))]
2528 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2530 [(set_attr "type" "alu")
2531 (set_attr "length" "4")])
2533 (define_insn "rotrv4qi_3_be"
2534 [(set (match_operand:V4QI 0 "register_operand" "=r")
2536 (match_operand:V4QI 1 "register_operand" " r")
2537 (parallel [(const_int 0) (const_int 3) (const_int 2) (const_int 1)])))]
2538 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2540 [(set_attr "type" "alu")
2541 (set_attr "length" "4")])
2543 (define_insn "v4qi_dup_10"
2544 [(set (match_operand:V4QI 0 "register_operand" "=r")
2546 (match_operand:V4QI 1 "register_operand" " r")
2547 (parallel [(const_int 0) (const_int 1) (const_int 0) (const_int 1)])))]
2548 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2550 [(set_attr "type" "dpack")
2551 (set_attr "length" "4")])
2553 (define_insn "v4qi_dup_32"
2554 [(set (match_operand:V4QI 0 "register_operand" "=r")
2556 (match_operand:V4QI 1 "register_operand" " r")
2557 (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)])))]
2558 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2560 [(set_attr "type" "dpack")
2561 (set_attr "length" "4")])
2563 (define_expand "vec_unpacks_lo_v4qi"
2564 [(match_operand:V2HI 0 "register_operand" "=r")
2565 (match_operand:V4QI 1 "register_operand" " r")]
2566 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2568 emit_insn (gen_sunpkd810 (operands[0], operands[1]));
2572 (define_expand "sunpkd810"
2573 [(match_operand:V2HI 0 "register_operand")
2574 (match_operand:V4QI 1 "register_operand")]
2575 "NDS32_EXT_DSP_P ()"
2577 if (TARGET_BIG_ENDIAN)
2578 emit_insn (gen_sunpkd810_imp_be (operands[0], operands[1]));
2580 emit_insn (gen_sunpkd810_imp (operands[0], operands[1]));
2584 (define_insn "<zs>unpkd810_imp"
2585 [(set (match_operand:V2HI 0 "register_operand" "=r")
2590 (match_operand:V4QI 1 "register_operand" " r")
2591 (parallel [(const_int 1)]))))
2596 (parallel [(const_int 0)]))))
2598 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2599 "<zs>unpkd810\t%0, %1"
2600 [(set_attr "type" "dpack")
2601 (set_attr "length" "4")])
2603 (define_insn "<zs>unpkd810_imp_inv"
2604 [(set (match_operand:V2HI 0 "register_operand" "=r")
2609 (match_operand:V4QI 1 "register_operand" " r")
2610 (parallel [(const_int 0)]))))
2615 (parallel [(const_int 1)]))))
2617 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2618 "<zs>unpkd810\t%0, %1"
2619 [(set_attr "type" "dpack")
2620 (set_attr "length" "4")])
2622 (define_insn "<zs>unpkd810_imp_be"
2623 [(set (match_operand:V2HI 0 "register_operand" "=r")
2628 (match_operand:V4QI 1 "register_operand" " r")
2629 (parallel [(const_int 2)]))))
2634 (parallel [(const_int 3)]))))
2636 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2637 "<zs>unpkd810\t%0, %1"
2638 [(set_attr "type" "dpack")
2639 (set_attr "length" "4")])
2641 (define_insn "<zs>unpkd810_imp_inv_be"
2642 [(set (match_operand:V2HI 0 "register_operand" "=r")
2647 (match_operand:V4QI 1 "register_operand" " r")
2648 (parallel [(const_int 3)]))))
2653 (parallel [(const_int 2)]))))
2655 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2656 "<zs>unpkd810\t%0, %1"
2657 [(set_attr "type" "dpack")
2658 (set_attr "length" "4")])
2660 (define_expand "sunpkd820"
2661 [(match_operand:V2HI 0 "register_operand")
2662 (match_operand:V4QI 1 "register_operand")]
2663 "NDS32_EXT_DSP_P ()"
2665 if (TARGET_BIG_ENDIAN)
2666 emit_insn (gen_sunpkd820_imp_be (operands[0], operands[1]));
2668 emit_insn (gen_sunpkd820_imp (operands[0], operands[1]));
2672 (define_insn "<zs>unpkd820_imp"
2673 [(set (match_operand:V2HI 0 "register_operand" "=r")
2678 (match_operand:V4QI 1 "register_operand" " r")
2679 (parallel [(const_int 2)]))))
2684 (parallel [(const_int 0)]))))
2686 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2687 "<zs>unpkd820\t%0, %1"
2688 [(set_attr "type" "dpack")
2689 (set_attr "length" "4")])
2691 (define_insn "<zs>unpkd820_imp_inv"
2692 [(set (match_operand:V2HI 0 "register_operand" "=r")
2697 (match_operand:V4QI 1 "register_operand" " r")
2698 (parallel [(const_int 0)]))))
2703 (parallel [(const_int 2)]))))
2705 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2706 "<zs>unpkd820\t%0, %1"
2707 [(set_attr "type" "dpack")
2708 (set_attr "length" "4")])
2710 (define_insn "<zs>unpkd820_imp_be"
2711 [(set (match_operand:V2HI 0 "register_operand" "=r")
2716 (match_operand:V4QI 1 "register_operand" " r")
2717 (parallel [(const_int 1)]))))
2722 (parallel [(const_int 3)]))))
2724 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2725 "<zs>unpkd820\t%0, %1"
2726 [(set_attr "type" "dpack")
2727 (set_attr "length" "4")])
2729 (define_insn "<zs>unpkd820_imp_inv_be"
2730 [(set (match_operand:V2HI 0 "register_operand" "=r")
2735 (match_operand:V4QI 1 "register_operand" " r")
2736 (parallel [(const_int 3)]))))
2741 (parallel [(const_int 1)]))))
2743 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2744 "<zs>unpkd820\t%0, %1"
2745 [(set_attr "type" "dpack")
2746 (set_attr "length" "4")])
2748 (define_expand "sunpkd830"
2749 [(match_operand:V2HI 0 "register_operand")
2750 (match_operand:V4QI 1 "register_operand")]
2751 "NDS32_EXT_DSP_P ()"
2753 if (TARGET_BIG_ENDIAN)
2754 emit_insn (gen_sunpkd830_imp_be (operands[0], operands[1]));
2756 emit_insn (gen_sunpkd830_imp (operands[0], operands[1]));
2760 (define_insn "<zs>unpkd830_imp"
2761 [(set (match_operand:V2HI 0 "register_operand" "=r")
2766 (match_operand:V4QI 1 "register_operand" " r")
2767 (parallel [(const_int 3)]))))
2772 (parallel [(const_int 0)]))))
2774 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2775 "<zs>unpkd830\t%0, %1"
2776 [(set_attr "type" "dpack")
2777 (set_attr "length" "4")])
2779 (define_insn "<zs>unpkd830_imp_inv"
2780 [(set (match_operand:V2HI 0 "register_operand" "=r")
2785 (match_operand:V4QI 1 "register_operand" " r")
2786 (parallel [(const_int 0)]))))
2791 (parallel [(const_int 3)]))))
2793 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2794 "<zs>unpkd830\t%0, %1"
2795 [(set_attr "type" "dpack")
2796 (set_attr "length" "4")])
2798 (define_insn "<zs>unpkd830_imp_be"
2799 [(set (match_operand:V2HI 0 "register_operand" "=r")
2804 (match_operand:V4QI 1 "register_operand" " r")
2805 (parallel [(const_int 0)]))))
2810 (parallel [(const_int 3)]))))
2812 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2813 "<zs>unpkd830\t%0, %1"
2814 [(set_attr "type" "dpack")
2815 (set_attr "length" "4")])
2817 (define_insn "<zs>unpkd830_imp_inv_be"
2818 [(set (match_operand:V2HI 0 "register_operand" "=r")
2823 (match_operand:V4QI 1 "register_operand" " r")
2824 (parallel [(const_int 3)]))))
2829 (parallel [(const_int 0)]))))
2831 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2832 "<zs>unpkd830\t%0, %1"
2833 [(set_attr "type" "dpack")
2834 (set_attr "length" "4")])
2836 (define_expand "sunpkd831"
2837 [(match_operand:V2HI 0 "register_operand")
2838 (match_operand:V4QI 1 "register_operand")]
2839 "NDS32_EXT_DSP_P ()"
2841 if (TARGET_BIG_ENDIAN)
2842 emit_insn (gen_sunpkd831_imp_be (operands[0], operands[1]));
2844 emit_insn (gen_sunpkd831_imp (operands[0], operands[1]));
2848 (define_insn "<zs>unpkd831_imp"
2849 [(set (match_operand:V2HI 0 "register_operand" "=r")
2854 (match_operand:V4QI 1 "register_operand" " r")
2855 (parallel [(const_int 3)]))))
2860 (parallel [(const_int 1)]))))
2862 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2863 "<zs>unpkd831\t%0, %1"
2864 [(set_attr "type" "dpack")
2865 (set_attr "length" "4")])
2867 (define_insn "<zs>unpkd831_imp_inv"
2868 [(set (match_operand:V2HI 0 "register_operand" "=r")
2873 (match_operand:V4QI 1 "register_operand" " r")
2874 (parallel [(const_int 1)]))))
2879 (parallel [(const_int 3)]))))
2881 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
2882 "<zs>unpkd831\t%0, %1"
2883 [(set_attr "type" "dpack")
2884 (set_attr "length" "4")])
2886 (define_insn "<zs>unpkd831_imp_be"
2887 [(set (match_operand:V2HI 0 "register_operand" "=r")
2892 (match_operand:V4QI 1 "register_operand" " r")
2893 (parallel [(const_int 0)]))))
2898 (parallel [(const_int 2)]))))
2900 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2901 "<zs>unpkd831\t%0, %1"
2902 [(set_attr "type" "dpack")
2903 (set_attr "length" "4")])
2905 (define_insn "<zs>unpkd831_imp_inv_be"
2906 [(set (match_operand:V2HI 0 "register_operand" "=r")
2911 (match_operand:V4QI 1 "register_operand" " r")
2912 (parallel [(const_int 2)]))))
2917 (parallel [(const_int 0)]))))
2919 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
2920 "<zs>unpkd831\t%0, %1"
2921 [(set_attr "type" "dpack")
2922 (set_attr "length" "4")])
2924 (define_expand "zunpkd810"
2925 [(match_operand:V2HI 0 "register_operand")
2926 (match_operand:V4QI 1 "register_operand")]
2927 "NDS32_EXT_DSP_P ()"
2929 if (TARGET_BIG_ENDIAN)
2930 emit_insn (gen_zunpkd810_imp_be (operands[0], operands[1]));
2932 emit_insn (gen_zunpkd810_imp (operands[0], operands[1]));
2936 (define_expand "zunpkd820"
2937 [(match_operand:V2HI 0 "register_operand")
2938 (match_operand:V4QI 1 "register_operand")]
2939 "NDS32_EXT_DSP_P ()"
2941 if (TARGET_BIG_ENDIAN)
2942 emit_insn (gen_zunpkd820_imp_be (operands[0], operands[1]));
2944 emit_insn (gen_zunpkd820_imp (operands[0], operands[1]));
2948 (define_expand "zunpkd830"
2949 [(match_operand:V2HI 0 "register_operand")
2950 (match_operand:V4QI 1 "register_operand")]
2951 "NDS32_EXT_DSP_P ()"
2953 if (TARGET_BIG_ENDIAN)
2954 emit_insn (gen_zunpkd830_imp_be (operands[0], operands[1]));
2956 emit_insn (gen_zunpkd830_imp (operands[0], operands[1]));
2960 (define_expand "zunpkd831"
2961 [(match_operand:V2HI 0 "register_operand")
2962 (match_operand:V4QI 1 "register_operand")]
2963 "NDS32_EXT_DSP_P ()"
2965 if (TARGET_BIG_ENDIAN)
2966 emit_insn (gen_zunpkd831_imp_be (operands[0], operands[1]));
2968 emit_insn (gen_zunpkd831_imp (operands[0], operands[1]));
2972 (define_expand "smbb"
2973 [(match_operand:SI 0 "register_operand" "")
2974 (match_operand:V2HI 1 "register_operand" "")
2975 (match_operand:V2HI 2 "register_operand" "")]
2976 "NDS32_EXT_DSP_P ()"
2978 if (TARGET_BIG_ENDIAN)
2979 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
2980 GEN_INT (1), GEN_INT (1)));
2982 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
2983 GEN_INT (0), GEN_INT (0)));
2987 (define_expand "smbt"
2988 [(match_operand:SI 0 "register_operand" "")
2989 (match_operand:V2HI 1 "register_operand" "")
2990 (match_operand:V2HI 2 "register_operand" "")]
2991 "NDS32_EXT_DSP_P ()"
2993 if (TARGET_BIG_ENDIAN)
2994 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
2995 GEN_INT (1), GEN_INT (0)));
2997 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
2998 GEN_INT (0), GEN_INT (1)));
3002 (define_expand "smtt"
3003 [(match_operand:SI 0 "register_operand" "")
3004 (match_operand:V2HI 1 "register_operand" "")
3005 (match_operand:V2HI 2 "register_operand" "")]
3006 "NDS32_EXT_DSP_P ()"
3008 if (TARGET_BIG_ENDIAN)
3009 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
3010 GEN_INT (0), GEN_INT (0)));
3012 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
3013 GEN_INT (1), GEN_INT (1)));
3017 (define_insn "mulhisi3v"
3018 [(set (match_operand:SI 0 "register_operand" "= r, r, r, r")
3022 (match_operand:V2HI 1 "register_operand" " r, r, r, r")
3023 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
3024 (sign_extend:SI (vec_select:HI
3025 (match_operand:V2HI 2 "register_operand" " r, r, r, r")
3026 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))))]
3027 "NDS32_EXT_DSP_P ()"
3029 if (TARGET_BIG_ENDIAN)
3031 const char *pats[] = { "smtt\t%0, %1, %2",
3034 "smbt\t%0, %1, %2" };
3035 return pats[which_alternative];
3039 const char *pats[] = { "smbb\t%0, %1, %2",
3042 "smbt\t%0, %2, %1" };
3043 return pats[which_alternative];
3046 [(set_attr "type" "dmul")
3047 (set_attr "length" "4")])
3049 (define_expand "kmabb"
3050 [(match_operand:SI 0 "register_operand" "")
3051 (match_operand:SI 1 "register_operand" "")
3052 (match_operand:V2HI 2 "register_operand" "")
3053 (match_operand:V2HI 3 "register_operand" "")]
3054 "NDS32_EXT_DSP_P ()"
3056 if (TARGET_BIG_ENDIAN)
3057 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
3058 GEN_INT (1), GEN_INT (1),
3061 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
3062 GEN_INT (0), GEN_INT (0),
3067 (define_expand "kmabt"
3068 [(match_operand:SI 0 "register_operand" "")
3069 (match_operand:SI 1 "register_operand" "")
3070 (match_operand:V2HI 2 "register_operand" "")
3071 (match_operand:V2HI 3 "register_operand" "")]
3072 "NDS32_EXT_DSP_P ()"
3074 if (TARGET_BIG_ENDIAN)
3075 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
3076 GEN_INT (1), GEN_INT (0),
3079 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
3080 GEN_INT (0), GEN_INT (1),
3085 (define_expand "kmatt"
3086 [(match_operand:SI 0 "register_operand" "")
3087 (match_operand:SI 1 "register_operand" "")
3088 (match_operand:V2HI 2 "register_operand" "")
3089 (match_operand:V2HI 3 "register_operand" "")]
3090 "NDS32_EXT_DSP_P ()"
3092 if (TARGET_BIG_ENDIAN)
3093 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
3094 GEN_INT (0), GEN_INT (0),
3097 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
3098 GEN_INT (1), GEN_INT (1),
3103 (define_insn "kma_internal"
3104 [(set (match_operand:SI 0 "register_operand" "= r, r, r, r")
3109 (match_operand:V2HI 1 "register_operand" " r, r, r, r")
3110 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
3113 (match_operand:V2HI 2 "register_operand" " r, r, r, r")
3114 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))
3115 (match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))]
3116 "NDS32_EXT_DSP_P ()"
3118 if (TARGET_BIG_ENDIAN)
3120 const char *pats[] = { "kmatt\t%0, %1, %2",
3121 "kmabt\t%0, %2, %1",
3122 "kmabb\t%0, %1, %2",
3123 "kmabt\t%0, %1, %2" };
3124 return pats[which_alternative];
3128 const char *pats[] = { "kmabb\t%0, %1, %2",
3129 "kmabt\t%0, %1, %2",
3130 "kmatt\t%0, %1, %2",
3131 "kmabt\t%0, %2, %1" };
3132 return pats[which_alternative];
3135 [(set_attr "type" "dmac")
3136 (set_attr "length" "4")])
3138 (define_expand "smds"
3139 [(match_operand:SI 0 "register_operand" "")
3140 (match_operand:V2HI 1 "register_operand" "")
3141 (match_operand:V2HI 2 "register_operand" "")]
3142 "NDS32_EXT_DSP_P ()"
3144 if (TARGET_BIG_ENDIAN)
3145 emit_insn (gen_smds_be (operands[0], operands[1], operands[2]));
3147 emit_insn (gen_smds_le (operands[0], operands[1], operands[2]));
3151 (define_expand "smds_le"
3152 [(set (match_operand:SI 0 "register_operand" "=r")
3155 (sign_extend:SI (vec_select:HI
3156 (match_operand:V2HI 1 "register_operand" " r")
3157 (parallel [(const_int 1)])))
3158 (sign_extend:SI (vec_select:HI
3159 (match_operand:V2HI 2 "register_operand" " r")
3160 (parallel [(const_int 1)]))))
3162 (sign_extend:SI (vec_select:HI
3164 (parallel [(const_int 0)])))
3165 (sign_extend:SI (vec_select:HI
3167 (parallel [(const_int 0)]))))))]
3168 "NDS32_EXT_DSP_P ()"
3172 (define_expand "smds_be"
3173 [(set (match_operand:SI 0 "register_operand" "=r")
3176 (sign_extend:SI (vec_select:HI
3177 (match_operand:V2HI 1 "register_operand" " r")
3178 (parallel [(const_int 0)])))
3179 (sign_extend:SI (vec_select:HI
3180 (match_operand:V2HI 2 "register_operand" " r")
3181 (parallel [(const_int 0)]))))
3183 (sign_extend:SI (vec_select:HI
3185 (parallel [(const_int 1)])))
3186 (sign_extend:SI (vec_select:HI
3188 (parallel [(const_int 1)]))))))]
3189 "NDS32_EXT_DSP_P ()"
3193 (define_expand "smdrs"
3194 [(match_operand:SI 0 "register_operand" "")
3195 (match_operand:V2HI 1 "register_operand" "")
3196 (match_operand:V2HI 2 "register_operand" "")]
3197 "NDS32_EXT_DSP_P ()"
3199 if (TARGET_BIG_ENDIAN)
3200 emit_insn (gen_smdrs_be (operands[0], operands[1], operands[2]));
3202 emit_insn (gen_smdrs_le (operands[0], operands[1], operands[2]));
3206 (define_expand "smdrs_le"
3207 [(set (match_operand:SI 0 "register_operand" "=r")
3210 (sign_extend:SI (vec_select:HI
3211 (match_operand:V2HI 1 "register_operand" " r")
3212 (parallel [(const_int 0)])))
3213 (sign_extend:SI (vec_select:HI
3214 (match_operand:V2HI 2 "register_operand" " r")
3215 (parallel [(const_int 0)]))))
3217 (sign_extend:SI (vec_select:HI
3219 (parallel [(const_int 1)])))
3220 (sign_extend:SI (vec_select:HI
3222 (parallel [(const_int 1)]))))))]
3223 "NDS32_EXT_DSP_P ()"
3227 (define_expand "smdrs_be"
3228 [(set (match_operand:SI 0 "register_operand" "=r")
3231 (sign_extend:SI (vec_select:HI
3232 (match_operand:V2HI 1 "register_operand" " r")
3233 (parallel [(const_int 1)])))
3234 (sign_extend:SI (vec_select:HI
3235 (match_operand:V2HI 2 "register_operand" " r")
3236 (parallel [(const_int 1)]))))
3238 (sign_extend:SI (vec_select:HI
3240 (parallel [(const_int 0)])))
3241 (sign_extend:SI (vec_select:HI
3243 (parallel [(const_int 0)]))))))]
3244 "NDS32_EXT_DSP_P ()"
3248 (define_expand "smxdsv"
3249 [(match_operand:SI 0 "register_operand" "")
3250 (match_operand:V2HI 1 "register_operand" "")
3251 (match_operand:V2HI 2 "register_operand" "")]
3252 "NDS32_EXT_DSP_P ()"
3254 if (TARGET_BIG_ENDIAN)
3255 emit_insn (gen_smxdsv_be (operands[0], operands[1], operands[2]));
3257 emit_insn (gen_smxdsv_le (operands[0], operands[1], operands[2]));
3262 (define_expand "smxdsv_le"
3263 [(set (match_operand:SI 0 "register_operand" "=r")
3266 (sign_extend:SI (vec_select:HI
3267 (match_operand:V2HI 1 "register_operand" " r")
3268 (parallel [(const_int 1)])))
3269 (sign_extend:SI (vec_select:HI
3270 (match_operand:V2HI 2 "register_operand" " r")
3271 (parallel [(const_int 0)]))))
3273 (sign_extend:SI (vec_select:HI
3275 (parallel [(const_int 0)])))
3276 (sign_extend:SI (vec_select:HI
3278 (parallel [(const_int 1)]))))))]
3279 "NDS32_EXT_DSP_P ()"
3283 (define_expand "smxdsv_be"
3284 [(set (match_operand:SI 0 "register_operand" "=r")
3287 (sign_extend:SI (vec_select:HI
3288 (match_operand:V2HI 1 "register_operand" " r")
3289 (parallel [(const_int 0)])))
3290 (sign_extend:SI (vec_select:HI
3291 (match_operand:V2HI 2 "register_operand" " r")
3292 (parallel [(const_int 1)]))))
3294 (sign_extend:SI (vec_select:HI
3296 (parallel [(const_int 1)])))
3297 (sign_extend:SI (vec_select:HI
3299 (parallel [(const_int 0)]))))))]
3300 "NDS32_EXT_DSP_P ()"
3304 (define_insn "smal1"
3305 [(set (match_operand:DI 0 "register_operand" "=r")
3306 (plus:DI (match_operand:DI 1 "register_operand" " r")
3311 (match_operand:V2HI 2 "register_operand" " r")
3312 (parallel [(const_int 0)])))
3316 (parallel [(const_int 1)])))))))]
3317 "NDS32_EXT_DSP_P ()"
3319 [(set_attr "type" "dmac")
3320 (set_attr "length" "4")])
3322 (define_insn "smal2"
3323 [(set (match_operand:DI 0 "register_operand" "=r")
3324 (plus:DI (match_operand:DI 1 "register_operand" " r")
3328 (match_operand:V2HI 2 "register_operand" " r")
3329 (parallel [(const_int 0)])))
3333 (parallel [(const_int 1)]))))))]
3334 "NDS32_EXT_DSP_P ()"
3336 [(set_attr "type" "dmac")
3337 (set_attr "length" "4")])
3339 (define_insn "smal3"
3340 [(set (match_operand:DI 0 "register_operand" "=r")
3341 (plus:DI (match_operand:DI 1 "register_operand" " r")
3346 (match_operand:V2HI 2 "register_operand" " r")
3347 (parallel [(const_int 1)])))
3351 (parallel [(const_int 0)])))))))]
3352 "NDS32_EXT_DSP_P ()"
3354 [(set_attr "type" "dmac")
3355 (set_attr "length" "4")])
3357 (define_insn "smal4"
3358 [(set (match_operand:DI 0 "register_operand" "=r")
3359 (plus:DI (match_operand:DI 1 "register_operand" " r")
3363 (match_operand:V2HI 2 "register_operand" " r")
3364 (parallel [(const_int 1)])))
3368 (parallel [(const_int 0)]))))))]
3369 "NDS32_EXT_DSP_P ()"
3371 [(set_attr "type" "dmac")
3372 (set_attr "length" "4")])
3374 (define_insn "smal5"
3375 [(set (match_operand:DI 0 "register_operand" "=r")
3381 (match_operand:V2HI 2 "register_operand" " r")
3382 (parallel [(const_int 0)])))
3386 (parallel [(const_int 1)])))))
3387 (match_operand:DI 1 "register_operand" " r")))]
3388 "NDS32_EXT_DSP_P ()"
3390 [(set_attr "type" "dmac")
3391 (set_attr "length" "4")])
3393 (define_insn "smal6"
3394 [(set (match_operand:DI 0 "register_operand" "=r")
3399 (match_operand:V2HI 2 "register_operand" " r")
3400 (parallel [(const_int 0)])))
3404 (parallel [(const_int 1)]))))
3405 (match_operand:DI 1 "register_operand" " r")))]
3406 "NDS32_EXT_DSP_P ()"
3408 [(set_attr "type" "dmac")
3409 (set_attr "length" "4")])
3411 (define_insn "smal7"
3412 [(set (match_operand:DI 0 "register_operand" "=r")
3418 (match_operand:V2HI 2 "register_operand" " r")
3419 (parallel [(const_int 1)])))
3423 (parallel [(const_int 0)])))))
3424 (match_operand:DI 1 "register_operand" " r")))]
3425 "NDS32_EXT_DSP_P ()"
3427 [(set_attr "type" "dmac")
3428 (set_attr "length" "4")])
3430 (define_insn "smal8"
3431 [(set (match_operand:DI 0 "register_operand" "=r")
3436 (match_operand:V2HI 2 "register_operand" " r")
3437 (parallel [(const_int 1)])))
3441 (parallel [(const_int 0)]))))
3442 (match_operand:DI 1 "register_operand" " r")))]
3443 "NDS32_EXT_DSP_P ()"
3445 [(set_attr "type" "dmac")
3446 (set_attr "length" "4")])
3448 ;; We need this dummy pattern for smal
3449 (define_insn_and_split "extendsidi2"
3450 [(set (match_operand:DI 0 "register_operand" "")
3451 (sign_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))]
3452 "NDS32_EXT_DSP_P ()"
3454 "NDS32_EXT_DSP_P ()"
3457 rtx high_part_dst, low_part_dst;
3459 low_part_dst = nds32_di_low_part_subreg (operands[0]);
3460 high_part_dst = nds32_di_high_part_subreg (operands[0]);
3462 emit_move_insn (low_part_dst, operands[1]);
3463 emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31)));
3466 [(set_attr "type" "alu")
3467 (set_attr "length" "4")])
3469 ;; We need this dummy pattern for usmar64/usmsr64
3470 (define_insn_and_split "zero_extendsidi2"
3471 [(set (match_operand:DI 0 "register_operand" "")
3472 (zero_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))]
3473 "NDS32_EXT_DSP_P ()"
3475 "NDS32_EXT_DSP_P ()"
3478 rtx high_part_dst, low_part_dst;
3480 low_part_dst = nds32_di_low_part_subreg (operands[0]);
3481 high_part_dst = nds32_di_high_part_subreg (operands[0]);
3483 emit_move_insn (low_part_dst, operands[1]);
3484 emit_move_insn (high_part_dst, const0_rtx);
3487 [(set_attr "type" "alu")
3488 (set_attr "length" "4")])
3490 (define_insn_and_split "extendhidi2"
3491 [(set (match_operand:DI 0 "register_operand" "")
3492 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
3493 "NDS32_EXT_DSP_P ()"
3495 "NDS32_EXT_DSP_P ()"
3498 rtx high_part_dst, low_part_dst;
3500 low_part_dst = nds32_di_low_part_subreg (operands[0]);
3501 high_part_dst = nds32_di_high_part_subreg (operands[0]);
3504 emit_insn (gen_extendhisi2 (low_part_dst, operands[1]));
3505 emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31)));
3508 [(set_attr "type" "alu")
3509 (set_attr "length" "4")])
3511 (define_insn "extendqihi2"
3512 [(set (match_operand:HI 0 "register_operand" "=r")
3513 (sign_extend:HI (match_operand:QI 1 "register_operand" " r")))]
3514 "NDS32_EXT_DSP_P ()"
3516 [(set_attr "type" "dpack")
3517 (set_attr "length" "4")])
3519 (define_insn "smulsi3_highpart"
3520 [(set (match_operand:SI 0 "register_operand" "=r")
3524 (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
3525 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))
3527 "NDS32_EXT_DSP_P ()"
3529 [(set_attr "type" "dmul")
3530 (set_attr "length" "4")])
3532 (define_insn "smmul_round"
3533 [(set (match_operand:SI 0 "register_operand" "=r")
3536 (unspec:DI [(mult:DI
3537 (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
3538 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))]
3541 "NDS32_EXT_DSP_P ()"
3542 "smmul.u\t%0, %1, %2"
3543 [(set_attr "type" "dmul")
3544 (set_attr "length" "4")])
3546 (define_insn "kmmac"
3547 [(set (match_operand:SI 0 "register_operand" "=r")
3548 (ss_plus:SI (match_operand:SI 1 "register_operand" " 0")
3552 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
3553 (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))
3555 "NDS32_EXT_DSP_P ()"
3557 [(set_attr "type" "dmac")
3558 (set_attr "length" "4")])
3560 (define_insn "kmmac_round"
3561 [(set (match_operand:SI 0 "register_operand" "=r")
3562 (ss_plus:SI (match_operand:SI 1 "register_operand" " 0")
3565 (unspec:DI [(mult:DI
3566 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
3567 (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))]
3570 "NDS32_EXT_DSP_P ()"
3571 "kmmac.u\t%0, %2, %3"
3572 [(set_attr "type" "dmac")
3573 (set_attr "length" "4")])
3575 (define_insn "kmmsb"
3576 [(set (match_operand:SI 0 "register_operand" "=r")
3577 (ss_minus:SI (match_operand:SI 1 "register_operand" " 0")
3581 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
3582 (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))
3584 "NDS32_EXT_DSP_P ()"
3586 [(set_attr "type" "dmac")
3587 (set_attr "length" "4")])
3589 (define_insn "kmmsb_round"
3590 [(set (match_operand:SI 0 "register_operand" "=r")
3591 (ss_minus:SI (match_operand:SI 1 "register_operand" " 0")
3594 (unspec:DI [(mult:DI
3595 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
3596 (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))]
3599 "NDS32_EXT_DSP_P ()"
3600 "kmmsb.u\t%0, %2, %3"
3601 [(set_attr "type" "dmac")
3602 (set_attr "length" "4")])
3604 (define_insn "kwmmul"
3605 [(set (match_operand:SI 0 "register_operand" "=r")
3609 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2))
3610 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))
3612 "NDS32_EXT_DSP_P ()"
3613 "kwmmul\t%0, %1, %2"
3614 [(set_attr "type" "dmul")
3615 (set_attr "length" "4")])
3617 (define_insn "kwmmul_round"
3618 [(set (match_operand:SI 0 "register_operand" "=r")
3623 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2))
3624 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))]
3627 "NDS32_EXT_DSP_P ()"
3628 "kwmmul.u\t%0, %1, %2"
3629 [(set_attr "type" "dmul")
3630 (set_attr "length" "4")])
3632 (define_expand "smmwb"
3633 [(match_operand:SI 0 "register_operand" "")
3634 (match_operand:SI 1 "register_operand" "")
3635 (match_operand:V2HI 2 "register_operand" "")]
3636 "NDS32_EXT_DSP_P ()"
3638 if (TARGET_BIG_ENDIAN)
3639 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1)));
3641 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0)));
3645 (define_expand "smmwt"
3646 [(match_operand:SI 0 "register_operand" "")
3647 (match_operand:SI 1 "register_operand" "")
3648 (match_operand:V2HI 2 "register_operand" "")]
3649 "NDS32_EXT_DSP_P ()"
3651 if (TARGET_BIG_ENDIAN)
3652 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0)));
3654 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1)));
3658 (define_insn "smulhisi3_highpart_1"
3659 [(set (match_operand:SI 0 "register_operand" "= r, r")
3663 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
3666 (match_operand:V2HI 2 "register_operand" " r, r")
3667 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))
3669 "NDS32_EXT_DSP_P ()"
3671 if (TARGET_BIG_ENDIAN)
3673 const char *pats[] = { "smmwt\t%0, %1, %2",
3674 "smmwb\t%0, %1, %2" };
3675 return pats[which_alternative];
3679 const char *pats[] = { "smmwb\t%0, %1, %2",
3680 "smmwt\t%0, %1, %2" };
3681 return pats[which_alternative];
3684 [(set_attr "type" "dmul")
3685 (set_attr "length" "4")])
3687 (define_insn "smulhisi3_highpart_2"
3688 [(set (match_operand:SI 0 "register_operand" "= r, r")
3694 (match_operand:V2HI 1 "register_operand" " r, r")
3695 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))
3696 (sign_extend:DI (match_operand:SI 2 "register_operand" " r, r")))
3698 "NDS32_EXT_DSP_P ()"
3700 if (TARGET_BIG_ENDIAN)
3702 const char *pats[] = { "smmwt\t%0, %1, %2",
3703 "smmwb\t%0, %1, %2" };
3704 return pats[which_alternative];
3708 const char *pats[] = { "smmwb\t%0, %1, %2",
3709 "smmwt\t%0, %1, %2" };
3710 return pats[which_alternative];
3713 [(set_attr "type" "dmul")
3714 (set_attr "length" "4")])
3716 (define_expand "smmwb_round"
3717 [(match_operand:SI 0 "register_operand" "")
3718 (match_operand:SI 1 "register_operand" "")
3719 (match_operand:V2HI 2 "register_operand" "")]
3720 "NDS32_EXT_DSP_P ()"
3722 if (TARGET_BIG_ENDIAN)
3723 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1)));
3725 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0)));
3729 (define_expand "smmwt_round"
3730 [(match_operand:SI 0 "register_operand" "")
3731 (match_operand:SI 1 "register_operand" "")
3732 (match_operand:V2HI 2 "register_operand" "")]
3733 "NDS32_EXT_DSP_P ()"
3735 if (TARGET_BIG_ENDIAN)
3736 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0)));
3738 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1)));
3742 (define_insn "smmw_round_internal"
3743 [(set (match_operand:SI 0 "register_operand" "= r, r")
3748 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
3751 (match_operand:V2HI 2 "register_operand" " r, r")
3752 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))]
3755 "NDS32_EXT_DSP_P ()"
3757 if (TARGET_BIG_ENDIAN)
3759 const char *pats[] = { "smmwt.u\t%0, %1, %2",
3760 "smmwb.u\t%0, %1, %2" };
3761 return pats[which_alternative];
3765 const char *pats[] = { "smmwb.u\t%0, %1, %2",
3766 "smmwt.u\t%0, %1, %2" };
3767 return pats[which_alternative];
3770 [(set_attr "type" "dmul")
3771 (set_attr "length" "4")])
3773 (define_expand "kmmawb"
3774 [(match_operand:SI 0 "register_operand" "")
3775 (match_operand:SI 1 "register_operand" "")
3776 (match_operand:SI 2 "register_operand" "")
3777 (match_operand:V2HI 3 "register_operand" "")]
3778 "NDS32_EXT_DSP_P ()"
3780 if (TARGET_BIG_ENDIAN)
3781 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
3783 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
3787 (define_expand "kmmawt"
3788 [(match_operand:SI 0 "register_operand" "")
3789 (match_operand:SI 1 "register_operand" "")
3790 (match_operand:SI 2 "register_operand" "")
3791 (match_operand:V2HI 3 "register_operand" "")]
3792 "NDS32_EXT_DSP_P ()"
3794 if (TARGET_BIG_ENDIAN)
3795 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
3797 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
3801 (define_insn "kmmaw_internal"
3802 [(set (match_operand:SI 0 "register_operand" "= r, r")
3804 (match_operand:SI 4 "register_operand" " 0, 0")
3808 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
3811 (match_operand:V2HI 2 "register_operand" " r, r")
3812 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))
3814 "NDS32_EXT_DSP_P ()"
3816 if (TARGET_BIG_ENDIAN)
3818 const char *pats[] = { "kmmawt\t%0, %1, %2",
3819 "kmmawb\t%0, %1, %2" };
3820 return pats[which_alternative];
3824 const char *pats[] = { "kmmawb\t%0, %1, %2",
3825 "kmmawt\t%0, %1, %2" };
3826 return pats[which_alternative];
3829 [(set_attr "type" "dmac")
3830 (set_attr "length" "4")])
3832 (define_expand "kmmawb_round"
3833 [(match_operand:SI 0 "register_operand" "")
3834 (match_operand:SI 1 "register_operand" "")
3835 (match_operand:SI 2 "register_operand" "")
3836 (match_operand:V2HI 3 "register_operand" "")]
3837 "NDS32_EXT_DSP_P ()"
3839 if (TARGET_BIG_ENDIAN)
3840 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
3842 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
3845 [(set_attr "type" "alu")
3846 (set_attr "length" "4")])
3848 (define_expand "kmmawt_round"
3849 [(match_operand:SI 0 "register_operand" "")
3850 (match_operand:SI 1 "register_operand" "")
3851 (match_operand:SI 2 "register_operand" "")
3852 (match_operand:V2HI 3 "register_operand" "")]
3853 "NDS32_EXT_DSP_P ()"
3855 if (TARGET_BIG_ENDIAN)
3856 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
3858 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
3861 [(set_attr "type" "dmac")
3862 (set_attr "length" "4")])
3865 (define_insn "kmmaw_round_internal"
3866 [(set (match_operand:SI 0 "register_operand" "= r, r")
3868 (match_operand:SI 4 "register_operand" " 0, 0")
3873 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
3876 (match_operand:V2HI 2 "register_operand" " r, r")
3877 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))]
3880 "NDS32_EXT_DSP_P ()"
3882 if (TARGET_BIG_ENDIAN)
3884 const char *pats[] = { "kmmawt.u\t%0, %1, %2",
3885 "kmmawb.u\t%0, %1, %2" };
3886 return pats[which_alternative];
3890 const char *pats[] = { "kmmawb.u\t%0, %1, %2",
3891 "kmmawt.u\t%0, %1, %2" };
3892 return pats[which_alternative];
3895 [(set_attr "type" "dmac")
3896 (set_attr "length" "4")])
3898 (define_expand "smalbb"
3899 [(match_operand:DI 0 "register_operand" "")
3900 (match_operand:DI 1 "register_operand" "")
3901 (match_operand:V2HI 2 "register_operand" "")
3902 (match_operand:V2HI 3 "register_operand" "")]
3903 "NDS32_EXT_DSP_P ()"
3905 if (TARGET_BIG_ENDIAN)
3906 emit_insn (gen_smaddhidi (operands[0], operands[2],
3907 operands[3], operands[1],
3908 GEN_INT (1), GEN_INT (1)));
3910 emit_insn (gen_smaddhidi (operands[0], operands[2],
3911 operands[3], operands[1],
3912 GEN_INT (0), GEN_INT (0)));
3916 (define_expand "smalbt"
3917 [(match_operand:DI 0 "register_operand" "")
3918 (match_operand:DI 1 "register_operand" "")
3919 (match_operand:V2HI 2 "register_operand" "")
3920 (match_operand:V2HI 3 "register_operand" "")]
3921 "NDS32_EXT_DSP_P ()"
3923 if (TARGET_BIG_ENDIAN)
3924 emit_insn (gen_smaddhidi (operands[0], operands[2],
3925 operands[3], operands[1],
3926 GEN_INT (1), GEN_INT (0)));
3928 emit_insn (gen_smaddhidi (operands[0], operands[2],
3929 operands[3], operands[1],
3930 GEN_INT (0), GEN_INT (1)));
3934 (define_expand "smaltt"
3935 [(match_operand:DI 0 "register_operand" "")
3936 (match_operand:DI 1 "register_operand" "")
3937 (match_operand:V2HI 2 "register_operand" "")
3938 (match_operand:V2HI 3 "register_operand" "")]
3939 "NDS32_EXT_DSP_P ()"
3941 if (TARGET_BIG_ENDIAN)
3942 emit_insn (gen_smaddhidi (operands[0], operands[2],
3943 operands[3], operands[1],
3944 GEN_INT (0), GEN_INT (0)));
3946 emit_insn (gen_smaddhidi (operands[0], operands[2],
3947 operands[3], operands[1],
3948 GEN_INT (1), GEN_INT (1)));
3952 (define_insn "smaddhidi"
3953 [(set (match_operand:DI 0 "register_operand" "= r, r, r, r")
3955 (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")
3959 (match_operand:V2HI 1 "register_operand" " r, r, r, r")
3960 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
3963 (match_operand:V2HI 2 "register_operand" " r, r, r, r")
3964 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))))]
3965 "NDS32_EXT_DSP_P ()"
3967 if (TARGET_BIG_ENDIAN)
3969 const char *pats[] = { "smaltt\t%0, %1, %2",
3970 "smalbt\t%0, %2, %1",
3971 "smalbb\t%0, %1, %2",
3972 "smalbt\t%0, %1, %2" };
3973 return pats[which_alternative];
3977 const char *pats[] = { "smalbb\t%0, %1, %2",
3978 "smalbt\t%0, %1, %2",
3979 "smaltt\t%0, %1, %2",
3980 "smalbt\t%0, %2, %1" };
3981 return pats[which_alternative];
3984 [(set_attr "type" "dmac")
3985 (set_attr "length" "4")])
3987 (define_insn "smaddhidi2"
3988 [(set (match_operand:DI 0 "register_operand" "= r, r, r, r")
3993 (match_operand:V2HI 1 "register_operand" " r, r, r, r")
3994 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
3997 (match_operand:V2HI 2 "register_operand" " r, r, r, r")
3998 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))
3999 (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")))]
4000 "NDS32_EXT_DSP_P ()"
4002 if (TARGET_BIG_ENDIAN)
4004 const char *pats[] = { "smaltt\t%0, %1, %2",
4005 "smalbt\t%0, %2, %1",
4006 "smalbb\t%0, %1, %2",
4007 "smalbt\t%0, %1, %2" };
4008 return pats[which_alternative];
4012 const char *pats[] = { "smalbb\t%0, %1, %2",
4013 "smalbt\t%0, %1, %2",
4014 "smaltt\t%0, %1, %2",
4015 "smalbt\t%0, %2, %1" };
4016 return pats[which_alternative];
4019 [(set_attr "type" "dmac")
4020 (set_attr "length" "4")])
4022 (define_expand "smalda1"
4023 [(match_operand:DI 0 "register_operand" "")
4024 (match_operand:DI 1 "register_operand" "")
4025 (match_operand:V2HI 2 "register_operand" " r")
4026 (match_operand:V2HI 3 "register_operand" " r")]
4027 "NDS32_EXT_DSP_P ()"
4029 if (TARGET_BIG_ENDIAN)
4030 emit_insn (gen_smalda1_be (operands[0], operands[1], operands[2], operands[3]));
4032 emit_insn (gen_smalda1_le (operands[0], operands[1], operands[2], operands[3]));
4036 (define_expand "smalds1"
4037 [(match_operand:DI 0 "register_operand" "")
4038 (match_operand:DI 1 "register_operand" "")
4039 (match_operand:V2HI 2 "register_operand" " r")
4040 (match_operand:V2HI 3 "register_operand" " r")]
4041 "NDS32_EXT_DSP_P ()"
4043 if (TARGET_BIG_ENDIAN)
4044 emit_insn (gen_smalds1_be (operands[0], operands[1], operands[2], operands[3]));
4046 emit_insn (gen_smalds1_le (operands[0], operands[1], operands[2], operands[3]));
4050 (define_insn "smalda1_le"
4051 [(set (match_operand:DI 0 "register_operand" "=r")
4053 (match_operand:DI 1 "register_operand" " 0")
4057 (sign_extend:SI (vec_select:HI
4058 (match_operand:V2HI 2 "register_operand" " r")
4059 (parallel [(const_int 1)])))
4060 (sign_extend:SI (vec_select:HI
4061 (match_operand:V2HI 3 "register_operand" " r")
4062 (parallel [(const_int 1)]))))
4064 (sign_extend:SI (vec_select:HI
4066 (parallel [(const_int 0)])))
4067 (sign_extend:SI (vec_select:HI
4069 (parallel [(const_int 0)]))))))))]
4070 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
4071 "smalda\t%0, %2, %3"
4072 [(set_attr "type" "dmac")
4073 (set_attr "length" "4")])
4075 (define_insn "smalds1_le"
4076 [(set (match_operand:DI 0 "register_operand" "=r")
4078 (match_operand:DI 1 "register_operand" " 0")
4082 (sign_extend:SI (vec_select:HI
4083 (match_operand:V2HI 2 "register_operand" " r")
4084 (parallel [(const_int 1)])))
4085 (sign_extend:SI (vec_select:HI
4086 (match_operand:V2HI 3 "register_operand" " r")
4087 (parallel [(const_int 1)]))))
4089 (sign_extend:SI (vec_select:HI
4091 (parallel [(const_int 0)])))
4092 (sign_extend:SI (vec_select:HI
4094 (parallel [(const_int 0)]))))))))]
4095 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
4096 "smalds\t%0, %2, %3"
4097 [(set_attr "type" "dmac")
4098 (set_attr "length" "4")])
4100 (define_insn "smalda1_be"
4101 [(set (match_operand:DI 0 "register_operand" "=r")
4103 (match_operand:DI 1 "register_operand" " 0")
4107 (sign_extend:SI (vec_select:HI
4108 (match_operand:V2HI 2 "register_operand" " r")
4109 (parallel [(const_int 0)])))
4110 (sign_extend:SI (vec_select:HI
4111 (match_operand:V2HI 3 "register_operand" " r")
4112 (parallel [(const_int 0)]))))
4114 (sign_extend:SI (vec_select:HI
4116 (parallel [(const_int 1)])))
4117 (sign_extend:SI (vec_select:HI
4119 (parallel [(const_int 1)]))))))))]
4120 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
4121 "smalda\t%0, %2, %3"
4122 [(set_attr "type" "dmac")
4123 (set_attr "length" "4")])
4125 (define_insn "smalds1_be"
4126 [(set (match_operand:DI 0 "register_operand" "=r")
4128 (match_operand:DI 1 "register_operand" " 0")
4132 (sign_extend:SI (vec_select:HI
4133 (match_operand:V2HI 2 "register_operand" " r")
4134 (parallel [(const_int 0)])))
4135 (sign_extend:SI (vec_select:HI
4136 (match_operand:V2HI 3 "register_operand" " r")
4137 (parallel [(const_int 0)]))))
4139 (sign_extend:SI (vec_select:HI
4141 (parallel [(const_int 1)])))
4142 (sign_extend:SI (vec_select:HI
4144 (parallel [(const_int 1)]))))))))]
4145 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
4146 "smalds\t%0, %2, %3"
4147 [(set_attr "type" "dmac")
4148 (set_attr "length" "4")])
4150 (define_expand "smaldrs3"
4151 [(match_operand:DI 0 "register_operand" "")
4152 (match_operand:DI 1 "register_operand" "")
4153 (match_operand:V2HI 2 "register_operand" " r")
4154 (match_operand:V2HI 3 "register_operand" " r")]
4155 "NDS32_EXT_DSP_P ()"
4157 if (TARGET_BIG_ENDIAN)
4158 emit_insn (gen_smaldrs3_be (operands[0], operands[1], operands[2], operands[3]));
4160 emit_insn (gen_smaldrs3_le (operands[0], operands[1], operands[2], operands[3]));
4164 (define_insn "smaldrs3_le"
4165 [(set (match_operand:DI 0 "register_operand" "=r")
4167 (match_operand:DI 1 "register_operand" " 0")
4171 (sign_extend:SI (vec_select:HI
4172 (match_operand:V2HI 2 "register_operand" " r")
4173 (parallel [(const_int 0)])))
4174 (sign_extend:SI (vec_select:HI
4175 (match_operand:V2HI 3 "register_operand" " r")
4176 (parallel [(const_int 0)]))))
4178 (sign_extend:SI (vec_select:HI
4180 (parallel [(const_int 1)])))
4181 (sign_extend:SI (vec_select:HI
4183 (parallel [(const_int 1)]))))))))]
4184 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
4185 "smaldrs\t%0, %2, %3"
4186 [(set_attr "type" "dmac")
4187 (set_attr "length" "4")])
4189 (define_insn "smaldrs3_be"
4190 [(set (match_operand:DI 0 "register_operand" "=r")
4192 (match_operand:DI 1 "register_operand" " 0")
4196 (sign_extend:SI (vec_select:HI
4197 (match_operand:V2HI 2 "register_operand" " r")
4198 (parallel [(const_int 1)])))
4199 (sign_extend:SI (vec_select:HI
4200 (match_operand:V2HI 3 "register_operand" " r")
4201 (parallel [(const_int 1)]))))
4203 (sign_extend:SI (vec_select:HI
4205 (parallel [(const_int 0)])))
4206 (sign_extend:SI (vec_select:HI
4208 (parallel [(const_int 0)]))))))))]
4209 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
4210 "smaldrs\t%0, %2, %3"
4211 [(set_attr "type" "dmac")
4212 (set_attr "length" "4")])
4214 (define_expand "smalxda1"
4215 [(match_operand:DI 0 "register_operand" "")
4216 (match_operand:DI 1 "register_operand" "")
4217 (match_operand:V2HI 2 "register_operand" " r")
4218 (match_operand:V2HI 3 "register_operand" " r")]
4219 "NDS32_EXT_DSP_P ()"
4221 if (TARGET_BIG_ENDIAN)
4222 emit_insn (gen_smalxda1_be (operands[0], operands[1], operands[2], operands[3]));
4224 emit_insn (gen_smalxda1_le (operands[0], operands[1], operands[2], operands[3]));
4228 (define_expand "smalxds1"
4229 [(match_operand:DI 0 "register_operand" "")
4230 (match_operand:DI 1 "register_operand" "")
4231 (match_operand:V2HI 2 "register_operand" " r")
4232 (match_operand:V2HI 3 "register_operand" " r")]
4233 "NDS32_EXT_DSP_P ()"
4235 if (TARGET_BIG_ENDIAN)
4236 emit_insn (gen_smalxds1_be (operands[0], operands[1], operands[2], operands[3]));
4238 emit_insn (gen_smalxds1_le (operands[0], operands[1], operands[2], operands[3]));
4242 (define_insn "smalxd<add_sub>1_le"
4243 [(set (match_operand:DI 0 "register_operand" "=r")
4245 (match_operand:DI 1 "register_operand" " 0")
4249 (sign_extend:SI (vec_select:HI
4250 (match_operand:V2HI 2 "register_operand" " r")
4251 (parallel [(const_int 1)])))
4252 (sign_extend:SI (vec_select:HI
4253 (match_operand:V2HI 3 "register_operand" " r")
4254 (parallel [(const_int 0)]))))
4256 (sign_extend:SI (vec_select:HI
4258 (parallel [(const_int 0)])))
4259 (sign_extend:SI (vec_select:HI
4261 (parallel [(const_int 1)]))))))))]
4262 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
4263 "smalxd<add_sub>\t%0, %2, %3"
4264 [(set_attr "type" "dmac")
4265 (set_attr "length" "4")])
4268 (define_insn "smalxd<add_sub>1_be"
4269 [(set (match_operand:DI 0 "register_operand" "=r")
4271 (match_operand:DI 1 "register_operand" " 0")
4275 (sign_extend:SI (vec_select:HI
4276 (match_operand:V2HI 2 "register_operand" " r")
4277 (parallel [(const_int 0)])))
4278 (sign_extend:SI (vec_select:HI
4279 (match_operand:V2HI 3 "register_operand" " r")
4280 (parallel [(const_int 1)]))))
4282 (sign_extend:SI (vec_select:HI
4284 (parallel [(const_int 1)])))
4285 (sign_extend:SI (vec_select:HI
4287 (parallel [(const_int 0)]))))))))]
4288 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
4289 "smalxd<add_sub>\t%0, %2, %3"
4290 [(set_attr "type" "dmac")
4291 (set_attr "length" "4")])
4293 (define_insn "smslda1"
4294 [(set (match_operand:DI 0 "register_operand" "=r")
4297 (match_operand:DI 1 "register_operand" " 0")
4300 (sign_extend:SI (vec_select:HI
4301 (match_operand:V2HI 2 "register_operand" " r")
4302 (parallel [(const_int 1)])))
4303 (sign_extend:SI (vec_select:HI
4304 (match_operand:V2HI 3 "register_operand" " r")
4305 (parallel [(const_int 1)]))))))
4308 (sign_extend:SI (vec_select:HI
4310 (parallel [(const_int 0)])))
4311 (sign_extend:SI (vec_select:HI
4313 (parallel [(const_int 0)])))))))]
4314 "NDS32_EXT_DSP_P ()"
4315 "smslda\t%0, %2, %3"
4316 [(set_attr "type" "dmac")
4317 (set_attr "length" "4")])
4319 (define_insn "smslxda1"
4320 [(set (match_operand:DI 0 "register_operand" "=r")
4323 (match_operand:DI 1 "register_operand" " 0")
4326 (sign_extend:SI (vec_select:HI
4327 (match_operand:V2HI 2 "register_operand" " r")
4328 (parallel [(const_int 1)])))
4329 (sign_extend:SI (vec_select:HI
4330 (match_operand:V2HI 3 "register_operand" " r")
4331 (parallel [(const_int 0)]))))))
4334 (sign_extend:SI (vec_select:HI
4336 (parallel [(const_int 0)])))
4337 (sign_extend:SI (vec_select:HI
4339 (parallel [(const_int 1)])))))))]
4340 "NDS32_EXT_DSP_P ()"
4341 "smslxda\t%0, %2, %3"
4342 [(set_attr "type" "dmac")
4343 (set_attr "length" "4")])
4345 ;; mada for synthetize smalda
4346 (define_insn_and_split "mada1"
4347 [(set (match_operand:SI 0 "register_operand" "=r")
4350 (sign_extend:SI (vec_select:HI
4351 (match_operand:V2HI 1 "register_operand" "r")
4352 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
4353 (sign_extend:SI (vec_select:HI
4354 (match_operand:V2HI 2 "register_operand" "r")
4355 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
4357 (sign_extend:SI (vec_select:HI
4359 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
4360 (sign_extend:SI (vec_select:HI
4362 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
4363 "NDS32_EXT_DSP_P () && !reload_completed"
4365 "NDS32_EXT_DSP_P () && !reload_completed"
4368 rtx result0 = gen_reg_rtx (SImode);
4369 rtx result1 = gen_reg_rtx (SImode);
4370 emit_insn (gen_mulhisi3v (result0, operands[1], operands[2],
4371 operands[3], operands[4]));
4372 emit_insn (gen_mulhisi3v (result1, operands[1], operands[2],
4373 operands[5], operands[6]));
4374 emit_insn (gen_addsi3 (operands[0], result0, result1));
4378 (define_insn_and_split "mada2"
4379 [(set (match_operand:SI 0 "register_operand" "=r")
4382 (sign_extend:SI (vec_select:HI
4383 (match_operand:V2HI 1 "register_operand" "r")
4384 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
4385 (sign_extend:SI (vec_select:HI
4386 (match_operand:V2HI 2 "register_operand" "r")
4387 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
4389 (sign_extend:SI (vec_select:HI
4391 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
4392 (sign_extend:SI (vec_select:HI
4394 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
4395 "NDS32_EXT_DSP_P () && !reload_completed"
4397 "NDS32_EXT_DSP_P () && !reload_completed"
4400 rtx result0 = gen_reg_rtx (SImode);
4401 rtx result1 = gen_reg_rtx (SImode);
4402 emit_insn (gen_mulhisi3v (result0, operands[1], operands[2],
4403 operands[3], operands[4]));
4404 emit_insn (gen_mulhisi3v (result1, operands[1], operands[2],
4405 operands[6], operands[5]));
4406 emit_insn (gen_addsi3 (operands[0], result0, result1));
4410 ;; sms for synthetize smalds
4411 (define_insn_and_split "sms1"
4412 [(set (match_operand:SI 0 "register_operand" "= r")
4415 (sign_extend:SI (vec_select:HI
4416 (match_operand:V2HI 1 "register_operand" " r")
4417 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
4418 (sign_extend:SI (vec_select:HI
4419 (match_operand:V2HI 2 "register_operand" " r")
4420 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
4422 (sign_extend:SI (vec_select:HI
4424 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
4425 (sign_extend:SI (vec_select:HI
4427 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
4429 && (!reload_completed
4430 || !nds32_need_split_sms_p (operands[3], operands[4],
4431 operands[5], operands[6]))"
4434 return nds32_output_sms (operands[3], operands[4],
4435 operands[5], operands[6]);
4438 && !reload_completed
4439 && nds32_need_split_sms_p (operands[3], operands[4],
4440 operands[5], operands[6])"
4443 nds32_split_sms (operands[0], operands[1], operands[2],
4444 operands[3], operands[4],
4445 operands[5], operands[6]);
4448 [(set_attr "type" "dmac")
4449 (set_attr "length" "4")])
4451 (define_insn_and_split "sms2"
4452 [(set (match_operand:SI 0 "register_operand" "= r")
4455 (sign_extend:SI (vec_select:HI
4456 (match_operand:V2HI 1 "register_operand" " r")
4457 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
4458 (sign_extend:SI (vec_select:HI
4459 (match_operand:V2HI 2 "register_operand" " r")
4460 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
4462 (sign_extend:SI (vec_select:HI
4464 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
4465 (sign_extend:SI (vec_select:HI
4467 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
4469 && (!reload_completed
4470 || !nds32_need_split_sms_p (operands[3], operands[4],
4471 operands[6], operands[5]))"
4473 return nds32_output_sms (operands[3], operands[4],
4474 operands[6], operands[5]);
4477 && !reload_completed
4478 && nds32_need_split_sms_p (operands[3], operands[4],
4479 operands[6], operands[5])"
4482 nds32_split_sms (operands[0], operands[1], operands[2],
4483 operands[3], operands[4],
4484 operands[6], operands[5]);
4487 [(set_attr "type" "dmac")
4488 (set_attr "length" "4")])
4491 [(set (match_operand:SI 0 "register_operand" "=r")
4494 (sign_extend:SI (vec_select:HI
4495 (match_operand:V2HI 1 "register_operand" "r")
4496 (parallel [(const_int 1)])))
4497 (sign_extend:SI (vec_select:HI
4498 (match_operand:V2HI 2 "register_operand" "r")
4499 (parallel [(const_int 1)]))))
4501 (sign_extend:SI (vec_select:HI
4503 (parallel [(const_int 0)])))
4504 (sign_extend:SI (vec_select:HI
4506 (parallel [(const_int 0)]))))))]
4507 "NDS32_EXT_DSP_P ()"
4509 [(set_attr "type" "dmac")
4510 (set_attr "length" "4")])
4512 (define_insn "kmxda"
4513 [(set (match_operand:SI 0 "register_operand" "=r")
4516 (sign_extend:SI (vec_select:HI
4517 (match_operand:V2HI 1 "register_operand" "r")
4518 (parallel [(const_int 1)])))
4519 (sign_extend:SI (vec_select:HI
4520 (match_operand:V2HI 2 "register_operand" "r")
4521 (parallel [(const_int 0)]))))
4523 (sign_extend:SI (vec_select:HI
4525 (parallel [(const_int 0)])))
4526 (sign_extend:SI (vec_select:HI
4528 (parallel [(const_int 1)]))))))]
4529 "NDS32_EXT_DSP_P ()"
4531 [(set_attr "type" "dmac")
4532 (set_attr "length" "4")])
4534 (define_insn "kmada"
4535 [(set (match_operand:SI 0 "register_operand" "=r")
4537 (match_operand:SI 1 "register_operand" " 0")
4540 (sign_extend:SI (vec_select:HI
4541 (match_operand:V2HI 2 "register_operand" " r")
4542 (parallel [(const_int 1)])))
4543 (sign_extend:SI (vec_select:HI
4544 (match_operand:V2HI 3 "register_operand" " r")
4545 (parallel [(const_int 1)]))))
4547 (sign_extend:SI (vec_select:HI
4549 (parallel [(const_int 0)])))
4550 (sign_extend:SI (vec_select:HI
4552 (parallel [(const_int 0)])))))))]
4553 "NDS32_EXT_DSP_P ()"
4555 [(set_attr "type" "dmac")
4556 (set_attr "length" "4")])
4558 (define_insn "kmada2"
4559 [(set (match_operand:SI 0 "register_operand" "=r")
4561 (match_operand:SI 1 "register_operand" " 0")
4564 (sign_extend:SI (vec_select:HI
4565 (match_operand:V2HI 2 "register_operand" " r")
4566 (parallel [(const_int 0)])))
4567 (sign_extend:SI (vec_select:HI
4568 (match_operand:V2HI 3 "register_operand" " r")
4569 (parallel [(const_int 0)]))))
4571 (sign_extend:SI (vec_select:HI
4573 (parallel [(const_int 1)])))
4574 (sign_extend:SI (vec_select:HI
4576 (parallel [(const_int 1)])))))))]
4577 "NDS32_EXT_DSP_P ()"
4579 [(set_attr "type" "dmac")
4580 (set_attr "length" "4")])
4582 (define_insn "kmaxda"
4583 [(set (match_operand:SI 0 "register_operand" "=r")
4585 (match_operand:SI 1 "register_operand" " 0")
4588 (sign_extend:SI (vec_select:HI
4589 (match_operand:V2HI 2 "register_operand" " r")
4590 (parallel [(const_int 1)])))
4591 (sign_extend:SI (vec_select:HI
4592 (match_operand:V2HI 3 "register_operand" " r")
4593 (parallel [(const_int 0)]))))
4595 (sign_extend:SI (vec_select:HI
4597 (parallel [(const_int 0)])))
4598 (sign_extend:SI (vec_select:HI
4600 (parallel [(const_int 1)])))))))]
4601 "NDS32_EXT_DSP_P ()"
4602 "kmaxda\t%0, %2, %3"
4603 [(set_attr "type" "dmac")
4604 (set_attr "length" "4")])
4606 (define_insn "kmads"
4607 [(set (match_operand:SI 0 "register_operand" "=r")
4609 (match_operand:SI 1 "register_operand" " 0")
4612 (sign_extend:SI (vec_select:HI
4613 (match_operand:V2HI 2 "register_operand" " r")
4614 (parallel [(const_int 1)])))
4615 (sign_extend:SI (vec_select:HI
4616 (match_operand:V2HI 3 "register_operand" " r")
4617 (parallel [(const_int 1)]))))
4619 (sign_extend:SI (vec_select:HI
4621 (parallel [(const_int 0)])))
4622 (sign_extend:SI (vec_select:HI
4624 (parallel [(const_int 0)])))))))]
4625 "NDS32_EXT_DSP_P ()"
4627 [(set_attr "type" "dmac")
4628 (set_attr "length" "4")])
4630 (define_insn "kmadrs"
4631 [(set (match_operand:SI 0 "register_operand" "=r")
4633 (match_operand:SI 1 "register_operand" " 0")
4636 (sign_extend:SI (vec_select:HI
4637 (match_operand:V2HI 2 "register_operand" " r")
4638 (parallel [(const_int 0)])))
4639 (sign_extend:SI (vec_select:HI
4640 (match_operand:V2HI 3 "register_operand" " r")
4641 (parallel [(const_int 0)]))))
4643 (sign_extend:SI (vec_select:HI
4645 (parallel [(const_int 1)])))
4646 (sign_extend:SI (vec_select:HI
4648 (parallel [(const_int 1)])))))))]
4649 "NDS32_EXT_DSP_P ()"
4650 "kmadrs\t%0, %2, %3"
4651 [(set_attr "type" "dmac")
4652 (set_attr "length" "4")])
4654 (define_insn "kmaxds"
4655 [(set (match_operand:SI 0 "register_operand" "=r")
4657 (match_operand:SI 1 "register_operand" " 0")
4660 (sign_extend:SI (vec_select:HI
4661 (match_operand:V2HI 2 "register_operand" " r")
4662 (parallel [(const_int 1)])))
4663 (sign_extend:SI (vec_select:HI
4664 (match_operand:V2HI 3 "register_operand" " r")
4665 (parallel [(const_int 0)]))))
4667 (sign_extend:SI (vec_select:HI
4669 (parallel [(const_int 0)])))
4670 (sign_extend:SI (vec_select:HI
4672 (parallel [(const_int 1)])))))))]
4673 "NDS32_EXT_DSP_P ()"
4674 "kmaxds\t%0, %2, %3"
4675 [(set_attr "type" "dmac")
4676 (set_attr "length" "4")])
4678 (define_insn "kmsda"
4679 [(set (match_operand:SI 0 "register_operand" "=r")
4681 (match_operand:SI 1 "register_operand" " 0")
4684 (sign_extend:SI (vec_select:HI
4685 (match_operand:V2HI 2 "register_operand" " r")
4686 (parallel [(const_int 1)])))
4687 (sign_extend:SI (vec_select:HI
4688 (match_operand:V2HI 3 "register_operand" " r")
4689 (parallel [(const_int 1)]))))
4691 (sign_extend:SI (vec_select:HI
4693 (parallel [(const_int 0)])))
4694 (sign_extend:SI (vec_select:HI
4696 (parallel [(const_int 0)])))))))]
4697 "NDS32_EXT_DSP_P ()"
4699 [(set_attr "type" "dmac")
4700 (set_attr "length" "4")])
4702 (define_insn "kmsxda"
4703 [(set (match_operand:SI 0 "register_operand" "=r")
4705 (match_operand:SI 1 "register_operand" " 0")
4708 (sign_extend:SI (vec_select:HI
4709 (match_operand:V2HI 2 "register_operand" " r")
4710 (parallel [(const_int 1)])))
4711 (sign_extend:SI (vec_select:HI
4712 (match_operand:V2HI 3 "register_operand" " r")
4713 (parallel [(const_int 0)]))))
4715 (sign_extend:SI (vec_select:HI
4717 (parallel [(const_int 0)])))
4718 (sign_extend:SI (vec_select:HI
4720 (parallel [(const_int 1)])))))))]
4721 "NDS32_EXT_DSP_P ()"
4722 "kmsxda\t%0, %2, %3"
4723 [(set_attr "type" "dmac")
4724 (set_attr "length" "4")])
4726 ;; smax[8|16] and umax[8|16]
4727 (define_insn "<opcode><mode>3"
4728 [(set (match_operand:VQIHI 0 "register_operand" "=r")
4729 (sumax:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
4730 (match_operand:VQIHI 2 "register_operand" " r")))]
4731 "NDS32_EXT_DSP_P ()"
4732 "<opcode><bits>\t%0, %1, %2"
4733 [(set_attr "type" "dalu")
4734 (set_attr "length" "4")])
4736 ;; smin[8|16] and umin[8|16]
4737 (define_insn "<opcode><mode>3"
4738 [(set (match_operand:VQIHI 0 "register_operand" "=r")
4739 (sumin:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
4740 (match_operand:VQIHI 2 "register_operand" " r")))]
4741 "NDS32_EXT_DSP_P ()"
4742 "<opcode><bits>\t%0, %1, %2"
4743 [(set_attr "type" "dalu")
4744 (set_attr "length" "4")])
4746 (define_insn "<opcode><mode>3_bb"
4747 [(set (match_operand:<VELT> 0 "register_operand" "=r")
4748 (sumin_max:<VELT> (vec_select:<VELT>
4749 (match_operand:VQIHI 1 "register_operand" " r")
4750 (parallel [(const_int 0)]))
4752 (match_operand:VQIHI 2 "register_operand" " r")
4753 (parallel [(const_int 0)]))))]
4754 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
4755 "<opcode><bits>\t%0, %1, %2"
4756 [(set_attr "type" "dalu")
4757 (set_attr "length" "4")])
4759 (define_insn_and_split "<opcode><mode>3_tt"
4760 [(set (match_operand:<VELT> 0 "register_operand" "=r")
4761 (sumin_max:<VELT> (vec_select:<VELT>
4762 (match_operand:VQIHI 1 "register_operand" " r")
4763 (parallel [(const_int 1)]))
4765 (match_operand:VQIHI 2 "register_operand" " r")
4766 (parallel [(const_int 1)]))))]
4767 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
4769 "NDS32_EXT_DSP_P () && !reload_completed"
4772 rtx tmp = gen_reg_rtx (<MODE>mode);
4773 emit_insn (gen_<opcode><mode>3 (tmp, operands[1], operands[2]));
4774 emit_insn (gen_rotr<mode>_1 (tmp, tmp));
4775 emit_move_insn (operands[0], simplify_gen_subreg (<VELT>mode, tmp, <MODE>mode, 0));
4778 [(set_attr "type" "dalu")
4779 (set_attr "length" "4")])
4781 (define_insn_and_split "<opcode>v4qi3_22"
4782 [(set (match_operand:QI 0 "register_operand" "=r")
4783 (sumin_max:QI (vec_select:QI
4784 (match_operand:V4QI 1 "register_operand" " r")
4785 (parallel [(const_int 2)]))
4787 (match_operand:V4QI 2 "register_operand" " r")
4788 (parallel [(const_int 2)]))))]
4789 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
4791 "NDS32_EXT_DSP_P () && !reload_completed"
4794 rtx tmp = gen_reg_rtx (V4QImode);
4795 emit_insn (gen_<opcode>v4qi3 (tmp, operands[1], operands[2]));
4796 emit_insn (gen_rotrv4qi_2 (tmp, tmp));
4797 emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0));
4800 [(set_attr "type" "dalu")
4801 (set_attr "length" "4")])
4803 (define_insn_and_split "<opcode>v4qi3_33"
4804 [(set (match_operand:QI 0 "register_operand" "=r")
4805 (sumin_max:QI (vec_select:QI
4806 (match_operand:V4QI 1 "register_operand" " r")
4807 (parallel [(const_int 3)]))
4809 (match_operand:V4QI 2 "register_operand" " r")
4810 (parallel [(const_int 3)]))))]
4811 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
4813 "NDS32_EXT_DSP_P () && !reload_completed"
4816 rtx tmp = gen_reg_rtx (V4QImode);
4817 emit_insn (gen_<opcode>v4qi3 (tmp, operands[1], operands[2]));
4818 emit_insn (gen_rotrv4qi_3 (tmp, tmp));
4819 emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0));
4822 [(set_attr "type" "dalu")
4823 (set_attr "length" "4")])
4825 (define_insn_and_split "<opcode>v2hi3_bbtt"
4826 [(set (match_operand:V2HI 0 "register_operand" "=r")
4829 (sumin_max:HI (vec_select:HI
4830 (match_operand:V2HI 1 "register_operand" " r")
4831 (parallel [(const_int 1)]))
4833 (match_operand:V2HI 2 "register_operand" " r")
4834 (parallel [(const_int 1)]))))
4836 (sumin_max:HI (vec_select:HI
4838 (parallel [(const_int 0)]))
4841 (parallel [(const_int 0)]))))
4843 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
4845 "NDS32_EXT_DSP_P ()"
4848 emit_insn (gen_<opcode>v2hi3 (operands[0], operands[1], operands[2]));
4851 [(set_attr "type" "dalu")
4852 (set_attr "length" "4")])
4854 (define_expand "abs<mode>2"
4855 [(set (match_operand:VQIHI 0 "register_operand" "=r")
4856 (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))]
4857 "NDS32_EXT_DSP_P () && TARGET_HW_ABS && !flag_wrapv"
4861 (define_insn "kabs<mode>2"
4862 [(set (match_operand:VQIHI 0 "register_operand" "=r")
4863 (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))]
4864 "NDS32_EXT_DSP_P ()"
4865 "kabs<bits>\t%0, %1"
4866 [(set_attr "type" "dalu")
4867 (set_attr "length" "4")])
4869 (define_insn "<su>mar64_1"
4870 [(set (match_operand:DI 0 "register_operand" "=r")
4872 (match_operand:DI 1 "register_operand" " 0")
4875 (match_operand:SI 2 "register_operand" " r"))
4877 (match_operand:SI 3 "register_operand" " r")))))]
4878 "NDS32_EXT_DSP_P ()"
4879 "<su>mar64\t%0, %2, %3"
4880 [(set_attr "type" "dmac")
4881 (set_attr "length" "4")])
4883 (define_insn "<su>mar64_2"
4884 [(set (match_operand:DI 0 "register_operand" "=r")
4888 (match_operand:SI 2 "register_operand" " r"))
4890 (match_operand:SI 3 "register_operand" " r")))
4891 (match_operand:DI 1 "register_operand" " 0")))]
4892 "NDS32_EXT_DSP_P ()"
4893 "<su>mar64\t%0, %2, %3"
4894 [(set_attr "type" "dmac")
4895 (set_attr "length" "4")])
4897 (define_insn "<su>mar64_3"
4898 [(set (match_operand:DI 0 "register_operand" "=r")
4900 (match_operand:DI 1 "register_operand" " 0")
4903 (match_operand:SI 2 "register_operand" " r")
4904 (match_operand:SI 3 "register_operand" " r")))))]
4905 "NDS32_EXT_DSP_P ()"
4906 "<su>mar64\t%0, %2, %3"
4907 [(set_attr "type" "dmac")
4908 (set_attr "length" "4")])
4910 (define_insn "<su>mar64_4"
4911 [(set (match_operand:DI 0 "register_operand" "=r")
4915 (match_operand:SI 2 "register_operand" " r")
4916 (match_operand:SI 3 "register_operand" " r")))
4917 (match_operand:DI 1 "register_operand" " 0")))]
4918 "NDS32_EXT_DSP_P ()"
4919 "<su>mar64\t%0, %2, %3"
4920 [(set_attr "type" "dmac")
4921 (set_attr "length" "4")])
4923 (define_insn "<su>msr64"
4924 [(set (match_operand:DI 0 "register_operand" "=r")
4926 (match_operand:DI 1 "register_operand" " 0")
4929 (match_operand:SI 2 "register_operand" " r"))
4931 (match_operand:SI 3 "register_operand" " r")))))]
4932 "NDS32_EXT_DSP_P ()"
4933 "<su>msr64\t%0, %2, %3"
4934 [(set_attr "type" "dmac")
4935 (set_attr "length" "4")])
4937 (define_insn "<su>msr64_2"
4938 [(set (match_operand:DI 0 "register_operand" "=r")
4940 (match_operand:DI 1 "register_operand" " 0")
4943 (match_operand:SI 2 "register_operand" " r")
4944 (match_operand:SI 3 "register_operand" " r")))))]
4945 "NDS32_EXT_DSP_P ()"
4946 "<su>msr64\t%0, %2, %3"
4947 [(set_attr "type" "dmac")
4948 (set_attr "length" "4")])
4950 ;; kmar64, kmsr64, ukmar64 and ukmsr64
4951 (define_insn "kmar64_1"
4952 [(set (match_operand:DI 0 "register_operand" "=r")
4954 (match_operand:DI 1 "register_operand" " 0")
4957 (match_operand:SI 2 "register_operand" " r"))
4959 (match_operand:SI 3 "register_operand" " r")))))]
4960 "NDS32_EXT_DSP_P ()"
4961 "kmar64\t%0, %2, %3"
4962 [(set_attr "type" "dmac")
4963 (set_attr "length" "4")])
4965 (define_insn "kmar64_2"
4966 [(set (match_operand:DI 0 "register_operand" "=r")
4970 (match_operand:SI 2 "register_operand" " r"))
4972 (match_operand:SI 3 "register_operand" " r")))
4973 (match_operand:DI 1 "register_operand" " 0")))]
4974 "NDS32_EXT_DSP_P ()"
4975 "kmar64\t%0, %2, %3"
4976 [(set_attr "type" "dmac")
4977 (set_attr "length" "4")])
4979 (define_insn "kmsr64"
4980 [(set (match_operand:DI 0 "register_operand" "=r")
4982 (match_operand:DI 1 "register_operand" " 0")
4985 (match_operand:SI 2 "register_operand" " r"))
4987 (match_operand:SI 3 "register_operand" " r")))))]
4988 "NDS32_EXT_DSP_P ()"
4989 "kmsr64\t%0, %2, %3"
4990 [(set_attr "type" "dmac")
4991 (set_attr "length" "4")])
4993 (define_insn "ukmar64_1"
4994 [(set (match_operand:DI 0 "register_operand" "=r")
4996 (match_operand:DI 1 "register_operand" " 0")
4999 (match_operand:SI 2 "register_operand" " r"))
5001 (match_operand:SI 3 "register_operand" " r")))))]
5002 "NDS32_EXT_DSP_P ()"
5003 "ukmar64\t%0, %2, %3"
5004 [(set_attr "type" "dmac")
5005 (set_attr "length" "4")])
5007 (define_insn "ukmar64_2"
5008 [(set (match_operand:DI 0 "register_operand" "=r")
5012 (match_operand:SI 2 "register_operand" " r"))
5014 (match_operand:SI 3 "register_operand" " r")))
5015 (match_operand:DI 1 "register_operand" " 0")))]
5016 "NDS32_EXT_DSP_P ()"
5017 "ukmar64\t%0, %2, %3"
5018 [(set_attr "type" "dmac")
5019 (set_attr "length" "4")])
5021 (define_insn "ukmsr64"
5022 [(set (match_operand:DI 0 "register_operand" "=r")
5024 (match_operand:DI 1 "register_operand" " 0")
5027 (match_operand:SI 2 "register_operand" " r"))
5029 (match_operand:SI 3 "register_operand" " r")))))]
5030 "NDS32_EXT_DSP_P ()"
5031 "ukmsr64\t%0, %2, %3"
5032 [(set_attr "type" "dmac")
5033 (set_attr "length" "4")])
5035 (define_insn "bpick1"
5036 [(set (match_operand:SI 0 "register_operand" "=r")
5039 (match_operand:SI 1 "register_operand" " r")
5040 (match_operand:SI 3 "register_operand" " r"))
5042 (match_operand:SI 2 "register_operand" " r")
5043 (not:SI (match_dup 3)))))]
5044 "NDS32_EXT_DSP_P ()"
5045 "bpick\t%0, %1, %2, %3"
5046 [(set_attr "type" "dbpick")
5047 (set_attr "length" "4")])
5049 (define_insn "bpick2"
5050 [(set (match_operand:SI 0 "register_operand" "=r")
5053 (match_operand:SI 1 "register_operand" " r")
5054 (match_operand:SI 2 "register_operand" " r"))
5056 (not:SI (match_dup 2))
5057 (match_operand:SI 3 "register_operand" " r"))))]
5058 "NDS32_EXT_DSP_P ()"
5059 "bpick\t%0, %1, %3, %2"
5060 [(set_attr "type" "dbpick")
5061 (set_attr "length" "4")])
5063 (define_insn "bpick3"
5064 [(set (match_operand:SI 0 "register_operand" "=r")
5067 (match_operand:SI 1 "register_operand" " r")
5068 (match_operand:SI 2 "register_operand" " r"))
5070 (match_operand:SI 3 "register_operand" " r")
5071 (not:SI (match_dup 1)))))]
5072 "NDS32_EXT_DSP_P ()"
5073 "bpick\t%0, %2, %3, %1"
5074 [(set_attr "type" "dbpick")
5075 (set_attr "length" "4")])
5077 (define_insn "bpick4"
5078 [(set (match_operand:SI 0 "register_operand" "=r")
5081 (match_operand:SI 1 "register_operand" " r")
5082 (match_operand:SI 2 "register_operand" " r"))
5084 (not:SI (match_dup 1))
5085 (match_operand:SI 3 "register_operand" " r"))))]
5086 "NDS32_EXT_DSP_P ()"
5087 "bpick\t%0, %2, %3, %1"
5088 [(set_attr "type" "dbpick")
5089 (set_attr "length" "4")])
5091 (define_insn "bpick5"
5092 [(set (match_operand:SI 0 "register_operand" "=r")
5095 (match_operand:SI 1 "register_operand" " r")
5096 (not:SI (match_operand:SI 2 "register_operand" " r")))
5098 (match_operand:SI 3 "register_operand" " r")
5100 "NDS32_EXT_DSP_P ()"
5101 "bpick\t%0, %3, %1, %2"
5102 [(set_attr "type" "dbpick")
5103 (set_attr "length" "4")])
5105 (define_insn "bpick6"
5106 [(set (match_operand:SI 0 "register_operand" "=r")
5109 (not:SI (match_operand:SI 1 "register_operand" " r"))
5110 (match_operand:SI 2 "register_operand" " r"))
5112 (match_operand:SI 3 "register_operand" " r")
5114 "NDS32_EXT_DSP_P ()"
5115 "bpick\t%0, %3, %2, %1"
5116 [(set_attr "type" "dbpick")
5117 (set_attr "length" "4")])
5119 (define_insn "bpick7"
5120 [(set (match_operand:SI 0 "register_operand" "=r")
5123 (match_operand:SI 1 "register_operand" " r")
5124 (not:SI (match_operand:SI 2 "register_operand" " r")))
5127 (match_operand:SI 3 "register_operand" " r"))))]
5128 "NDS32_EXT_DSP_P ()"
5129 "bpick\t%0, %3, %1, %2"
5130 [(set_attr "type" "dbpick")
5131 (set_attr "length" "4")])
5133 (define_insn "bpick8"
5134 [(set (match_operand:SI 0 "register_operand" "=r")
5137 (not:SI (match_operand:SI 1 "register_operand" " r"))
5138 (match_operand:SI 2 "register_operand" " r"))
5141 (match_operand:SI 3 "register_operand" " r"))))]
5142 "NDS32_EXT_DSP_P ()"
5143 "bpick\t%0, %3, %2, %1"
5144 [(set_attr "type" "dbpick")
5145 (set_attr "length" "4")])
5147 (define_insn "sraiu"
5148 [(set (match_operand:SI 0 "register_operand" "= r, r")
5149 (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r, r")
5150 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r"))]
5152 "NDS32_EXT_DSP_P ()"
5156 [(set_attr "type" "daluround")
5157 (set_attr "length" "4")])
5160 [(set (match_operand:SI 0 "register_operand" "= r, r")
5161 (ss_ashift:SI (match_operand:SI 1 "register_operand" " r, r")
5162 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))]
5163 "NDS32_EXT_DSP_P ()"
5167 [(set_attr "type" "dalu")
5168 (set_attr "length" "4")])
5170 (define_insn "kslraw_round"
5171 [(set (match_operand:SI 0 "register_operand" "=r")
5173 (lt:SI (match_operand:SI 2 "register_operand" " r")
5175 (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r")
5176 (neg:SI (match_dup 2)))]
5178 (ss_ashift:SI (match_dup 1)
5180 "NDS32_EXT_DSP_P ()"
5181 "kslraw.u\t%0, %1, %2"
5182 [(set_attr "type" "daluround")
5183 (set_attr "length" "4")])
5185 (define_insn_and_split "<shift>di3"
5186 [(set (match_operand:DI 0 "register_operand" "")
5187 (shift_rotate:DI (match_operand:DI 1 "register_operand" "")
5188 (match_operand:SI 2 "nds32_rimm6u_operand" "")))]
5189 "NDS32_EXT_DSP_P () && !reload_completed"
5191 "NDS32_EXT_DSP_P () && !reload_completed"
5194 if (REGNO (operands[0]) == REGNO (operands[1]))
5196 rtx tmp = gen_reg_rtx (DImode);
5197 nds32_split_<code>di3 (tmp, operands[1], operands[2]);
5198 emit_move_insn (operands[0], tmp);
5201 nds32_split_<code>di3 (operands[0], operands[1], operands[2]);
5205 (define_insn "sclip32"
5206 [(set (match_operand:SI 0 "register_operand" "=r")
5207 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
5208 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS_OV))]
5209 "NDS32_EXT_DSP_P ()"
5210 "sclip32\t%0, %1, %2"
5211 [(set_attr "type" "dclip")
5212 (set_attr "length" "4")]
5215 (define_insn "uclip32"
5216 [(set (match_operand:SI 0 "register_operand" "=r")
5217 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
5218 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP_OV))]
5219 "NDS32_EXT_DSP_P ()"
5220 "uclip32\t%0, %1, %2"
5221 [(set_attr "type" "dclip")
5222 (set_attr "length" "4")]
5225 (define_insn "bitrev"
5226 [(set (match_operand:SI 0 "register_operand" "=r, r")
5227 (unspec:SI [(match_operand:SI 1 "register_operand" " r, r")
5228 (match_operand:SI 2 "nds32_rimm5u_operand" " r, Iu05")]
5233 bitrevi\t%0, %1, %2"
5234 [(set_attr "type" "dalu")
5235 (set_attr "length" "4")]
5239 (define_insn "<su>wext"
5240 [(set (match_operand:SI 0 "register_operand" "=r, r")
5243 (match_operand:DI 1 "register_operand" " r, r")
5244 (match_operand:SI 2 "nds32_rimm5u_operand" " r,Iu05"))))]
5245 "NDS32_EXT_DSP_P ()"
5249 [(set_attr "type" "dwext")
5250 (set_attr "length" "4")])
5252 ;; 32-bit add/sub instruction: raddw and rsubw.
5253 (define_insn "r<opcode>si3"
5254 [(set (match_operand:SI 0 "register_operand" "=r")
5258 (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
5259 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))
5261 "NDS32_EXT_DSP_P ()"
5262 "r<opcode>w\t%0, %1, %2"
5263 [(set_attr "type" "dalu")
5264 (set_attr "length" "4")])
5266 ;; 32-bit add/sub instruction: uraddw and ursubw.
5267 (define_insn "ur<opcode>si3"
5268 [(set (match_operand:SI 0 "register_operand" "=r")
5272 (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
5273 (zero_extend:DI (match_operand:SI 2 "register_operand" " r")))
5275 "NDS32_EXT_DSP_P ()"
5276 "ur<opcode>w\t%0, %1, %2"
5277 [(set_attr "type" "dalu")
5278 (set_attr "length" "4")])