gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c

   1 /* { dg-do compile } */
   2 /* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */
   3
   4 #include "vdiv-template.h"
   5
   6 /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
   7 /* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
   8
   9 /* Division by constant is done by calculating a reciprocal and
  10    then multiplying.  Hence we do not expect 6 vfdivs.  */
  11 /* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */
  12 /* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */
  13
  14 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */
  15 /* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */
  16 /* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */
  17 /* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */
  18 /* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */
  19 /* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */
  20 /* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */