gcc/testsuite/gcc.target/riscv/shift-and-2.c

   1 /* { dg-do compile { target { riscv64*-*-* } } } */
   2 /* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
   3
   4 /* Test for <optab>si3_mask_1.  */
   5 extern int k;
   6 void
   7 sub2 (int i, long j)
   8 {
   9   k = i << (j & 0x1f);
  10 }
  11
  12 /* Test for <optab>si3_extend_mask.  */
  13 unsigned long
  14 sub3 (int mask)
  15 {
  16   return 1 << (mask & 0xff);
  17 }
  18
  19 /* Test for <optab>si3_extend_mask_1.  */
  20 int
  21 sub4 (int i, int j)
  22 {
  23   return i << (j & 0x1f);
  24 }
  25
  26 /* Test for <optab>di3_mask.  */
  27 long
  28 sub5 (long i, int j)
  29 {
  30   char k = j & 0x3f;
  31   return i << k;
  32 }
  33
  34 /* Test for <optab>di3_mask_1.  */
  35 long
  36 sub6 (long i, long j)
  37 {
  38   return i << (j & 0x3f);
  39 }
  40 /* { dg-final { scan-assembler-not "andi" } } */
  41 /* { dg-final { scan-assembler-not "sext.w" } } */