1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2024 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-nat.h"
31 #include "aarch64-tdep.h"
32 #include "aarch64-linux-tdep.h"
33 #include "aarch32-linux-nat.h"
34 #include "aarch32-tdep.h"
36 #include "nat/aarch64-linux.h"
37 #include "nat/aarch64-linux-hw-point.h"
38 #include "nat/aarch64-scalable-linux-ptrace.h"
40 #include "elf/external.h"
41 #include "elf/common.h"
43 #include "nat/gdb_ptrace.h"
44 #include <sys/utsname.h>
45 #include <asm/ptrace.h>
48 #include "linux-tdep.h"
51 /* Defines ps_err_e, struct ps_prochandle. */
52 #include "gdb_proc_service.h"
53 #include "arch-utils.h"
55 #include "arch/aarch64-mte-linux.h"
57 #include "nat/aarch64-mte-linux-ptrace.h"
58 #include "arch/aarch64-scalable-linux.h"
63 #define TRAP_HWBKPT 0x0004
66 class aarch64_linux_nat_target final
67 : public aarch64_nat_target
<linux_nat_target
>
70 /* Add our register access methods. */
71 void fetch_registers (struct regcache
*, int) override
;
72 void store_registers (struct regcache
*, int) override
;
74 const struct target_desc
*read_description () override
;
76 /* Add our hardware breakpoint and watchpoint implementation. */
77 bool stopped_by_watchpoint () override
;
78 bool stopped_data_address (CORE_ADDR
*) override
;
80 int can_do_single_step () override
;
82 /* Override the GNU/Linux inferior startup hook. */
83 void post_startup_inferior (ptid_t
) override
;
85 /* Override the GNU/Linux post attach hook. */
86 void post_attach (int pid
) override
;
88 /* These three defer to common nat/ code. */
89 void low_new_thread (struct lwp_info
*lp
) override
90 { aarch64_linux_new_thread (lp
); }
91 void low_delete_thread (struct arch_lwp_info
*lp
) override
92 { aarch64_linux_delete_thread (lp
); }
93 void low_prepare_to_resume (struct lwp_info
*lp
) override
94 { aarch64_linux_prepare_to_resume (lp
); }
96 void low_new_fork (struct lwp_info
*parent
, pid_t child_pid
) override
;
97 void low_forget_process (pid_t pid
) override
;
99 /* Add our siginfo layout converter. */
100 bool low_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
103 struct gdbarch
*thread_architecture (ptid_t
) override
;
105 bool supports_memory_tagging () override
;
107 /* Read memory allocation tags from memory via PTRACE. */
108 bool fetch_memtags (CORE_ADDR address
, size_t len
,
109 gdb::byte_vector
&tags
, int type
) override
;
111 /* Write allocation tags to memory via PTRACE. */
112 bool store_memtags (CORE_ADDR address
, size_t len
,
113 const gdb::byte_vector
&tags
, int type
) override
;
116 static aarch64_linux_nat_target the_aarch64_linux_nat_target
;
118 /* Called whenever GDB is no longer debugging process PID. It deletes
119 data structures that keep track of debug register state. */
122 aarch64_linux_nat_target::low_forget_process (pid_t pid
)
124 aarch64_remove_debug_reg_state (pid
);
127 /* Fill GDB's register array with the general-purpose register values
128 from the current thread. */
131 fetch_gregs_from_thread (struct regcache
*regcache
)
134 struct gdbarch
*gdbarch
= regcache
->arch ();
138 /* Make sure REGS can hold all registers contents on both aarch64
140 static_assert (sizeof (regs
) >= 18 * 4);
142 tid
= regcache
->ptid ().lwp ();
144 iovec
.iov_base
= ®s
;
145 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
146 iovec
.iov_len
= 18 * 4;
148 iovec
.iov_len
= sizeof (regs
);
150 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
152 perror_with_name (_("Unable to fetch general registers"));
154 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
155 aarch32_gp_regcache_supply (regcache
, (uint32_t *) regs
, 1);
160 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
161 regcache
->raw_supply (regno
, ®s
[regno
- AARCH64_X0_REGNUM
]);
165 /* Store to the current thread the valid general-purpose register
166 values in the GDB's register array. */
169 store_gregs_to_thread (const struct regcache
*regcache
)
174 struct gdbarch
*gdbarch
= regcache
->arch ();
176 /* Make sure REGS can hold all registers contents on both aarch64
178 static_assert (sizeof (regs
) >= 18 * 4);
179 tid
= regcache
->ptid ().lwp ();
181 iovec
.iov_base
= ®s
;
182 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
183 iovec
.iov_len
= 18 * 4;
185 iovec
.iov_len
= sizeof (regs
);
187 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
189 perror_with_name (_("Unable to fetch general registers"));
191 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
192 aarch32_gp_regcache_collect (regcache
, (uint32_t *) regs
, 1);
197 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
198 if (REG_VALID
== regcache
->get_register_status (regno
))
199 regcache
->raw_collect (regno
, ®s
[regno
- AARCH64_X0_REGNUM
]);
202 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
204 perror_with_name (_("Unable to store general registers"));
207 /* Fill GDB's register array with the fp/simd register values
208 from the current thread. */
211 fetch_fpregs_from_thread (struct regcache
*regcache
)
216 struct gdbarch
*gdbarch
= regcache
->arch ();
218 /* Make sure REGS can hold all VFP registers contents on both aarch64
220 static_assert (sizeof regs
>= ARM_VFP3_REGS_SIZE
);
222 tid
= regcache
->ptid ().lwp ();
224 iovec
.iov_base
= ®s
;
226 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
228 iovec
.iov_len
= ARM_VFP3_REGS_SIZE
;
230 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
232 perror_with_name (_("Unable to fetch VFP registers"));
234 aarch32_vfp_regcache_supply (regcache
, (gdb_byte
*) ®s
, 32);
240 iovec
.iov_len
= sizeof (regs
);
242 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
244 perror_with_name (_("Unable to fetch vFP/SIMD registers"));
246 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
247 regcache
->raw_supply (regno
, ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
249 regcache
->raw_supply (AARCH64_FPSR_REGNUM
, ®s
.fpsr
);
250 regcache
->raw_supply (AARCH64_FPCR_REGNUM
, ®s
.fpcr
);
254 /* Store to the current thread the valid fp/simd register
255 values in the GDB's register array. */
258 store_fpregs_to_thread (const struct regcache
*regcache
)
263 struct gdbarch
*gdbarch
= regcache
->arch ();
265 /* Make sure REGS can hold all VFP registers contents on both aarch64
267 static_assert (sizeof regs
>= ARM_VFP3_REGS_SIZE
);
268 tid
= regcache
->ptid ().lwp ();
270 iovec
.iov_base
= ®s
;
272 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
274 iovec
.iov_len
= ARM_VFP3_REGS_SIZE
;
276 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
278 perror_with_name (_("Unable to fetch VFP registers"));
280 aarch32_vfp_regcache_collect (regcache
, (gdb_byte
*) ®s
, 32);
286 iovec
.iov_len
= sizeof (regs
);
288 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
290 perror_with_name (_("Unable to fetch FP/SIMD registers"));
292 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
293 if (REG_VALID
== regcache
->get_register_status (regno
))
294 regcache
->raw_collect
295 (regno
, (char *) ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
297 if (REG_VALID
== regcache
->get_register_status (AARCH64_FPSR_REGNUM
))
298 regcache
->raw_collect (AARCH64_FPSR_REGNUM
, (char *) ®s
.fpsr
);
299 if (REG_VALID
== regcache
->get_register_status (AARCH64_FPCR_REGNUM
))
300 regcache
->raw_collect (AARCH64_FPCR_REGNUM
, (char *) ®s
.fpcr
);
303 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
305 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
307 perror_with_name (_("Unable to store VFP registers"));
311 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_FPREGSET
, &iovec
);
313 perror_with_name (_("Unable to store FP/SIMD registers"));
317 /* Fill GDB's REGCACHE with the valid SVE register values from the thread
318 associated with REGCACHE.
320 This function handles reading data from SVE or SSVE states, depending
321 on which state is active at the moment. */
324 fetch_sveregs_from_thread (struct regcache
*regcache
)
326 /* Fetch SVE state from the thread and copy it into the register cache. */
327 aarch64_sve_regs_copy_to_reg_buf (regcache
->ptid ().lwp (), regcache
);
330 /* Store the valid SVE register values from GDB's REGCACHE to the thread
331 associated with REGCACHE.
333 This function handles writing data to SVE or SSVE states, depending
334 on which state is active at the moment. */
337 store_sveregs_to_thread (struct regcache
*regcache
)
339 /* Fetch SVE state from the register cache and update the thread TID with
341 aarch64_sve_regs_copy_from_reg_buf (regcache
->ptid ().lwp (), regcache
);
344 /* Fill GDB's REGCACHE with the ZA register set contents from the
345 thread associated with REGCACHE. If there is no active ZA register state,
346 make the ZA register contents zero. */
349 fetch_za_from_thread (struct regcache
*regcache
)
351 aarch64_gdbarch_tdep
*tdep
352 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
354 /* Read ZA state from the thread to the register cache. */
355 aarch64_za_regs_copy_to_reg_buf (regcache
->ptid ().lwp (),
358 tdep
->sme_svg_regnum
,
359 tdep
->sme_svcr_regnum
);
362 /* Store the NT_ARM_ZA register set contents from GDB's REGCACHE to the thread
363 associated with REGCACHE. */
366 store_za_to_thread (struct regcache
*regcache
)
368 aarch64_gdbarch_tdep
*tdep
369 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
371 /* Write ZA state from the register cache to the thread. */
372 aarch64_za_regs_copy_from_reg_buf (regcache
->ptid ().lwp (),
375 tdep
->sme_svg_regnum
,
376 tdep
->sme_svcr_regnum
);
379 /* Fill GDB's REGCACHE with the ZT register set contents from the
380 thread associated with REGCACHE. If there is no active ZA register state,
381 make the ZT register contents zero. */
384 fetch_zt_from_thread (struct regcache
*regcache
)
386 aarch64_gdbarch_tdep
*tdep
387 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
389 /* Read ZT state from the thread to the register cache. */
390 aarch64_zt_regs_copy_to_reg_buf (regcache
->ptid ().lwp (),
392 tdep
->sme2_zt0_regnum
);
395 /* Store the NT_ARM_ZT register set contents from GDB's REGCACHE to the
396 thread associated with REGCACHE. */
399 store_zt_to_thread (struct regcache
*regcache
)
401 aarch64_gdbarch_tdep
*tdep
402 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
404 /* Write ZT state from the register cache to the thread. */
405 aarch64_zt_regs_copy_from_reg_buf (regcache
->ptid ().lwp (),
407 tdep
->sme2_zt0_regnum
);
410 /* Fill GDB's register array with the pointer authentication mask values from
411 the current thread. */
414 fetch_pauth_masks_from_thread (struct regcache
*regcache
)
416 aarch64_gdbarch_tdep
*tdep
417 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
420 uint64_t pauth_regset
[2] = {0, 0};
421 int tid
= regcache
->ptid ().lwp ();
423 iovec
.iov_base
= &pauth_regset
;
424 iovec
.iov_len
= sizeof (pauth_regset
);
426 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_PAC_MASK
, &iovec
);
428 perror_with_name (_("unable to fetch pauth registers"));
430 regcache
->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
),
432 regcache
->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
),
436 /* Fill GDB's register array with the MTE register values from
437 the current thread. */
440 fetch_mteregs_from_thread (struct regcache
*regcache
)
442 aarch64_gdbarch_tdep
*tdep
443 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
444 int regno
= tdep
->mte_reg_base
;
446 gdb_assert (regno
!= -1);
448 uint64_t tag_ctl
= 0;
451 iovec
.iov_base
= &tag_ctl
;
452 iovec
.iov_len
= sizeof (tag_ctl
);
454 int tid
= get_ptrace_pid (regcache
->ptid ());
455 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_TAGGED_ADDR_CTRL
, &iovec
) != 0)
456 perror_with_name (_("unable to fetch MTE registers"));
458 regcache
->raw_supply (regno
, &tag_ctl
);
461 /* Store to the current thread the valid MTE register set in the GDB's
465 store_mteregs_to_thread (struct regcache
*regcache
)
467 aarch64_gdbarch_tdep
*tdep
468 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
469 int regno
= tdep
->mte_reg_base
;
471 gdb_assert (regno
!= -1);
473 uint64_t tag_ctl
= 0;
475 if (REG_VALID
!= regcache
->get_register_status (regno
))
478 regcache
->raw_collect (regno
, (char *) &tag_ctl
);
482 iovec
.iov_base
= &tag_ctl
;
483 iovec
.iov_len
= sizeof (tag_ctl
);
485 int tid
= get_ptrace_pid (regcache
->ptid ());
486 if (ptrace (PTRACE_SETREGSET
, tid
, NT_ARM_TAGGED_ADDR_CTRL
, &iovec
) != 0)
487 perror_with_name (_("unable to store MTE registers"));
490 /* Fill GDB's register array with the TLS register values from
491 the current thread. */
494 fetch_tlsregs_from_thread (struct regcache
*regcache
)
496 aarch64_gdbarch_tdep
*tdep
497 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
498 int regno
= tdep
->tls_regnum_base
;
500 gdb_assert (regno
!= -1);
501 gdb_assert (tdep
->tls_register_count
> 0);
503 uint64_t tpidrs
[tdep
->tls_register_count
];
504 memset(tpidrs
, 0, sizeof(tpidrs
));
507 iovec
.iov_base
= tpidrs
;
508 iovec
.iov_len
= sizeof (tpidrs
);
510 int tid
= get_ptrace_pid (regcache
->ptid ());
511 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_TLS
, &iovec
) != 0)
512 perror_with_name (_("unable to fetch TLS registers"));
514 for (int i
= 0; i
< tdep
->tls_register_count
; i
++)
515 regcache
->raw_supply (regno
+ i
, &tpidrs
[i
]);
518 /* Store to the current thread the valid TLS register set in GDB's
522 store_tlsregs_to_thread (struct regcache
*regcache
)
524 aarch64_gdbarch_tdep
*tdep
525 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
526 int regno
= tdep
->tls_regnum_base
;
528 gdb_assert (regno
!= -1);
529 gdb_assert (tdep
->tls_register_count
> 0);
531 uint64_t tpidrs
[tdep
->tls_register_count
];
532 memset(tpidrs
, 0, sizeof(tpidrs
));
534 for (int i
= 0; i
< tdep
->tls_register_count
; i
++)
536 if (REG_VALID
!= regcache
->get_register_status (regno
+ i
))
539 regcache
->raw_collect (regno
+ i
, (char *) &tpidrs
[i
]);
543 iovec
.iov_base
= &tpidrs
;
544 iovec
.iov_len
= sizeof (tpidrs
);
546 int tid
= get_ptrace_pid (regcache
->ptid ());
547 if (ptrace (PTRACE_SETREGSET
, tid
, NT_ARM_TLS
, &iovec
) != 0)
548 perror_with_name (_("unable to store TLS register"));
551 /* The AArch64 version of the "fetch_registers" target_ops method. Fetch
552 REGNO from the target and place the result into REGCACHE. */
555 aarch64_fetch_registers (struct regcache
*regcache
, int regno
)
557 aarch64_gdbarch_tdep
*tdep
558 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
560 /* Do we need to fetch all registers? */
563 fetch_gregs_from_thread (regcache
);
565 /* We attempt to fetch SVE registers if there is support for either
566 SVE or SME (due to the SSVE state of SME). */
567 if (tdep
->has_sve () || tdep
->has_sme ())
568 fetch_sveregs_from_thread (regcache
);
570 fetch_fpregs_from_thread (regcache
);
572 if (tdep
->has_pauth ())
573 fetch_pauth_masks_from_thread (regcache
);
575 if (tdep
->has_mte ())
576 fetch_mteregs_from_thread (regcache
);
578 if (tdep
->has_tls ())
579 fetch_tlsregs_from_thread (regcache
);
581 if (tdep
->has_sme ())
582 fetch_za_from_thread (regcache
);
584 if (tdep
->has_sme2 ())
585 fetch_zt_from_thread (regcache
);
587 /* General purpose register? */
588 else if (regno
< AARCH64_V0_REGNUM
)
589 fetch_gregs_from_thread (regcache
);
591 else if ((tdep
->has_sve () || tdep
->has_sme ())
592 && regno
<= AARCH64_SVE_VG_REGNUM
)
593 fetch_sveregs_from_thread (regcache
);
594 /* FPSIMD register? */
595 else if (regno
<= AARCH64_FPCR_REGNUM
)
596 fetch_fpregs_from_thread (regcache
);
597 /* PAuth register? */
598 else if (tdep
->has_pauth ()
599 && (regno
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
600 || regno
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
)))
601 fetch_pauth_masks_from_thread (regcache
);
603 else if (tdep
->has_sme () && regno
>= tdep
->sme_reg_base
604 && regno
< tdep
->sme_reg_base
+ 3)
605 fetch_za_from_thread (regcache
);
607 else if (tdep
->has_sme2 () && regno
== tdep
->sme2_zt0_regnum
)
608 fetch_zt_from_thread (regcache
);
610 else if (tdep
->has_mte ()
611 && (regno
== tdep
->mte_reg_base
))
612 fetch_mteregs_from_thread (regcache
);
614 else if (tdep
->has_tls ()
615 && regno
>= tdep
->tls_regnum_base
616 && regno
< tdep
->tls_regnum_base
+ tdep
->tls_register_count
)
617 fetch_tlsregs_from_thread (regcache
);
620 /* A version of the "fetch_registers" target_ops method used when running
621 32-bit ARM code on an AArch64 target. Fetch REGNO from the target and
622 place the result into REGCACHE. */
625 aarch32_fetch_registers (struct regcache
*regcache
, int regno
)
627 arm_gdbarch_tdep
*tdep
628 = gdbarch_tdep
<arm_gdbarch_tdep
> (regcache
->arch ());
632 fetch_gregs_from_thread (regcache
);
633 if (tdep
->vfp_register_count
> 0)
634 fetch_fpregs_from_thread (regcache
);
636 else if (regno
< ARM_F0_REGNUM
|| regno
== ARM_PS_REGNUM
)
637 fetch_gregs_from_thread (regcache
);
638 else if (tdep
->vfp_register_count
> 0
639 && regno
>= ARM_D0_REGNUM
640 && (regno
< ARM_D0_REGNUM
+ tdep
->vfp_register_count
641 || regno
== ARM_FPSCR_REGNUM
))
642 fetch_fpregs_from_thread (regcache
);
645 /* Implement the "fetch_registers" target_ops method. */
648 aarch64_linux_nat_target::fetch_registers (struct regcache
*regcache
,
651 if (gdbarch_bfd_arch_info (regcache
->arch ())->bits_per_word
== 32)
652 aarch32_fetch_registers (regcache
, regno
);
654 aarch64_fetch_registers (regcache
, regno
);
657 /* The AArch64 version of the "store_registers" target_ops method. Copy
658 the value of register REGNO from REGCACHE into the the target. */
661 aarch64_store_registers (struct regcache
*regcache
, int regno
)
663 aarch64_gdbarch_tdep
*tdep
664 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (regcache
->arch ());
666 /* Do we need to store all registers? */
669 store_gregs_to_thread (regcache
);
671 /* We attempt to store SVE registers if there is support for either
672 SVE or SME (due to the SSVE state of SME). */
673 if (tdep
->has_sve () || tdep
->has_sme ())
674 store_sveregs_to_thread (regcache
);
676 store_fpregs_to_thread (regcache
);
678 if (tdep
->has_mte ())
679 store_mteregs_to_thread (regcache
);
681 if (tdep
->has_tls ())
682 store_tlsregs_to_thread (regcache
);
684 if (tdep
->has_sme ())
685 store_za_to_thread (regcache
);
687 if (tdep
->has_sme2 ())
688 store_zt_to_thread (regcache
);
690 /* General purpose register? */
691 else if (regno
< AARCH64_V0_REGNUM
)
692 store_gregs_to_thread (regcache
);
694 else if ((tdep
->has_sve () || tdep
->has_sme ())
695 && regno
<= AARCH64_SVE_VG_REGNUM
)
696 store_sveregs_to_thread (regcache
);
697 /* FPSIMD register? */
698 else if (regno
<= AARCH64_FPCR_REGNUM
)
699 store_fpregs_to_thread (regcache
);
701 else if (tdep
->has_sme () && regno
>= tdep
->sme_reg_base
702 && regno
< tdep
->sme_reg_base
+ 3)
703 store_za_to_thread (regcache
);
704 else if (tdep
->has_sme2 () && regno
== tdep
->sme2_zt0_regnum
)
705 store_zt_to_thread (regcache
);
707 else if (tdep
->has_mte ()
708 && (regno
== tdep
->mte_reg_base
))
709 store_mteregs_to_thread (regcache
);
711 else if (tdep
->has_tls ()
712 && regno
>= tdep
->tls_regnum_base
713 && regno
< tdep
->tls_regnum_base
+ tdep
->tls_register_count
)
714 store_tlsregs_to_thread (regcache
);
716 /* PAuth registers are read-only. */
719 /* A version of the "store_registers" target_ops method used when running
720 32-bit ARM code on an AArch64 target. Copy the value of register REGNO
721 from REGCACHE into the the target. */
724 aarch32_store_registers (struct regcache
*regcache
, int regno
)
726 arm_gdbarch_tdep
*tdep
727 = gdbarch_tdep
<arm_gdbarch_tdep
> (regcache
->arch ());
731 store_gregs_to_thread (regcache
);
732 if (tdep
->vfp_register_count
> 0)
733 store_fpregs_to_thread (regcache
);
735 else if (regno
< ARM_F0_REGNUM
|| regno
== ARM_PS_REGNUM
)
736 store_gregs_to_thread (regcache
);
737 else if (tdep
->vfp_register_count
> 0
738 && regno
>= ARM_D0_REGNUM
739 && (regno
< ARM_D0_REGNUM
+ tdep
->vfp_register_count
740 || regno
== ARM_FPSCR_REGNUM
))
741 store_fpregs_to_thread (regcache
);
744 /* Implement the "store_registers" target_ops method. */
747 aarch64_linux_nat_target::store_registers (struct regcache
*regcache
,
750 if (gdbarch_bfd_arch_info (regcache
->arch ())->bits_per_word
== 32)
751 aarch32_store_registers (regcache
, regno
);
753 aarch64_store_registers (regcache
, regno
);
756 /* Fill register REGNO (if it is a general-purpose register) in
757 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
758 do this for all registers. */
761 fill_gregset (const struct regcache
*regcache
,
762 gdb_gregset_t
*gregsetp
, int regno
)
764 regcache_collect_regset (&aarch64_linux_gregset
, regcache
,
765 regno
, (gdb_byte
*) gregsetp
,
766 AARCH64_LINUX_SIZEOF_GREGSET
);
769 /* Fill GDB's register array with the general-purpose register values
773 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
775 regcache_supply_regset (&aarch64_linux_gregset
, regcache
, -1,
776 (const gdb_byte
*) gregsetp
,
777 AARCH64_LINUX_SIZEOF_GREGSET
);
780 /* Fill register REGNO (if it is a floating-point register) in
781 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
782 do this for all registers. */
785 fill_fpregset (const struct regcache
*regcache
,
786 gdb_fpregset_t
*fpregsetp
, int regno
)
788 regcache_collect_regset (&aarch64_linux_fpregset
, regcache
,
789 regno
, (gdb_byte
*) fpregsetp
,
790 AARCH64_LINUX_SIZEOF_FPREGSET
);
793 /* Fill GDB's register array with the floating-point register values
797 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
*fpregsetp
)
799 regcache_supply_regset (&aarch64_linux_fpregset
, regcache
, -1,
800 (const gdb_byte
*) fpregsetp
,
801 AARCH64_LINUX_SIZEOF_FPREGSET
);
804 /* linux_nat_new_fork hook. */
807 aarch64_linux_nat_target::low_new_fork (struct lwp_info
*parent
,
811 struct aarch64_debug_reg_state
*parent_state
;
812 struct aarch64_debug_reg_state
*child_state
;
814 /* NULL means no watchpoint has ever been set in the parent. In
815 that case, there's nothing to do. */
816 if (parent
->arch_private
== NULL
)
819 /* GDB core assumes the child inherits the watchpoints/hw
820 breakpoints of the parent, and will remove them all from the
821 forked off process. Copy the debug registers mirrors into the
822 new process so that all breakpoints and watchpoints can be
825 parent_pid
= parent
->ptid
.pid ();
826 parent_state
= aarch64_get_debug_reg_state (parent_pid
);
827 child_state
= aarch64_get_debug_reg_state (child_pid
);
828 *child_state
= *parent_state
;
832 /* Called by libthread_db. Returns a pointer to the thread local
833 storage (or its descriptor). */
836 ps_get_thread_area (struct ps_prochandle
*ph
,
837 lwpid_t lwpid
, int idx
, void **base
)
839 gdbarch
*arch
= current_inferior ()->arch ();
840 int is_64bit_p
= (gdbarch_bfd_arch_info (arch
)->bits_per_word
== 64);
842 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
, is_64bit_p
);
846 /* Implement the virtual inf_ptrace_target::post_startup_inferior method. */
849 aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid
)
851 low_forget_process (ptid
.pid ());
852 aarch64_linux_get_debug_reg_capacity (ptid
.pid ());
853 linux_nat_target::post_startup_inferior (ptid
);
856 /* Implement the "post_attach" target_ops method. */
859 aarch64_linux_nat_target::post_attach (int pid
)
861 low_forget_process (pid
);
862 /* Set the hardware debug register capacity. If
863 aarch64_linux_get_debug_reg_capacity is not called
864 (as it is in aarch64_linux_child_post_startup_inferior) then
865 software watchpoints will be used instead of hardware
866 watchpoints when attaching to a target. */
867 aarch64_linux_get_debug_reg_capacity (pid
);
868 linux_nat_target::post_attach (pid
);
871 /* Implement the "read_description" target_ops method. */
873 const struct target_desc
*
874 aarch64_linux_nat_target::read_description ()
877 gdb_byte regbuf
[ARM_VFP3_REGS_SIZE
];
880 if (inferior_ptid
== null_ptid
)
881 return this->beneath ()->read_description ();
883 tid
= inferior_ptid
.pid ();
885 iovec
.iov_base
= regbuf
;
886 iovec
.iov_len
= ARM_VFP3_REGS_SIZE
;
888 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
890 return aarch32_read_description ();
892 CORE_ADDR hwcap
= linux_get_hwcap ();
893 CORE_ADDR hwcap2
= linux_get_hwcap2 ();
895 aarch64_features features
;
896 /* SVE/SSVE check. Reading VQ may return either the regular vector length
897 or the streaming vector length, depending on whether streaming mode is
899 features
.vq
= aarch64_sve_get_vq (tid
);
900 features
.pauth
= hwcap
& AARCH64_HWCAP_PACA
;
901 features
.mte
= hwcap2
& HWCAP2_MTE
;
902 features
.tls
= aarch64_tls_register_count (tid
);
903 /* SME feature check. */
904 features
.svq
= aarch64_za_get_svq (tid
);
906 /* Check for SME2 support. */
907 if ((hwcap2
& HWCAP2_SME2
) || (hwcap2
& HWCAP2_SME2P1
))
908 features
.sme2
= supports_zt_registers (tid
);
910 return aarch64_read_description (features
);
913 /* Convert a native/host siginfo object, into/from the siginfo in the
914 layout of the inferiors' architecture. Returns true if any
915 conversion was done; false otherwise. If DIRECTION is 1, then copy
916 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
920 aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
923 struct gdbarch
*gdbarch
= get_frame_arch (get_current_frame ());
925 /* Is the inferior 32-bit? If so, then do fixup the siginfo
927 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
930 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
933 aarch64_siginfo_from_compat_siginfo (native
,
934 (struct compat_siginfo
*) inf
);
942 /* Implement the "stopped_data_address" target_ops method. */
945 aarch64_linux_nat_target::stopped_data_address (CORE_ADDR
*addr_p
)
948 struct aarch64_debug_reg_state
*state
;
950 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
953 /* This must be a hardware breakpoint. */
954 if (siginfo
.si_signo
!= SIGTRAP
955 || (siginfo
.si_code
& 0xffff) != TRAP_HWBKPT
)
958 /* Make sure to ignore the top byte, otherwise we may not recognize a
959 hardware watchpoint hit. The stopped data addresses coming from the
960 kernel can potentially be tagged addresses. */
961 struct gdbarch
*gdbarch
= thread_architecture (inferior_ptid
);
962 const CORE_ADDR addr_trap
963 = gdbarch_remove_non_address_bits (gdbarch
, (CORE_ADDR
) siginfo
.si_addr
);
965 /* Check if the address matches any watched address. */
966 state
= aarch64_get_debug_reg_state (inferior_ptid
.pid ());
967 return aarch64_stopped_data_address (state
, addr_trap
, addr_p
);
970 /* Implement the "stopped_by_watchpoint" target_ops method. */
973 aarch64_linux_nat_target::stopped_by_watchpoint ()
977 return stopped_data_address (&addr
);
980 /* Implement the "can_do_single_step" target_ops method. */
983 aarch64_linux_nat_target::can_do_single_step ()
988 /* Implement the "thread_architecture" target_ops method.
990 Returns the gdbarch for the thread identified by PTID. If the thread in
991 question is a 32-bit ARM thread, then the architecture returned will be
992 that of the process itself.
994 If the thread is an AArch64 thread then we need to check the current
995 vector length; if the vector length has changed then we need to lookup a
996 new gdbarch that matches the new vector length. */
999 aarch64_linux_nat_target::thread_architecture (ptid_t ptid
)
1001 /* Find the current gdbarch the same way as process_stratum_target. */
1002 inferior
*inf
= find_inferior_ptid (this, ptid
);
1003 gdb_assert (inf
!= NULL
);
1005 /* If this is a 32-bit architecture, then this is ARM, not AArch64.
1006 There's no SVE vectors here, so just return the inferior
1008 if (gdbarch_bfd_arch_info (inf
->arch ())->bits_per_word
== 32)
1009 return inf
->arch ();
1011 /* Only return the inferior's gdbarch if both vq and svq match the ones in
1013 aarch64_gdbarch_tdep
*tdep
1014 = gdbarch_tdep
<aarch64_gdbarch_tdep
> (inf
->arch ());
1015 uint64_t vq
= aarch64_sve_get_vq (ptid
.lwp ());
1016 uint64_t svq
= aarch64_za_get_svq (ptid
.lwp ());
1017 if (vq
== tdep
->vq
&& svq
== tdep
->sme_svq
)
1018 return inf
->arch ();
1020 /* We reach here if any vector length for the thread is different from its
1021 value at process start. Lookup gdbarch via info (potentially creating a
1022 new one) by using a target description that corresponds to the new vq/svq
1023 value and the current architecture features. */
1025 const struct target_desc
*tdesc
= gdbarch_target_desc (inf
->arch ());
1026 aarch64_features features
= aarch64_features_from_target_desc (tdesc
);
1030 /* Check for the SME2 feature. */
1031 features
.sme2
= supports_zt_registers (ptid
.lwp ());
1033 struct gdbarch_info info
;
1034 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_aarch64
, bfd_mach_aarch64
);
1035 info
.target_desc
= aarch64_read_description (features
);
1036 return gdbarch_find_by_info (info
);
1039 /* Implement the "supports_memory_tagging" target_ops method. */
1042 aarch64_linux_nat_target::supports_memory_tagging ()
1044 return (linux_get_hwcap2 () & HWCAP2_MTE
) != 0;
1047 /* Implement the "fetch_memtags" target_ops method. */
1050 aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address
, size_t len
,
1051 gdb::byte_vector
&tags
, int type
)
1053 int tid
= get_ptrace_pid (inferior_ptid
);
1055 /* Allocation tags? */
1056 if (type
== static_cast<int> (aarch64_memtag_type::mte_allocation
))
1057 return aarch64_mte_fetch_memtags (tid
, address
, len
, tags
);
1062 /* Implement the "store_memtags" target_ops method. */
1065 aarch64_linux_nat_target::store_memtags (CORE_ADDR address
, size_t len
,
1066 const gdb::byte_vector
&tags
, int type
)
1068 int tid
= get_ptrace_pid (inferior_ptid
);
1070 /* Allocation tags? */
1071 if (type
== static_cast<int> (aarch64_memtag_type::mte_allocation
))
1072 return aarch64_mte_store_memtags (tid
, address
, len
, tags
);
1077 void _initialize_aarch64_linux_nat ();
1079 _initialize_aarch64_linux_nat ()
1081 aarch64_initialize_hw_point ();
1083 /* Register the target. */
1084 linux_target
= &the_aarch64_linux_nat_target
;
1085 add_inf_child_target (&the_aarch64_linux_nat_target
);