1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1993-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "frame-unwind.h"
23 #include "frame-base.h"
24 #include "dwarf2/frame.h"
35 #include "reggroups.h"
36 #include "arch-utils.h"
39 #include "trad-frame.h"
43 #include "alpha-tdep.h"
46 /* Instruction decoding. The notations for registers, immediates and
47 opcodes are the same as the one used in Compaq's Alpha architecture
50 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
52 /* Memory instruction format */
53 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
54 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
55 #define MEM_DISP(insn) \
56 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
58 static const int lda_opcode
= 0x08;
59 static const int stq_opcode
= 0x2d;
61 /* Branch instruction format */
62 #define BR_RA(insn) MEM_RA(insn)
64 static const int br_opcode
= 0x30;
65 static const int bne_opcode
= 0x3d;
67 /* Operate instruction format */
68 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
69 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
70 #define OPR_RA(insn) MEM_RA(insn)
71 #define OPR_RC(insn) ((insn & 0x1f))
72 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
74 static const int subq_opcode
= 0x10;
75 static const int subq_function
= 0x29;
78 /* Return the name of the REGNO register.
80 An empty name corresponds to a register number that used to
81 be used for a virtual register. That virtual register has
82 been removed, but the index is still reserved to maintain
83 compatibility with existing remote alpha targets. */
86 alpha_register_name (struct gdbarch
*gdbarch
, int regno
)
88 static const char * const register_names
[] =
90 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
91 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
92 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
93 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
94 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
95 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
96 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
97 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
101 static_assert (ALPHA_NUM_REGS
== ARRAY_SIZE (register_names
));
102 return register_names
[regno
];
106 alpha_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
108 return (strlen (alpha_register_name (gdbarch
, regno
)) == 0);
112 alpha_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
114 return (regno
== ALPHA_ZERO_REGNUM
115 || strlen (alpha_register_name (gdbarch
, regno
)) == 0);
119 alpha_register_type (struct gdbarch
*gdbarch
, int regno
)
121 if (regno
== ALPHA_SP_REGNUM
|| regno
== ALPHA_GP_REGNUM
)
122 return builtin_type (gdbarch
)->builtin_data_ptr
;
123 if (regno
== ALPHA_PC_REGNUM
)
124 return builtin_type (gdbarch
)->builtin_func_ptr
;
126 /* Don't need to worry about little vs big endian until
127 some jerk tries to port to alpha-unicosmk. */
128 if (regno
>= ALPHA_FP0_REGNUM
&& regno
< ALPHA_FP0_REGNUM
+ 31)
129 return builtin_type (gdbarch
)->builtin_double
;
131 return builtin_type (gdbarch
)->builtin_int64
;
134 /* Is REGNUM a member of REGGROUP? */
137 alpha_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
138 const struct reggroup
*group
)
140 /* Filter out any registers eliminated, but whose regnum is
141 reserved for backward compatibility, e.g. the vfp. */
142 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
145 if (group
== all_reggroup
)
148 /* Zero should not be saved or restored. Technically it is a general
149 register (just as $f31 would be a float if we represented it), but
150 there's no point displaying it during "info regs", so leave it out
151 of all groups except for "all". */
152 if (regnum
== ALPHA_ZERO_REGNUM
)
155 /* All other registers are saved and restored. */
156 if (group
== save_reggroup
|| group
== restore_reggroup
)
159 /* All other groups are non-overlapping. */
161 /* Since this is really a PALcode memory slot... */
162 if (regnum
== ALPHA_UNIQUE_REGNUM
)
163 return group
== system_reggroup
;
165 /* Force the FPCR to be considered part of the floating point state. */
166 if (regnum
== ALPHA_FPCR_REGNUM
)
167 return group
== float_reggroup
;
169 if (regnum
>= ALPHA_FP0_REGNUM
&& regnum
< ALPHA_FP0_REGNUM
+ 31)
170 return group
== float_reggroup
;
172 return group
== general_reggroup
;
175 /* The following represents exactly the conversion performed by
176 the LDS instruction. This applies to both single-precision
177 floating point and 32-bit integers. */
180 alpha_lds (struct gdbarch
*gdbarch
, void *out
, const void *in
)
182 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
184 = extract_unsigned_integer ((const gdb_byte
*) in
, 4, byte_order
);
185 ULONGEST frac
= (mem
>> 0) & 0x7fffff;
186 ULONGEST sign
= (mem
>> 31) & 1;
187 ULONGEST exp_msb
= (mem
>> 30) & 1;
188 ULONGEST exp_low
= (mem
>> 23) & 0x7f;
191 exp
= (exp_msb
<< 10) | exp_low
;
203 reg
= (sign
<< 63) | (exp
<< 52) | (frac
<< 29);
204 store_unsigned_integer ((gdb_byte
*) out
, 8, byte_order
, reg
);
207 /* Similarly, this represents exactly the conversion performed by
208 the STS instruction. */
211 alpha_sts (struct gdbarch
*gdbarch
, void *out
, const void *in
)
213 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
216 reg
= extract_unsigned_integer ((const gdb_byte
*) in
, 8, byte_order
);
217 mem
= ((reg
>> 32) & 0xc0000000) | ((reg
>> 29) & 0x3fffffff);
218 store_unsigned_integer ((gdb_byte
*) out
, 4, byte_order
, mem
);
221 /* The alpha needs a conversion between register and memory format if the
222 register is a floating point register and memory format is float, as the
223 register format must be double or memory format is an integer with 4
224 bytes, as the representation of integers in floating point
225 registers is different. */
228 alpha_convert_register_p (struct gdbarch
*gdbarch
, int regno
,
231 return (regno
>= ALPHA_FP0_REGNUM
&& regno
< ALPHA_FP0_REGNUM
+ 31
232 && type
->length () == 4);
236 alpha_register_to_value (frame_info_ptr frame
, int regnum
,
237 struct type
*valtype
, gdb_byte
*out
,
238 int *optimizedp
, int *unavailablep
)
240 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
241 struct value
*value
= get_frame_register_value (frame
, regnum
);
243 gdb_assert (value
!= NULL
);
244 *optimizedp
= value
->optimized_out ();
245 *unavailablep
= !value
->entirely_available ();
247 if (*optimizedp
|| *unavailablep
)
249 release_value (value
);
253 /* Convert to VALTYPE. */
255 gdb_assert (valtype
->length () == 4);
256 alpha_sts (gdbarch
, out
, value
->contents_all ().data ());
258 release_value (value
);
263 alpha_value_to_register (frame_info_ptr frame
, int regnum
,
264 struct type
*valtype
, const gdb_byte
*in
)
266 gdb_byte out
[ALPHA_REGISTER_SIZE
];
268 gdb_assert (valtype
->length () == 4);
269 gdb_assert (register_size (get_frame_arch (frame
), regnum
)
270 <= ALPHA_REGISTER_SIZE
);
271 alpha_lds (get_frame_arch (frame
), out
, in
);
273 put_frame_register (frame
, regnum
, out
);
277 /* The alpha passes the first six arguments in the registers, the rest on
278 the stack. The register arguments are stored in ARG_REG_BUFFER, and
279 then moved into the register file; this simplifies the passing of a
280 large struct which extends from the registers to the stack, plus avoids
281 three ptrace invocations per word.
283 We don't bother tracking which register values should go in integer
284 regs or fp regs; we load the same values into both.
286 If the called function is returning a structure, the address of the
287 structure to be returned is passed as a hidden first argument. */
290 alpha_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
291 struct regcache
*regcache
, CORE_ADDR bp_addr
,
292 int nargs
, struct value
**args
, CORE_ADDR sp
,
293 function_call_return_method return_method
,
294 CORE_ADDR struct_addr
)
296 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
298 int accumulate_size
= (return_method
== return_method_struct
) ? 8 : 0;
301 const gdb_byte
*contents
;
305 struct alpha_arg
*alpha_args
= XALLOCAVEC (struct alpha_arg
, nargs
);
306 struct alpha_arg
*m_arg
;
307 gdb_byte arg_reg_buffer
[ALPHA_REGISTER_SIZE
* ALPHA_NUM_ARG_REGS
];
308 int required_arg_regs
;
309 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
311 /* The ABI places the address of the called function in T12. */
312 regcache_cooked_write_signed (regcache
, ALPHA_T12_REGNUM
, func_addr
);
314 /* Set the return address register to point to the entry point
315 of the program, where a breakpoint lies in wait. */
316 regcache_cooked_write_signed (regcache
, ALPHA_RA_REGNUM
, bp_addr
);
318 /* Lay out the arguments in memory. */
319 for (i
= 0, m_arg
= alpha_args
; i
< nargs
; i
++, m_arg
++)
321 struct value
*arg
= args
[i
];
322 struct type
*arg_type
= check_typedef (arg
->type ());
324 /* Cast argument to long if necessary as the compiler does it too. */
325 switch (arg_type
->code ())
330 case TYPE_CODE_RANGE
:
332 if (arg_type
->length () == 4)
334 /* 32-bit values must be sign-extended to 64 bits
335 even if the base data type is unsigned. */
336 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
337 arg
= value_cast (arg_type
, arg
);
339 if (arg_type
->length () < ALPHA_REGISTER_SIZE
)
341 arg_type
= builtin_type (gdbarch
)->builtin_int64
;
342 arg
= value_cast (arg_type
, arg
);
347 /* "float" arguments loaded in registers must be passed in
348 register format, aka "double". */
349 if (accumulate_size
< sizeof (arg_reg_buffer
)
350 && arg_type
->length () == 4)
352 arg_type
= builtin_type (gdbarch
)->builtin_double
;
353 arg
= value_cast (arg_type
, arg
);
355 /* Tru64 5.1 has a 128-bit long double, and passes this by
356 invisible reference. No one else uses this data type. */
357 else if (arg_type
->length () == 16)
359 /* Allocate aligned storage. */
360 sp
= (sp
& -16) - 16;
362 /* Write the real data into the stack. */
363 write_memory (sp
, arg
->contents ().data (), 16);
365 /* Construct the indirection. */
366 arg_type
= lookup_pointer_type (arg_type
);
367 arg
= value_from_pointer (arg_type
, sp
);
371 case TYPE_CODE_COMPLEX
:
372 /* ??? The ABI says that complex values are passed as two
373 separate scalar values. This distinction only matters
374 for complex float. However, GCC does not implement this. */
376 /* Tru64 5.1 has a 128-bit long double, and passes this by
377 invisible reference. */
378 if (arg_type
->length () == 32)
380 /* Allocate aligned storage. */
381 sp
= (sp
& -16) - 16;
383 /* Write the real data into the stack. */
384 write_memory (sp
, arg
->contents ().data (), 32);
386 /* Construct the indirection. */
387 arg_type
= lookup_pointer_type (arg_type
);
388 arg
= value_from_pointer (arg_type
, sp
);
395 m_arg
->len
= arg_type
->length ();
396 m_arg
->offset
= accumulate_size
;
397 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 7) & ~7;
398 m_arg
->contents
= arg
->contents ().data ();
401 /* Determine required argument register loads, loading an argument register
402 is expensive as it uses three ptrace calls. */
403 required_arg_regs
= accumulate_size
/ 8;
404 if (required_arg_regs
> ALPHA_NUM_ARG_REGS
)
405 required_arg_regs
= ALPHA_NUM_ARG_REGS
;
407 /* Make room for the arguments on the stack. */
408 if (accumulate_size
< sizeof(arg_reg_buffer
))
411 accumulate_size
-= sizeof(arg_reg_buffer
);
412 sp
-= accumulate_size
;
414 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
417 /* `Push' arguments on the stack. */
418 for (i
= nargs
; m_arg
--, --i
>= 0;)
420 const gdb_byte
*contents
= m_arg
->contents
;
421 int offset
= m_arg
->offset
;
422 int len
= m_arg
->len
;
424 /* Copy the bytes destined for registers into arg_reg_buffer. */
425 if (offset
< sizeof(arg_reg_buffer
))
427 if (offset
+ len
<= sizeof(arg_reg_buffer
))
429 memcpy (arg_reg_buffer
+ offset
, contents
, len
);
434 int tlen
= sizeof(arg_reg_buffer
) - offset
;
435 memcpy (arg_reg_buffer
+ offset
, contents
, tlen
);
442 /* Everything else goes to the stack. */
443 write_memory (sp
+ offset
- sizeof(arg_reg_buffer
), contents
, len
);
445 if (return_method
== return_method_struct
)
446 store_unsigned_integer (arg_reg_buffer
, ALPHA_REGISTER_SIZE
,
447 byte_order
, struct_addr
);
449 /* Load the argument registers. */
450 for (i
= 0; i
< required_arg_regs
; i
++)
452 regcache
->cooked_write (ALPHA_A0_REGNUM
+ i
,
453 arg_reg_buffer
+ i
* ALPHA_REGISTER_SIZE
);
454 regcache
->cooked_write (ALPHA_FPA0_REGNUM
+ i
,
455 arg_reg_buffer
+ i
* ALPHA_REGISTER_SIZE
);
458 /* Finally, update the stack pointer. */
459 regcache_cooked_write_signed (regcache
, ALPHA_SP_REGNUM
, sp
);
464 /* Extract from REGCACHE the value about to be returned from a function
465 and copy it into VALBUF. */
468 alpha_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
471 struct gdbarch
*gdbarch
= regcache
->arch ();
472 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
473 gdb_byte raw_buffer
[ALPHA_REGISTER_SIZE
];
476 switch (valtype
->code ())
479 switch (valtype
->length ())
482 regcache
->cooked_read (ALPHA_FP0_REGNUM
, raw_buffer
);
483 alpha_sts (gdbarch
, valbuf
, raw_buffer
);
487 regcache
->cooked_read (ALPHA_FP0_REGNUM
, valbuf
);
491 regcache_cooked_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &l
);
492 read_memory (l
, valbuf
, 16);
496 internal_error (_("unknown floating point width"));
500 case TYPE_CODE_COMPLEX
:
501 switch (valtype
->length ())
504 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
505 regcache
->cooked_read (ALPHA_FP0_REGNUM
, valbuf
);
509 regcache
->cooked_read (ALPHA_FP0_REGNUM
, valbuf
);
510 regcache
->cooked_read (ALPHA_FP0_REGNUM
+ 1, valbuf
+ 8);
514 regcache_cooked_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &l
);
515 read_memory (l
, valbuf
, 32);
519 internal_error (_("unknown floating point width"));
524 /* Assume everything else degenerates to an integer. */
525 regcache_cooked_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &l
);
526 store_unsigned_integer (valbuf
, valtype
->length (), byte_order
, l
);
531 /* Insert the given value into REGCACHE as if it was being
532 returned by a function. */
535 alpha_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
536 const gdb_byte
*valbuf
)
538 struct gdbarch
*gdbarch
= regcache
->arch ();
539 gdb_byte raw_buffer
[ALPHA_REGISTER_SIZE
];
542 switch (valtype
->code ())
545 switch (valtype
->length ())
548 alpha_lds (gdbarch
, raw_buffer
, valbuf
);
549 regcache
->cooked_write (ALPHA_FP0_REGNUM
, raw_buffer
);
553 regcache
->cooked_write (ALPHA_FP0_REGNUM
, valbuf
);
557 /* FIXME: 128-bit long doubles are returned like structures:
558 by writing into indirect storage provided by the caller
559 as the first argument. */
560 error (_("Cannot set a 128-bit long double return value."));
563 internal_error (_("unknown floating point width"));
567 case TYPE_CODE_COMPLEX
:
568 switch (valtype
->length ())
571 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
572 regcache
->cooked_write (ALPHA_FP0_REGNUM
, valbuf
);
576 regcache
->cooked_write (ALPHA_FP0_REGNUM
, valbuf
);
577 regcache
->cooked_write (ALPHA_FP0_REGNUM
+ 1, valbuf
+ 8);
581 /* FIXME: 128-bit long doubles are returned like structures:
582 by writing into indirect storage provided by the caller
583 as the first argument. */
584 error (_("Cannot set a 128-bit long double return value."));
587 internal_error (_("unknown floating point width"));
592 /* Assume everything else degenerates to an integer. */
593 /* 32-bit values must be sign-extended to 64 bits
594 even if the base data type is unsigned. */
595 if (valtype
->length () == 4)
596 valtype
= builtin_type (gdbarch
)->builtin_int32
;
597 l
= unpack_long (valtype
, valbuf
);
598 regcache_cooked_write_unsigned (regcache
, ALPHA_V0_REGNUM
, l
);
603 static enum return_value_convention
604 alpha_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
605 struct type
*type
, struct regcache
*regcache
,
606 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
608 enum type_code code
= type
->code ();
609 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
611 if ((code
== TYPE_CODE_STRUCT
612 || code
== TYPE_CODE_UNION
613 || code
== TYPE_CODE_ARRAY
)
614 && tdep
->return_in_memory (type
))
619 regcache_raw_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &addr
);
620 read_memory (addr
, readbuf
, type
->length ());
623 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
627 alpha_extract_return_value (type
, regcache
, readbuf
);
629 alpha_store_return_value (type
, regcache
, writebuf
);
631 return RETURN_VALUE_REGISTER_CONVENTION
;
635 alpha_return_in_memory_always (struct type
*type
)
641 constexpr gdb_byte alpha_break_insn
[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
643 typedef BP_MANIPULATION (alpha_break_insn
) alpha_breakpoint
;
646 /* This returns the PC of the first insn after the prologue.
647 If we can't find the prologue, then return 0. */
650 alpha_after_prologue (CORE_ADDR pc
)
652 struct symtab_and_line sal
;
653 CORE_ADDR func_addr
, func_end
;
655 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
658 sal
= find_pc_line (func_addr
, 0);
659 if (sal
.end
< func_end
)
662 /* The line after the prologue is after the end of the function. In this
663 case, tell the caller to find the prologue the hard way. */
667 /* Read an instruction from memory at PC, looking through breakpoints. */
670 alpha_read_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
672 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
673 gdb_byte buf
[ALPHA_INSN_SIZE
];
676 res
= target_read_memory (pc
, buf
, sizeof (buf
));
678 memory_error (TARGET_XFER_E_IO
, pc
);
679 return extract_unsigned_integer (buf
, sizeof (buf
), byte_order
);
682 /* To skip prologues, I use this predicate. Returns either PC itself
683 if the code at PC does not look like a function prologue; otherwise
684 returns an address that (if we're lucky) follows the prologue. If
685 LENIENT, then we must skip everything which is involved in setting
686 up the frame (it's OK to skip more, just so long as we don't skip
687 anything which might clobber the registers which are being saved. */
690 alpha_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
694 CORE_ADDR post_prologue_pc
;
695 gdb_byte buf
[ALPHA_INSN_SIZE
];
697 /* Silently return the unaltered pc upon memory errors.
698 This could happen on OSF/1 if decode_line_1 tries to skip the
699 prologue for quickstarted shared library functions when the
700 shared library is not yet mapped in.
701 Reading target memory is slow over serial lines, so we perform
702 this check only if the target has shared libraries (which all
703 Alpha targets do). */
704 if (target_read_memory (pc
, buf
, sizeof (buf
)))
707 /* See if we can determine the end of the prologue via the symbol table.
708 If so, then return either PC, or the PC after the prologue, whichever
711 post_prologue_pc
= alpha_after_prologue (pc
);
712 if (post_prologue_pc
!= 0)
713 return std::max (pc
, post_prologue_pc
);
715 /* Can't determine prologue from the symbol table, need to examine
718 /* Skip the typical prologue instructions. These are the stack adjustment
719 instruction and the instructions that save registers on the stack
720 or in the gcc frame. */
721 for (offset
= 0; offset
< 100; offset
+= ALPHA_INSN_SIZE
)
723 inst
= alpha_read_insn (gdbarch
, pc
+ offset
);
725 if ((inst
& 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
727 if ((inst
& 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
729 if ((inst
& 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
731 if ((inst
& 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
734 if (((inst
& 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
735 || (inst
& 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
736 && (inst
& 0x03e00000) != 0x03e00000) /* reg != $zero */
739 if (inst
== 0x47de040f) /* bis sp,sp,fp */
741 if (inst
== 0x47fe040f) /* bis zero,sp,fp */
750 static const int ldl_l_opcode
= 0x2a;
751 static const int ldq_l_opcode
= 0x2b;
752 static const int stl_c_opcode
= 0x2e;
753 static const int stq_c_opcode
= 0x2f;
755 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L
756 instruction and ending with a STL_C/STQ_C instruction. If such a sequence
757 is found, attempt to step through it. A breakpoint is placed at the end of
760 static std::vector
<CORE_ADDR
>
761 alpha_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
763 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
765 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
766 unsigned int insn
= alpha_read_insn (gdbarch
, loc
);
769 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
770 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
771 int bc_insn_count
= 0; /* Conditional branch instruction count. */
773 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
774 if (INSN_OPCODE (insn
) != ldl_l_opcode
775 && INSN_OPCODE (insn
) != ldq_l_opcode
)
778 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
780 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
782 loc
+= ALPHA_INSN_SIZE
;
783 insn
= alpha_read_insn (gdbarch
, loc
);
785 /* Assume that there is at most one branch in the atomic
786 sequence. If a branch is found, put a breakpoint in
787 its destination address. */
788 if (INSN_OPCODE (insn
) >= br_opcode
)
790 int immediate
= (insn
& 0x001fffff) << 2;
792 immediate
= (immediate
^ 0x400000) - 0x400000;
794 if (bc_insn_count
>= 1)
795 return {}; /* More than one branch found, fallback
796 to the standard single-step code. */
798 breaks
[1] = loc
+ ALPHA_INSN_SIZE
+ immediate
;
804 if (INSN_OPCODE (insn
) == stl_c_opcode
805 || INSN_OPCODE (insn
) == stq_c_opcode
)
809 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
810 if (INSN_OPCODE (insn
) != stl_c_opcode
811 && INSN_OPCODE (insn
) != stq_c_opcode
)
815 loc
+= ALPHA_INSN_SIZE
;
817 /* Insert a breakpoint right after the end of the atomic sequence. */
820 /* Check for duplicated breakpoints. Check also for a breakpoint
821 placed (branch instruction's destination) anywhere in sequence. */
823 && (breaks
[1] == breaks
[0]
824 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
827 std::vector
<CORE_ADDR
> next_pcs
;
829 for (index
= 0; index
<= last_breakpoint
; index
++)
830 next_pcs
.push_back (breaks
[index
]);
836 /* Figure out where the longjmp will land.
837 We expect the first arg to be a pointer to the jmp_buf structure from
838 which we extract the PC (JB_PC) that we will land at. The PC is copied
839 into the "pc". This routine returns true on success. */
842 alpha_get_longjmp_target (frame_info_ptr frame
, CORE_ADDR
*pc
)
844 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
845 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
846 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
848 gdb_byte raw_buffer
[ALPHA_REGISTER_SIZE
];
850 jb_addr
= get_frame_register_unsigned (frame
, ALPHA_A0_REGNUM
);
852 if (target_read_memory (jb_addr
+ (tdep
->jb_pc
* tdep
->jb_elt_size
),
853 raw_buffer
, tdep
->jb_elt_size
))
856 *pc
= extract_unsigned_integer (raw_buffer
, tdep
->jb_elt_size
, byte_order
);
861 /* Frame unwinder for signal trampolines. We use alpha tdep bits that
862 describe the location and shape of the sigcontext structure. After
863 that, all registers are in memory, so it's easy. */
864 /* ??? Shouldn't we be able to do this generically, rather than with
865 OSABI data specific to Alpha? */
867 struct alpha_sigtramp_unwind_cache
869 CORE_ADDR sigcontext_addr
;
872 static struct alpha_sigtramp_unwind_cache
*
873 alpha_sigtramp_frame_unwind_cache (frame_info_ptr this_frame
,
874 void **this_prologue_cache
)
876 struct alpha_sigtramp_unwind_cache
*info
;
878 if (*this_prologue_cache
)
879 return (struct alpha_sigtramp_unwind_cache
*) *this_prologue_cache
;
881 info
= FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache
);
882 *this_prologue_cache
= info
;
884 gdbarch
*arch
= get_frame_arch (this_frame
);
885 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (arch
);
886 info
->sigcontext_addr
= tdep
->sigcontext_addr (this_frame
);
891 /* Return the address of REGNUM in a sigtramp frame. Since this is
892 all arithmetic, it doesn't seem worthwhile to cache it. */
895 alpha_sigtramp_register_address (struct gdbarch
*gdbarch
,
896 CORE_ADDR sigcontext_addr
, int regnum
)
898 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
900 if (regnum
>= 0 && regnum
< 32)
901 return sigcontext_addr
+ tdep
->sc_regs_offset
+ regnum
* 8;
902 else if (regnum
>= ALPHA_FP0_REGNUM
&& regnum
< ALPHA_FP0_REGNUM
+ 32)
903 return sigcontext_addr
+ tdep
->sc_fpregs_offset
+ regnum
* 8;
904 else if (regnum
== ALPHA_PC_REGNUM
)
905 return sigcontext_addr
+ tdep
->sc_pc_offset
;
910 /* Given a GDB frame, determine the address of the calling function's
911 frame. This will be used to create a new GDB frame struct. */
914 alpha_sigtramp_frame_this_id (frame_info_ptr this_frame
,
915 void **this_prologue_cache
,
916 struct frame_id
*this_id
)
918 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
919 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
920 struct alpha_sigtramp_unwind_cache
*info
921 = alpha_sigtramp_frame_unwind_cache (this_frame
, this_prologue_cache
);
922 CORE_ADDR stack_addr
, code_addr
;
924 /* If the OSABI couldn't locate the sigcontext, give up. */
925 if (info
->sigcontext_addr
== 0)
928 /* If we have dynamic signal trampolines, find their start.
929 If we do not, then we must assume there is a symbol record
930 that can provide the start address. */
931 if (tdep
->dynamic_sigtramp_offset
)
934 code_addr
= get_frame_pc (this_frame
);
935 offset
= tdep
->dynamic_sigtramp_offset (gdbarch
, code_addr
);
942 code_addr
= get_frame_func (this_frame
);
944 /* The stack address is trivially read from the sigcontext. */
945 stack_addr
= alpha_sigtramp_register_address (gdbarch
, info
->sigcontext_addr
,
947 stack_addr
= get_frame_memory_unsigned (this_frame
, stack_addr
,
948 ALPHA_REGISTER_SIZE
);
950 *this_id
= frame_id_build (stack_addr
, code_addr
);
953 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
955 static struct value
*
956 alpha_sigtramp_frame_prev_register (frame_info_ptr this_frame
,
957 void **this_prologue_cache
, int regnum
)
959 struct alpha_sigtramp_unwind_cache
*info
960 = alpha_sigtramp_frame_unwind_cache (this_frame
, this_prologue_cache
);
963 if (info
->sigcontext_addr
!= 0)
965 /* All integer and fp registers are stored in memory. */
966 addr
= alpha_sigtramp_register_address (get_frame_arch (this_frame
),
967 info
->sigcontext_addr
, regnum
);
969 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
972 /* This extra register may actually be in the sigcontext, but our
973 current description of it in alpha_sigtramp_frame_unwind_cache
974 doesn't include it. Too bad. Fall back on whatever's in the
976 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
980 alpha_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
981 frame_info_ptr this_frame
,
982 void **this_prologue_cache
)
984 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
985 CORE_ADDR pc
= get_frame_pc (this_frame
);
988 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
989 look at tramp-frame.h and other simpler per-architecture
990 sigtramp unwinders. */
992 /* We shouldn't even bother to try if the OSABI didn't register a
993 sigcontext_addr handler or pc_in_sigtramp handler. */
994 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
995 if (tdep
->sigcontext_addr
== NULL
)
998 if (tdep
->pc_in_sigtramp
== NULL
)
1001 /* Otherwise we should be in a signal frame. */
1002 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
1003 if (tdep
->pc_in_sigtramp (gdbarch
, pc
, name
))
1009 static const struct frame_unwind alpha_sigtramp_frame_unwind
=
1013 default_frame_unwind_stop_reason
,
1014 alpha_sigtramp_frame_this_id
,
1015 alpha_sigtramp_frame_prev_register
,
1017 alpha_sigtramp_frame_sniffer
1022 /* Heuristic_proc_start may hunt through the text section for a long
1023 time across a 2400 baud serial line. Allows the user to limit this
1025 static int heuristic_fence_post
= 0;
1027 /* Attempt to locate the start of the function containing PC. We assume that
1028 the previous function ends with an about_to_return insn. Not foolproof by
1029 any means, since gcc is happy to put the epilogue in the middle of a
1030 function. But we're guessing anyway... */
1033 alpha_heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1035 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
1036 CORE_ADDR last_non_nop
= pc
;
1037 CORE_ADDR fence
= pc
- heuristic_fence_post
;
1038 CORE_ADDR orig_pc
= pc
;
1040 struct inferior
*inf
;
1045 /* First see if we can find the start of the function from minimal
1046 symbol information. This can succeed with a binary that doesn't
1047 have debug info, but hasn't been stripped. */
1048 func
= get_pc_function_start (pc
);
1052 if (heuristic_fence_post
== -1
1053 || fence
< tdep
->vm_min_address
)
1054 fence
= tdep
->vm_min_address
;
1056 /* Search back for previous return; also stop at a 0, which might be
1057 seen for instance before the start of a code section. Don't include
1058 nops, since this usually indicates padding between functions. */
1059 for (pc
-= ALPHA_INSN_SIZE
; pc
>= fence
; pc
-= ALPHA_INSN_SIZE
)
1061 unsigned int insn
= alpha_read_insn (gdbarch
, pc
);
1064 case 0: /* invalid insn */
1065 case 0x6bfa8001: /* ret $31,($26),1 */
1066 return last_non_nop
;
1068 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
1069 case 0x47ff041f: /* nop: bis $31,$31,$31 */
1078 inf
= current_inferior ();
1080 /* It's not clear to me why we reach this point when stopping quietly,
1081 but with this test, at least we don't print out warnings for every
1082 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
1083 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
1085 static int blurb_printed
= 0;
1087 if (fence
== tdep
->vm_min_address
)
1088 warning (_("Hit beginning of text section without finding \
1089 enclosing function for address %s"), paddress (gdbarch
, orig_pc
));
1091 warning (_("Hit heuristic-fence-post without finding \
1092 enclosing function for address %s"), paddress (gdbarch
, orig_pc
));
1097 This warning occurs if you are debugging a function without any symbols\n\
1098 (for example, in a stripped executable). In that case, you may wish to\n\
1099 increase the size of the search with the `set heuristic-fence-post' command.\n\
1101 Otherwise, you told GDB there was a function where there isn't one, or\n\
1102 (more likely) you have encountered a bug in GDB.\n"));
1110 /* Fallback alpha frame unwinder. Uses instruction scanning and knows
1111 something about the traditional layout of alpha stack frames. */
1113 struct alpha_heuristic_unwind_cache
1117 trad_frame_saved_reg
*saved_regs
;
1121 /* If a probing loop sequence starts at PC, simulate it and compute
1122 FRAME_SIZE and PC after its execution. Otherwise, return with PC and
1123 FRAME_SIZE unchanged. */
1126 alpha_heuristic_analyze_probing_loop (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
,
1129 CORE_ADDR cur_pc
= *pc
;
1130 int cur_frame_size
= *frame_size
;
1131 int nb_of_iterations
, reg_index
, reg_probe
;
1134 /* The following pattern is recognized as a probing loop:
1136 lda REG_INDEX,NB_OF_ITERATIONS
1137 lda REG_PROBE,<immediate>(sp)
1140 stq zero,<immediate>(REG_PROBE)
1141 subq REG_INDEX,0x1,REG_INDEX
1142 lda REG_PROBE,<immediate>(REG_PROBE)
1143 bne REG_INDEX, LOOP_START
1145 lda sp,<immediate>(REG_PROBE)
1147 If anything different is found, the function returns without
1148 changing PC and FRAME_SIZE. Otherwise, PC will point immediately
1149 after this sequence, and FRAME_SIZE will be updated. */
1151 /* lda REG_INDEX,NB_OF_ITERATIONS */
1153 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1154 if (INSN_OPCODE (insn
) != lda_opcode
)
1156 reg_index
= MEM_RA (insn
);
1157 nb_of_iterations
= MEM_DISP (insn
);
1159 /* lda REG_PROBE,<immediate>(sp) */
1161 cur_pc
+= ALPHA_INSN_SIZE
;
1162 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1163 if (INSN_OPCODE (insn
) != lda_opcode
1164 || MEM_RB (insn
) != ALPHA_SP_REGNUM
)
1166 reg_probe
= MEM_RA (insn
);
1167 cur_frame_size
-= MEM_DISP (insn
);
1169 /* stq zero,<immediate>(REG_PROBE) */
1171 cur_pc
+= ALPHA_INSN_SIZE
;
1172 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1173 if (INSN_OPCODE (insn
) != stq_opcode
1174 || MEM_RA (insn
) != 0x1f
1175 || MEM_RB (insn
) != reg_probe
)
1178 /* subq REG_INDEX,0x1,REG_INDEX */
1180 cur_pc
+= ALPHA_INSN_SIZE
;
1181 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1182 if (INSN_OPCODE (insn
) != subq_opcode
1183 || !OPR_HAS_IMMEDIATE (insn
)
1184 || OPR_FUNCTION (insn
) != subq_function
1185 || OPR_LIT(insn
) != 1
1186 || OPR_RA (insn
) != reg_index
1187 || OPR_RC (insn
) != reg_index
)
1190 /* lda REG_PROBE,<immediate>(REG_PROBE) */
1192 cur_pc
+= ALPHA_INSN_SIZE
;
1193 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1194 if (INSN_OPCODE (insn
) != lda_opcode
1195 || MEM_RA (insn
) != reg_probe
1196 || MEM_RB (insn
) != reg_probe
)
1198 cur_frame_size
-= MEM_DISP (insn
) * nb_of_iterations
;
1200 /* bne REG_INDEX, LOOP_START */
1202 cur_pc
+= ALPHA_INSN_SIZE
;
1203 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1204 if (INSN_OPCODE (insn
) != bne_opcode
1205 || MEM_RA (insn
) != reg_index
)
1208 /* lda sp,<immediate>(REG_PROBE) */
1210 cur_pc
+= ALPHA_INSN_SIZE
;
1211 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1212 if (INSN_OPCODE (insn
) != lda_opcode
1213 || MEM_RA (insn
) != ALPHA_SP_REGNUM
1214 || MEM_RB (insn
) != reg_probe
)
1216 cur_frame_size
-= MEM_DISP (insn
);
1219 *frame_size
= cur_frame_size
;
1222 static struct alpha_heuristic_unwind_cache
*
1223 alpha_heuristic_frame_unwind_cache (frame_info_ptr this_frame
,
1224 void **this_prologue_cache
,
1227 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1228 struct alpha_heuristic_unwind_cache
*info
;
1230 CORE_ADDR limit_pc
, cur_pc
;
1231 int frame_reg
, frame_size
, return_reg
, reg
;
1233 if (*this_prologue_cache
)
1234 return (struct alpha_heuristic_unwind_cache
*) *this_prologue_cache
;
1236 info
= FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache
);
1237 *this_prologue_cache
= info
;
1238 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1240 limit_pc
= get_frame_pc (this_frame
);
1242 start_pc
= alpha_heuristic_proc_start (gdbarch
, limit_pc
);
1243 info
->start_pc
= start_pc
;
1245 frame_reg
= ALPHA_SP_REGNUM
;
1249 /* If we've identified a likely place to start, do code scanning. */
1252 /* Limit the forward search to 50 instructions. */
1253 if (start_pc
+ 200 < limit_pc
)
1254 limit_pc
= start_pc
+ 200;
1256 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= ALPHA_INSN_SIZE
)
1258 unsigned int word
= alpha_read_insn (gdbarch
, cur_pc
);
1260 if ((word
& 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1264 /* Consider only the first stack allocation instruction
1265 to contain the static size of the frame. */
1266 if (frame_size
== 0)
1267 frame_size
= (-word
) & 0xffff;
1271 /* Exit loop if a positive stack adjustment is found, which
1272 usually means that the stack cleanup code in the function
1273 epilogue is reached. */
1277 else if ((word
& 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1279 reg
= (word
& 0x03e00000) >> 21;
1281 /* Ignore this instruction if we have already encountered
1282 an instruction saving the same register earlier in the
1283 function code. The current instruction does not tell
1284 us where the original value upon function entry is saved.
1285 All it says is that the function we are scanning reused
1286 that register for some computation of its own, and is now
1287 saving its result. */
1288 if (info
->saved_regs
[reg
].is_addr ())
1294 /* Do not compute the address where the register was saved yet,
1295 because we don't know yet if the offset will need to be
1296 relative to $sp or $fp (we can not compute the address
1297 relative to $sp if $sp is updated during the execution of
1298 the current subroutine, for instance when doing some alloca).
1299 So just store the offset for the moment, and compute the
1300 address later when we know whether this frame has a frame
1302 /* Hack: temporarily add one, so that the offset is non-zero
1303 and we can tell which registers have save offsets below. */
1304 info
->saved_regs
[reg
].set_addr ((word
& 0xffff) + 1);
1306 /* Starting with OSF/1-3.2C, the system libraries are shipped
1307 without local symbols, but they still contain procedure
1308 descriptors without a symbol reference. GDB is currently
1309 unable to find these procedure descriptors and uses
1310 heuristic_proc_desc instead.
1311 As some low level compiler support routines (__div*, __add*)
1312 use a non-standard return address register, we have to
1313 add some heuristics to determine the return address register,
1314 or stepping over these routines will fail.
1315 Usually the return address register is the first register
1316 saved on the stack, but assembler optimization might
1317 rearrange the register saves.
1318 So we recognize only a few registers (t7, t9, ra) within
1319 the procedure prologue as valid return address registers.
1320 If we encounter a return instruction, we extract the
1321 return address register from it.
1323 FIXME: Rewriting GDB to access the procedure descriptors,
1324 e.g. via the minimal symbol table, might obviate this
1326 if (return_reg
== -1
1327 && cur_pc
< (start_pc
+ 80)
1328 && (reg
== ALPHA_T7_REGNUM
1329 || reg
== ALPHA_T9_REGNUM
1330 || reg
== ALPHA_RA_REGNUM
))
1333 else if ((word
& 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1334 return_reg
= (word
>> 16) & 0x1f;
1335 else if (word
== 0x47de040f) /* bis sp,sp,fp */
1336 frame_reg
= ALPHA_GCC_FP_REGNUM
;
1337 else if (word
== 0x47fe040f) /* bis zero,sp,fp */
1338 frame_reg
= ALPHA_GCC_FP_REGNUM
;
1340 alpha_heuristic_analyze_probing_loop (gdbarch
, &cur_pc
, &frame_size
);
1343 /* If we haven't found a valid return address register yet, keep
1344 searching in the procedure prologue. */
1345 if (return_reg
== -1)
1347 while (cur_pc
< (limit_pc
+ 80) && cur_pc
< (start_pc
+ 80))
1349 unsigned int word
= alpha_read_insn (gdbarch
, cur_pc
);
1351 if ((word
& 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1353 reg
= (word
& 0x03e00000) >> 21;
1354 if (reg
== ALPHA_T7_REGNUM
1355 || reg
== ALPHA_T9_REGNUM
1356 || reg
== ALPHA_RA_REGNUM
)
1362 else if ((word
& 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1364 return_reg
= (word
>> 16) & 0x1f;
1368 cur_pc
+= ALPHA_INSN_SIZE
;
1373 /* Failing that, do default to the customary RA. */
1374 if (return_reg
== -1)
1375 return_reg
= ALPHA_RA_REGNUM
;
1376 info
->return_reg
= return_reg
;
1378 val
= get_frame_register_unsigned (this_frame
, frame_reg
);
1379 info
->vfp
= val
+ frame_size
;
1381 /* Convert offsets to absolute addresses. See above about adding
1382 one to the offsets to make all detected offsets non-zero. */
1383 for (reg
= 0; reg
< ALPHA_NUM_REGS
; ++reg
)
1384 if (info
->saved_regs
[reg
].is_addr ())
1385 info
->saved_regs
[reg
].set_addr (info
->saved_regs
[reg
].addr ()
1388 /* The stack pointer of the previous frame is computed by popping
1389 the current stack frame. */
1390 if (!info
->saved_regs
[ALPHA_SP_REGNUM
].is_addr ())
1391 info
->saved_regs
[ALPHA_SP_REGNUM
].set_value (info
->vfp
);
1396 /* Given a GDB frame, determine the address of the calling function's
1397 frame. This will be used to create a new GDB frame struct. */
1400 alpha_heuristic_frame_this_id (frame_info_ptr this_frame
,
1401 void **this_prologue_cache
,
1402 struct frame_id
*this_id
)
1404 struct alpha_heuristic_unwind_cache
*info
1405 = alpha_heuristic_frame_unwind_cache (this_frame
, this_prologue_cache
, 0);
1407 *this_id
= frame_id_build (info
->vfp
, info
->start_pc
);
1410 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
1412 static struct value
*
1413 alpha_heuristic_frame_prev_register (frame_info_ptr this_frame
,
1414 void **this_prologue_cache
, int regnum
)
1416 struct alpha_heuristic_unwind_cache
*info
1417 = alpha_heuristic_frame_unwind_cache (this_frame
, this_prologue_cache
, 0);
1419 /* The PC of the previous frame is stored in the link register of
1420 the current frame. Frob regnum so that we pull the value from
1421 the correct place. */
1422 if (regnum
== ALPHA_PC_REGNUM
)
1423 regnum
= info
->return_reg
;
1425 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1428 static const struct frame_unwind alpha_heuristic_frame_unwind
=
1432 default_frame_unwind_stop_reason
,
1433 alpha_heuristic_frame_this_id
,
1434 alpha_heuristic_frame_prev_register
,
1436 default_frame_sniffer
1440 alpha_heuristic_frame_base_address (frame_info_ptr this_frame
,
1441 void **this_prologue_cache
)
1443 struct alpha_heuristic_unwind_cache
*info
1444 = alpha_heuristic_frame_unwind_cache (this_frame
, this_prologue_cache
, 0);
1449 static const struct frame_base alpha_heuristic_frame_base
= {
1450 &alpha_heuristic_frame_unwind
,
1451 alpha_heuristic_frame_base_address
,
1452 alpha_heuristic_frame_base_address
,
1453 alpha_heuristic_frame_base_address
1456 /* Just like reinit_frame_cache, but with the right arguments to be
1457 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
1460 reinit_frame_cache_sfunc (const char *args
,
1461 int from_tty
, struct cmd_list_element
*c
)
1463 reinit_frame_cache ();
1466 /* Helper routines for alpha*-nat.c files to move register sets to and
1467 from core files. The UNIQUE pointer is allowed to be NULL, as most
1468 targets don't supply this value in their core files. */
1471 alpha_supply_int_regs (struct regcache
*regcache
, int regno
,
1472 const void *r0_r30
, const void *pc
, const void *unique
)
1474 const gdb_byte
*regs
= (const gdb_byte
*) r0_r30
;
1477 for (i
= 0; i
< 31; ++i
)
1478 if (regno
== i
|| regno
== -1)
1479 regcache
->raw_supply (i
, regs
+ i
* 8);
1481 if (regno
== ALPHA_ZERO_REGNUM
|| regno
== -1)
1483 const gdb_byte zero
[8] = { 0 };
1485 regcache
->raw_supply (ALPHA_ZERO_REGNUM
, zero
);
1488 if (regno
== ALPHA_PC_REGNUM
|| regno
== -1)
1489 regcache
->raw_supply (ALPHA_PC_REGNUM
, pc
);
1491 if (regno
== ALPHA_UNIQUE_REGNUM
|| regno
== -1)
1492 regcache
->raw_supply (ALPHA_UNIQUE_REGNUM
, unique
);
1496 alpha_fill_int_regs (const struct regcache
*regcache
,
1497 int regno
, void *r0_r30
, void *pc
, void *unique
)
1499 gdb_byte
*regs
= (gdb_byte
*) r0_r30
;
1502 for (i
= 0; i
< 31; ++i
)
1503 if (regno
== i
|| regno
== -1)
1504 regcache
->raw_collect (i
, regs
+ i
* 8);
1506 if (regno
== ALPHA_PC_REGNUM
|| regno
== -1)
1507 regcache
->raw_collect (ALPHA_PC_REGNUM
, pc
);
1509 if (unique
&& (regno
== ALPHA_UNIQUE_REGNUM
|| regno
== -1))
1510 regcache
->raw_collect (ALPHA_UNIQUE_REGNUM
, unique
);
1514 alpha_supply_fp_regs (struct regcache
*regcache
, int regno
,
1515 const void *f0_f30
, const void *fpcr
)
1517 const gdb_byte
*regs
= (const gdb_byte
*) f0_f30
;
1520 for (i
= ALPHA_FP0_REGNUM
; i
< ALPHA_FP0_REGNUM
+ 31; ++i
)
1521 if (regno
== i
|| regno
== -1)
1522 regcache
->raw_supply (i
, regs
+ (i
- ALPHA_FP0_REGNUM
) * 8);
1524 if (regno
== ALPHA_FPCR_REGNUM
|| regno
== -1)
1525 regcache
->raw_supply (ALPHA_FPCR_REGNUM
, fpcr
);
1529 alpha_fill_fp_regs (const struct regcache
*regcache
,
1530 int regno
, void *f0_f30
, void *fpcr
)
1532 gdb_byte
*regs
= (gdb_byte
*) f0_f30
;
1535 for (i
= ALPHA_FP0_REGNUM
; i
< ALPHA_FP0_REGNUM
+ 31; ++i
)
1536 if (regno
== i
|| regno
== -1)
1537 regcache
->raw_collect (i
, regs
+ (i
- ALPHA_FP0_REGNUM
) * 8);
1539 if (regno
== ALPHA_FPCR_REGNUM
|| regno
== -1)
1540 regcache
->raw_collect (ALPHA_FPCR_REGNUM
, fpcr
);
1545 /* Return nonzero if the G_floating register value in REG is equal to
1546 zero for FP control instructions. */
1549 fp_register_zero_p (LONGEST reg
)
1551 /* Check that all bits except the sign bit are zero. */
1552 const LONGEST zero_mask
= ((LONGEST
) 1 << 63) ^ -1;
1554 return ((reg
& zero_mask
) == 0);
1557 /* Return the value of the sign bit for the G_floating register
1558 value held in REG. */
1561 fp_register_sign_bit (LONGEST reg
)
1563 const LONGEST sign_mask
= (LONGEST
) 1 << 63;
1565 return ((reg
& sign_mask
) != 0);
1568 /* alpha_software_single_step() is called just before we want to resume
1569 the inferior, if we want to single-step it but there is no hardware
1570 or kernel single-step support (NetBSD on Alpha, for example). We find
1571 the target of the coming instruction and breakpoint it. */
1574 alpha_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1576 struct gdbarch
*gdbarch
= regcache
->arch ();
1583 insn
= alpha_read_insn (gdbarch
, pc
);
1585 /* Opcode is top 6 bits. */
1586 op
= (insn
>> 26) & 0x3f;
1590 /* Jump format: target PC is:
1592 return (regcache_raw_get_unsigned (regcache
, (insn
>> 16) & 0x1f) & ~3);
1595 if ((op
& 0x30) == 0x30)
1597 /* Branch format: target PC is:
1598 (new PC) + (4 * sext(displacement)) */
1599 if (op
== 0x30 /* BR */
1600 || op
== 0x34) /* BSR */
1603 offset
= (insn
& 0x001fffff);
1604 if (offset
& 0x00100000)
1605 offset
|= 0xffe00000;
1606 offset
*= ALPHA_INSN_SIZE
;
1607 return (pc
+ ALPHA_INSN_SIZE
+ offset
);
1610 /* Need to determine if branch is taken; read RA. */
1611 regno
= (insn
>> 21) & 0x1f;
1614 case 0x31: /* FBEQ */
1615 case 0x36: /* FBGE */
1616 case 0x37: /* FBGT */
1617 case 0x33: /* FBLE */
1618 case 0x32: /* FBLT */
1619 case 0x35: /* FBNE */
1620 regno
+= gdbarch_fp0_regnum (gdbarch
);
1623 rav
= regcache_raw_get_signed (regcache
, regno
);
1627 case 0x38: /* BLBC */
1631 case 0x3c: /* BLBS */
1635 case 0x39: /* BEQ */
1639 case 0x3d: /* BNE */
1643 case 0x3a: /* BLT */
1647 case 0x3b: /* BLE */
1651 case 0x3f: /* BGT */
1655 case 0x3e: /* BGE */
1660 /* Floating point branches. */
1662 case 0x31: /* FBEQ */
1663 if (fp_register_zero_p (rav
))
1666 case 0x36: /* FBGE */
1667 if (fp_register_sign_bit (rav
) == 0 || fp_register_zero_p (rav
))
1670 case 0x37: /* FBGT */
1671 if (fp_register_sign_bit (rav
) == 0 && ! fp_register_zero_p (rav
))
1674 case 0x33: /* FBLE */
1675 if (fp_register_sign_bit (rav
) == 1 || fp_register_zero_p (rav
))
1678 case 0x32: /* FBLT */
1679 if (fp_register_sign_bit (rav
) == 1 && ! fp_register_zero_p (rav
))
1682 case 0x35: /* FBNE */
1683 if (! fp_register_zero_p (rav
))
1689 /* Not a branch or branch not taken; target PC is:
1691 return (pc
+ ALPHA_INSN_SIZE
);
1694 std::vector
<CORE_ADDR
>
1695 alpha_software_single_step (struct regcache
*regcache
)
1697 struct gdbarch
*gdbarch
= regcache
->arch ();
1699 CORE_ADDR pc
= regcache_read_pc (regcache
);
1701 std::vector
<CORE_ADDR
> next_pcs
1702 = alpha_deal_with_atomic_sequence (gdbarch
, pc
);
1703 if (!next_pcs
.empty ())
1706 CORE_ADDR next_pc
= alpha_next_pc (regcache
, pc
);
1711 /* Initialize the current architecture based on INFO. If possible, re-use an
1712 architecture from ARCHES, which is a list of architectures already created
1713 during this debugging session.
1715 Called e.g. at program startup, when reading a core file, and when reading
1718 static struct gdbarch
*
1719 alpha_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1721 /* Find a candidate among extant architectures. */
1722 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1724 return arches
->gdbarch
;
1727 = gdbarch_alloc (&info
, gdbarch_tdep_up (new alpha_gdbarch_tdep
));
1728 alpha_gdbarch_tdep
*tdep
= gdbarch_tdep
<alpha_gdbarch_tdep
> (gdbarch
);
1730 /* Lowest text address. This is used by heuristic_proc_start()
1731 to decide when to stop looking. */
1732 tdep
->vm_min_address
= (CORE_ADDR
) 0x120000000LL
;
1734 tdep
->dynamic_sigtramp_offset
= NULL
;
1735 tdep
->sigcontext_addr
= NULL
;
1736 tdep
->sc_pc_offset
= 2 * 8;
1737 tdep
->sc_regs_offset
= 4 * 8;
1738 tdep
->sc_fpregs_offset
= tdep
->sc_regs_offset
+ 32 * 8 + 8;
1740 tdep
->jb_pc
= -1; /* longjmp support not enabled by default. */
1742 tdep
->return_in_memory
= alpha_return_in_memory_always
;
1745 set_gdbarch_short_bit (gdbarch
, 16);
1746 set_gdbarch_int_bit (gdbarch
, 32);
1747 set_gdbarch_long_bit (gdbarch
, 64);
1748 set_gdbarch_long_long_bit (gdbarch
, 64);
1749 set_gdbarch_wchar_bit (gdbarch
, 64);
1750 set_gdbarch_wchar_signed (gdbarch
, 0);
1751 set_gdbarch_float_bit (gdbarch
, 32);
1752 set_gdbarch_double_bit (gdbarch
, 64);
1753 set_gdbarch_long_double_bit (gdbarch
, 64);
1754 set_gdbarch_ptr_bit (gdbarch
, 64);
1757 set_gdbarch_num_regs (gdbarch
, ALPHA_NUM_REGS
);
1758 set_gdbarch_sp_regnum (gdbarch
, ALPHA_SP_REGNUM
);
1759 set_gdbarch_pc_regnum (gdbarch
, ALPHA_PC_REGNUM
);
1760 set_gdbarch_fp0_regnum (gdbarch
, ALPHA_FP0_REGNUM
);
1762 set_gdbarch_register_name (gdbarch
, alpha_register_name
);
1763 set_gdbarch_register_type (gdbarch
, alpha_register_type
);
1765 set_gdbarch_cannot_fetch_register (gdbarch
, alpha_cannot_fetch_register
);
1766 set_gdbarch_cannot_store_register (gdbarch
, alpha_cannot_store_register
);
1768 set_gdbarch_convert_register_p (gdbarch
, alpha_convert_register_p
);
1769 set_gdbarch_register_to_value (gdbarch
, alpha_register_to_value
);
1770 set_gdbarch_value_to_register (gdbarch
, alpha_value_to_register
);
1772 set_gdbarch_register_reggroup_p (gdbarch
, alpha_register_reggroup_p
);
1774 /* Prologue heuristics. */
1775 set_gdbarch_skip_prologue (gdbarch
, alpha_skip_prologue
);
1779 set_gdbarch_return_value (gdbarch
, alpha_return_value
);
1781 /* Settings for calling functions in the inferior. */
1782 set_gdbarch_push_dummy_call (gdbarch
, alpha_push_dummy_call
);
1784 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1785 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
1787 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1788 alpha_breakpoint::kind_from_pc
);
1789 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1790 alpha_breakpoint::bp_from_kind
);
1791 set_gdbarch_decr_pc_after_break (gdbarch
, ALPHA_INSN_SIZE
);
1792 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
1794 /* Handles single stepping of atomic sequences. */
1795 set_gdbarch_software_single_step (gdbarch
, alpha_software_single_step
);
1797 /* Hook in ABI-specific overrides, if they have been registered. */
1798 gdbarch_init_osabi (info
, gdbarch
);
1800 /* Now that we have tuned the configuration, set a few final things
1801 based on what the OS ABI has told us. */
1803 if (tdep
->jb_pc
>= 0)
1804 set_gdbarch_get_longjmp_target (gdbarch
, alpha_get_longjmp_target
);
1806 frame_unwind_append_unwinder (gdbarch
, &alpha_sigtramp_frame_unwind
);
1807 frame_unwind_append_unwinder (gdbarch
, &alpha_heuristic_frame_unwind
);
1809 frame_base_set_default (gdbarch
, &alpha_heuristic_frame_base
);
1815 alpha_dwarf2_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1817 dwarf2_append_unwinders (gdbarch
);
1818 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
1821 void _initialize_alpha_tdep ();
1823 _initialize_alpha_tdep ()
1826 gdbarch_register (bfd_arch_alpha
, alpha_gdbarch_init
, NULL
);
1828 /* Let the user set the fence post for heuristic_proc_start. */
1830 /* We really would like to have both "0" and "unlimited" work, but
1831 command.c doesn't deal with that. So make it a var_zinteger
1832 because the user can always use "999999" or some such for unlimited. */
1833 /* We need to throw away the frame cache when we set this, since it
1834 might change our ability to get backtraces. */
1835 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
1836 &heuristic_fence_post
, _("\
1837 Set the distance searched for the start of a function."), _("\
1838 Show the distance searched for the start of a function."), _("\
1839 If you are debugging a stripped executable, GDB needs to search through the\n\
1840 program for the start of a function. This command sets the distance of the\n\
1841 search. The only need to set it is when debugging a stripped executable."),
1842 reinit_frame_cache_sfunc
,
1843 NULL
, /* FIXME: i18n: The distance searched for
1844 the start of a function is \"%d\". */
1845 &setlist
, &showlist
);