1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2023 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "opcode/i386.h"
26 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "gdbsupport/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "gdbsupport/byte-vector.h"
52 #include "amd64-ravenscar-thread.h"
54 /* Note that the AMD64 architecture was previously known as x86-64.
55 The latter is (forever) engraved into the canonical system name as
56 returned by config.guess, and used as the name for the AMD64 port
57 of GNU/Linux. The BSD's have renamed their ports to amd64; they
58 don't like to shout. For GDB we prefer the amd64_-prefix over the
59 x86_64_-prefix since it's so much easier to type. */
61 /* Register information. */
63 static const char * const amd64_register_names
[] =
65 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
67 /* %r8 is indeed register number 8. */
68 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
69 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
71 /* %st0 is register number 24. */
72 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
75 /* %xmm0 is register number 40. */
76 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
77 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
81 static const char * const amd64_ymm_names
[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
85 "ymm8", "ymm9", "ymm10", "ymm11",
86 "ymm12", "ymm13", "ymm14", "ymm15"
89 static const char * const amd64_ymm_avx512_names
[] =
91 "ymm16", "ymm17", "ymm18", "ymm19",
92 "ymm20", "ymm21", "ymm22", "ymm23",
93 "ymm24", "ymm25", "ymm26", "ymm27",
94 "ymm28", "ymm29", "ymm30", "ymm31"
97 static const char * const amd64_ymmh_names
[] =
99 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
100 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
101 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
102 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
105 static const char * const amd64_ymmh_avx512_names
[] =
107 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
108 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
109 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
110 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
113 static const char * const amd64_mpx_names
[] =
115 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
118 static const char * const amd64_k_names
[] =
120 "k0", "k1", "k2", "k3",
121 "k4", "k5", "k6", "k7"
124 static const char * const amd64_zmmh_names
[] =
126 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
127 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
128 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
129 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
130 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
131 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
132 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
133 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
136 static const char * const amd64_zmm_names
[] =
138 "zmm0", "zmm1", "zmm2", "zmm3",
139 "zmm4", "zmm5", "zmm6", "zmm7",
140 "zmm8", "zmm9", "zmm10", "zmm11",
141 "zmm12", "zmm13", "zmm14", "zmm15",
142 "zmm16", "zmm17", "zmm18", "zmm19",
143 "zmm20", "zmm21", "zmm22", "zmm23",
144 "zmm24", "zmm25", "zmm26", "zmm27",
145 "zmm28", "zmm29", "zmm30", "zmm31"
148 static const char * const amd64_xmm_avx512_names
[] = {
149 "xmm16", "xmm17", "xmm18", "xmm19",
150 "xmm20", "xmm21", "xmm22", "xmm23",
151 "xmm24", "xmm25", "xmm26", "xmm27",
152 "xmm28", "xmm29", "xmm30", "xmm31"
155 static const char * const amd64_pkeys_names
[] = {
159 /* DWARF Register Number Mapping as defined in the System V psABI,
162 static int amd64_dwarf_regmap
[] =
164 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
165 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
166 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
167 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
169 /* Frame Pointer Register RBP. */
172 /* Stack Pointer Register RSP. */
175 /* Extended Integer Registers 8 - 15. */
176 AMD64_R8_REGNUM
, /* %r8 */
177 AMD64_R9_REGNUM
, /* %r9 */
178 AMD64_R10_REGNUM
, /* %r10 */
179 AMD64_R11_REGNUM
, /* %r11 */
180 AMD64_R12_REGNUM
, /* %r12 */
181 AMD64_R13_REGNUM
, /* %r13 */
182 AMD64_R14_REGNUM
, /* %r14 */
183 AMD64_R15_REGNUM
, /* %r15 */
185 /* Return Address RA. Mapped to RIP. */
188 /* SSE Registers 0 - 7. */
189 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
190 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
191 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
192 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
194 /* Extended SSE Registers 8 - 15. */
195 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
196 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
197 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
198 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
200 /* Floating Point Registers 0-7. */
201 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
202 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
203 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
204 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
206 /* MMX Registers 0 - 7.
207 We have to handle those registers specifically, as their register
208 number within GDB depends on the target (or they may even not be
209 available at all). */
210 -1, -1, -1, -1, -1, -1, -1, -1,
212 /* Control and Status Flags Register. */
215 /* Selector Registers. */
225 /* Segment Base Address Registers. */
231 /* Special Selector Registers. */
235 /* Floating Point Control Registers. */
241 static const int amd64_dwarf_regmap_len
=
242 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
244 /* Convert DWARF register number REG to the appropriate register
245 number used by GDB. */
248 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
250 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
251 int ymm0_regnum
= tdep
->ymm0_regnum
;
254 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
255 regnum
= amd64_dwarf_regmap
[reg
];
258 && i386_xmm_regnum_p (gdbarch
, regnum
))
259 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
264 /* Map architectural register numbers to gdb register numbers. */
266 static const int amd64_arch_regmap
[16] =
268 AMD64_RAX_REGNUM
, /* %rax */
269 AMD64_RCX_REGNUM
, /* %rcx */
270 AMD64_RDX_REGNUM
, /* %rdx */
271 AMD64_RBX_REGNUM
, /* %rbx */
272 AMD64_RSP_REGNUM
, /* %rsp */
273 AMD64_RBP_REGNUM
, /* %rbp */
274 AMD64_RSI_REGNUM
, /* %rsi */
275 AMD64_RDI_REGNUM
, /* %rdi */
276 AMD64_R8_REGNUM
, /* %r8 */
277 AMD64_R9_REGNUM
, /* %r9 */
278 AMD64_R10_REGNUM
, /* %r10 */
279 AMD64_R11_REGNUM
, /* %r11 */
280 AMD64_R12_REGNUM
, /* %r12 */
281 AMD64_R13_REGNUM
, /* %r13 */
282 AMD64_R14_REGNUM
, /* %r14 */
283 AMD64_R15_REGNUM
/* %r15 */
286 static const int amd64_arch_regmap_len
=
287 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
289 /* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
293 amd64_arch_reg_to_regnum (int reg
)
295 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
297 return amd64_arch_regmap
[reg
];
300 /* Register names for byte pseudo-registers. */
302 static const char * const amd64_byte_names
[] =
304 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
305 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306 "ah", "bh", "ch", "dh"
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
312 /* Register names for word pseudo-registers. */
314 static const char * const amd64_word_names
[] =
316 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
317 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
320 /* Register names for dword pseudo-registers. */
322 static const char * const amd64_dword_names
[] =
324 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
325 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
329 /* Return the name of register REGNUM. */
332 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
334 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
335 if (i386_byte_regnum_p (gdbarch
, regnum
))
336 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
337 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
338 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
339 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
340 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
341 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
342 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
343 else if (i386_word_regnum_p (gdbarch
, regnum
))
344 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
345 else if (i386_dword_regnum_p (gdbarch
, regnum
))
346 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
348 return i386_pseudo_register_name (gdbarch
, regnum
);
351 static struct value
*
352 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
353 readable_regcache
*regcache
,
356 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
358 value
*result_value
= value::allocate (register_type (gdbarch
, regnum
));
359 result_value
->set_lval (lval_register
);
360 VALUE_REGNUM (result_value
) = regnum
;
361 gdb_byte
*buf
= result_value
->contents_raw ().data ();
363 if (i386_byte_regnum_p (gdbarch
, regnum
))
365 int gpnum
= regnum
- tdep
->al_regnum
;
367 /* Extract (always little endian). */
368 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
370 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
371 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
373 /* Special handling for AH, BH, CH, DH. */
374 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
375 if (status
== REG_VALID
)
376 memcpy (buf
, raw_buf
+ 1, 1);
378 result_value
->mark_bytes_unavailable (0,
379 result_value
->type ()->length ());
383 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
384 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
385 if (status
== REG_VALID
)
386 memcpy (buf
, raw_buf
, 1);
388 result_value
->mark_bytes_unavailable (0,
389 result_value
->type ()->length ());
392 else if (i386_dword_regnum_p (gdbarch
, regnum
))
394 int gpnum
= regnum
- tdep
->eax_regnum
;
395 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
396 /* Extract (always little endian). */
397 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
398 if (status
== REG_VALID
)
399 memcpy (buf
, raw_buf
, 4);
401 result_value
->mark_bytes_unavailable (0,
402 result_value
->type ()->length ());
405 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
412 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
418 if (i386_byte_regnum_p (gdbarch
, regnum
))
420 int gpnum
= regnum
- tdep
->al_regnum
;
422 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
424 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
425 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
427 /* Read ... AH, BH, CH, DH. */
428 regcache
->raw_read (gpnum
, raw_buf
);
429 /* ... Modify ... (always little endian). */
430 memcpy (raw_buf
+ 1, buf
, 1);
432 regcache
->raw_write (gpnum
, raw_buf
);
436 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
439 regcache
->raw_read (gpnum
, raw_buf
);
440 /* ... Modify ... (always little endian). */
441 memcpy (raw_buf
, buf
, 1);
443 regcache
->raw_write (gpnum
, raw_buf
);
446 else if (i386_dword_regnum_p (gdbarch
, regnum
))
448 int gpnum
= regnum
- tdep
->eax_regnum
;
449 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
452 regcache
->raw_read (gpnum
, raw_buf
);
453 /* ... Modify ... (always little endian). */
454 memcpy (raw_buf
, buf
, 4);
456 regcache
->raw_write (gpnum
, raw_buf
);
459 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
462 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
465 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
466 struct agent_expr
*ax
, int regnum
)
468 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
470 if (i386_byte_regnum_p (gdbarch
, regnum
))
472 int gpnum
= regnum
- tdep
->al_regnum
;
474 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
475 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
477 ax_reg_mask (ax
, gpnum
);
480 else if (i386_dword_regnum_p (gdbarch
, regnum
))
482 int gpnum
= regnum
- tdep
->eax_regnum
;
484 ax_reg_mask (ax
, gpnum
);
488 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
493 /* Register classes as defined in the psABI. */
507 /* Return the union class of CLASS1 and CLASS2. See the psABI for
510 static enum amd64_reg_class
511 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
513 /* Rule (a): If both classes are equal, this is the resulting class. */
514 if (class1
== class2
)
517 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
518 is the other class. */
519 if (class1
== AMD64_NO_CLASS
)
521 if (class2
== AMD64_NO_CLASS
)
524 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
525 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
528 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
529 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
530 return AMD64_INTEGER
;
532 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
533 MEMORY is used as class. */
534 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
535 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
536 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
539 /* Rule (f): Otherwise class SSE is used. */
543 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
545 /* Return true if TYPE is a structure or union with unaligned fields. */
548 amd64_has_unaligned_fields (struct type
*type
)
550 if (type
->code () == TYPE_CODE_STRUCT
551 || type
->code () == TYPE_CODE_UNION
)
553 for (int i
= 0; i
< type
->num_fields (); i
++)
555 struct type
*subtype
= check_typedef (type
->field (i
).type ());
557 /* Ignore static fields, empty fields (for example nested
558 empty structures), and bitfields (these are handled by
560 if (field_is_static (&type
->field (i
))
561 || (TYPE_FIELD_BITSIZE (type
, i
) == 0
562 && subtype
->length () == 0)
563 || TYPE_FIELD_PACKED (type
, i
))
566 int bitpos
= type
->field (i
).loc_bitpos ();
571 int align
= type_align (subtype
);
573 error (_("could not determine alignment of type"));
575 int bytepos
= bitpos
/ 8;
576 if (bytepos
% align
!= 0)
579 if (amd64_has_unaligned_fields (subtype
))
587 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
588 structures and union types, and store the result in THECLASS. */
591 amd64_classify_aggregate_field (struct type
*type
, int i
,
592 enum amd64_reg_class theclass
[2],
593 unsigned int bitoffset
)
595 struct type
*subtype
= check_typedef (type
->field (i
).type ());
596 enum amd64_reg_class subclass
[2];
597 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
600 bitsize
= subtype
->length () * 8;
602 /* Ignore static fields, or empty fields, for example nested
604 if (field_is_static (&type
->field (i
)) || bitsize
== 0)
607 int bitpos
= bitoffset
+ type
->field (i
).loc_bitpos ();
608 int pos
= bitpos
/ 64;
609 int endpos
= (bitpos
+ bitsize
- 1) / 64;
611 if (subtype
->code () == TYPE_CODE_STRUCT
612 || subtype
->code () == TYPE_CODE_UNION
)
614 /* Each field of an object is classified recursively. */
616 for (j
= 0; j
< subtype
->num_fields (); j
++)
617 amd64_classify_aggregate_field (subtype
, j
, theclass
, bitpos
);
621 gdb_assert (pos
== 0 || pos
== 1);
623 amd64_classify (subtype
, subclass
);
624 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
625 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
626 /* This is a bit of an odd case: We have a field that would
627 normally fit in one of the two eightbytes, except that
628 it is placed in a way that this field straddles them.
629 This has been seen with a structure containing an array.
631 The ABI is a bit unclear in this case, but we assume that
632 this field's class (stored in subclass[0]) must also be merged
633 into class[1]. In other words, our field has a piece stored
634 in the second eight-byte, and thus its class applies to
635 the second eight-byte as well.
637 In the case where the field length exceeds 8 bytes,
638 it should not be necessary to merge the field class
639 into class[1]. As LEN > 8, subclass[1] is necessarily
640 different from AMD64_NO_CLASS. If subclass[1] is equal
641 to subclass[0], then the normal class[1]/subclass[1]
642 merging will take care of everything. For subclass[1]
643 to be different from subclass[0], I can only see the case
644 where we have a SSE/SSEUP or X87/X87UP pair, which both
645 use up all 16 bytes of the aggregate, and are already
646 handled just fine (because each portion sits on its own
648 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
650 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
653 /* Classify TYPE according to the rules for aggregate (structures and
654 arrays) and union types, and store the result in CLASS. */
657 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
659 /* 1. If the size of an object is larger than two times eight bytes, or
660 it is a non-trivial C++ object, or it has unaligned fields, then it
663 It is important that the trivially_copyable check is before the
664 unaligned fields check, as C++ classes with virtual base classes
665 will have fields (for the virtual base classes) with non-constant
666 loc_bitpos attributes, which will cause an assert to trigger within
667 the unaligned field check. As classes with virtual bases are not
668 trivially copyable, checking that first avoids this problem. */
669 if (TYPE_HAS_DYNAMIC_LENGTH (type
)
670 || type
->length () > 16
671 || !language_pass_by_reference (type
).trivially_copyable
672 || amd64_has_unaligned_fields (type
))
674 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
678 /* 2. Both eightbytes get initialized to class NO_CLASS. */
679 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
681 /* 3. Each field of an object is classified recursively so that
682 always two fields are considered. The resulting class is
683 calculated according to the classes of the fields in the
686 if (type
->code () == TYPE_CODE_ARRAY
)
688 struct type
*subtype
= check_typedef (type
->target_type ());
690 /* All fields in an array have the same type. */
691 amd64_classify (subtype
, theclass
);
692 if (type
->length () > 8 && theclass
[1] == AMD64_NO_CLASS
)
693 theclass
[1] = theclass
[0];
699 /* Structure or union. */
700 gdb_assert (type
->code () == TYPE_CODE_STRUCT
701 || type
->code () == TYPE_CODE_UNION
);
703 for (i
= 0; i
< type
->num_fields (); i
++)
704 amd64_classify_aggregate_field (type
, i
, theclass
, 0);
707 /* 4. Then a post merger cleanup is done: */
709 /* Rule (a): If one of the classes is MEMORY, the whole argument is
711 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
712 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
714 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
716 if (theclass
[0] == AMD64_SSEUP
)
717 theclass
[0] = AMD64_SSE
;
718 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
719 theclass
[1] = AMD64_SSE
;
722 /* Classify TYPE, and store the result in CLASS. */
725 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
727 enum type_code code
= type
->code ();
728 int len
= type
->length ();
730 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
732 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
733 long, long long, and pointers are in the INTEGER class. Similarly,
734 range types, used by languages such as Ada, are also in the INTEGER
736 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
737 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
738 || code
== TYPE_CODE_CHAR
739 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
740 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
741 theclass
[0] = AMD64_INTEGER
;
743 /* Arguments of types _Float16, float, double, _Decimal32, _Decimal64 and
744 __m64 are in class SSE. */
745 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
746 && (len
== 2 || len
== 4 || len
== 8))
748 theclass
[0] = AMD64_SSE
;
750 /* Arguments of types __float128, _Decimal128 and __m128 are split into
751 two halves. The least significant ones belong to class SSE, the most
752 significant one to class SSEUP. */
753 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
754 /* FIXME: __float128, __m128. */
755 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
757 /* The 64-bit mantissa of arguments of type long double belongs to
758 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
760 else if (code
== TYPE_CODE_FLT
&& len
== 16)
761 /* Class X87 and X87UP. */
762 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
764 /* Arguments of complex T - where T is one of the types _Float16, float or
765 double - get treated as if they are implemented as:
773 else if (code
== TYPE_CODE_COMPLEX
&& (len
== 8 || len
== 4))
774 theclass
[0] = AMD64_SSE
;
775 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
776 theclass
[0] = theclass
[1] = AMD64_SSE
;
778 /* A variable of type complex long double is classified as type
780 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
781 theclass
[0] = AMD64_COMPLEX_X87
;
784 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
785 || code
== TYPE_CODE_UNION
)
786 amd64_classify_aggregate (type
, theclass
);
789 static enum return_value_convention
790 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
791 struct type
*type
, struct regcache
*regcache
,
792 struct value
**read_value
, const gdb_byte
*writebuf
)
794 enum amd64_reg_class theclass
[2];
795 int len
= type
->length ();
796 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
797 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
802 gdb_assert (!(read_value
&& writebuf
));
804 /* 1. Classify the return type with the classification algorithm. */
805 amd64_classify (type
, theclass
);
807 /* 2. If the type has class MEMORY, then the caller provides space
808 for the return value and passes the address of this storage in
809 %rdi as if it were the first argument to the function. In effect,
810 this address becomes a hidden first argument.
812 On return %rax will contain the address that has been passed in
813 by the caller in %rdi. */
814 if (theclass
[0] == AMD64_MEMORY
)
816 /* As indicated by the comment above, the ABI guarantees that we
817 can always find the return value just after the function has
820 if (read_value
!= nullptr)
824 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
825 *read_value
= value_at_non_lval (type
, addr
);
828 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
831 gdb_byte
*readbuf
= nullptr;
832 if (read_value
!= nullptr)
834 *read_value
= value::allocate (type
);
835 readbuf
= (*read_value
)->contents_raw ().data ();
838 /* 8. If the class is COMPLEX_X87, the real part of the value is
839 returned in %st0 and the imaginary part in %st1. */
840 if (theclass
[0] == AMD64_COMPLEX_X87
)
844 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
845 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
850 i387_return_value (gdbarch
, regcache
);
851 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
852 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
854 /* Fix up the tag word such that both %st(0) and %st(1) are
856 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
859 return RETURN_VALUE_REGISTER_CONVENTION
;
862 gdb_assert (theclass
[1] != AMD64_MEMORY
);
863 gdb_assert (len
<= 16);
865 for (i
= 0; len
> 0; i
++, len
-= 8)
873 /* 3. If the class is INTEGER, the next available register
874 of the sequence %rax, %rdx is used. */
875 regnum
= integer_regnum
[integer_reg
++];
879 /* 4. If the class is SSE, the next available SSE register
880 of the sequence %xmm0, %xmm1 is used. */
881 regnum
= sse_regnum
[sse_reg
++];
885 /* 5. If the class is SSEUP, the eightbyte is passed in the
886 upper half of the last used SSE register. */
887 gdb_assert (sse_reg
> 0);
888 regnum
= sse_regnum
[sse_reg
- 1];
893 /* 6. If the class is X87, the value is returned on the X87
894 stack in %st0 as 80-bit x87 number. */
895 regnum
= AMD64_ST0_REGNUM
;
897 i387_return_value (gdbarch
, regcache
);
901 /* 7. If the class is X87UP, the value is returned together
902 with the previous X87 value in %st0. */
903 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
904 regnum
= AMD64_ST0_REGNUM
;
913 gdb_assert (!"Unexpected register class.");
916 gdb_assert (regnum
!= -1);
919 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
922 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
926 return RETURN_VALUE_REGISTER_CONVENTION
;
931 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
932 CORE_ADDR sp
, function_call_return_method return_method
)
934 static int integer_regnum
[] =
936 AMD64_RDI_REGNUM
, /* %rdi */
937 AMD64_RSI_REGNUM
, /* %rsi */
938 AMD64_RDX_REGNUM
, /* %rdx */
939 AMD64_RCX_REGNUM
, /* %rcx */
940 AMD64_R8_REGNUM
, /* %r8 */
941 AMD64_R9_REGNUM
/* %r9 */
943 static int sse_regnum
[] =
945 /* %xmm0 ... %xmm7 */
946 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
947 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
948 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
949 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
951 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
952 int num_stack_args
= 0;
953 int num_elements
= 0;
959 /* Reserve a register for the "hidden" argument. */
960 if (return_method
== return_method_struct
)
963 for (i
= 0; i
< nargs
; i
++)
965 struct type
*type
= args
[i
]->type ();
966 int len
= type
->length ();
967 enum amd64_reg_class theclass
[2];
968 int needed_integer_regs
= 0;
969 int needed_sse_regs
= 0;
972 /* Classify argument. */
973 amd64_classify (type
, theclass
);
975 /* Calculate the number of integer and SSE registers needed for
977 for (j
= 0; j
< 2; j
++)
979 if (theclass
[j
] == AMD64_INTEGER
)
980 needed_integer_regs
++;
981 else if (theclass
[j
] == AMD64_SSE
)
985 /* Check whether enough registers are available, and if the
986 argument should be passed in registers at all. */
987 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
988 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
989 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
991 /* The argument will be passed on the stack. */
992 num_elements
+= ((len
+ 7) / 8);
993 stack_args
[num_stack_args
++] = args
[i
];
997 /* The argument will be passed in registers. */
998 const gdb_byte
*valbuf
= args
[i
]->contents ().data ();
1001 gdb_assert (len
<= 16);
1003 for (j
= 0; len
> 0; j
++, len
-= 8)
1008 switch (theclass
[j
])
1011 regnum
= integer_regnum
[integer_reg
++];
1015 regnum
= sse_regnum
[sse_reg
++];
1019 gdb_assert (sse_reg
> 0);
1020 regnum
= sse_regnum
[sse_reg
- 1];
1024 case AMD64_NO_CLASS
:
1028 gdb_assert (!"Unexpected register class.");
1031 gdb_assert (regnum
!= -1);
1032 memset (buf
, 0, sizeof buf
);
1033 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
1034 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
1039 /* Allocate space for the arguments on the stack. */
1040 sp
-= num_elements
* 8;
1042 /* The psABI says that "The end of the input argument area shall be
1043 aligned on a 16 byte boundary." */
1046 /* Write out the arguments to the stack. */
1047 for (i
= 0; i
< num_stack_args
; i
++)
1049 struct type
*type
= stack_args
[i
]->type ();
1050 const gdb_byte
*valbuf
= stack_args
[i
]->contents ().data ();
1051 int len
= type
->length ();
1053 write_memory (sp
+ element
* 8, valbuf
, len
);
1054 element
+= ((len
+ 7) / 8);
1057 /* The psABI says that "For calls that may call functions that use
1058 varargs or stdargs (prototype-less calls or calls to functions
1059 containing ellipsis (...) in the declaration) %al is used as
1060 hidden argument to specify the number of SSE registers used. */
1061 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
1066 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1067 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1068 int nargs
, struct value
**args
, CORE_ADDR sp
,
1069 function_call_return_method return_method
,
1070 CORE_ADDR struct_addr
)
1072 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1075 /* BND registers can be in arbitrary values at the moment of the
1076 inferior call. This can cause boundary violations that are not
1077 due to a real bug or even desired by the user. The best to be done
1078 is set the BND registers to allow access to the whole memory, INIT
1079 state, before pushing the inferior call. */
1080 i387_reset_bnd_regs (gdbarch
, regcache
);
1082 /* Pass arguments. */
1083 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1085 /* Pass "hidden" argument". */
1086 if (return_method
== return_method_struct
)
1088 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1089 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1092 /* Store return address. */
1094 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1095 write_memory (sp
, buf
, 8);
1097 /* Finally, update the stack pointer... */
1098 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1099 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1101 /* ...and fake a frame pointer. */
1102 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1107 /* Displaced instruction handling. */
1109 /* A partially decoded instruction.
1110 This contains enough details for displaced stepping purposes. */
1114 /* The number of opcode bytes. */
1116 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1118 int enc_prefix_offset
;
1119 /* The offset to the first opcode byte. */
1121 /* The offset to the modrm byte or -1 if not present. */
1124 /* The raw instruction. */
1128 struct amd64_displaced_step_copy_insn_closure
1129 : public displaced_step_copy_insn_closure
1131 amd64_displaced_step_copy_insn_closure (int insn_buf_len
)
1132 : insn_buf (insn_buf_len
, 0)
1135 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1140 /* Details of the instruction. */
1141 struct amd64_insn insn_details
;
1143 /* The possibly modified insn. */
1144 gdb::byte_vector insn_buf
;
1147 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1148 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1149 at which point delete these in favor of libopcodes' versions). */
1151 static const unsigned char onebyte_has_modrm
[256] = {
1152 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1153 /* ------------------------------- */
1154 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1155 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1156 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1157 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1158 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1159 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1160 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1161 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1162 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1163 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1164 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1165 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1166 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1167 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1168 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1169 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1170 /* ------------------------------- */
1171 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1174 static const unsigned char twobyte_has_modrm
[256] = {
1175 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1176 /* ------------------------------- */
1177 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1178 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1179 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1180 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1181 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1182 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1183 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1184 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1185 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1186 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1187 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1188 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1189 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1190 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1191 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1192 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1193 /* ------------------------------- */
1194 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1197 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1200 rex_prefix_p (gdb_byte pfx
)
1202 return REX_PREFIX_P (pfx
);
1205 /* True if PFX is the start of the 2-byte VEX prefix. */
1208 vex2_prefix_p (gdb_byte pfx
)
1213 /* True if PFX is the start of the 3-byte VEX prefix. */
1216 vex3_prefix_p (gdb_byte pfx
)
1221 /* Skip the legacy instruction prefixes in INSN.
1222 We assume INSN is properly sentineled so we don't have to worry
1223 about falling off the end of the buffer. */
1226 amd64_skip_prefixes (gdb_byte
*insn
)
1232 case DATA_PREFIX_OPCODE
:
1233 case ADDR_PREFIX_OPCODE
:
1234 case CS_PREFIX_OPCODE
:
1235 case DS_PREFIX_OPCODE
:
1236 case ES_PREFIX_OPCODE
:
1237 case FS_PREFIX_OPCODE
:
1238 case GS_PREFIX_OPCODE
:
1239 case SS_PREFIX_OPCODE
:
1240 case LOCK_PREFIX_OPCODE
:
1241 case REPE_PREFIX_OPCODE
:
1242 case REPNE_PREFIX_OPCODE
:
1254 /* Return an integer register (other than RSP) that is unused as an input
1256 In order to not require adding a rex prefix if the insn doesn't already
1257 have one, the result is restricted to RAX ... RDI, sans RSP.
1258 The register numbering of the result follows architecture ordering,
1262 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1264 /* 1 bit for each reg */
1265 int used_regs_mask
= 0;
1267 /* There can be at most 3 int regs used as inputs in an insn, and we have
1268 7 to choose from (RAX ... RDI, sans RSP).
1269 This allows us to take a conservative approach and keep things simple.
1270 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1271 that implicitly specify RAX. */
1274 used_regs_mask
|= 1 << EAX_REG_NUM
;
1275 /* Similarily avoid RDX, implicit operand in divides. */
1276 used_regs_mask
|= 1 << EDX_REG_NUM
;
1278 used_regs_mask
|= 1 << ESP_REG_NUM
;
1280 /* If the opcode is one byte long and there's no ModRM byte,
1281 assume the opcode specifies a register. */
1282 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1283 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1285 /* Mark used regs in the modrm/sib bytes. */
1286 if (details
->modrm_offset
!= -1)
1288 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1289 int mod
= MODRM_MOD_FIELD (modrm
);
1290 int reg
= MODRM_REG_FIELD (modrm
);
1291 int rm
= MODRM_RM_FIELD (modrm
);
1292 int have_sib
= mod
!= 3 && rm
== 4;
1294 /* Assume the reg field of the modrm byte specifies a register. */
1295 used_regs_mask
|= 1 << reg
;
1299 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1300 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1301 used_regs_mask
|= 1 << base
;
1302 used_regs_mask
|= 1 << idx
;
1306 used_regs_mask
|= 1 << rm
;
1310 gdb_assert (used_regs_mask
< 256);
1311 gdb_assert (used_regs_mask
!= 255);
1313 /* Finally, find a free reg. */
1317 for (i
= 0; i
< 8; ++i
)
1319 if (! (used_regs_mask
& (1 << i
)))
1323 /* We shouldn't get here. */
1324 internal_error (_("unable to find free reg"));
1328 /* Extract the details of INSN that we need. */
1331 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1333 gdb_byte
*start
= insn
;
1336 details
->raw_insn
= insn
;
1338 details
->opcode_len
= -1;
1339 details
->enc_prefix_offset
= -1;
1340 details
->opcode_offset
= -1;
1341 details
->modrm_offset
= -1;
1343 /* Skip legacy instruction prefixes. */
1344 insn
= amd64_skip_prefixes (insn
);
1346 /* Skip REX/VEX instruction encoding prefixes. */
1347 if (rex_prefix_p (*insn
))
1349 details
->enc_prefix_offset
= insn
- start
;
1352 else if (vex2_prefix_p (*insn
))
1354 /* Don't record the offset in this case because this prefix has
1355 no REX.B equivalent. */
1358 else if (vex3_prefix_p (*insn
))
1360 details
->enc_prefix_offset
= insn
- start
;
1364 details
->opcode_offset
= insn
- start
;
1366 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1368 /* Two or three-byte opcode. */
1370 need_modrm
= twobyte_has_modrm
[*insn
];
1372 /* Check for three-byte opcode. */
1382 details
->opcode_len
= 3;
1385 details
->opcode_len
= 2;
1391 /* One-byte opcode. */
1392 need_modrm
= onebyte_has_modrm
[*insn
];
1393 details
->opcode_len
= 1;
1399 details
->modrm_offset
= insn
- start
;
1403 /* Update %rip-relative addressing in INSN.
1405 %rip-relative addressing only uses a 32-bit displacement.
1406 32 bits is not enough to be guaranteed to cover the distance between where
1407 the real instruction is and where its copy is.
1408 Convert the insn to use base+disp addressing.
1409 We set base = pc + insn_length so we can leave disp unchanged. */
1412 fixup_riprel (struct gdbarch
*gdbarch
,
1413 amd64_displaced_step_copy_insn_closure
*dsc
,
1414 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1416 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1417 int modrm_offset
= insn_details
->modrm_offset
;
1420 int arch_tmp_regno
, tmp_regno
;
1421 ULONGEST orig_value
;
1423 /* Compute the rip-relative address. */
1424 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1425 dsc
->insn_buf
.size (), from
);
1426 rip_base
= from
+ insn_length
;
1428 /* We need a register to hold the address.
1429 Pick one not used in the insn.
1430 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1431 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1432 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1434 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1435 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1437 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1438 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1440 if (insn_details
->enc_prefix_offset
!= -1)
1442 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1443 if (rex_prefix_p (pfx
[0]))
1445 else if (vex3_prefix_p (pfx
[0]))
1446 pfx
[1] |= VEX3_NOT_B
;
1448 gdb_assert_not_reached ("unhandled prefix");
1451 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1452 dsc
->tmp_regno
= tmp_regno
;
1453 dsc
->tmp_save
= orig_value
;
1456 /* Convert the ModRM field to be base+disp. */
1457 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1458 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1460 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1462 displaced_debug_printf ("%%rip-relative addressing used.");
1463 displaced_debug_printf ("using temp reg %d, old value %s, new value %s",
1464 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1465 paddress (gdbarch
, rip_base
));
1469 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1470 amd64_displaced_step_copy_insn_closure
*dsc
,
1471 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1473 const struct amd64_insn
*details
= &dsc
->insn_details
;
1475 if (details
->modrm_offset
!= -1)
1477 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1479 if ((modrm
& 0xc7) == 0x05)
1481 /* The insn uses rip-relative addressing.
1483 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1488 displaced_step_copy_insn_closure_up
1489 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1490 CORE_ADDR from
, CORE_ADDR to
,
1491 struct regcache
*regs
)
1493 int len
= gdbarch_max_insn_length (gdbarch
);
1494 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1495 continually watch for running off the end of the buffer. */
1496 int fixup_sentinel_space
= len
;
1497 std::unique_ptr
<amd64_displaced_step_copy_insn_closure
> dsc
1498 (new amd64_displaced_step_copy_insn_closure (len
+ fixup_sentinel_space
));
1499 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1500 struct amd64_insn
*details
= &dsc
->insn_details
;
1502 read_memory (from
, buf
, len
);
1504 /* Set up the sentinel space so we don't have to worry about running
1505 off the end of the buffer. An excessive number of leading prefixes
1506 could otherwise cause this. */
1507 memset (buf
+ len
, 0, fixup_sentinel_space
);
1509 amd64_get_insn_details (buf
, details
);
1511 /* GDB may get control back after the insn after the syscall.
1512 Presumably this is a kernel bug.
1513 If this is a syscall, make sure there's a nop afterwards. */
1517 if (amd64_syscall_p (details
, &syscall_length
))
1518 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1521 /* Modify the insn to cope with the address where it will be executed from.
1522 In particular, handle any rip-relative addressing. */
1523 fixup_displaced_copy (gdbarch
, dsc
.get (), from
, to
, regs
);
1525 write_memory (to
, buf
, len
);
1527 displaced_debug_printf ("copy %s->%s: %s",
1528 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1529 displaced_step_dump_bytes (buf
, len
).c_str ());
1531 /* This is a work around for a problem with g++ 4.8. */
1532 return displaced_step_copy_insn_closure_up (dsc
.release ());
1536 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1538 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1540 if (insn
[0] == 0xff)
1542 /* jump near, absolute indirect (/4) */
1543 if ((insn
[1] & 0x38) == 0x20)
1546 /* jump far, absolute indirect (/5) */
1547 if ((insn
[1] & 0x38) == 0x28)
1554 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1557 amd64_jmp_p (const struct amd64_insn
*details
)
1559 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1561 /* jump short, relative. */
1562 if (insn
[0] == 0xeb)
1565 /* jump near, relative. */
1566 if (insn
[0] == 0xe9)
1569 return amd64_absolute_jmp_p (details
);
1573 amd64_absolute_call_p (const struct amd64_insn
*details
)
1575 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1577 if (insn
[0] == 0xff)
1579 /* Call near, absolute indirect (/2) */
1580 if ((insn
[1] & 0x38) == 0x10)
1583 /* Call far, absolute indirect (/3) */
1584 if ((insn
[1] & 0x38) == 0x18)
1592 amd64_ret_p (const struct amd64_insn
*details
)
1594 /* NOTE: gcc can emit "repz ; ret". */
1595 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1599 case 0xc2: /* ret near, pop N bytes */
1600 case 0xc3: /* ret near */
1601 case 0xca: /* ret far, pop N bytes */
1602 case 0xcb: /* ret far */
1603 case 0xcf: /* iret */
1612 amd64_call_p (const struct amd64_insn
*details
)
1614 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1616 if (amd64_absolute_call_p (details
))
1619 /* call near, relative */
1620 if (insn
[0] == 0xe8)
1626 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1627 length in bytes. Otherwise, return zero. */
1630 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1632 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1634 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1643 /* Classify the instruction at ADDR using PRED.
1644 Throw an error if the memory can't be read. */
1647 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1648 int (*pred
) (const struct amd64_insn
*))
1650 struct amd64_insn details
;
1652 int len
, classification
;
1654 len
= gdbarch_max_insn_length (gdbarch
);
1655 buf
= (gdb_byte
*) alloca (len
);
1657 read_code (addr
, buf
, len
);
1658 amd64_get_insn_details (buf
, &details
);
1660 classification
= pred (&details
);
1662 return classification
;
1665 /* The gdbarch insn_is_call method. */
1668 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1670 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1673 /* The gdbarch insn_is_ret method. */
1676 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1678 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1681 /* The gdbarch insn_is_jump method. */
1684 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1686 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1689 /* Fix up the state of registers and memory after having single-stepped
1690 a displaced instruction. */
1693 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1694 struct displaced_step_copy_insn_closure
*dsc_
,
1695 CORE_ADDR from
, CORE_ADDR to
,
1696 struct regcache
*regs
)
1698 amd64_displaced_step_copy_insn_closure
*dsc
1699 = (amd64_displaced_step_copy_insn_closure
*) dsc_
;
1700 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1701 /* The offset we applied to the instruction's address. */
1702 ULONGEST insn_offset
= to
- from
;
1703 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1704 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1706 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
1707 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1710 /* If we used a tmp reg, restore it. */
1714 displaced_debug_printf ("restoring reg %d to %s",
1715 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1716 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1719 /* The list of issues to contend with here is taken from
1720 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1721 Yay for Free Software! */
1723 /* Relocate the %rip back to the program's instruction stream,
1726 /* Except in the case of absolute or indirect jump or call
1727 instructions, or a return instruction, the new rip is relative to
1728 the displaced instruction; make it relative to the original insn.
1729 Well, signal handler returns don't need relocation either, but we use the
1730 value of %rip to recognize those; see below. */
1731 if (! amd64_absolute_jmp_p (insn_details
)
1732 && ! amd64_absolute_call_p (insn_details
)
1733 && ! amd64_ret_p (insn_details
))
1738 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1740 /* A signal trampoline system call changes the %rip, resuming
1741 execution of the main program after the signal handler has
1742 returned. That makes them like 'return' instructions; we
1743 shouldn't relocate %rip.
1745 But most system calls don't, and we do need to relocate %rip.
1747 Our heuristic for distinguishing these cases: if stepping
1748 over the system call instruction left control directly after
1749 the instruction, the we relocate --- control almost certainly
1750 doesn't belong in the displaced copy. Otherwise, we assume
1751 the instruction has put control where it belongs, and leave
1752 it unrelocated. Goodness help us if there are PC-relative
1754 if (amd64_syscall_p (insn_details
, &insn_len
)
1755 && orig_rip
!= to
+ insn_len
1756 /* GDB can get control back after the insn after the syscall.
1757 Presumably this is a kernel bug.
1758 Fixup ensures its a nop, we add one to the length for it. */
1759 && orig_rip
!= to
+ insn_len
+ 1)
1760 displaced_debug_printf ("syscall changed %%rip; not relocating");
1763 ULONGEST rip
= orig_rip
- insn_offset
;
1765 /* If we just stepped over a breakpoint insn, we don't backup
1766 the pc on purpose; this is to match behaviour without
1769 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1771 displaced_debug_printf ("relocated %%rip from %s to %s",
1772 paddress (gdbarch
, orig_rip
),
1773 paddress (gdbarch
, rip
));
1777 /* If the instruction was PUSHFL, then the TF bit will be set in the
1778 pushed value, and should be cleared. We'll leave this for later,
1779 since GDB already messes up the TF flag when stepping over a
1782 /* If the instruction was a call, the return address now atop the
1783 stack is the address following the copied instruction. We need
1784 to make it the address following the original instruction. */
1785 if (amd64_call_p (insn_details
))
1789 const ULONGEST retaddr_len
= 8;
1791 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1792 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1793 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1794 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1796 displaced_debug_printf ("relocated return addr at %s to %s",
1797 paddress (gdbarch
, rsp
),
1798 paddress (gdbarch
, retaddr
));
1802 /* If the instruction INSN uses RIP-relative addressing, return the
1803 offset into the raw INSN where the displacement to be adjusted is
1804 found. Returns 0 if the instruction doesn't use RIP-relative
1808 rip_relative_offset (struct amd64_insn
*insn
)
1810 if (insn
->modrm_offset
!= -1)
1812 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1814 if ((modrm
& 0xc7) == 0x05)
1816 /* The displacement is found right after the ModRM byte. */
1817 return insn
->modrm_offset
+ 1;
1825 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1827 target_write_memory (*to
, buf
, len
);
1832 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1833 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1835 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1836 int len
= gdbarch_max_insn_length (gdbarch
);
1837 /* Extra space for sentinels. */
1838 int fixup_sentinel_space
= len
;
1839 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1840 struct amd64_insn insn_details
;
1842 LONGEST rel32
, newrel
;
1846 read_memory (oldloc
, buf
, len
);
1848 /* Set up the sentinel space so we don't have to worry about running
1849 off the end of the buffer. An excessive number of leading prefixes
1850 could otherwise cause this. */
1851 memset (buf
+ len
, 0, fixup_sentinel_space
);
1854 amd64_get_insn_details (insn
, &insn_details
);
1856 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1858 /* Skip legacy instruction prefixes. */
1859 insn
= amd64_skip_prefixes (insn
);
1861 /* Adjust calls with 32-bit relative addresses as push/jump, with
1862 the address pushed being the location where the original call in
1863 the user program would return to. */
1864 if (insn
[0] == 0xe8)
1866 gdb_byte push_buf
[32];
1870 /* Where "ret" in the original code will return to. */
1871 ret_addr
= oldloc
+ insn_length
;
1873 /* If pushing an address higher than or equal to 0x80000000,
1874 avoid 'pushq', as that sign extends its 32-bit operand, which
1875 would be incorrect. */
1876 if (ret_addr
<= 0x7fffffff)
1878 push_buf
[0] = 0x68; /* pushq $... */
1879 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1884 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1885 push_buf
[i
++] = 0x83;
1886 push_buf
[i
++] = 0xec;
1887 push_buf
[i
++] = 0x08;
1889 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1890 push_buf
[i
++] = 0x04;
1891 push_buf
[i
++] = 0x24;
1892 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1893 ret_addr
& 0xffffffff);
1896 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1897 push_buf
[i
++] = 0x44;
1898 push_buf
[i
++] = 0x24;
1899 push_buf
[i
++] = 0x04;
1900 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1904 gdb_assert (i
<= sizeof (push_buf
));
1905 /* Push the push. */
1906 append_insns (to
, i
, push_buf
);
1908 /* Convert the relative call to a relative jump. */
1911 /* Adjust the destination offset. */
1912 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1913 newrel
= (oldloc
- *to
) + rel32
;
1914 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1916 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1917 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1918 hex_string (newrel
), paddress (gdbarch
, *to
));
1920 /* Write the adjusted jump into its displaced location. */
1921 append_insns (to
, 5, insn
);
1925 offset
= rip_relative_offset (&insn_details
);
1928 /* Adjust jumps with 32-bit relative addresses. Calls are
1929 already handled above. */
1930 if (insn
[0] == 0xe9)
1932 /* Adjust conditional jumps. */
1933 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1939 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1940 newrel
= (oldloc
- *to
) + rel32
;
1941 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1942 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1943 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1944 hex_string (newrel
), paddress (gdbarch
, *to
));
1947 /* Write the adjusted instruction into its displaced location. */
1948 append_insns (to
, insn_length
, buf
);
1952 /* The maximum number of saved registers. This should include %rip. */
1953 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1955 struct amd64_frame_cache
1960 CORE_ADDR sp_offset
;
1963 /* Saved registers. */
1964 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1968 /* Do we have a frame? */
1972 /* Initialize a frame cache. */
1975 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1982 cache
->sp_offset
= -8;
1985 /* Saved registers. We initialize these to -1 since zero is a valid
1986 offset (that's where %rbp is supposed to be stored).
1987 The values start out as being offsets, and are later converted to
1988 addresses (at which point -1 is interpreted as an address, still meaning
1990 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1991 cache
->saved_regs
[i
] = -1;
1992 cache
->saved_sp
= 0;
1993 cache
->saved_sp_reg
= -1;
1995 /* Frameless until proven otherwise. */
1996 cache
->frameless_p
= 1;
1999 /* Allocate and initialize a frame cache. */
2001 static struct amd64_frame_cache
*
2002 amd64_alloc_frame_cache (void)
2004 struct amd64_frame_cache
*cache
;
2006 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
2007 amd64_init_frame_cache (cache
);
2011 /* GCC 4.4 and later, can put code in the prologue to realign the
2012 stack pointer. Check whether PC points to such code, and update
2013 CACHE accordingly. Return the first instruction after the code
2014 sequence or CURRENT_PC, whichever is smaller. If we don't
2015 recognize the code, return PC. */
2018 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2019 struct amd64_frame_cache
*cache
)
2021 /* There are 2 code sequences to re-align stack before the frame
2024 1. Use a caller-saved saved register:
2030 2. Use a callee-saved saved register:
2037 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2039 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2040 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2045 int offset
, offset_and
;
2047 if (target_read_code (pc
, buf
, sizeof buf
))
2050 /* Check caller-saved saved register. The first instruction has
2051 to be "leaq 8(%rsp), %reg". */
2052 if ((buf
[0] & 0xfb) == 0x48
2057 /* MOD must be binary 10 and R/M must be binary 100. */
2058 if ((buf
[2] & 0xc7) != 0x44)
2061 /* REG has register number. */
2062 reg
= (buf
[2] >> 3) & 7;
2064 /* Check the REX.R bit. */
2072 /* Check callee-saved saved register. The first instruction
2073 has to be "pushq %reg". */
2075 if ((buf
[0] & 0xf8) == 0x50)
2077 else if ((buf
[0] & 0xf6) == 0x40
2078 && (buf
[1] & 0xf8) == 0x50)
2080 /* Check the REX.B bit. */
2081 if ((buf
[0] & 1) != 0)
2090 reg
+= buf
[offset
] & 0x7;
2094 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2095 if ((buf
[offset
] & 0xfb) != 0x48
2096 || buf
[offset
+ 1] != 0x8d
2097 || buf
[offset
+ 3] != 0x24
2098 || buf
[offset
+ 4] != 0x10)
2101 /* MOD must be binary 10 and R/M must be binary 100. */
2102 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2105 /* REG has register number. */
2106 r
= (buf
[offset
+ 2] >> 3) & 7;
2108 /* Check the REX.R bit. */
2109 if (buf
[offset
] == 0x4c)
2112 /* Registers in pushq and leaq have to be the same. */
2119 /* Rigister can't be %rsp nor %rbp. */
2120 if (reg
== 4 || reg
== 5)
2123 /* The next instruction has to be "andq $-XXX, %rsp". */
2124 if (buf
[offset
] != 0x48
2125 || buf
[offset
+ 2] != 0xe4
2126 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2129 offset_and
= offset
;
2130 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2132 /* The next instruction has to be "pushq -8(%reg)". */
2134 if (buf
[offset
] == 0xff)
2136 else if ((buf
[offset
] & 0xf6) == 0x40
2137 && buf
[offset
+ 1] == 0xff)
2139 /* Check the REX.B bit. */
2140 if ((buf
[offset
] & 0x1) != 0)
2147 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2149 if (buf
[offset
+ 1] != 0xf8
2150 || (buf
[offset
] & 0xf8) != 0x70)
2153 /* R/M has register. */
2154 r
+= buf
[offset
] & 7;
2156 /* Registers in leaq and pushq have to be the same. */
2160 if (current_pc
> pc
+ offset_and
)
2161 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2163 return std::min (pc
+ offset
+ 2, current_pc
);
2166 /* Similar to amd64_analyze_stack_align for x32. */
2169 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2170 struct amd64_frame_cache
*cache
)
2172 /* There are 2 code sequences to re-align stack before the frame
2175 1. Use a caller-saved saved register:
2183 [addr32] leal 8(%rsp), %reg
2185 [addr32] pushq -8(%reg)
2187 2. Use a callee-saved saved register:
2197 [addr32] leal 16(%rsp), %reg
2199 [addr32] pushq -8(%reg)
2201 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2203 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2204 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2206 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2208 0x83 0xe4 0xf0 andl $-16, %esp
2209 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2214 int offset
, offset_and
;
2216 if (target_read_memory (pc
, buf
, sizeof buf
))
2219 /* Skip optional addr32 prefix. */
2220 offset
= buf
[0] == 0x67 ? 1 : 0;
2222 /* Check caller-saved saved register. The first instruction has
2223 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2224 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2225 && buf
[offset
+ 1] == 0x8d
2226 && buf
[offset
+ 3] == 0x24
2227 && buf
[offset
+ 4] == 0x8)
2229 /* MOD must be binary 10 and R/M must be binary 100. */
2230 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2233 /* REG has register number. */
2234 reg
= (buf
[offset
+ 2] >> 3) & 7;
2236 /* Check the REX.R bit. */
2237 if ((buf
[offset
] & 0x4) != 0)
2244 /* Check callee-saved saved register. The first instruction
2245 has to be "pushq %reg". */
2247 if ((buf
[offset
] & 0xf6) == 0x40
2248 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2250 /* Check the REX.B bit. */
2251 if ((buf
[offset
] & 1) != 0)
2256 else if ((buf
[offset
] & 0xf8) != 0x50)
2260 reg
+= buf
[offset
] & 0x7;
2264 /* Skip optional addr32 prefix. */
2265 if (buf
[offset
] == 0x67)
2268 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2269 "leal 16(%rsp), %reg". */
2270 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2271 || buf
[offset
+ 1] != 0x8d
2272 || buf
[offset
+ 3] != 0x24
2273 || buf
[offset
+ 4] != 0x10)
2276 /* MOD must be binary 10 and R/M must be binary 100. */
2277 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2280 /* REG has register number. */
2281 r
= (buf
[offset
+ 2] >> 3) & 7;
2283 /* Check the REX.R bit. */
2284 if ((buf
[offset
] & 0x4) != 0)
2287 /* Registers in pushq and leaq have to be the same. */
2294 /* Rigister can't be %rsp nor %rbp. */
2295 if (reg
== 4 || reg
== 5)
2298 /* The next instruction may be "andq $-XXX, %rsp" or
2299 "andl $-XXX, %esp". */
2300 if (buf
[offset
] != 0x48)
2303 if (buf
[offset
+ 2] != 0xe4
2304 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2307 offset_and
= offset
;
2308 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2310 /* Skip optional addr32 prefix. */
2311 if (buf
[offset
] == 0x67)
2314 /* The next instruction has to be "pushq -8(%reg)". */
2316 if (buf
[offset
] == 0xff)
2318 else if ((buf
[offset
] & 0xf6) == 0x40
2319 && buf
[offset
+ 1] == 0xff)
2321 /* Check the REX.B bit. */
2322 if ((buf
[offset
] & 0x1) != 0)
2329 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2331 if (buf
[offset
+ 1] != 0xf8
2332 || (buf
[offset
] & 0xf8) != 0x70)
2335 /* R/M has register. */
2336 r
+= buf
[offset
] & 7;
2338 /* Registers in leaq and pushq have to be the same. */
2342 if (current_pc
> pc
+ offset_and
)
2343 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2345 return std::min (pc
+ offset
+ 2, current_pc
);
2348 /* Do a limited analysis of the prologue at PC and update CACHE
2349 accordingly. Bail out early if CURRENT_PC is reached. Return the
2350 address where the analysis stopped.
2352 We will handle only functions beginning with:
2355 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2357 or (for the X32 ABI):
2360 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2362 The `endbr64` instruction can be found before these sequences, and will be
2365 Any function that doesn't start with one of these sequences will be
2366 assumed to have no prologue and thus no valid frame pointer in
2370 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2371 CORE_ADDR pc
, CORE_ADDR current_pc
,
2372 struct amd64_frame_cache
*cache
)
2374 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2375 /* The `endbr64` instruction. */
2376 static const gdb_byte endbr64
[4] = { 0xf3, 0x0f, 0x1e, 0xfa };
2377 /* There are two variations of movq %rsp, %rbp. */
2378 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2379 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2380 /* Ditto for movl %esp, %ebp. */
2381 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2382 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2387 if (current_pc
<= pc
)
2390 if (gdbarch_ptr_bit (gdbarch
) == 32)
2391 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2393 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2395 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2397 /* Check for the `endbr64` instruction, skip it if found. */
2398 if (op
== endbr64
[0])
2400 read_code (pc
+ 1, buf
, 3);
2402 if (memcmp (buf
, &endbr64
[1], 3) == 0)
2405 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2408 if (current_pc
<= pc
)
2411 if (op
== 0x55) /* pushq %rbp */
2413 /* Take into account that we've executed the `pushq %rbp' that
2414 starts this instruction sequence. */
2415 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2416 cache
->sp_offset
+= 8;
2418 /* If that's all, return now. */
2419 if (current_pc
<= pc
+ 1)
2422 read_code (pc
+ 1, buf
, 3);
2424 /* Check for `movq %rsp, %rbp'. */
2425 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2426 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2428 /* OK, we actually have a frame. */
2429 cache
->frameless_p
= 0;
2433 /* For X32, also check for `movl %esp, %ebp'. */
2434 if (gdbarch_ptr_bit (gdbarch
) == 32)
2436 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2437 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2439 /* OK, we actually have a frame. */
2440 cache
->frameless_p
= 0;
2451 /* Work around false termination of prologue - GCC PR debug/48827.
2453 START_PC is the first instruction of a function, PC is its minimal already
2454 determined advanced address. Function returns PC if it has nothing to do.
2458 <-- here is 0 lines advance - the false prologue end marker.
2459 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2460 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2461 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2462 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2463 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2464 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2465 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2466 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2470 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2472 struct symtab_and_line start_pc_sal
, next_sal
;
2473 gdb_byte buf
[4 + 8 * 7];
2479 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2480 if (start_pc_sal
.symtab
== NULL
2481 || producer_is_gcc_ge_4 (start_pc_sal
.symtab
->compunit ()
2483 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2486 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2487 if (next_sal
.line
!= start_pc_sal
.line
)
2490 /* START_PC can be from overlayed memory, ignored here. */
2491 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2495 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2502 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2504 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2505 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2506 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2510 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2512 /* 8-bit displacement. */
2516 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2518 /* 32-bit displacement. */
2526 if (offset
- 4 != buf
[3])
2529 return next_sal
.end
;
2532 /* Return PC of first real instruction. */
2535 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2537 struct amd64_frame_cache cache
;
2539 CORE_ADDR func_addr
;
2541 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2543 CORE_ADDR post_prologue_pc
2544 = skip_prologue_using_sal (gdbarch
, func_addr
);
2545 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2547 /* LLVM backend (Clang/Flang) always emits a line note before the
2548 prologue and another one after. We trust clang and newer Intel
2549 compilers to emit usable line notes. */
2550 if (post_prologue_pc
2552 && cust
->producer () != nullptr
2553 && (producer_is_llvm (cust
->producer ())
2554 || producer_is_icc_ge_19 (cust
->producer ()))))
2555 return std::max (start_pc
, post_prologue_pc
);
2558 amd64_init_frame_cache (&cache
);
2559 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2561 if (cache
.frameless_p
)
2564 return amd64_skip_xmm_prologue (pc
, start_pc
);
2568 /* Normal frames. */
2571 amd64_frame_cache_1 (frame_info_ptr this_frame
,
2572 struct amd64_frame_cache
*cache
)
2574 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2575 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2579 cache
->pc
= get_frame_func (this_frame
);
2581 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2584 if (cache
->frameless_p
)
2586 /* We didn't find a valid frame. If we're at the start of a
2587 function, or somewhere half-way its prologue, the function's
2588 frame probably hasn't been fully setup yet. Try to
2589 reconstruct the base address for the stack frame by looking
2590 at the stack pointer. For truly "frameless" functions this
2593 if (cache
->saved_sp_reg
!= -1)
2595 /* Stack pointer has been saved. */
2596 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2597 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2599 /* We're halfway aligning the stack. */
2600 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2601 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2603 /* This will be added back below. */
2604 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2608 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2609 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2615 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2616 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2619 /* Now that we have the base address for the stack frame we can
2620 calculate the value of %rsp in the calling frame. */
2621 cache
->saved_sp
= cache
->base
+ 16;
2623 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2624 frame we find it at the same offset from the reconstructed base
2625 address. If we're halfway aligning the stack, %rip is handled
2626 differently (see above). */
2627 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2628 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2630 /* Adjust all the saved registers such that they contain addresses
2631 instead of offsets. */
2632 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2633 if (cache
->saved_regs
[i
] != -1)
2634 cache
->saved_regs
[i
] += cache
->base
;
2639 static struct amd64_frame_cache
*
2640 amd64_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2642 struct amd64_frame_cache
*cache
;
2645 return (struct amd64_frame_cache
*) *this_cache
;
2647 cache
= amd64_alloc_frame_cache ();
2648 *this_cache
= cache
;
2652 amd64_frame_cache_1 (this_frame
, cache
);
2654 catch (const gdb_exception_error
&ex
)
2656 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2663 static enum unwind_stop_reason
2664 amd64_frame_unwind_stop_reason (frame_info_ptr this_frame
,
2667 struct amd64_frame_cache
*cache
=
2668 amd64_frame_cache (this_frame
, this_cache
);
2671 return UNWIND_UNAVAILABLE
;
2673 /* This marks the outermost frame. */
2674 if (cache
->base
== 0)
2675 return UNWIND_OUTERMOST
;
2677 return UNWIND_NO_REASON
;
2681 amd64_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
2682 struct frame_id
*this_id
)
2684 struct amd64_frame_cache
*cache
=
2685 amd64_frame_cache (this_frame
, this_cache
);
2688 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2689 else if (cache
->base
== 0)
2691 /* This marks the outermost frame. */
2695 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2698 static struct value
*
2699 amd64_frame_prev_register (frame_info_ptr this_frame
, void **this_cache
,
2702 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2703 struct amd64_frame_cache
*cache
=
2704 amd64_frame_cache (this_frame
, this_cache
);
2706 gdb_assert (regnum
>= 0);
2708 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2709 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2711 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2712 return frame_unwind_got_memory (this_frame
, regnum
,
2713 cache
->saved_regs
[regnum
]);
2715 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2718 static const struct frame_unwind amd64_frame_unwind
=
2722 amd64_frame_unwind_stop_reason
,
2723 amd64_frame_this_id
,
2724 amd64_frame_prev_register
,
2726 default_frame_sniffer
2729 /* Generate a bytecode expression to get the value of the saved PC. */
2732 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2733 struct agent_expr
*ax
, struct axs_value
*value
,
2736 /* The following sequence assumes the traditional use of the base
2738 ax_reg (ax
, AMD64_RBP_REGNUM
);
2740 ax_simple (ax
, aop_add
);
2741 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2742 value
->kind
= axs_lvalue_memory
;
2746 /* Signal trampolines. */
2748 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2749 64-bit variants. This would require using identical frame caches
2750 on both platforms. */
2752 static struct amd64_frame_cache
*
2753 amd64_sigtramp_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2755 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2756 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
2757 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2758 struct amd64_frame_cache
*cache
;
2764 return (struct amd64_frame_cache
*) *this_cache
;
2766 cache
= amd64_alloc_frame_cache ();
2770 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2771 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2773 addr
= tdep
->sigcontext_addr (this_frame
);
2774 gdb_assert (tdep
->sc_reg_offset
);
2775 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2776 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2777 if (tdep
->sc_reg_offset
[i
] != -1)
2778 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2782 catch (const gdb_exception_error
&ex
)
2784 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2788 *this_cache
= cache
;
2792 static enum unwind_stop_reason
2793 amd64_sigtramp_frame_unwind_stop_reason (frame_info_ptr this_frame
,
2796 struct amd64_frame_cache
*cache
=
2797 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2800 return UNWIND_UNAVAILABLE
;
2802 return UNWIND_NO_REASON
;
2806 amd64_sigtramp_frame_this_id (frame_info_ptr this_frame
,
2807 void **this_cache
, struct frame_id
*this_id
)
2809 struct amd64_frame_cache
*cache
=
2810 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2813 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2814 else if (cache
->base
== 0)
2816 /* This marks the outermost frame. */
2820 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2823 static struct value
*
2824 amd64_sigtramp_frame_prev_register (frame_info_ptr this_frame
,
2825 void **this_cache
, int regnum
)
2827 /* Make sure we've initialized the cache. */
2828 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2830 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2834 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2835 frame_info_ptr this_frame
,
2838 gdbarch
*arch
= get_frame_arch (this_frame
);
2839 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (arch
);
2841 /* We shouldn't even bother if we don't have a sigcontext_addr
2843 if (tdep
->sigcontext_addr
== NULL
)
2846 if (tdep
->sigtramp_p
!= NULL
)
2848 if (tdep
->sigtramp_p (this_frame
))
2852 if (tdep
->sigtramp_start
!= 0)
2854 CORE_ADDR pc
= get_frame_pc (this_frame
);
2856 gdb_assert (tdep
->sigtramp_end
!= 0);
2857 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2864 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2868 amd64_sigtramp_frame_unwind_stop_reason
,
2869 amd64_sigtramp_frame_this_id
,
2870 amd64_sigtramp_frame_prev_register
,
2872 amd64_sigtramp_frame_sniffer
2877 amd64_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
2879 struct amd64_frame_cache
*cache
=
2880 amd64_frame_cache (this_frame
, this_cache
);
2885 static const struct frame_base amd64_frame_base
=
2887 &amd64_frame_unwind
,
2888 amd64_frame_base_address
,
2889 amd64_frame_base_address
,
2890 amd64_frame_base_address
2893 /* Normal frames, but in a function epilogue. */
2895 /* Implement the stack_frame_destroyed_p gdbarch method.
2897 The epilogue is defined here as the 'ret' instruction, which will
2898 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2899 the function's stack frame. */
2902 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2906 if (compunit_epilogue_unwind_valid (find_pc_compunit_symtab (pc
)))
2909 if (target_read_memory (pc
, &insn
, 1))
2910 return 0; /* Can't read memory at pc. */
2912 if (insn
!= 0xc3) /* 'ret' instruction. */
2919 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2920 frame_info_ptr this_frame
,
2921 void **this_prologue_cache
)
2923 if (frame_relative_level (this_frame
) == 0)
2924 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2925 get_frame_pc (this_frame
));
2930 static struct amd64_frame_cache
*
2931 amd64_epilogue_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2933 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2935 struct amd64_frame_cache
*cache
;
2939 return (struct amd64_frame_cache
*) *this_cache
;
2941 cache
= amd64_alloc_frame_cache ();
2942 *this_cache
= cache
;
2946 /* Cache base will be %rsp plus cache->sp_offset (-8). */
2947 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2948 cache
->base
= extract_unsigned_integer (buf
, 8,
2949 byte_order
) + cache
->sp_offset
;
2951 /* Cache pc will be the frame func. */
2952 cache
->pc
= get_frame_func (this_frame
);
2954 /* The previous value of %rsp is cache->base plus 16. */
2955 cache
->saved_sp
= cache
->base
+ 16;
2957 /* The saved %rip will be at cache->base plus 8. */
2958 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2962 catch (const gdb_exception_error
&ex
)
2964 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2971 static enum unwind_stop_reason
2972 amd64_epilogue_frame_unwind_stop_reason (frame_info_ptr this_frame
,
2975 struct amd64_frame_cache
*cache
2976 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2979 return UNWIND_UNAVAILABLE
;
2981 return UNWIND_NO_REASON
;
2985 amd64_epilogue_frame_this_id (frame_info_ptr this_frame
,
2987 struct frame_id
*this_id
)
2989 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2993 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2995 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2998 static const struct frame_unwind amd64_epilogue_frame_unwind
=
3002 amd64_epilogue_frame_unwind_stop_reason
,
3003 amd64_epilogue_frame_this_id
,
3004 amd64_frame_prev_register
,
3006 amd64_epilogue_frame_sniffer
3009 static struct frame_id
3010 amd64_dummy_id (struct gdbarch
*gdbarch
, frame_info_ptr this_frame
)
3014 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
3016 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
3019 /* 16 byte align the SP per frame requirements. */
3022 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3024 return sp
& -(CORE_ADDR
)16;
3028 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3029 in the floating-point register set REGSET to register cache
3030 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3033 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3034 int regnum
, const void *fpregs
, size_t len
)
3036 struct gdbarch
*gdbarch
= regcache
->arch ();
3037 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3039 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3040 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
3043 /* Collect register REGNUM from the register cache REGCACHE and store
3044 it in the buffer specified by FPREGS and LEN as described by the
3045 floating-point register set REGSET. If REGNUM is -1, do this for
3046 all registers in REGSET. */
3049 amd64_collect_fpregset (const struct regset
*regset
,
3050 const struct regcache
*regcache
,
3051 int regnum
, void *fpregs
, size_t len
)
3053 struct gdbarch
*gdbarch
= regcache
->arch ();
3054 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3056 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3057 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
3060 const struct regset amd64_fpregset
=
3062 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
3066 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3067 %rdi. We expect its value to be a pointer to the jmp_buf structure
3068 from which we extract the address that we will land at. This
3069 address is copied into PC. This routine returns non-zero on
3073 amd64_get_longjmp_target (frame_info_ptr frame
, CORE_ADDR
*pc
)
3077 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3078 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3079 int jb_pc_offset
= tdep
->jb_pc_offset
;
3080 int len
= builtin_type (gdbarch
)->builtin_func_ptr
->length ();
3082 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3083 longjmp will land. */
3084 if (jb_pc_offset
== -1)
3087 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3088 jb_addr
= extract_typed_address
3089 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3090 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3093 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3098 static const int amd64_record_regmap
[] =
3100 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3101 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3102 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3103 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3104 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3105 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3108 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3111 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3113 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3119 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3120 const target_desc
*default_tdesc
)
3122 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3123 const struct target_desc
*tdesc
= info
.target_desc
;
3124 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3125 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3126 static const char *const stap_register_indirection_prefixes
[] = { "(",
3128 static const char *const stap_register_indirection_suffixes
[] = { ")",
3131 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3132 floating-point registers. */
3133 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3134 tdep
->fpregset
= &amd64_fpregset
;
3136 if (! tdesc_has_registers (tdesc
))
3137 tdesc
= default_tdesc
;
3138 tdep
->tdesc
= tdesc
;
3140 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3141 tdep
->register_names
= amd64_register_names
;
3143 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3145 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3146 tdep
->k_register_names
= amd64_k_names
;
3147 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3148 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3150 tdep
->num_zmm_regs
= 32;
3151 tdep
->num_xmm_avx512_regs
= 16;
3152 tdep
->num_ymm_avx512_regs
= 16;
3154 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3155 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3156 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3157 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3160 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3162 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3163 tdep
->num_ymm_regs
= 16;
3164 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3167 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3169 tdep
->mpx_register_names
= amd64_mpx_names
;
3170 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3171 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3174 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3176 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3179 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3181 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3182 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3183 tdep
->num_pkeys_regs
= 1;
3186 tdep
->num_byte_regs
= 20;
3187 tdep
->num_word_regs
= 16;
3188 tdep
->num_dword_regs
= 16;
3189 /* Avoid wiring in the MMX registers for now. */
3190 tdep
->num_mmx_regs
= 0;
3192 set_gdbarch_pseudo_register_read_value (gdbarch
,
3193 amd64_pseudo_register_read_value
);
3194 set_gdbarch_pseudo_register_write (gdbarch
,
3195 amd64_pseudo_register_write
);
3196 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3197 amd64_ax_pseudo_register_collect
);
3199 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3201 /* AMD64 has an FPU and 16 SSE registers. */
3202 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3203 tdep
->num_xmm_regs
= 16;
3205 /* This is what all the fuss is about. */
3206 set_gdbarch_long_bit (gdbarch
, 64);
3207 set_gdbarch_long_long_bit (gdbarch
, 64);
3208 set_gdbarch_ptr_bit (gdbarch
, 64);
3210 /* In contrast to the i386, on AMD64 a `long double' actually takes
3211 up 128 bits, even though it's still based on the i387 extended
3212 floating-point format which has only 80 significant bits. */
3213 set_gdbarch_long_double_bit (gdbarch
, 128);
3215 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3217 /* Register numbers of various important registers. */
3218 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3219 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3220 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3221 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3223 /* The "default" register numbering scheme for AMD64 is referred to
3224 as the "DWARF Register Number Mapping" in the System V psABI.
3225 The preferred debugging format for all known AMD64 targets is
3226 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3227 DWARF-1), but we provide the same mapping just in case. This
3228 mapping is also used for stabs, which GCC does support. */
3229 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3230 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3232 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3233 be in use on any of the supported AMD64 targets. */
3235 /* Call dummy code. */
3236 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3237 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3238 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3240 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3241 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3242 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3244 set_gdbarch_return_value_as_value (gdbarch
, amd64_return_value
);
3246 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3248 tdep
->record_regmap
= amd64_record_regmap
;
3250 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3252 /* Hook the function epilogue frame unwinder. This unwinder is
3253 appended to the list first, so that it supercedes the other
3254 unwinders in function epilogues. */
3255 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3257 /* Hook the prologue-based frame unwinders. */
3258 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3259 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3260 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3262 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3264 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3266 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3268 /* SystemTap variables and functions. */
3269 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3270 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3271 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3272 stap_register_indirection_prefixes
);
3273 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3274 stap_register_indirection_suffixes
);
3275 set_gdbarch_stap_is_single_operand (gdbarch
,
3276 i386_stap_is_single_operand
);
3277 set_gdbarch_stap_parse_special_token (gdbarch
,
3278 i386_stap_parse_special_token
);
3279 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3280 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3281 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3283 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3284 amd64_in_indirect_branch_thunk
);
3286 register_amd64_ravenscar_ops (gdbarch
);
3289 /* Initialize ARCH for x86-64, no osabi. */
3292 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3294 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3298 static struct type
*
3299 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3301 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3303 switch (regnum
- tdep
->eax_regnum
)
3305 case AMD64_RBP_REGNUM
: /* %ebp */
3306 case AMD64_RSP_REGNUM
: /* %esp */
3307 return builtin_type (gdbarch
)->builtin_data_ptr
;
3308 case AMD64_RIP_REGNUM
: /* %eip */
3309 return builtin_type (gdbarch
)->builtin_func_ptr
;
3312 return i386_pseudo_register_type (gdbarch
, regnum
);
3316 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3317 const target_desc
*default_tdesc
)
3319 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3321 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3323 tdep
->num_dword_regs
= 17;
3324 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3326 set_gdbarch_long_bit (gdbarch
, 32);
3327 set_gdbarch_ptr_bit (gdbarch
, 32);
3330 /* Initialize ARCH for x64-32, no osabi. */
3333 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3335 amd64_x32_init_abi (info
, arch
,
3336 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3339 /* Return the target description for a specified XSAVE feature mask. */
3341 const struct target_desc
*
3342 amd64_target_description (uint64_t xcr0
, bool segments
)
3344 static target_desc
*amd64_tdescs \
3345 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3346 target_desc
**tdesc
;
3348 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3349 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3350 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3351 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3355 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3361 void _initialize_amd64_tdep ();
3363 _initialize_amd64_tdep ()
3365 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3366 amd64_none_init_abi
);
3367 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3368 amd64_x32_none_init_abi
);
3372 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3373 sense that the instruction pointer and data pointer are simply
3374 64-bit offsets into the code segment and the data segment instead
3375 of a selector offset pair. The functions below store the upper 32
3376 bits of these pointers (instead of just the 16-bits of the segment
3379 /* Fill register REGNUM in REGCACHE with the appropriate
3380 floating-point or SSE register value from *FXSAVE. If REGNUM is
3381 -1, do this for all registers. This function masks off any of the
3382 reserved bits in *FXSAVE. */
3385 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3388 struct gdbarch
*gdbarch
= regcache
->arch ();
3389 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3391 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3394 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3396 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3398 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3399 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3400 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3401 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3405 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3408 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3411 struct gdbarch
*gdbarch
= regcache
->arch ();
3412 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3414 i387_supply_xsave (regcache
, regnum
, xsave
);
3417 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3419 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3422 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3424 /* If the FISEG and FOSEG registers have not been initialised yet
3425 (their CLEAR_BV bit is set) then their default values of zero will
3426 have already been setup by I387_SUPPLY_XSAVE. */
3427 if (!(clear_bv
& X86_XSTATE_X87
))
3429 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3430 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3431 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3432 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3437 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3438 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3439 all registers. This function doesn't touch any of the reserved
3443 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3446 struct gdbarch
*gdbarch
= regcache
->arch ();
3447 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3448 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3450 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3452 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3454 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3455 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3456 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3457 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3461 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3464 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3465 void *xsave
, int gcore
)
3467 struct gdbarch
*gdbarch
= regcache
->arch ();
3468 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3469 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3471 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3473 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3475 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3476 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3478 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3479 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),