gdb/arch/arm.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 1988-2024 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARCH_ARM_H
  20 #define ARCH_ARM_H
  21
  22 #include "gdbsupport/tdesc.h"
  23
  24 /* Prologue helper macros for ARMv8.1-m PACBTI.  */
  25 #define IS_PAC(instruction)     (instruction == 0xf3af801d)
  26 #define IS_PACBTI(instruction)  (instruction == 0xf3af800d)
  27 #define IS_BTI(instruction)     (instruction == 0xf3af800f)
  28 #define IS_PACG(instruction)    ((instruction & 0xfff0f0f0) == 0xfb60f000)
  29 #define IS_AUT(instruction)     (instruction == 0xf3af802d)
  30 #define IS_AUTG(instruction)    ((instruction & 0xfff00ff0) == 0xfb500f00)
  31
  32 /* DWARF register numbers according to the AADWARF32 document.  */
  33 enum arm_dwarf_regnum {
  34   ARM_DWARF_RA_AUTH_CODE = 143
  35 };
  36
  37 /* Register numbers of various important registers.  */
  38
  39 enum gdb_regnum {
  40   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  41   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  42   ARM_AP_REGNUM = 11,
  43   ARM_IP_REGNUM = 12,
  44   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  45   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  46   ARM_PC_REGNUM = 15,           /* Contains program counter */
  47   /* F0..F7 are the fp registers for the (obsolete) FPA architecture.  */
  48   ARM_F0_REGNUM = 16,           /* first floating point register */
  49   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  50   ARM_F7_REGNUM = 23,           /* last floating point register */
  51   ARM_FPS_REGNUM = 24,          /* floating point status register */
  52   ARM_PS_REGNUM = 25,           /* Contains processor status */
  53   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  54   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  55   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  56   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  57   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  58   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  59   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  60   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  61   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  62   ARM_D0_REGNUM,                /* VFP double-precision registers.  */
  63   ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  64   ARM_FPSCR_REGNUM,
  65
  66   /* Other useful registers.  */
  67   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  68   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  69   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  70   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  71 };
  72
  73 /* Register count constants.  */
  74 enum arm_register_counts {
  75   /* Number of Q registers for MVE.  */
  76   ARM_MVE_NUM_Q_REGS = 8,
  77   /* Number of argument registers.  */
  78   ARM_NUM_ARG_REGS = 4,
  79   /* Number of floating point argument registers.  */
  80   ARM_NUM_FP_ARG_REGS = 4,
  81   /* Number of registers (old, defined as ARM_FPSCR_REGNUM + 1.  */
  82   ARM_NUM_REGS = ARM_FPSCR_REGNUM + 1
  83 };
  84
  85 /* Enum describing the different kinds of breakpoints.  */
  86 enum arm_breakpoint_kinds
  87 {
  88    ARM_BP_KIND_THUMB = 2,
  89    ARM_BP_KIND_THUMB2 = 3,
  90    ARM_BP_KIND_ARM = 4,
  91 };
  92
  93 /* Supported Arm FP hardware types.  */
  94 enum arm_fp_type {
  95    ARM_FP_TYPE_NONE = 0,
  96    ARM_FP_TYPE_VFPV2,
  97    ARM_FP_TYPE_VFPV3,
  98    ARM_FP_TYPE_IWMMXT,
  99    ARM_FP_TYPE_INVALID
 100 };
 101
 102 /* Supported M-profile Arm types.  */
 103 enum arm_m_profile_type {
 104    ARM_M_TYPE_M_PROFILE,
 105    ARM_M_TYPE_VFP_D16,
 106    ARM_M_TYPE_WITH_FPA,
 107    ARM_M_TYPE_MVE,
 108    ARM_M_TYPE_SYSTEM,
 109    ARM_M_TYPE_INVALID
 110 };
 111
 112 /* System control registers accessible through an addresses.  */
 113 enum system_register_address : CORE_ADDR
 114 {
 115   /* M-profile Floating-Point Context Control Register address, defined in
 116      ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference
 117      manuals.  */
 118   FPCCR = 0xe000ef34,
 119
 120   /* M-profile Floating-Point Context Address Register address, defined in
 121      ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.98) reference
 122      manuals.  */
 123   FPCAR = 0xe000ef38
 124 };
 125
 126 /* Instruction condition field values.  */
 127 #define INST_EQ         0x0
 128 #define INST_NE         0x1
 129 #define INST_CS         0x2
 130 #define INST_CC         0x3
 131 #define INST_MI         0x4
 132 #define INST_PL         0x5
 133 #define INST_VS         0x6
 134 #define INST_VC         0x7
 135 #define INST_HI         0x8
 136 #define INST_LS         0x9
 137 #define INST_GE         0xa
 138 #define INST_LT         0xb
 139 #define INST_GT         0xc
 140 #define INST_LE         0xd
 141 #define INST_AL         0xe
 142 #define INST_NV         0xf
 143
 144 #define FLAG_N          0x80000000
 145 #define FLAG_Z          0x40000000
 146 #define FLAG_C          0x20000000
 147 #define FLAG_V          0x10000000
 148
 149 #define CPSR_T          0x20
 150
 151 #define XPSR_T          0x01000000
 152
 153 /* Size of registers.  */
 154
 155 #define ARM_INT_REGISTER_SIZE           4
 156 /* IEEE extended doubles are 80 bits.  DWORD aligned they use 96 bits.  */
 157 #define ARM_FP_REGISTER_SIZE            12
 158 #define ARM_VFP_REGISTER_SIZE           8
 159 #define IWMMXT_VEC_REGISTER_SIZE        8
 160
 161 /* Size of register sets.  */
 162
 163 /* r0-r12,sp,lr,pc,cpsr.  */
 164 #define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE)
 165 /* f0-f8,fps.  */
 166 #define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
 167 /* d0-d15,fpscr.  */
 168 #define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
 169 /* d0-d31,fpscr.  */
 170 #define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
 171 /* wR0-wR15,fpscr.  */
 172 #define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \
 173                           + 6 * ARM_INT_REGISTER_SIZE)
 174
 175 /* Addresses for calling Thumb functions have the bit 0 set.
 176    Here are some macros to test, set, or clear bit 0 of addresses.  */
 177 #define IS_THUMB_ADDR(addr)    ((addr) & 1)
 178 #define MAKE_THUMB_ADDR(addr)  ((addr) | 1)
 179 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
 180
 181 /* Support routines for instruction parsing.  */
 182 #define submask(x) ((1L << ((x) + 1)) - 1)
 183 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
 184 #define bit(obj,st) (((obj) >> (st)) & 1)
 185 #define sbits(obj,st,fn) \
 186   ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
 187 #define BranchDest(addr,instr) \
 188   ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
 189
 190 /* Forward declaration.  */
 191 struct reg_buffer_common;
 192
 193 /* Return the size in bytes of the complete Thumb instruction whose
 194    first halfword is INST1.  */
 195 int thumb_insn_size (unsigned short inst1);
 196
 197 /* Returns true if the condition evaluates to true.  */
 198 int condition_true (unsigned long cond, unsigned long status_reg);
 199
 200 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise.  */
 201 int arm_instruction_changes_pc (uint32_t this_instr);
 202
 203 /* Return 1 if the 16-bit Thumb instruction INST might change
 204    control flow, 0 otherwise.  */
 205 int thumb_instruction_changes_pc (unsigned short inst);
 206
 207 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
 208    might change control flow, 0 otherwise.  */
 209 int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2);
 210
 211 /* Advance the state of the IT block and return that state.  */
 212 int thumb_advance_itstate (unsigned int itstate);
 213
 214 /* Decode shifted register value.  */
 215
 216 unsigned long shifted_reg_val (reg_buffer_common *regcache,
 217                                unsigned long inst,
 218                                int carry,
 219                                unsigned long pc_val,
 220                                unsigned long status_reg);
 221
 222 /* Create an Arm target description with the given FP hardware type.  */
 223
 224 target_desc *arm_create_target_description (arm_fp_type fp_type, bool tls);
 225
 226 /* Create an Arm M-profile target description with the given hardware type.  */
 227
 228 target_desc *arm_create_mprofile_target_description (arm_m_profile_type m_type);
 229
 230 #endif /* ARCH_ARM_H */