1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "arch/arm-get-next-pcs.h"
52 #include "gdb/sim-arm.h"
55 #include "coff/internal.h"
61 #include "record-full.h"
64 #include "features/arm/arm-with-m.c"
65 #include "features/arm/arm-with-m-fpa-layout.c"
66 #include "features/arm/arm-with-m-vfp-d16.c"
67 #include "features/arm/arm-with-iwmmxt.c"
68 #include "features/arm/arm-with-vfpv2.c"
69 #include "features/arm/arm-with-vfpv3.c"
70 #include "features/arm/arm-with-neon.c"
74 /* Macros for setting and testing a bit in a minimal symbol that marks
75 it as Thumb function. The MSB of the minimal symbol's "info" field
76 is used for this purpose.
78 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
79 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
81 #define MSYMBOL_SET_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym) = 1
84 #define MSYMBOL_IS_SPECIAL(msym) \
85 MSYMBOL_TARGET_FLAG_1 (msym)
87 /* Per-objfile data used for mapping symbols. */
88 static const struct objfile_data
*arm_objfile_data_key
;
90 struct arm_mapping_symbol
95 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
96 DEF_VEC_O(arm_mapping_symbol_s
);
98 struct arm_per_objfile
100 VEC(arm_mapping_symbol_s
) **section_maps
;
103 /* The list of available "set arm ..." and "show arm ..." commands. */
104 static struct cmd_list_element
*setarmcmdlist
= NULL
;
105 static struct cmd_list_element
*showarmcmdlist
= NULL
;
107 /* The type of floating-point to use. Keep this in sync with enum
108 arm_float_model, and the help string in _initialize_arm_tdep. */
109 static const char *const fp_model_strings
[] =
119 /* A variable that can be configured by the user. */
120 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
121 static const char *current_fp_model
= "auto";
123 /* The ABI to use. Keep this in sync with arm_abi_kind. */
124 static const char *const arm_abi_strings
[] =
132 /* A variable that can be configured by the user. */
133 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
134 static const char *arm_abi_string
= "auto";
136 /* The execution mode to assume. */
137 static const char *const arm_mode_strings
[] =
145 static const char *arm_fallback_mode_string
= "auto";
146 static const char *arm_force_mode_string
= "auto";
148 /* The standard register names, and all the valid aliases for them. Note
149 that `fp', `sp' and `pc' are not added in this alias list, because they
150 have been added as builtin user registers in
151 std-regs.c:_initialize_frame_reg. */
156 } arm_register_aliases
[] = {
157 /* Basic register numbers. */
174 /* Synonyms (argument and variable registers). */
187 /* Other platform-specific names for r9. */
193 /* Names used by GCC (not listed in the ARM EABI). */
195 /* A special name from the older ATPCS. */
199 static const char *const arm_register_names
[] =
200 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
201 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
202 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
203 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
204 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
205 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
206 "fps", "cpsr" }; /* 24 25 */
208 /* Holds the current set of options to be passed to the disassembler. */
209 static char *arm_disassembler_options
;
211 /* Valid register name styles. */
212 static const char **valid_disassembly_styles
;
214 /* Disassembly style to use. Default to "std" register names. */
215 static const char *disassembly_style
;
217 /* This is used to keep the bfd arch_info in sync with the disassembly
219 static void set_disassembly_style_sfunc(char *, int,
220 struct cmd_list_element
*);
221 static void show_disassembly_style_sfunc (struct ui_file
*, int,
222 struct cmd_list_element
*,
225 static void convert_from_extended (const struct floatformat
*, const void *,
227 static void convert_to_extended (const struct floatformat
*, void *,
230 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
231 struct regcache
*regcache
,
232 int regnum
, gdb_byte
*buf
);
233 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
234 struct regcache
*regcache
,
235 int regnum
, const gdb_byte
*buf
);
238 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
241 /* get_next_pcs operations. */
242 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
243 arm_get_next_pcs_read_memory_unsigned_integer
,
244 arm_get_next_pcs_syscall_next_pc
,
245 arm_get_next_pcs_addr_bits_remove
,
246 arm_get_next_pcs_is_thumb
,
250 struct arm_prologue_cache
252 /* The stack pointer at the time this frame was created; i.e. the
253 caller's stack pointer when this function was called. It is used
254 to identify this frame. */
257 /* The frame base for this frame is just prev_sp - frame size.
258 FRAMESIZE is the distance from the frame pointer to the
259 initial stack pointer. */
263 /* The register used to hold the frame pointer for this frame. */
266 /* Saved register offsets. */
267 struct trad_frame_saved_reg
*saved_regs
;
270 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
271 CORE_ADDR prologue_start
,
272 CORE_ADDR prologue_end
,
273 struct arm_prologue_cache
*cache
);
275 /* Architecture version for displaced stepping. This effects the behaviour of
276 certain instructions, and really should not be hard-wired. */
278 #define DISPLACED_STEPPING_ARCH_VERSION 5
280 /* Set to true if the 32-bit mode is in use. */
284 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
287 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
289 if (gdbarch_tdep (gdbarch
)->is_m
)
295 /* Determine if the processor is currently executing in Thumb mode. */
298 arm_is_thumb (struct regcache
*regcache
)
301 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
303 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Determine if FRAME is executing in Thumb mode. */
311 arm_frame_is_thumb (struct frame_info
*frame
)
314 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
316 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
317 directly (from a signal frame or dummy frame) or by interpreting
318 the saved LR (from a prologue or DWARF frame). So consult it and
319 trust the unwinders. */
320 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
322 return (cpsr
& t_bit
) != 0;
325 /* Callback for VEC_lower_bound. */
328 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
329 const struct arm_mapping_symbol
*rhs
)
331 return lhs
->value
< rhs
->value
;
334 /* Search for the mapping symbol covering MEMADDR. If one is found,
335 return its type. Otherwise, return 0. If START is non-NULL,
336 set *START to the location of the mapping symbol. */
339 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
341 struct obj_section
*sec
;
343 /* If there are mapping symbols, consult them. */
344 sec
= find_pc_section (memaddr
);
347 struct arm_per_objfile
*data
;
348 VEC(arm_mapping_symbol_s
) *map
;
349 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
353 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
354 arm_objfile_data_key
);
357 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
358 if (!VEC_empty (arm_mapping_symbol_s
, map
))
360 struct arm_mapping_symbol
*map_sym
;
362 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
363 arm_compare_mapping_symbols
);
365 /* VEC_lower_bound finds the earliest ordered insertion
366 point. If the following symbol starts at this exact
367 address, we use that; otherwise, the preceding
368 mapping symbol covers this address. */
369 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
371 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
372 if (map_sym
->value
== map_key
.value
)
375 *start
= map_sym
->value
+ obj_section_addr (sec
);
376 return map_sym
->type
;
382 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
384 *start
= map_sym
->value
+ obj_section_addr (sec
);
385 return map_sym
->type
;
394 /* Determine if the program counter specified in MEMADDR is in a Thumb
395 function. This function should be called for addresses unrelated to
396 any executing frame; otherwise, prefer arm_frame_is_thumb. */
399 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
401 struct bound_minimal_symbol sym
;
403 struct displaced_step_closure
* dsc
404 = get_displaced_step_closure_by_addr(memaddr
);
406 /* If checking the mode of displaced instruction in copy area, the mode
407 should be determined by instruction on the original address. */
411 fprintf_unfiltered (gdb_stdlog
,
412 "displaced: check mode of %.8lx instead of %.8lx\n",
413 (unsigned long) dsc
->insn_addr
,
414 (unsigned long) memaddr
);
415 memaddr
= dsc
->insn_addr
;
418 /* If bit 0 of the address is set, assume this is a Thumb address. */
419 if (IS_THUMB_ADDR (memaddr
))
422 /* If the user wants to override the symbol table, let him. */
423 if (strcmp (arm_force_mode_string
, "arm") == 0)
425 if (strcmp (arm_force_mode_string
, "thumb") == 0)
428 /* ARM v6-M and v7-M are always in Thumb mode. */
429 if (gdbarch_tdep (gdbarch
)->is_m
)
432 /* If there are mapping symbols, consult them. */
433 type
= arm_find_mapping_symbol (memaddr
, NULL
);
437 /* Thumb functions have a "special" bit set in minimal symbols. */
438 sym
= lookup_minimal_symbol_by_pc (memaddr
);
440 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
442 /* If the user wants to override the fallback mode, let them. */
443 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
445 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
448 /* If we couldn't find any symbol, but we're talking to a running
449 target, then trust the current value of $cpsr. This lets
450 "display/i $pc" always show the correct mode (though if there is
451 a symbol table we will not reach here, so it still may not be
452 displayed in the mode it will be executed). */
453 if (target_has_registers
)
454 return arm_frame_is_thumb (get_current_frame ());
456 /* Otherwise we're out of luck; we assume ARM. */
460 /* Determine if the address specified equals any of these magic return
461 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
464 From ARMv6-M Reference Manual B1.5.8
465 Table B1-5 Exception return behavior
467 EXC_RETURN Return To Return Stack
468 0xFFFFFFF1 Handler mode Main
469 0xFFFFFFF9 Thread mode Main
470 0xFFFFFFFD Thread mode Process
472 From ARMv7-M Reference Manual B1.5.8
473 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
475 EXC_RETURN Return To Return Stack
476 0xFFFFFFF1 Handler mode Main
477 0xFFFFFFF9 Thread mode Main
478 0xFFFFFFFD Thread mode Process
480 Table B1-9 EXC_RETURN definition of exception return behavior, with
483 EXC_RETURN Return To Return Stack Frame Type
484 0xFFFFFFE1 Handler mode Main Extended
485 0xFFFFFFE9 Thread mode Main Extended
486 0xFFFFFFED Thread mode Process Extended
487 0xFFFFFFF1 Handler mode Main Basic
488 0xFFFFFFF9 Thread mode Main Basic
489 0xFFFFFFFD Thread mode Process Basic
491 For more details see "B1.5.8 Exception return behavior"
492 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
495 arm_m_addr_is_magic (CORE_ADDR addr
)
499 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
500 the exception return behavior. */
507 /* Address is magic. */
511 /* Address is not magic. */
516 /* Remove useless bits from addresses in a running program. */
518 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
520 /* On M-profile devices, do not strip the low bit from EXC_RETURN
521 (the magic exception return address). */
522 if (gdbarch_tdep (gdbarch
)->is_m
523 && arm_m_addr_is_magic (val
))
527 return UNMAKE_THUMB_ADDR (val
);
529 return (val
& 0x03fffffc);
532 /* Return 1 if PC is the start of a compiler helper function which
533 can be safely ignored during prologue skipping. IS_THUMB is true
534 if the function is known to be a Thumb function due to the way it
537 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
539 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
540 struct bound_minimal_symbol msym
;
542 msym
= lookup_minimal_symbol_by_pc (pc
);
543 if (msym
.minsym
!= NULL
544 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
545 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
547 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
549 /* The GNU linker's Thumb call stub to foo is named
551 if (strstr (name
, "_from_thumb") != NULL
)
554 /* On soft-float targets, __truncdfsf2 is called to convert promoted
555 arguments to their argument types in non-prototyped
557 if (startswith (name
, "__truncdfsf2"))
559 if (startswith (name
, "__aeabi_d2f"))
562 /* Internal functions related to thread-local storage. */
563 if (startswith (name
, "__tls_get_addr"))
565 if (startswith (name
, "__aeabi_read_tp"))
570 /* If we run against a stripped glibc, we may be unable to identify
571 special functions by name. Check for one important case,
572 __aeabi_read_tp, by comparing the *code* against the default
573 implementation (this is hand-written ARM assembler in glibc). */
576 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
577 == 0xe3e00a0f /* mov r0, #0xffff0fff */
578 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
579 == 0xe240f01f) /* sub pc, r0, #31 */
586 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
587 the first 16-bit of instruction, and INSN2 is the second 16-bit of
589 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
590 ((bits ((insn1), 0, 3) << 12) \
591 | (bits ((insn1), 10, 10) << 11) \
592 | (bits ((insn2), 12, 14) << 8) \
593 | bits ((insn2), 0, 7))
595 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
596 the 32-bit instruction. */
597 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
598 ((bits ((insn), 16, 19) << 12) \
599 | bits ((insn), 0, 11))
601 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
604 thumb_expand_immediate (unsigned int imm
)
606 unsigned int count
= imm
>> 7;
614 return (imm
& 0xff) | ((imm
& 0xff) << 16);
616 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
618 return (imm
& 0xff) | ((imm
& 0xff) << 8)
619 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
622 return (0x80 | (imm
& 0x7f)) << (32 - count
);
625 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
626 epilogue, 0 otherwise. */
629 thumb_instruction_restores_sp (unsigned short insn
)
631 return (insn
== 0x46bd /* mov sp, r7 */
632 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
633 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
636 /* Analyze a Thumb prologue, looking for a recognizable stack frame
637 and frame pointer. Scan until we encounter a store that could
638 clobber the stack frame unexpectedly, or an unknown instruction.
639 Return the last address which is definitely safe to skip for an
640 initial breakpoint. */
643 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
644 CORE_ADDR start
, CORE_ADDR limit
,
645 struct arm_prologue_cache
*cache
)
647 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
648 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
651 struct pv_area
*stack
;
652 struct cleanup
*back_to
;
654 CORE_ADDR unrecognized_pc
= 0;
656 for (i
= 0; i
< 16; i
++)
657 regs
[i
] = pv_register (i
, 0);
658 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
659 back_to
= make_cleanup_free_pv_area (stack
);
661 while (start
< limit
)
665 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
667 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
672 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
675 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
676 whether to save LR (R14). */
677 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
679 /* Calculate offsets of saved R0-R7 and LR. */
680 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
681 if (mask
& (1 << regno
))
683 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
685 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
688 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
690 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
691 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
694 else if (thumb_instruction_restores_sp (insn
))
696 /* Don't scan past the epilogue. */
699 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
700 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
702 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
703 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
704 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
706 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
707 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
708 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
710 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
711 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
712 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
713 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
714 regs
[bits (insn
, 6, 8)]);
715 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
716 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
718 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
719 int rm
= bits (insn
, 3, 6);
720 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
722 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
724 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
725 int src_reg
= (insn
& 0x78) >> 3;
726 regs
[dst_reg
] = regs
[src_reg
];
728 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
730 /* Handle stores to the stack. Normally pushes are used,
731 but with GCC -mtpcs-frame, there may be other stores
732 in the prologue to create the frame. */
733 int regno
= (insn
>> 8) & 0x7;
736 offset
= (insn
& 0xff) << 2;
737 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
739 if (pv_area_store_would_trash (stack
, addr
))
742 pv_area_store (stack
, addr
, 4, regs
[regno
]);
744 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
746 int rd
= bits (insn
, 0, 2);
747 int rn
= bits (insn
, 3, 5);
750 offset
= bits (insn
, 6, 10) << 2;
751 addr
= pv_add_constant (regs
[rn
], offset
);
753 if (pv_area_store_would_trash (stack
, addr
))
756 pv_area_store (stack
, addr
, 4, regs
[rd
]);
758 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
759 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
760 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
761 /* Ignore stores of argument registers to the stack. */
763 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
764 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
765 /* Ignore block loads from the stack, potentially copying
766 parameters from memory. */
768 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
769 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
770 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
771 /* Similarly ignore single loads from the stack. */
773 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
774 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
775 /* Skip register copies, i.e. saves to another register
776 instead of the stack. */
778 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
779 /* Recognize constant loads; even with small stacks these are necessary
781 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
782 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
784 /* Constant pool loads, for the same reason. */
785 unsigned int constant
;
788 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
789 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
790 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
792 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
794 unsigned short inst2
;
796 inst2
= read_code_unsigned_integer (start
+ 2, 2,
797 byte_order_for_code
);
799 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
801 /* BL, BLX. Allow some special function calls when
802 skipping the prologue; GCC generates these before
803 storing arguments to the stack. */
805 int j1
, j2
, imm1
, imm2
;
807 imm1
= sbits (insn
, 0, 10);
808 imm2
= bits (inst2
, 0, 10);
809 j1
= bit (inst2
, 13);
810 j2
= bit (inst2
, 11);
812 offset
= ((imm1
<< 12) + (imm2
<< 1));
813 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
815 nextpc
= start
+ 4 + offset
;
816 /* For BLX make sure to clear the low bits. */
817 if (bit (inst2
, 12) == 0)
818 nextpc
= nextpc
& 0xfffffffc;
820 if (!skip_prologue_function (gdbarch
, nextpc
,
821 bit (inst2
, 12) != 0))
825 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
827 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
829 pv_t addr
= regs
[bits (insn
, 0, 3)];
832 if (pv_area_store_would_trash (stack
, addr
))
835 /* Calculate offsets of saved registers. */
836 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
837 if (inst2
& (1 << regno
))
839 addr
= pv_add_constant (addr
, -4);
840 pv_area_store (stack
, addr
, 4, regs
[regno
]);
844 regs
[bits (insn
, 0, 3)] = addr
;
847 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
849 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
851 int regno1
= bits (inst2
, 12, 15);
852 int regno2
= bits (inst2
, 8, 11);
853 pv_t addr
= regs
[bits (insn
, 0, 3)];
855 offset
= inst2
& 0xff;
857 addr
= pv_add_constant (addr
, offset
);
859 addr
= pv_add_constant (addr
, -offset
);
861 if (pv_area_store_would_trash (stack
, addr
))
864 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
865 pv_area_store (stack
, pv_add_constant (addr
, 4),
869 regs
[bits (insn
, 0, 3)] = addr
;
872 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
873 && (inst2
& 0x0c00) == 0x0c00
874 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
876 int regno
= bits (inst2
, 12, 15);
877 pv_t addr
= regs
[bits (insn
, 0, 3)];
879 offset
= inst2
& 0xff;
881 addr
= pv_add_constant (addr
, offset
);
883 addr
= pv_add_constant (addr
, -offset
);
885 if (pv_area_store_would_trash (stack
, addr
))
888 pv_area_store (stack
, addr
, 4, regs
[regno
]);
891 regs
[bits (insn
, 0, 3)] = addr
;
894 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
895 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
897 int regno
= bits (inst2
, 12, 15);
900 offset
= inst2
& 0xfff;
901 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
903 if (pv_area_store_would_trash (stack
, addr
))
906 pv_area_store (stack
, addr
, 4, regs
[regno
]);
909 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
910 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
911 /* Ignore stores of argument registers to the stack. */
914 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
915 && (inst2
& 0x0d00) == 0x0c00
916 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
917 /* Ignore stores of argument registers to the stack. */
920 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
922 && (inst2
& 0x8000) == 0x0000
923 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
924 /* Ignore block loads from the stack, potentially copying
925 parameters from memory. */
928 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
930 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
931 /* Similarly ignore dual loads from the stack. */
934 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
935 && (inst2
& 0x0d00) == 0x0c00
936 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
937 /* Similarly ignore single loads from the stack. */
940 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
941 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
942 /* Similarly ignore single loads from the stack. */
945 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
946 && (inst2
& 0x8000) == 0x0000)
948 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
949 | (bits (inst2
, 12, 14) << 8)
950 | bits (inst2
, 0, 7));
952 regs
[bits (inst2
, 8, 11)]
953 = pv_add_constant (regs
[bits (insn
, 0, 3)],
954 thumb_expand_immediate (imm
));
957 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
958 && (inst2
& 0x8000) == 0x0000)
960 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
961 | (bits (inst2
, 12, 14) << 8)
962 | bits (inst2
, 0, 7));
964 regs
[bits (inst2
, 8, 11)]
965 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
968 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
969 && (inst2
& 0x8000) == 0x0000)
971 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
972 | (bits (inst2
, 12, 14) << 8)
973 | bits (inst2
, 0, 7));
975 regs
[bits (inst2
, 8, 11)]
976 = pv_add_constant (regs
[bits (insn
, 0, 3)],
977 - (CORE_ADDR
) thumb_expand_immediate (imm
));
980 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
981 && (inst2
& 0x8000) == 0x0000)
983 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
984 | (bits (inst2
, 12, 14) << 8)
985 | bits (inst2
, 0, 7));
987 regs
[bits (inst2
, 8, 11)]
988 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
991 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
993 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
994 | (bits (inst2
, 12, 14) << 8)
995 | bits (inst2
, 0, 7));
997 regs
[bits (inst2
, 8, 11)]
998 = pv_constant (thumb_expand_immediate (imm
));
1001 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1004 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1006 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1009 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1010 && (inst2
& 0xf0f0) == 0)
1012 int dst_reg
= (inst2
& 0x0f00) >> 8;
1013 int src_reg
= inst2
& 0xf;
1014 regs
[dst_reg
] = regs
[src_reg
];
1017 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1019 /* Constant pool loads. */
1020 unsigned int constant
;
1023 offset
= bits (inst2
, 0, 11);
1025 loc
= start
+ 4 + offset
;
1027 loc
= start
+ 4 - offset
;
1029 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1030 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1033 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1035 /* Constant pool loads. */
1036 unsigned int constant
;
1039 offset
= bits (inst2
, 0, 7) << 2;
1041 loc
= start
+ 4 + offset
;
1043 loc
= start
+ 4 - offset
;
1045 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1046 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1048 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1049 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1052 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1054 /* Don't scan past anything that might change control flow. */
1059 /* The optimizer might shove anything into the prologue,
1060 so we just skip what we don't recognize. */
1061 unrecognized_pc
= start
;
1066 else if (thumb_instruction_changes_pc (insn
))
1068 /* Don't scan past anything that might change control flow. */
1073 /* The optimizer might shove anything into the prologue,
1074 so we just skip what we don't recognize. */
1075 unrecognized_pc
= start
;
1082 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1083 paddress (gdbarch
, start
));
1085 if (unrecognized_pc
== 0)
1086 unrecognized_pc
= start
;
1090 do_cleanups (back_to
);
1091 return unrecognized_pc
;
1094 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1096 /* Frame pointer is fp. Frame size is constant. */
1097 cache
->framereg
= ARM_FP_REGNUM
;
1098 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1100 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1102 /* Frame pointer is r7. Frame size is constant. */
1103 cache
->framereg
= THUMB_FP_REGNUM
;
1104 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1108 /* Try the stack pointer... this is a bit desperate. */
1109 cache
->framereg
= ARM_SP_REGNUM
;
1110 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1113 for (i
= 0; i
< 16; i
++)
1114 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1115 cache
->saved_regs
[i
].addr
= offset
;
1117 do_cleanups (back_to
);
1118 return unrecognized_pc
;
1122 /* Try to analyze the instructions starting from PC, which load symbol
1123 __stack_chk_guard. Return the address of instruction after loading this
1124 symbol, set the dest register number to *BASEREG, and set the size of
1125 instructions for loading symbol in OFFSET. Return 0 if instructions are
1129 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1130 unsigned int *destreg
, int *offset
)
1132 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1133 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1134 unsigned int low
, high
, address
;
1139 unsigned short insn1
1140 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1142 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1144 *destreg
= bits (insn1
, 8, 10);
1146 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1147 address
= read_memory_unsigned_integer (address
, 4,
1148 byte_order_for_code
);
1150 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1152 unsigned short insn2
1153 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1155 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1158 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1160 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1162 /* movt Rd, #const */
1163 if ((insn1
& 0xfbc0) == 0xf2c0)
1165 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1166 *destreg
= bits (insn2
, 8, 11);
1168 address
= (high
<< 16 | low
);
1175 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1177 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1179 address
= bits (insn
, 0, 11) + pc
+ 8;
1180 address
= read_memory_unsigned_integer (address
, 4,
1181 byte_order_for_code
);
1183 *destreg
= bits (insn
, 12, 15);
1186 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1188 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1191 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1193 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1195 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1196 *destreg
= bits (insn
, 12, 15);
1198 address
= (high
<< 16 | low
);
1206 /* Try to skip a sequence of instructions used for stack protector. If PC
1207 points to the first instruction of this sequence, return the address of
1208 first instruction after this sequence, otherwise, return original PC.
1210 On arm, this sequence of instructions is composed of mainly three steps,
1211 Step 1: load symbol __stack_chk_guard,
1212 Step 2: load from address of __stack_chk_guard,
1213 Step 3: store it to somewhere else.
1215 Usually, instructions on step 2 and step 3 are the same on various ARM
1216 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1217 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1218 instructions in step 1 vary from different ARM architectures. On ARMv7,
1221 movw Rn, #:lower16:__stack_chk_guard
1222 movt Rn, #:upper16:__stack_chk_guard
1229 .word __stack_chk_guard
1231 Since ldr/str is a very popular instruction, we can't use them as
1232 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1233 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1234 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1237 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1239 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1240 unsigned int basereg
;
1241 struct bound_minimal_symbol stack_chk_guard
;
1243 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1246 /* Try to parse the instructions in Step 1. */
1247 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1252 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1253 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1254 Otherwise, this sequence cannot be for stack protector. */
1255 if (stack_chk_guard
.minsym
== NULL
1256 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1261 unsigned int destreg
;
1263 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1265 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1266 if ((insn
& 0xf800) != 0x6800)
1268 if (bits (insn
, 3, 5) != basereg
)
1270 destreg
= bits (insn
, 0, 2);
1272 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1273 byte_order_for_code
);
1274 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1275 if ((insn
& 0xf800) != 0x6000)
1277 if (destreg
!= bits (insn
, 0, 2))
1282 unsigned int destreg
;
1284 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1286 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1287 if ((insn
& 0x0e500000) != 0x04100000)
1289 if (bits (insn
, 16, 19) != basereg
)
1291 destreg
= bits (insn
, 12, 15);
1292 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1293 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1294 4, byte_order_for_code
);
1295 if ((insn
& 0x0e500000) != 0x04000000)
1297 if (bits (insn
, 12, 15) != destreg
)
1300 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1303 return pc
+ offset
+ 4;
1305 return pc
+ offset
+ 8;
1308 /* Advance the PC across any function entry prologue instructions to
1309 reach some "real" code.
1311 The APCS (ARM Procedure Call Standard) defines the following
1315 [stmfd sp!, {a1,a2,a3,a4}]
1316 stmfd sp!, {...,fp,ip,lr,pc}
1317 [stfe f7, [sp, #-12]!]
1318 [stfe f6, [sp, #-12]!]
1319 [stfe f5, [sp, #-12]!]
1320 [stfe f4, [sp, #-12]!]
1321 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1324 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1326 CORE_ADDR func_addr
, limit_pc
;
1328 /* See if we can determine the end of the prologue via the symbol table.
1329 If so, then return either PC, or the PC after the prologue, whichever
1331 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1333 CORE_ADDR post_prologue_pc
1334 = skip_prologue_using_sal (gdbarch
, func_addr
);
1335 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1337 if (post_prologue_pc
)
1339 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1342 /* GCC always emits a line note before the prologue and another
1343 one after, even if the two are at the same address or on the
1344 same line. Take advantage of this so that we do not need to
1345 know every instruction that might appear in the prologue. We
1346 will have producer information for most binaries; if it is
1347 missing (e.g. for -gstabs), assuming the GNU tools. */
1348 if (post_prologue_pc
1350 || COMPUNIT_PRODUCER (cust
) == NULL
1351 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1352 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1353 return post_prologue_pc
;
1355 if (post_prologue_pc
!= 0)
1357 CORE_ADDR analyzed_limit
;
1359 /* For non-GCC compilers, make sure the entire line is an
1360 acceptable prologue; GDB will round this function's
1361 return value up to the end of the following line so we
1362 can not skip just part of a line (and we do not want to).
1364 RealView does not treat the prologue specially, but does
1365 associate prologue code with the opening brace; so this
1366 lets us skip the first line if we think it is the opening
1368 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1369 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1370 post_prologue_pc
, NULL
);
1372 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1373 post_prologue_pc
, NULL
);
1375 if (analyzed_limit
!= post_prologue_pc
)
1378 return post_prologue_pc
;
1382 /* Can't determine prologue from the symbol table, need to examine
1385 /* Find an upper limit on the function prologue using the debug
1386 information. If the debug information could not be used to provide
1387 that bound, then use an arbitrary large number as the upper bound. */
1388 /* Like arm_scan_prologue, stop no later than pc + 64. */
1389 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1391 limit_pc
= pc
+ 64; /* Magic. */
1394 /* Check if this is Thumb code. */
1395 if (arm_pc_is_thumb (gdbarch
, pc
))
1396 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1398 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1402 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1403 This function decodes a Thumb function prologue to determine:
1404 1) the size of the stack frame
1405 2) which registers are saved on it
1406 3) the offsets of saved regs
1407 4) the offset from the stack pointer to the frame pointer
1409 A typical Thumb function prologue would create this stack frame
1410 (offsets relative to FP)
1411 old SP -> 24 stack parameters
1414 R7 -> 0 local variables (16 bytes)
1415 SP -> -12 additional stack space (12 bytes)
1416 The frame size would thus be 36 bytes, and the frame offset would be
1417 12 bytes. The frame register is R7.
1419 The comments for thumb_skip_prolog() describe the algorithm we use
1420 to detect the end of the prolog. */
1424 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1425 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1427 CORE_ADDR prologue_start
;
1428 CORE_ADDR prologue_end
;
1430 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1433 /* See comment in arm_scan_prologue for an explanation of
1435 if (prologue_end
> prologue_start
+ 64)
1437 prologue_end
= prologue_start
+ 64;
1441 /* We're in the boondocks: we have no idea where the start of the
1445 prologue_end
= std::min (prologue_end
, prev_pc
);
1447 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1450 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1454 arm_instruction_restores_sp (unsigned int insn
)
1456 if (bits (insn
, 28, 31) != INST_NV
)
1458 if ((insn
& 0x0df0f000) == 0x0080d000
1459 /* ADD SP (register or immediate). */
1460 || (insn
& 0x0df0f000) == 0x0040d000
1461 /* SUB SP (register or immediate). */
1462 || (insn
& 0x0ffffff0) == 0x01a0d000
1464 || (insn
& 0x0fff0000) == 0x08bd0000
1466 || (insn
& 0x0fff0000) == 0x049d0000)
1467 /* POP of a single register. */
1474 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1475 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1476 fill it in. Return the first address not recognized as a prologue
1479 We recognize all the instructions typically found in ARM prologues,
1480 plus harmless instructions which can be skipped (either for analysis
1481 purposes, or a more restrictive set that can be skipped when finding
1482 the end of the prologue). */
1485 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1486 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1487 struct arm_prologue_cache
*cache
)
1489 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1491 CORE_ADDR offset
, current_pc
;
1492 pv_t regs
[ARM_FPS_REGNUM
];
1493 struct pv_area
*stack
;
1494 struct cleanup
*back_to
;
1495 CORE_ADDR unrecognized_pc
= 0;
1497 /* Search the prologue looking for instructions that set up the
1498 frame pointer, adjust the stack pointer, and save registers.
1500 Be careful, however, and if it doesn't look like a prologue,
1501 don't try to scan it. If, for instance, a frameless function
1502 begins with stmfd sp!, then we will tell ourselves there is
1503 a frame, which will confuse stack traceback, as well as "finish"
1504 and other operations that rely on a knowledge of the stack
1507 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1508 regs
[regno
] = pv_register (regno
, 0);
1509 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1510 back_to
= make_cleanup_free_pv_area (stack
);
1512 for (current_pc
= prologue_start
;
1513 current_pc
< prologue_end
;
1517 = read_code_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1519 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1521 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1524 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1525 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1527 unsigned imm
= insn
& 0xff; /* immediate value */
1528 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1529 int rd
= bits (insn
, 12, 15);
1530 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1531 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1534 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1535 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1537 unsigned imm
= insn
& 0xff; /* immediate value */
1538 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1539 int rd
= bits (insn
, 12, 15);
1540 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1541 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1544 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1547 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1549 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1550 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1551 regs
[bits (insn
, 12, 15)]);
1554 else if ((insn
& 0xffff0000) == 0xe92d0000)
1555 /* stmfd sp!, {..., fp, ip, lr, pc}
1557 stmfd sp!, {a1, a2, a3, a4} */
1559 int mask
= insn
& 0xffff;
1561 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1564 /* Calculate offsets of saved registers. */
1565 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1566 if (mask
& (1 << regno
))
1569 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1570 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1573 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1574 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1575 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1577 /* No need to add this to saved_regs -- it's just an arg reg. */
1580 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1581 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1582 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1584 /* No need to add this to saved_regs -- it's just an arg reg. */
1587 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1589 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1591 /* No need to add this to saved_regs -- it's just arg regs. */
1594 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1596 unsigned imm
= insn
& 0xff; /* immediate value */
1597 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1598 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1599 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1601 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1603 unsigned imm
= insn
& 0xff; /* immediate value */
1604 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1605 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1606 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1608 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1610 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1612 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1615 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1616 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1617 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1619 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1621 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1623 int n_saved_fp_regs
;
1624 unsigned int fp_start_reg
, fp_bound_reg
;
1626 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1629 if ((insn
& 0x800) == 0x800) /* N0 is set */
1631 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1632 n_saved_fp_regs
= 3;
1634 n_saved_fp_regs
= 1;
1638 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1639 n_saved_fp_regs
= 2;
1641 n_saved_fp_regs
= 4;
1644 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1645 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1646 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1648 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1649 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1650 regs
[fp_start_reg
++]);
1653 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1655 /* Allow some special function calls when skipping the
1656 prologue; GCC generates these before storing arguments to
1658 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1660 if (skip_prologue_function (gdbarch
, dest
, 0))
1665 else if ((insn
& 0xf0000000) != 0xe0000000)
1666 break; /* Condition not true, exit early. */
1667 else if (arm_instruction_changes_pc (insn
))
1668 /* Don't scan past anything that might change control flow. */
1670 else if (arm_instruction_restores_sp (insn
))
1672 /* Don't scan past the epilogue. */
1675 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1676 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1677 /* Ignore block loads from the stack, potentially copying
1678 parameters from memory. */
1680 else if ((insn
& 0xfc500000) == 0xe4100000
1681 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1682 /* Similarly ignore single loads from the stack. */
1684 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1685 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1686 register instead of the stack. */
1690 /* The optimizer might shove anything into the prologue, if
1691 we build up cache (cache != NULL) from scanning prologue,
1692 we just skip what we don't recognize and scan further to
1693 make cache as complete as possible. However, if we skip
1694 prologue, we'll stop immediately on unrecognized
1696 unrecognized_pc
= current_pc
;
1704 if (unrecognized_pc
== 0)
1705 unrecognized_pc
= current_pc
;
1709 int framereg
, framesize
;
1711 /* The frame size is just the distance from the frame register
1712 to the original stack pointer. */
1713 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1715 /* Frame pointer is fp. */
1716 framereg
= ARM_FP_REGNUM
;
1717 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1721 /* Try the stack pointer... this is a bit desperate. */
1722 framereg
= ARM_SP_REGNUM
;
1723 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1726 cache
->framereg
= framereg
;
1727 cache
->framesize
= framesize
;
1729 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1730 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1731 cache
->saved_regs
[regno
].addr
= offset
;
1735 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1736 paddress (gdbarch
, unrecognized_pc
));
1738 do_cleanups (back_to
);
1739 return unrecognized_pc
;
1743 arm_scan_prologue (struct frame_info
*this_frame
,
1744 struct arm_prologue_cache
*cache
)
1746 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1747 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1748 CORE_ADDR prologue_start
, prologue_end
;
1749 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1750 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1752 /* Assume there is no frame until proven otherwise. */
1753 cache
->framereg
= ARM_SP_REGNUM
;
1754 cache
->framesize
= 0;
1756 /* Check for Thumb prologue. */
1757 if (arm_frame_is_thumb (this_frame
))
1759 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1763 /* Find the function prologue. If we can't find the function in
1764 the symbol table, peek in the stack frame to find the PC. */
1765 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1768 /* One way to find the end of the prologue (which works well
1769 for unoptimized code) is to do the following:
1771 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1774 prologue_end = prev_pc;
1775 else if (sal.end < prologue_end)
1776 prologue_end = sal.end;
1778 This mechanism is very accurate so long as the optimizer
1779 doesn't move any instructions from the function body into the
1780 prologue. If this happens, sal.end will be the last
1781 instruction in the first hunk of prologue code just before
1782 the first instruction that the scheduler has moved from
1783 the body to the prologue.
1785 In order to make sure that we scan all of the prologue
1786 instructions, we use a slightly less accurate mechanism which
1787 may scan more than necessary. To help compensate for this
1788 lack of accuracy, the prologue scanning loop below contains
1789 several clauses which'll cause the loop to terminate early if
1790 an implausible prologue instruction is encountered.
1796 is a suitable endpoint since it accounts for the largest
1797 possible prologue plus up to five instructions inserted by
1800 if (prologue_end
> prologue_start
+ 64)
1802 prologue_end
= prologue_start
+ 64; /* See above. */
1807 /* We have no symbol information. Our only option is to assume this
1808 function has a standard stack frame and the normal frame register.
1809 Then, we can find the value of our frame pointer on entrance to
1810 the callee (or at the present moment if this is the innermost frame).
1811 The value stored there should be the address of the stmfd + 8. */
1812 CORE_ADDR frame_loc
;
1813 ULONGEST return_value
;
1815 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1816 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
1821 prologue_start
= gdbarch_addr_bits_remove
1822 (gdbarch
, return_value
) - 8;
1823 prologue_end
= prologue_start
+ 64; /* See above. */
1827 if (prev_pc
< prologue_end
)
1828 prologue_end
= prev_pc
;
1830 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1833 static struct arm_prologue_cache
*
1834 arm_make_prologue_cache (struct frame_info
*this_frame
)
1837 struct arm_prologue_cache
*cache
;
1838 CORE_ADDR unwound_fp
;
1840 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1841 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1843 arm_scan_prologue (this_frame
, cache
);
1845 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1846 if (unwound_fp
== 0)
1849 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1851 /* Calculate actual addresses of saved registers using offsets
1852 determined by arm_scan_prologue. */
1853 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1854 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1855 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1860 /* Implementation of the stop_reason hook for arm_prologue frames. */
1862 static enum unwind_stop_reason
1863 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1866 struct arm_prologue_cache
*cache
;
1869 if (*this_cache
== NULL
)
1870 *this_cache
= arm_make_prologue_cache (this_frame
);
1871 cache
= (struct arm_prologue_cache
*) *this_cache
;
1873 /* This is meant to halt the backtrace at "_start". */
1874 pc
= get_frame_pc (this_frame
);
1875 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1876 return UNWIND_OUTERMOST
;
1878 /* If we've hit a wall, stop. */
1879 if (cache
->prev_sp
== 0)
1880 return UNWIND_OUTERMOST
;
1882 return UNWIND_NO_REASON
;
1885 /* Our frame ID for a normal frame is the current function's starting PC
1886 and the caller's SP when we were called. */
1889 arm_prologue_this_id (struct frame_info
*this_frame
,
1891 struct frame_id
*this_id
)
1893 struct arm_prologue_cache
*cache
;
1897 if (*this_cache
== NULL
)
1898 *this_cache
= arm_make_prologue_cache (this_frame
);
1899 cache
= (struct arm_prologue_cache
*) *this_cache
;
1901 /* Use function start address as part of the frame ID. If we cannot
1902 identify the start address (due to missing symbol information),
1903 fall back to just using the current PC. */
1904 pc
= get_frame_pc (this_frame
);
1905 func
= get_frame_func (this_frame
);
1909 id
= frame_id_build (cache
->prev_sp
, func
);
1913 static struct value
*
1914 arm_prologue_prev_register (struct frame_info
*this_frame
,
1918 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1919 struct arm_prologue_cache
*cache
;
1921 if (*this_cache
== NULL
)
1922 *this_cache
= arm_make_prologue_cache (this_frame
);
1923 cache
= (struct arm_prologue_cache
*) *this_cache
;
1925 /* If we are asked to unwind the PC, then we need to return the LR
1926 instead. The prologue may save PC, but it will point into this
1927 frame's prologue, not the next frame's resume location. Also
1928 strip the saved T bit. A valid LR may have the low bit set, but
1929 a valid PC never does. */
1930 if (prev_regnum
== ARM_PC_REGNUM
)
1934 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1935 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1936 arm_addr_bits_remove (gdbarch
, lr
));
1939 /* SP is generally not saved to the stack, but this frame is
1940 identified by the next frame's stack pointer at the time of the call.
1941 The value was already reconstructed into PREV_SP. */
1942 if (prev_regnum
== ARM_SP_REGNUM
)
1943 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1945 /* The CPSR may have been changed by the call instruction and by the
1946 called function. The only bit we can reconstruct is the T bit,
1947 by checking the low bit of LR as of the call. This is a reliable
1948 indicator of Thumb-ness except for some ARM v4T pre-interworking
1949 Thumb code, which could get away with a clear low bit as long as
1950 the called function did not use bx. Guess that all other
1951 bits are unchanged; the condition flags are presumably lost,
1952 but the processor status is likely valid. */
1953 if (prev_regnum
== ARM_PS_REGNUM
)
1956 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1958 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1959 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1960 if (IS_THUMB_ADDR (lr
))
1964 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1967 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1971 struct frame_unwind arm_prologue_unwind
= {
1973 arm_prologue_unwind_stop_reason
,
1974 arm_prologue_this_id
,
1975 arm_prologue_prev_register
,
1977 default_frame_sniffer
1980 /* Maintain a list of ARM exception table entries per objfile, similar to the
1981 list of mapping symbols. We only cache entries for standard ARM-defined
1982 personality routines; the cache will contain only the frame unwinding
1983 instructions associated with the entry (not the descriptors). */
1985 static const struct objfile_data
*arm_exidx_data_key
;
1987 struct arm_exidx_entry
1992 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1993 DEF_VEC_O(arm_exidx_entry_s
);
1995 struct arm_exidx_data
1997 VEC(arm_exidx_entry_s
) **section_maps
;
2001 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2003 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2006 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2007 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2011 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2012 const struct arm_exidx_entry
*rhs
)
2014 return lhs
->addr
< rhs
->addr
;
2017 static struct obj_section
*
2018 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2020 struct obj_section
*osect
;
2022 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2023 if (bfd_get_section_flags (objfile
->obfd
,
2024 osect
->the_bfd_section
) & SEC_ALLOC
)
2026 bfd_vma start
, size
;
2027 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2028 size
= bfd_get_section_size (osect
->the_bfd_section
);
2030 if (start
<= vma
&& vma
< start
+ size
)
2037 /* Parse contents of exception table and exception index sections
2038 of OBJFILE, and fill in the exception table entry cache.
2040 For each entry that refers to a standard ARM-defined personality
2041 routine, extract the frame unwinding instructions (from either
2042 the index or the table section). The unwinding instructions
2044 - extracting them from the rest of the table data
2045 - converting to host endianness
2046 - appending the implicit 0xb0 ("Finish") code
2048 The extracted and normalized instructions are stored for later
2049 retrieval by the arm_find_exidx_entry routine. */
2052 arm_exidx_new_objfile (struct objfile
*objfile
)
2054 struct cleanup
*cleanups
;
2055 struct arm_exidx_data
*data
;
2056 asection
*exidx
, *extab
;
2057 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2058 bfd_size_type exidx_size
= 0, extab_size
= 0;
2059 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2062 /* If we've already touched this file, do nothing. */
2063 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2065 cleanups
= make_cleanup (null_cleanup
, NULL
);
2067 /* Read contents of exception table and index. */
2068 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2071 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2072 exidx_size
= bfd_get_section_size (exidx
);
2073 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2074 make_cleanup (xfree
, exidx_data
);
2076 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2077 exidx_data
, 0, exidx_size
))
2079 do_cleanups (cleanups
);
2084 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2087 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2088 extab_size
= bfd_get_section_size (extab
);
2089 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2090 make_cleanup (xfree
, extab_data
);
2092 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2093 extab_data
, 0, extab_size
))
2095 do_cleanups (cleanups
);
2100 /* Allocate exception table data structure. */
2101 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2102 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2103 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2104 objfile
->obfd
->section_count
,
2105 VEC(arm_exidx_entry_s
) *);
2107 /* Fill in exception table. */
2108 for (i
= 0; i
< exidx_size
/ 8; i
++)
2110 struct arm_exidx_entry new_exidx_entry
;
2111 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2112 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2113 bfd_vma addr
= 0, word
= 0;
2114 int n_bytes
= 0, n_words
= 0;
2115 struct obj_section
*sec
;
2116 gdb_byte
*entry
= NULL
;
2118 /* Extract address of start of function. */
2119 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2120 idx
+= exidx_vma
+ i
* 8;
2122 /* Find section containing function and compute section offset. */
2123 sec
= arm_obj_section_from_vma (objfile
, idx
);
2126 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2128 /* Determine address of exception table entry. */
2131 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2133 else if ((val
& 0xff000000) == 0x80000000)
2135 /* Exception table entry embedded in .ARM.exidx
2136 -- must be short form. */
2140 else if (!(val
& 0x80000000))
2142 /* Exception table entry in .ARM.extab. */
2143 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2144 addr
+= exidx_vma
+ i
* 8 + 4;
2146 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2148 word
= bfd_h_get_32 (objfile
->obfd
,
2149 extab_data
+ addr
- extab_vma
);
2152 if ((word
& 0xff000000) == 0x80000000)
2157 else if ((word
& 0xff000000) == 0x81000000
2158 || (word
& 0xff000000) == 0x82000000)
2162 n_words
= ((word
>> 16) & 0xff);
2164 else if (!(word
& 0x80000000))
2167 struct obj_section
*pers_sec
;
2168 int gnu_personality
= 0;
2170 /* Custom personality routine. */
2171 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2172 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2174 /* Check whether we've got one of the variants of the
2175 GNU personality routines. */
2176 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2179 static const char *personality
[] =
2181 "__gcc_personality_v0",
2182 "__gxx_personality_v0",
2183 "__gcj_personality_v0",
2184 "__gnu_objc_personality_v0",
2188 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2191 for (k
= 0; personality
[k
]; k
++)
2192 if (lookup_minimal_symbol_by_pc_name
2193 (pc
, personality
[k
], objfile
))
2195 gnu_personality
= 1;
2200 /* If so, the next word contains a word count in the high
2201 byte, followed by the same unwind instructions as the
2202 pre-defined forms. */
2204 && addr
+ 4 <= extab_vma
+ extab_size
)
2206 word
= bfd_h_get_32 (objfile
->obfd
,
2207 extab_data
+ addr
- extab_vma
);
2210 n_words
= ((word
>> 24) & 0xff);
2216 /* Sanity check address. */
2218 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2219 n_words
= n_bytes
= 0;
2221 /* The unwind instructions reside in WORD (only the N_BYTES least
2222 significant bytes are valid), followed by N_WORDS words in the
2223 extab section starting at ADDR. */
2224 if (n_bytes
|| n_words
)
2227 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2228 n_bytes
+ n_words
* 4 + 1);
2231 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2235 word
= bfd_h_get_32 (objfile
->obfd
,
2236 extab_data
+ addr
- extab_vma
);
2239 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2240 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2241 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2242 *p
++ = (gdb_byte
) (word
& 0xff);
2245 /* Implied "Finish" to terminate the list. */
2249 /* Push entry onto vector. They are guaranteed to always
2250 appear in order of increasing addresses. */
2251 new_exidx_entry
.addr
= idx
;
2252 new_exidx_entry
.entry
= entry
;
2253 VEC_safe_push (arm_exidx_entry_s
,
2254 data
->section_maps
[sec
->the_bfd_section
->index
],
2258 do_cleanups (cleanups
);
2261 /* Search for the exception table entry covering MEMADDR. If one is found,
2262 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2263 set *START to the start of the region covered by this entry. */
2266 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2268 struct obj_section
*sec
;
2270 sec
= find_pc_section (memaddr
);
2273 struct arm_exidx_data
*data
;
2274 VEC(arm_exidx_entry_s
) *map
;
2275 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2278 data
= ((struct arm_exidx_data
*)
2279 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2282 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2283 if (!VEC_empty (arm_exidx_entry_s
, map
))
2285 struct arm_exidx_entry
*map_sym
;
2287 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2288 arm_compare_exidx_entries
);
2290 /* VEC_lower_bound finds the earliest ordered insertion
2291 point. If the following symbol starts at this exact
2292 address, we use that; otherwise, the preceding
2293 exception table entry covers this address. */
2294 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2296 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2297 if (map_sym
->addr
== map_key
.addr
)
2300 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2301 return map_sym
->entry
;
2307 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2309 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2310 return map_sym
->entry
;
2319 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2320 instruction list from the ARM exception table entry ENTRY, allocate and
2321 return a prologue cache structure describing how to unwind this frame.
2323 Return NULL if the unwinding instruction list contains a "spare",
2324 "reserved" or "refuse to unwind" instruction as defined in section
2325 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2326 for the ARM Architecture" document. */
2328 static struct arm_prologue_cache
*
2329 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2334 struct arm_prologue_cache
*cache
;
2335 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2336 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2342 /* Whenever we reload SP, we actually have to retrieve its
2343 actual value in the current frame. */
2346 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2348 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2349 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2353 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2354 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2360 /* Decode next unwind instruction. */
2363 if ((insn
& 0xc0) == 0)
2365 int offset
= insn
& 0x3f;
2366 vsp
+= (offset
<< 2) + 4;
2368 else if ((insn
& 0xc0) == 0x40)
2370 int offset
= insn
& 0x3f;
2371 vsp
-= (offset
<< 2) + 4;
2373 else if ((insn
& 0xf0) == 0x80)
2375 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2378 /* The special case of an all-zero mask identifies
2379 "Refuse to unwind". We return NULL to fall back
2380 to the prologue analyzer. */
2384 /* Pop registers r4..r15 under mask. */
2385 for (i
= 0; i
< 12; i
++)
2386 if (mask
& (1 << i
))
2388 cache
->saved_regs
[4 + i
].addr
= vsp
;
2392 /* Special-case popping SP -- we need to reload vsp. */
2393 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2396 else if ((insn
& 0xf0) == 0x90)
2398 int reg
= insn
& 0xf;
2400 /* Reserved cases. */
2401 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2404 /* Set SP from another register and mark VSP for reload. */
2405 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2408 else if ((insn
& 0xf0) == 0xa0)
2410 int count
= insn
& 0x7;
2411 int pop_lr
= (insn
& 0x8) != 0;
2414 /* Pop r4..r[4+count]. */
2415 for (i
= 0; i
<= count
; i
++)
2417 cache
->saved_regs
[4 + i
].addr
= vsp
;
2421 /* If indicated by flag, pop LR as well. */
2424 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2428 else if (insn
== 0xb0)
2430 /* We could only have updated PC by popping into it; if so, it
2431 will show up as address. Otherwise, copy LR into PC. */
2432 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2433 cache
->saved_regs
[ARM_PC_REGNUM
]
2434 = cache
->saved_regs
[ARM_LR_REGNUM
];
2439 else if (insn
== 0xb1)
2441 int mask
= *entry
++;
2444 /* All-zero mask and mask >= 16 is "spare". */
2445 if (mask
== 0 || mask
>= 16)
2448 /* Pop r0..r3 under mask. */
2449 for (i
= 0; i
< 4; i
++)
2450 if (mask
& (1 << i
))
2452 cache
->saved_regs
[i
].addr
= vsp
;
2456 else if (insn
== 0xb2)
2458 ULONGEST offset
= 0;
2463 offset
|= (*entry
& 0x7f) << shift
;
2466 while (*entry
++ & 0x80);
2468 vsp
+= 0x204 + (offset
<< 2);
2470 else if (insn
== 0xb3)
2472 int start
= *entry
>> 4;
2473 int count
= (*entry
++) & 0xf;
2476 /* Only registers D0..D15 are valid here. */
2477 if (start
+ count
>= 16)
2480 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2481 for (i
= 0; i
<= count
; i
++)
2483 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2487 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2490 else if ((insn
& 0xf8) == 0xb8)
2492 int count
= insn
& 0x7;
2495 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2496 for (i
= 0; i
<= count
; i
++)
2498 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2502 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2505 else if (insn
== 0xc6)
2507 int start
= *entry
>> 4;
2508 int count
= (*entry
++) & 0xf;
2511 /* Only registers WR0..WR15 are valid. */
2512 if (start
+ count
>= 16)
2515 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2516 for (i
= 0; i
<= count
; i
++)
2518 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2522 else if (insn
== 0xc7)
2524 int mask
= *entry
++;
2527 /* All-zero mask and mask >= 16 is "spare". */
2528 if (mask
== 0 || mask
>= 16)
2531 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2532 for (i
= 0; i
< 4; i
++)
2533 if (mask
& (1 << i
))
2535 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2539 else if ((insn
& 0xf8) == 0xc0)
2541 int count
= insn
& 0x7;
2544 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2545 for (i
= 0; i
<= count
; i
++)
2547 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2551 else if (insn
== 0xc8)
2553 int start
= *entry
>> 4;
2554 int count
= (*entry
++) & 0xf;
2557 /* Only registers D0..D31 are valid. */
2558 if (start
+ count
>= 16)
2561 /* Pop VFP double-precision registers
2562 D[16+start]..D[16+start+count]. */
2563 for (i
= 0; i
<= count
; i
++)
2565 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2569 else if (insn
== 0xc9)
2571 int start
= *entry
>> 4;
2572 int count
= (*entry
++) & 0xf;
2575 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2576 for (i
= 0; i
<= count
; i
++)
2578 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2582 else if ((insn
& 0xf8) == 0xd0)
2584 int count
= insn
& 0x7;
2587 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2588 for (i
= 0; i
<= count
; i
++)
2590 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2596 /* Everything else is "spare". */
2601 /* If we restore SP from a register, assume this was the frame register.
2602 Otherwise just fall back to SP as frame register. */
2603 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2604 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2606 cache
->framereg
= ARM_SP_REGNUM
;
2608 /* Determine offset to previous frame. */
2610 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2612 /* We already got the previous SP. */
2613 cache
->prev_sp
= vsp
;
2618 /* Unwinding via ARM exception table entries. Note that the sniffer
2619 already computes a filled-in prologue cache, which is then used
2620 with the same arm_prologue_this_id and arm_prologue_prev_register
2621 routines also used for prologue-parsing based unwinding. */
2624 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2625 struct frame_info
*this_frame
,
2626 void **this_prologue_cache
)
2628 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2629 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2630 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2631 struct arm_prologue_cache
*cache
;
2634 /* See if we have an ARM exception table entry covering this address. */
2635 addr_in_block
= get_frame_address_in_block (this_frame
);
2636 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2640 /* The ARM exception table does not describe unwind information
2641 for arbitrary PC values, but is guaranteed to be correct only
2642 at call sites. We have to decide here whether we want to use
2643 ARM exception table information for this frame, or fall back
2644 to using prologue parsing. (Note that if we have DWARF CFI,
2645 this sniffer isn't even called -- CFI is always preferred.)
2647 Before we make this decision, however, we check whether we
2648 actually have *symbol* information for the current frame.
2649 If not, prologue parsing would not work anyway, so we might
2650 as well use the exception table and hope for the best. */
2651 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2655 /* If the next frame is "normal", we are at a call site in this
2656 frame, so exception information is guaranteed to be valid. */
2657 if (get_next_frame (this_frame
)
2658 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2661 /* We also assume exception information is valid if we're currently
2662 blocked in a system call. The system library is supposed to
2663 ensure this, so that e.g. pthread cancellation works. */
2664 if (arm_frame_is_thumb (this_frame
))
2668 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
2669 2, byte_order_for_code
, &insn
)
2670 && (insn
& 0xff00) == 0xdf00 /* svc */)
2677 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
2678 4, byte_order_for_code
, &insn
)
2679 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2683 /* Bail out if we don't know that exception information is valid. */
2687 /* The ARM exception index does not mark the *end* of the region
2688 covered by the entry, and some functions will not have any entry.
2689 To correctly recognize the end of the covered region, the linker
2690 should have inserted dummy records with a CANTUNWIND marker.
2692 Unfortunately, current versions of GNU ld do not reliably do
2693 this, and thus we may have found an incorrect entry above.
2694 As a (temporary) sanity check, we only use the entry if it
2695 lies *within* the bounds of the function. Note that this check
2696 might reject perfectly valid entries that just happen to cover
2697 multiple functions; therefore this check ought to be removed
2698 once the linker is fixed. */
2699 if (func_start
> exidx_region
)
2703 /* Decode the list of unwinding instructions into a prologue cache.
2704 Note that this may fail due to e.g. a "refuse to unwind" code. */
2705 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2709 *this_prologue_cache
= cache
;
2713 struct frame_unwind arm_exidx_unwind
= {
2715 default_frame_unwind_stop_reason
,
2716 arm_prologue_this_id
,
2717 arm_prologue_prev_register
,
2719 arm_exidx_unwind_sniffer
2722 static struct arm_prologue_cache
*
2723 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2725 struct arm_prologue_cache
*cache
;
2728 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2729 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2731 /* Still rely on the offset calculated from prologue. */
2732 arm_scan_prologue (this_frame
, cache
);
2734 /* Since we are in epilogue, the SP has been restored. */
2735 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2737 /* Calculate actual addresses of saved registers using offsets
2738 determined by arm_scan_prologue. */
2739 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2740 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2741 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2746 /* Implementation of function hook 'this_id' in
2747 'struct frame_uwnind' for epilogue unwinder. */
2750 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2752 struct frame_id
*this_id
)
2754 struct arm_prologue_cache
*cache
;
2757 if (*this_cache
== NULL
)
2758 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2759 cache
= (struct arm_prologue_cache
*) *this_cache
;
2761 /* Use function start address as part of the frame ID. If we cannot
2762 identify the start address (due to missing symbol information),
2763 fall back to just using the current PC. */
2764 pc
= get_frame_pc (this_frame
);
2765 func
= get_frame_func (this_frame
);
2769 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2772 /* Implementation of function hook 'prev_register' in
2773 'struct frame_uwnind' for epilogue unwinder. */
2775 static struct value
*
2776 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2777 void **this_cache
, int regnum
)
2779 if (*this_cache
== NULL
)
2780 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2782 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2785 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2787 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2790 /* Implementation of function hook 'sniffer' in
2791 'struct frame_uwnind' for epilogue unwinder. */
2794 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2795 struct frame_info
*this_frame
,
2796 void **this_prologue_cache
)
2798 if (frame_relative_level (this_frame
) == 0)
2800 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2801 CORE_ADDR pc
= get_frame_pc (this_frame
);
2803 if (arm_frame_is_thumb (this_frame
))
2804 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2806 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2812 /* Frame unwinder from epilogue. */
2814 static const struct frame_unwind arm_epilogue_frame_unwind
=
2817 default_frame_unwind_stop_reason
,
2818 arm_epilogue_frame_this_id
,
2819 arm_epilogue_frame_prev_register
,
2821 arm_epilogue_frame_sniffer
,
2824 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2825 trampoline, return the target PC. Otherwise return 0.
2827 void call0a (char c, short s, int i, long l) {}
2831 (*pointer_to_call0a) (c, s, i, l);
2834 Instead of calling a stub library function _call_via_xx (xx is
2835 the register name), GCC may inline the trampoline in the object
2836 file as below (register r2 has the address of call0a).
2839 .type main, %function
2848 The trampoline 'bx r2' doesn't belong to main. */
2851 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2853 /* The heuristics of recognizing such trampoline is that FRAME is
2854 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2855 if (arm_frame_is_thumb (frame
))
2859 if (target_read_memory (pc
, buf
, 2) == 0)
2861 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2862 enum bfd_endian byte_order_for_code
2863 = gdbarch_byte_order_for_code (gdbarch
);
2865 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2867 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2870 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2872 /* Clear the LSB so that gdb core sets step-resume
2873 breakpoint at the right address. */
2874 return UNMAKE_THUMB_ADDR (dest
);
2882 static struct arm_prologue_cache
*
2883 arm_make_stub_cache (struct frame_info
*this_frame
)
2885 struct arm_prologue_cache
*cache
;
2887 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2888 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2890 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2895 /* Our frame ID for a stub frame is the current SP and LR. */
2898 arm_stub_this_id (struct frame_info
*this_frame
,
2900 struct frame_id
*this_id
)
2902 struct arm_prologue_cache
*cache
;
2904 if (*this_cache
== NULL
)
2905 *this_cache
= arm_make_stub_cache (this_frame
);
2906 cache
= (struct arm_prologue_cache
*) *this_cache
;
2908 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2912 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2913 struct frame_info
*this_frame
,
2914 void **this_prologue_cache
)
2916 CORE_ADDR addr_in_block
;
2918 CORE_ADDR pc
, start_addr
;
2921 addr_in_block
= get_frame_address_in_block (this_frame
);
2922 pc
= get_frame_pc (this_frame
);
2923 if (in_plt_section (addr_in_block
)
2924 /* We also use the stub winder if the target memory is unreadable
2925 to avoid having the prologue unwinder trying to read it. */
2926 || target_read_memory (pc
, dummy
, 4) != 0)
2929 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2930 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2936 struct frame_unwind arm_stub_unwind
= {
2938 default_frame_unwind_stop_reason
,
2940 arm_prologue_prev_register
,
2942 arm_stub_unwind_sniffer
2945 /* Put here the code to store, into CACHE->saved_regs, the addresses
2946 of the saved registers of frame described by THIS_FRAME. CACHE is
2949 static struct arm_prologue_cache
*
2950 arm_m_exception_cache (struct frame_info
*this_frame
)
2952 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2953 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2954 struct arm_prologue_cache
*cache
;
2955 CORE_ADDR unwound_sp
;
2958 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2959 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2961 unwound_sp
= get_frame_register_unsigned (this_frame
,
2964 /* The hardware saves eight 32-bit words, comprising xPSR,
2965 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2966 "B1.5.6 Exception entry behavior" in
2967 "ARMv7-M Architecture Reference Manual". */
2968 cache
->saved_regs
[0].addr
= unwound_sp
;
2969 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2970 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2971 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2972 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2973 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2974 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2975 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2977 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2978 aligner between the top of the 32-byte stack frame and the
2979 previous context's stack pointer. */
2980 cache
->prev_sp
= unwound_sp
+ 32;
2981 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2982 && (xpsr
& (1 << 9)) != 0)
2983 cache
->prev_sp
+= 4;
2988 /* Implementation of function hook 'this_id' in
2989 'struct frame_uwnind'. */
2992 arm_m_exception_this_id (struct frame_info
*this_frame
,
2994 struct frame_id
*this_id
)
2996 struct arm_prologue_cache
*cache
;
2998 if (*this_cache
== NULL
)
2999 *this_cache
= arm_m_exception_cache (this_frame
);
3000 cache
= (struct arm_prologue_cache
*) *this_cache
;
3002 /* Our frame ID for a stub frame is the current SP and LR. */
3003 *this_id
= frame_id_build (cache
->prev_sp
,
3004 get_frame_pc (this_frame
));
3007 /* Implementation of function hook 'prev_register' in
3008 'struct frame_uwnind'. */
3010 static struct value
*
3011 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3015 struct arm_prologue_cache
*cache
;
3017 if (*this_cache
== NULL
)
3018 *this_cache
= arm_m_exception_cache (this_frame
);
3019 cache
= (struct arm_prologue_cache
*) *this_cache
;
3021 /* The value was already reconstructed into PREV_SP. */
3022 if (prev_regnum
== ARM_SP_REGNUM
)
3023 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3026 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3030 /* Implementation of function hook 'sniffer' in
3031 'struct frame_uwnind'. */
3034 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3035 struct frame_info
*this_frame
,
3036 void **this_prologue_cache
)
3038 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3040 /* No need to check is_m; this sniffer is only registered for
3041 M-profile architectures. */
3043 /* Check if exception frame returns to a magic PC value. */
3044 return arm_m_addr_is_magic (this_pc
);
3047 /* Frame unwinder for M-profile exceptions. */
3049 struct frame_unwind arm_m_exception_unwind
=
3052 default_frame_unwind_stop_reason
,
3053 arm_m_exception_this_id
,
3054 arm_m_exception_prev_register
,
3056 arm_m_exception_unwind_sniffer
3060 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3062 struct arm_prologue_cache
*cache
;
3064 if (*this_cache
== NULL
)
3065 *this_cache
= arm_make_prologue_cache (this_frame
);
3066 cache
= (struct arm_prologue_cache
*) *this_cache
;
3068 return cache
->prev_sp
- cache
->framesize
;
3071 struct frame_base arm_normal_base
= {
3072 &arm_prologue_unwind
,
3073 arm_normal_frame_base
,
3074 arm_normal_frame_base
,
3075 arm_normal_frame_base
3078 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3079 dummy frame. The frame ID's base needs to match the TOS value
3080 saved by save_dummy_frame_tos() and returned from
3081 arm_push_dummy_call, and the PC needs to match the dummy frame's
3084 static struct frame_id
3085 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3087 return frame_id_build (get_frame_register_unsigned (this_frame
,
3089 get_frame_pc (this_frame
));
3092 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3093 be used to construct the previous frame's ID, after looking up the
3094 containing function). */
3097 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3100 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3101 return arm_addr_bits_remove (gdbarch
, pc
);
3105 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3107 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3110 static struct value
*
3111 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3114 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3116 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3121 /* The PC is normally copied from the return column, which
3122 describes saves of LR. However, that version may have an
3123 extra bit set to indicate Thumb state. The bit is not
3125 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3126 return frame_unwind_got_constant (this_frame
, regnum
,
3127 arm_addr_bits_remove (gdbarch
, lr
));
3130 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3131 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3132 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3133 if (IS_THUMB_ADDR (lr
))
3137 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3140 internal_error (__FILE__
, __LINE__
,
3141 _("Unexpected register %d"), regnum
);
3146 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3147 struct dwarf2_frame_state_reg
*reg
,
3148 struct frame_info
*this_frame
)
3154 reg
->how
= DWARF2_FRAME_REG_FN
;
3155 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3158 reg
->how
= DWARF2_FRAME_REG_CFA
;
3163 /* Implement the stack_frame_destroyed_p gdbarch method. */
3166 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3168 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3169 unsigned int insn
, insn2
;
3170 int found_return
= 0, found_stack_adjust
= 0;
3171 CORE_ADDR func_start
, func_end
;
3175 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3178 /* The epilogue is a sequence of instructions along the following lines:
3180 - add stack frame size to SP or FP
3181 - [if frame pointer used] restore SP from FP
3182 - restore registers from SP [may include PC]
3183 - a return-type instruction [if PC wasn't already restored]
3185 In a first pass, we scan forward from the current PC and verify the
3186 instructions we find as compatible with this sequence, ending in a
3189 However, this is not sufficient to distinguish indirect function calls
3190 within a function from indirect tail calls in the epilogue in some cases.
3191 Therefore, if we didn't already find any SP-changing instruction during
3192 forward scan, we add a backward scanning heuristic to ensure we actually
3193 are in the epilogue. */
3196 while (scan_pc
< func_end
&& !found_return
)
3198 if (target_read_memory (scan_pc
, buf
, 2))
3202 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3204 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3206 else if (insn
== 0x46f7) /* mov pc, lr */
3208 else if (thumb_instruction_restores_sp (insn
))
3210 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3213 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3215 if (target_read_memory (scan_pc
, buf
, 2))
3219 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3221 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3223 if (insn2
& 0x8000) /* <registers> include PC. */
3226 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3227 && (insn2
& 0x0fff) == 0x0b04)
3229 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3232 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3233 && (insn2
& 0x0e00) == 0x0a00)
3245 /* Since any instruction in the epilogue sequence, with the possible
3246 exception of return itself, updates the stack pointer, we need to
3247 scan backwards for at most one instruction. Try either a 16-bit or
3248 a 32-bit instruction. This is just a heuristic, so we do not worry
3249 too much about false positives. */
3251 if (pc
- 4 < func_start
)
3253 if (target_read_memory (pc
- 4, buf
, 4))
3256 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3257 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3259 if (thumb_instruction_restores_sp (insn2
))
3260 found_stack_adjust
= 1;
3261 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3262 found_stack_adjust
= 1;
3263 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3264 && (insn2
& 0x0fff) == 0x0b04)
3265 found_stack_adjust
= 1;
3266 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3267 && (insn2
& 0x0e00) == 0x0a00)
3268 found_stack_adjust
= 1;
3270 return found_stack_adjust
;
3274 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3276 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3279 CORE_ADDR func_start
, func_end
;
3281 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3284 /* We are in the epilogue if the previous instruction was a stack
3285 adjustment and the next instruction is a possible return (bx, mov
3286 pc, or pop). We could have to scan backwards to find the stack
3287 adjustment, or forwards to find the return, but this is a decent
3288 approximation. First scan forwards. */
3291 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3292 if (bits (insn
, 28, 31) != INST_NV
)
3294 if ((insn
& 0x0ffffff0) == 0x012fff10)
3297 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3300 else if ((insn
& 0x0fff0000) == 0x08bd0000
3301 && (insn
& 0x0000c000) != 0)
3302 /* POP (LDMIA), including PC or LR. */
3309 /* Scan backwards. This is just a heuristic, so do not worry about
3310 false positives from mode changes. */
3312 if (pc
< func_start
+ 4)
3315 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3316 if (arm_instruction_restores_sp (insn
))
3322 /* Implement the stack_frame_destroyed_p gdbarch method. */
3325 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3327 if (arm_pc_is_thumb (gdbarch
, pc
))
3328 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3330 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3333 /* When arguments must be pushed onto the stack, they go on in reverse
3334 order. The code below implements a FILO (stack) to do this. */
3339 struct stack_item
*prev
;
3343 static struct stack_item
*
3344 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3346 struct stack_item
*si
;
3347 si
= XNEW (struct stack_item
);
3348 si
->data
= (gdb_byte
*) xmalloc (len
);
3351 memcpy (si
->data
, contents
, len
);
3355 static struct stack_item
*
3356 pop_stack_item (struct stack_item
*si
)
3358 struct stack_item
*dead
= si
;
3366 /* Return the alignment (in bytes) of the given type. */
3369 arm_type_align (struct type
*t
)
3375 t
= check_typedef (t
);
3376 switch (TYPE_CODE (t
))
3379 /* Should never happen. */
3380 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3384 case TYPE_CODE_ENUM
:
3388 case TYPE_CODE_RANGE
:
3390 case TYPE_CODE_CHAR
:
3391 case TYPE_CODE_BOOL
:
3392 return TYPE_LENGTH (t
);
3394 case TYPE_CODE_ARRAY
:
3395 if (TYPE_VECTOR (t
))
3397 /* Use the natural alignment for vector types (the same for
3398 scalar type), but the maximum alignment is 64-bit. */
3399 if (TYPE_LENGTH (t
) > 8)
3402 return TYPE_LENGTH (t
);
3405 return arm_type_align (TYPE_TARGET_TYPE (t
));
3406 case TYPE_CODE_COMPLEX
:
3407 return arm_type_align (TYPE_TARGET_TYPE (t
));
3409 case TYPE_CODE_STRUCT
:
3410 case TYPE_CODE_UNION
:
3412 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3414 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3422 /* Possible base types for a candidate for passing and returning in
3425 enum arm_vfp_cprc_base_type
3434 /* The length of one element of base type B. */
3437 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3441 case VFP_CPRC_SINGLE
:
3443 case VFP_CPRC_DOUBLE
:
3445 case VFP_CPRC_VEC64
:
3447 case VFP_CPRC_VEC128
:
3450 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3455 /* The character ('s', 'd' or 'q') for the type of VFP register used
3456 for passing base type B. */
3459 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3463 case VFP_CPRC_SINGLE
:
3465 case VFP_CPRC_DOUBLE
:
3467 case VFP_CPRC_VEC64
:
3469 case VFP_CPRC_VEC128
:
3472 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3477 /* Determine whether T may be part of a candidate for passing and
3478 returning in VFP registers, ignoring the limit on the total number
3479 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3480 classification of the first valid component found; if it is not
3481 VFP_CPRC_UNKNOWN, all components must have the same classification
3482 as *BASE_TYPE. If it is found that T contains a type not permitted
3483 for passing and returning in VFP registers, a type differently
3484 classified from *BASE_TYPE, or two types differently classified
3485 from each other, return -1, otherwise return the total number of
3486 base-type elements found (possibly 0 in an empty structure or
3487 array). Vector types are not currently supported, matching the
3488 generic AAPCS support. */
3491 arm_vfp_cprc_sub_candidate (struct type
*t
,
3492 enum arm_vfp_cprc_base_type
*base_type
)
3494 t
= check_typedef (t
);
3495 switch (TYPE_CODE (t
))
3498 switch (TYPE_LENGTH (t
))
3501 if (*base_type
== VFP_CPRC_UNKNOWN
)
3502 *base_type
= VFP_CPRC_SINGLE
;
3503 else if (*base_type
!= VFP_CPRC_SINGLE
)
3508 if (*base_type
== VFP_CPRC_UNKNOWN
)
3509 *base_type
= VFP_CPRC_DOUBLE
;
3510 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3519 case TYPE_CODE_COMPLEX
:
3520 /* Arguments of complex T where T is one of the types float or
3521 double get treated as if they are implemented as:
3530 switch (TYPE_LENGTH (t
))
3533 if (*base_type
== VFP_CPRC_UNKNOWN
)
3534 *base_type
= VFP_CPRC_SINGLE
;
3535 else if (*base_type
!= VFP_CPRC_SINGLE
)
3540 if (*base_type
== VFP_CPRC_UNKNOWN
)
3541 *base_type
= VFP_CPRC_DOUBLE
;
3542 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3551 case TYPE_CODE_ARRAY
:
3553 if (TYPE_VECTOR (t
))
3555 /* A 64-bit or 128-bit containerized vector type are VFP
3557 switch (TYPE_LENGTH (t
))
3560 if (*base_type
== VFP_CPRC_UNKNOWN
)
3561 *base_type
= VFP_CPRC_VEC64
;
3564 if (*base_type
== VFP_CPRC_UNKNOWN
)
3565 *base_type
= VFP_CPRC_VEC128
;
3576 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3580 if (TYPE_LENGTH (t
) == 0)
3582 gdb_assert (count
== 0);
3585 else if (count
== 0)
3587 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3588 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3589 return TYPE_LENGTH (t
) / unitlen
;
3594 case TYPE_CODE_STRUCT
:
3599 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3603 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3604 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3606 if (sub_count
== -1)
3610 if (TYPE_LENGTH (t
) == 0)
3612 gdb_assert (count
== 0);
3615 else if (count
== 0)
3617 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3618 if (TYPE_LENGTH (t
) != unitlen
* count
)
3623 case TYPE_CODE_UNION
:
3628 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3630 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3632 if (sub_count
== -1)
3634 count
= (count
> sub_count
? count
: sub_count
);
3636 if (TYPE_LENGTH (t
) == 0)
3638 gdb_assert (count
== 0);
3641 else if (count
== 0)
3643 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3644 if (TYPE_LENGTH (t
) != unitlen
* count
)
3656 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3657 if passed to or returned from a non-variadic function with the VFP
3658 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3659 *BASE_TYPE to the base type for T and *COUNT to the number of
3660 elements of that base type before returning. */
3663 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3666 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3667 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3668 if (c
<= 0 || c
> 4)
3675 /* Return 1 if the VFP ABI should be used for passing arguments to and
3676 returning values from a function of type FUNC_TYPE, 0
3680 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3682 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3683 /* Variadic functions always use the base ABI. Assume that functions
3684 without debug info are not variadic. */
3685 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3687 /* The VFP ABI is only supported as a variant of AAPCS. */
3688 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3690 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3693 /* We currently only support passing parameters in integer registers, which
3694 conforms with GCC's default model, and VFP argument passing following
3695 the VFP variant of AAPCS. Several other variants exist and
3696 we should probably support some of them based on the selected ABI. */
3699 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3700 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3701 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3702 CORE_ADDR struct_addr
)
3704 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3708 struct stack_item
*si
= NULL
;
3711 unsigned vfp_regs_free
= (1 << 16) - 1;
3713 /* Determine the type of this function and whether the VFP ABI
3715 ftype
= check_typedef (value_type (function
));
3716 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3717 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3718 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3720 /* Set the return address. For the ARM, the return breakpoint is
3721 always at BP_ADDR. */
3722 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3724 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3726 /* Walk through the list of args and determine how large a temporary
3727 stack is required. Need to take care here as structs may be
3728 passed on the stack, and we have to push them. */
3731 argreg
= ARM_A1_REGNUM
;
3734 /* The struct_return pointer occupies the first parameter
3735 passing register. */
3739 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3740 gdbarch_register_name (gdbarch
, argreg
),
3741 paddress (gdbarch
, struct_addr
));
3742 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3746 for (argnum
= 0; argnum
< nargs
; argnum
++)
3749 struct type
*arg_type
;
3750 struct type
*target_type
;
3751 enum type_code typecode
;
3752 const bfd_byte
*val
;
3754 enum arm_vfp_cprc_base_type vfp_base_type
;
3756 int may_use_core_reg
= 1;
3758 arg_type
= check_typedef (value_type (args
[argnum
]));
3759 len
= TYPE_LENGTH (arg_type
);
3760 target_type
= TYPE_TARGET_TYPE (arg_type
);
3761 typecode
= TYPE_CODE (arg_type
);
3762 val
= value_contents (args
[argnum
]);
3764 align
= arm_type_align (arg_type
);
3765 /* Round alignment up to a whole number of words. */
3766 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3767 /* Different ABIs have different maximum alignments. */
3768 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3770 /* The APCS ABI only requires word alignment. */
3771 align
= INT_REGISTER_SIZE
;
3775 /* The AAPCS requires at most doubleword alignment. */
3776 if (align
> INT_REGISTER_SIZE
* 2)
3777 align
= INT_REGISTER_SIZE
* 2;
3781 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3789 /* Because this is a CPRC it cannot go in a core register or
3790 cause a core register to be skipped for alignment.
3791 Either it goes in VFP registers and the rest of this loop
3792 iteration is skipped for this argument, or it goes on the
3793 stack (and the stack alignment code is correct for this
3795 may_use_core_reg
= 0;
3797 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3798 shift
= unit_length
/ 4;
3799 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3800 for (regno
= 0; regno
< 16; regno
+= shift
)
3801 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3810 vfp_regs_free
&= ~(mask
<< regno
);
3811 reg_scaled
= regno
/ shift
;
3812 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3813 for (i
= 0; i
< vfp_base_count
; i
++)
3817 if (reg_char
== 'q')
3818 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3819 val
+ i
* unit_length
);
3822 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3823 reg_char
, reg_scaled
+ i
);
3824 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3826 regcache_cooked_write (regcache
, regnum
,
3827 val
+ i
* unit_length
);
3834 /* This CPRC could not go in VFP registers, so all VFP
3835 registers are now marked as used. */
3840 /* Push stack padding for dowubleword alignment. */
3841 if (nstack
& (align
- 1))
3843 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3844 nstack
+= INT_REGISTER_SIZE
;
3847 /* Doubleword aligned quantities must go in even register pairs. */
3848 if (may_use_core_reg
3849 && argreg
<= ARM_LAST_ARG_REGNUM
3850 && align
> INT_REGISTER_SIZE
3854 /* If the argument is a pointer to a function, and it is a
3855 Thumb function, create a LOCAL copy of the value and set
3856 the THUMB bit in it. */
3857 if (TYPE_CODE_PTR
== typecode
3858 && target_type
!= NULL
3859 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3861 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3862 if (arm_pc_is_thumb (gdbarch
, regval
))
3864 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3865 store_unsigned_integer (copy
, len
, byte_order
,
3866 MAKE_THUMB_ADDR (regval
));
3871 /* Copy the argument to general registers or the stack in
3872 register-sized pieces. Large arguments are split between
3873 registers and stack. */
3876 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3878 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3880 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3882 /* The argument is being passed in a general purpose
3884 if (byte_order
== BFD_ENDIAN_BIG
)
3885 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3887 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3889 gdbarch_register_name
3891 phex (regval
, INT_REGISTER_SIZE
));
3892 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3897 gdb_byte buf
[INT_REGISTER_SIZE
];
3899 memset (buf
, 0, sizeof (buf
));
3900 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3902 /* Push the arguments onto the stack. */
3904 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3906 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3907 nstack
+= INT_REGISTER_SIZE
;
3914 /* If we have an odd number of words to push, then decrement the stack
3915 by one word now, so first stack argument will be dword aligned. */
3922 write_memory (sp
, si
->data
, si
->len
);
3923 si
= pop_stack_item (si
);
3926 /* Finally, update teh SP register. */
3927 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3933 /* Always align the frame to an 8-byte boundary. This is required on
3934 some platforms and harmless on the rest. */
3937 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3939 /* Align the stack to eight bytes. */
3940 return sp
& ~ (CORE_ADDR
) 7;
3944 print_fpu_flags (struct ui_file
*file
, int flags
)
3946 if (flags
& (1 << 0))
3947 fputs_filtered ("IVO ", file
);
3948 if (flags
& (1 << 1))
3949 fputs_filtered ("DVZ ", file
);
3950 if (flags
& (1 << 2))
3951 fputs_filtered ("OFL ", file
);
3952 if (flags
& (1 << 3))
3953 fputs_filtered ("UFL ", file
);
3954 if (flags
& (1 << 4))
3955 fputs_filtered ("INX ", file
);
3956 fputc_filtered ('\n', file
);
3959 /* Print interesting information about the floating point processor
3960 (if present) or emulator. */
3962 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3963 struct frame_info
*frame
, const char *args
)
3965 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3968 type
= (status
>> 24) & 127;
3969 if (status
& (1 << 31))
3970 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3972 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3973 /* i18n: [floating point unit] mask */
3974 fputs_filtered (_("mask: "), file
);
3975 print_fpu_flags (file
, status
>> 16);
3976 /* i18n: [floating point unit] flags */
3977 fputs_filtered (_("flags: "), file
);
3978 print_fpu_flags (file
, status
);
3981 /* Construct the ARM extended floating point type. */
3982 static struct type
*
3983 arm_ext_type (struct gdbarch
*gdbarch
)
3985 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3987 if (!tdep
->arm_ext_type
)
3989 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3990 floatformats_arm_ext
);
3992 return tdep
->arm_ext_type
;
3995 static struct type
*
3996 arm_neon_double_type (struct gdbarch
*gdbarch
)
3998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4000 if (tdep
->neon_double_type
== NULL
)
4002 struct type
*t
, *elem
;
4004 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4006 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4007 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4008 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4009 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4010 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4011 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4012 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4013 append_composite_type_field (t
, "u64", elem
);
4014 elem
= builtin_type (gdbarch
)->builtin_float
;
4015 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4016 elem
= builtin_type (gdbarch
)->builtin_double
;
4017 append_composite_type_field (t
, "f64", elem
);
4019 TYPE_VECTOR (t
) = 1;
4020 TYPE_NAME (t
) = "neon_d";
4021 tdep
->neon_double_type
= t
;
4024 return tdep
->neon_double_type
;
4027 /* FIXME: The vector types are not correctly ordered on big-endian
4028 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4029 bits of d0 - regardless of what unit size is being held in d0. So
4030 the offset of the first uint8 in d0 is 7, but the offset of the
4031 first float is 4. This code works as-is for little-endian
4034 static struct type
*
4035 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4037 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4039 if (tdep
->neon_quad_type
== NULL
)
4041 struct type
*t
, *elem
;
4043 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4045 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4046 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4047 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4048 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4049 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4050 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4051 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4052 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4053 elem
= builtin_type (gdbarch
)->builtin_float
;
4054 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4055 elem
= builtin_type (gdbarch
)->builtin_double
;
4056 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4058 TYPE_VECTOR (t
) = 1;
4059 TYPE_NAME (t
) = "neon_q";
4060 tdep
->neon_quad_type
= t
;
4063 return tdep
->neon_quad_type
;
4066 /* Return the GDB type object for the "standard" data type of data in
4069 static struct type
*
4070 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4072 int num_regs
= gdbarch_num_regs (gdbarch
);
4074 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4075 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4076 return builtin_type (gdbarch
)->builtin_float
;
4078 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4079 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4080 return arm_neon_quad_type (gdbarch
);
4082 /* If the target description has register information, we are only
4083 in this function so that we can override the types of
4084 double-precision registers for NEON. */
4085 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4087 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4089 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4090 && TYPE_CODE (t
) == TYPE_CODE_FLT
4091 && gdbarch_tdep (gdbarch
)->have_neon
)
4092 return arm_neon_double_type (gdbarch
);
4097 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4099 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4100 return builtin_type (gdbarch
)->builtin_void
;
4102 return arm_ext_type (gdbarch
);
4104 else if (regnum
== ARM_SP_REGNUM
)
4105 return builtin_type (gdbarch
)->builtin_data_ptr
;
4106 else if (regnum
== ARM_PC_REGNUM
)
4107 return builtin_type (gdbarch
)->builtin_func_ptr
;
4108 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4109 /* These registers are only supported on targets which supply
4110 an XML description. */
4111 return builtin_type (gdbarch
)->builtin_int0
;
4113 return builtin_type (gdbarch
)->builtin_uint32
;
4116 /* Map a DWARF register REGNUM onto the appropriate GDB register
4120 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4122 /* Core integer regs. */
4123 if (reg
>= 0 && reg
<= 15)
4126 /* Legacy FPA encoding. These were once used in a way which
4127 overlapped with VFP register numbering, so their use is
4128 discouraged, but GDB doesn't support the ARM toolchain
4129 which used them for VFP. */
4130 if (reg
>= 16 && reg
<= 23)
4131 return ARM_F0_REGNUM
+ reg
- 16;
4133 /* New assignments for the FPA registers. */
4134 if (reg
>= 96 && reg
<= 103)
4135 return ARM_F0_REGNUM
+ reg
- 96;
4137 /* WMMX register assignments. */
4138 if (reg
>= 104 && reg
<= 111)
4139 return ARM_WCGR0_REGNUM
+ reg
- 104;
4141 if (reg
>= 112 && reg
<= 127)
4142 return ARM_WR0_REGNUM
+ reg
- 112;
4144 if (reg
>= 192 && reg
<= 199)
4145 return ARM_WC0_REGNUM
+ reg
- 192;
4147 /* VFP v2 registers. A double precision value is actually
4148 in d1 rather than s2, but the ABI only defines numbering
4149 for the single precision registers. This will "just work"
4150 in GDB for little endian targets (we'll read eight bytes,
4151 starting in s0 and then progressing to s1), but will be
4152 reversed on big endian targets with VFP. This won't
4153 be a problem for the new Neon quad registers; you're supposed
4154 to use DW_OP_piece for those. */
4155 if (reg
>= 64 && reg
<= 95)
4159 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4160 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4164 /* VFP v3 / Neon registers. This range is also used for VFP v2
4165 registers, except that it now describes d0 instead of s0. */
4166 if (reg
>= 256 && reg
<= 287)
4170 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4171 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4178 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4180 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4183 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4185 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4186 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4188 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4189 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4191 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4192 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4194 if (reg
< NUM_GREGS
)
4195 return SIM_ARM_R0_REGNUM
+ reg
;
4198 if (reg
< NUM_FREGS
)
4199 return SIM_ARM_FP0_REGNUM
+ reg
;
4202 if (reg
< NUM_SREGS
)
4203 return SIM_ARM_FPS_REGNUM
+ reg
;
4206 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4209 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4210 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4211 It is thought that this is is the floating-point register format on
4212 little-endian systems. */
4215 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4216 void *dbl
, int endianess
)
4220 if (endianess
== BFD_ENDIAN_BIG
)
4221 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4223 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4225 floatformat_from_doublest (fmt
, &d
, dbl
);
4229 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4234 floatformat_to_doublest (fmt
, ptr
, &d
);
4235 if (endianess
== BFD_ENDIAN_BIG
)
4236 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4238 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4242 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4243 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4244 NULL if an error occurs. BUF is freed. */
4247 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4248 int old_len
, int new_len
)
4251 int bytes_to_read
= new_len
- old_len
;
4253 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4254 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4256 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4264 /* An IT block is at most the 2-byte IT instruction followed by
4265 four 4-byte instructions. The furthest back we must search to
4266 find an IT block that affects the current instruction is thus
4267 2 + 3 * 4 == 14 bytes. */
4268 #define MAX_IT_BLOCK_PREFIX 14
4270 /* Use a quick scan if there are more than this many bytes of
4272 #define IT_SCAN_THRESHOLD 32
4274 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4275 A breakpoint in an IT block may not be hit, depending on the
4278 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4282 CORE_ADDR boundary
, func_start
;
4284 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4285 int i
, any
, last_it
, last_it_count
;
4287 /* If we are using BKPT breakpoints, none of this is necessary. */
4288 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4291 /* ARM mode does not have this problem. */
4292 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4295 /* We are setting a breakpoint in Thumb code that could potentially
4296 contain an IT block. The first step is to find how much Thumb
4297 code there is; we do not need to read outside of known Thumb
4299 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4301 /* Thumb-2 code must have mapping symbols to have a chance. */
4304 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4306 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4307 && func_start
> boundary
)
4308 boundary
= func_start
;
4310 /* Search for a candidate IT instruction. We have to do some fancy
4311 footwork to distinguish a real IT instruction from the second
4312 half of a 32-bit instruction, but there is no need for that if
4313 there's no candidate. */
4314 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4316 /* No room for an IT instruction. */
4319 buf
= (gdb_byte
*) xmalloc (buf_len
);
4320 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4323 for (i
= 0; i
< buf_len
; i
+= 2)
4325 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4326 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4339 /* OK, the code bytes before this instruction contain at least one
4340 halfword which resembles an IT instruction. We know that it's
4341 Thumb code, but there are still two possibilities. Either the
4342 halfword really is an IT instruction, or it is the second half of
4343 a 32-bit Thumb instruction. The only way we can tell is to
4344 scan forwards from a known instruction boundary. */
4345 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4349 /* There's a lot of code before this instruction. Start with an
4350 optimistic search; it's easy to recognize halfwords that can
4351 not be the start of a 32-bit instruction, and use that to
4352 lock on to the instruction boundaries. */
4353 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4356 buf_len
= IT_SCAN_THRESHOLD
;
4359 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4361 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4362 if (thumb_insn_size (inst1
) == 2)
4369 /* At this point, if DEFINITE, BUF[I] is the first place we
4370 are sure that we know the instruction boundaries, and it is far
4371 enough from BPADDR that we could not miss an IT instruction
4372 affecting BPADDR. If ! DEFINITE, give up - start from a
4376 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4380 buf_len
= bpaddr
- boundary
;
4386 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4389 buf_len
= bpaddr
- boundary
;
4393 /* Scan forwards. Find the last IT instruction before BPADDR. */
4398 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4400 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4405 else if (inst1
& 0x0002)
4407 else if (inst1
& 0x0004)
4412 i
+= thumb_insn_size (inst1
);
4418 /* There wasn't really an IT instruction after all. */
4421 if (last_it_count
< 1)
4422 /* It was too far away. */
4425 /* This really is a trouble spot. Move the breakpoint to the IT
4427 return bpaddr
- buf_len
+ last_it
;
4430 /* ARM displaced stepping support.
4432 Generally ARM displaced stepping works as follows:
4434 1. When an instruction is to be single-stepped, it is first decoded by
4435 arm_process_displaced_insn. Depending on the type of instruction, it is
4436 then copied to a scratch location, possibly in a modified form. The
4437 copy_* set of functions performs such modification, as necessary. A
4438 breakpoint is placed after the modified instruction in the scratch space
4439 to return control to GDB. Note in particular that instructions which
4440 modify the PC will no longer do so after modification.
4442 2. The instruction is single-stepped, by setting the PC to the scratch
4443 location address, and resuming. Control returns to GDB when the
4446 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4447 function used for the current instruction. This function's job is to
4448 put the CPU/memory state back to what it would have been if the
4449 instruction had been executed unmodified in its original location. */
4451 /* NOP instruction (mov r0, r0). */
4452 #define ARM_NOP 0xe1a00000
4453 #define THUMB_NOP 0x4600
4455 /* Helper for register reads for displaced stepping. In particular, this
4456 returns the PC as it would be seen by the instruction at its original
4460 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4464 CORE_ADDR from
= dsc
->insn_addr
;
4466 if (regno
== ARM_PC_REGNUM
)
4468 /* Compute pipeline offset:
4469 - When executing an ARM instruction, PC reads as the address of the
4470 current instruction plus 8.
4471 - When executing a Thumb instruction, PC reads as the address of the
4472 current instruction plus 4. */
4479 if (debug_displaced
)
4480 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4481 (unsigned long) from
);
4482 return (ULONGEST
) from
;
4486 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4487 if (debug_displaced
)
4488 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4489 regno
, (unsigned long) ret
);
4495 displaced_in_arm_mode (struct regcache
*regs
)
4498 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4500 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4502 return (ps
& t_bit
) == 0;
4505 /* Write to the PC as from a branch instruction. */
4508 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4512 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4513 architecture versions < 6. */
4514 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4515 val
& ~(ULONGEST
) 0x3);
4517 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4518 val
& ~(ULONGEST
) 0x1);
4521 /* Write to the PC as from a branch-exchange instruction. */
4524 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4527 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4529 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4533 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4534 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4536 else if ((val
& 2) == 0)
4538 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4539 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4543 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4544 mode, align dest to 4 bytes). */
4545 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4546 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4547 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4551 /* Write to the PC as if from a load instruction. */
4554 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4557 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4558 bx_write_pc (regs
, val
);
4560 branch_write_pc (regs
, dsc
, val
);
4563 /* Write to the PC as if from an ALU instruction. */
4566 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4569 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4570 bx_write_pc (regs
, val
);
4572 branch_write_pc (regs
, dsc
, val
);
4575 /* Helper for writing to registers for displaced stepping. Writing to the PC
4576 has a varying effects depending on the instruction which does the write:
4577 this is controlled by the WRITE_PC argument. */
4580 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4581 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4583 if (regno
== ARM_PC_REGNUM
)
4585 if (debug_displaced
)
4586 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4587 (unsigned long) val
);
4590 case BRANCH_WRITE_PC
:
4591 branch_write_pc (regs
, dsc
, val
);
4595 bx_write_pc (regs
, val
);
4599 load_write_pc (regs
, dsc
, val
);
4603 alu_write_pc (regs
, dsc
, val
);
4606 case CANNOT_WRITE_PC
:
4607 warning (_("Instruction wrote to PC in an unexpected way when "
4608 "single-stepping"));
4612 internal_error (__FILE__
, __LINE__
,
4613 _("Invalid argument to displaced_write_reg"));
4616 dsc
->wrote_to_pc
= 1;
4620 if (debug_displaced
)
4621 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4622 regno
, (unsigned long) val
);
4623 regcache_cooked_write_unsigned (regs
, regno
, val
);
4627 /* This function is used to concisely determine if an instruction INSN
4628 references PC. Register fields of interest in INSN should have the
4629 corresponding fields of BITMASK set to 0b1111. The function
4630 returns return 1 if any of these fields in INSN reference the PC
4631 (also 0b1111, r15), else it returns 0. */
4634 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4636 uint32_t lowbit
= 1;
4638 while (bitmask
!= 0)
4642 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4648 mask
= lowbit
* 0xf;
4650 if ((insn
& mask
) == mask
)
4659 /* The simplest copy function. Many instructions have the same effect no
4660 matter what address they are executed at: in those cases, use this. */
4663 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4664 const char *iname
, struct displaced_step_closure
*dsc
)
4666 if (debug_displaced
)
4667 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4668 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4671 dsc
->modinsn
[0] = insn
;
4677 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4678 uint16_t insn2
, const char *iname
,
4679 struct displaced_step_closure
*dsc
)
4681 if (debug_displaced
)
4682 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4683 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4686 dsc
->modinsn
[0] = insn1
;
4687 dsc
->modinsn
[1] = insn2
;
4693 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4696 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4698 struct displaced_step_closure
*dsc
)
4700 if (debug_displaced
)
4701 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4702 "opcode/class '%s' unmodified\n", insn
,
4705 dsc
->modinsn
[0] = insn
;
4710 /* Preload instructions with immediate offset. */
4713 cleanup_preload (struct gdbarch
*gdbarch
,
4714 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4716 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4717 if (!dsc
->u
.preload
.immed
)
4718 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4722 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4723 struct displaced_step_closure
*dsc
, unsigned int rn
)
4726 /* Preload instructions:
4728 {pli/pld} [rn, #+/-imm]
4730 {pli/pld} [r0, #+/-imm]. */
4732 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4733 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4734 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4735 dsc
->u
.preload
.immed
= 1;
4737 dsc
->cleanup
= &cleanup_preload
;
4741 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4742 struct displaced_step_closure
*dsc
)
4744 unsigned int rn
= bits (insn
, 16, 19);
4746 if (!insn_references_pc (insn
, 0x000f0000ul
))
4747 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4749 if (debug_displaced
)
4750 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4751 (unsigned long) insn
);
4753 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4755 install_preload (gdbarch
, regs
, dsc
, rn
);
4761 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4762 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4764 unsigned int rn
= bits (insn1
, 0, 3);
4765 unsigned int u_bit
= bit (insn1
, 7);
4766 int imm12
= bits (insn2
, 0, 11);
4769 if (rn
!= ARM_PC_REGNUM
)
4770 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4772 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4773 PLD (literal) Encoding T1. */
4774 if (debug_displaced
)
4775 fprintf_unfiltered (gdb_stdlog
,
4776 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4777 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4783 /* Rewrite instruction {pli/pld} PC imm12 into:
4784 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4788 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4790 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4791 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4793 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4795 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4796 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4797 dsc
->u
.preload
.immed
= 0;
4799 /* {pli/pld} [r0, r1] */
4800 dsc
->modinsn
[0] = insn1
& 0xfff0;
4801 dsc
->modinsn
[1] = 0xf001;
4804 dsc
->cleanup
= &cleanup_preload
;
4808 /* Preload instructions with register offset. */
4811 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4812 struct displaced_step_closure
*dsc
, unsigned int rn
,
4815 ULONGEST rn_val
, rm_val
;
4817 /* Preload register-offset instructions:
4819 {pli/pld} [rn, rm {, shift}]
4821 {pli/pld} [r0, r1 {, shift}]. */
4823 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4824 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4825 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4826 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4827 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4828 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4829 dsc
->u
.preload
.immed
= 0;
4831 dsc
->cleanup
= &cleanup_preload
;
4835 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4836 struct regcache
*regs
,
4837 struct displaced_step_closure
*dsc
)
4839 unsigned int rn
= bits (insn
, 16, 19);
4840 unsigned int rm
= bits (insn
, 0, 3);
4843 if (!insn_references_pc (insn
, 0x000f000ful
))
4844 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4846 if (debug_displaced
)
4847 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4848 (unsigned long) insn
);
4850 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4852 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4856 /* Copy/cleanup coprocessor load and store instructions. */
4859 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4860 struct regcache
*regs
,
4861 struct displaced_step_closure
*dsc
)
4863 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4865 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4867 if (dsc
->u
.ldst
.writeback
)
4868 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4872 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4873 struct displaced_step_closure
*dsc
,
4874 int writeback
, unsigned int rn
)
4878 /* Coprocessor load/store instructions:
4880 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4882 {stc/stc2} [r0, #+/-imm].
4884 ldc/ldc2 are handled identically. */
4886 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4887 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4888 /* PC should be 4-byte aligned. */
4889 rn_val
= rn_val
& 0xfffffffc;
4890 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4892 dsc
->u
.ldst
.writeback
= writeback
;
4893 dsc
->u
.ldst
.rn
= rn
;
4895 dsc
->cleanup
= &cleanup_copro_load_store
;
4899 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4900 struct regcache
*regs
,
4901 struct displaced_step_closure
*dsc
)
4903 unsigned int rn
= bits (insn
, 16, 19);
4905 if (!insn_references_pc (insn
, 0x000f0000ul
))
4906 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4908 if (debug_displaced
)
4909 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4910 "load/store insn %.8lx\n", (unsigned long) insn
);
4912 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4914 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4920 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4921 uint16_t insn2
, struct regcache
*regs
,
4922 struct displaced_step_closure
*dsc
)
4924 unsigned int rn
= bits (insn1
, 0, 3);
4926 if (rn
!= ARM_PC_REGNUM
)
4927 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4928 "copro load/store", dsc
);
4930 if (debug_displaced
)
4931 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4932 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4934 dsc
->modinsn
[0] = insn1
& 0xfff0;
4935 dsc
->modinsn
[1] = insn2
;
4938 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4939 doesn't support writeback, so pass 0. */
4940 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4945 /* Clean up branch instructions (actually perform the branch, by setting
4949 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4950 struct displaced_step_closure
*dsc
)
4952 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4953 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4954 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4955 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4960 if (dsc
->u
.branch
.link
)
4962 /* The value of LR should be the next insn of current one. In order
4963 not to confuse logic hanlding later insn `bx lr', if current insn mode
4964 is Thumb, the bit 0 of LR value should be set to 1. */
4965 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4968 next_insn_addr
|= 0x1;
4970 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4974 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4977 /* Copy B/BL/BLX instructions with immediate destinations. */
4980 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4981 struct displaced_step_closure
*dsc
,
4982 unsigned int cond
, int exchange
, int link
, long offset
)
4984 /* Implement "BL<cond> <label>" as:
4986 Preparation: cond <- instruction condition
4987 Insn: mov r0, r0 (nop)
4988 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4990 B<cond> similar, but don't set r14 in cleanup. */
4992 dsc
->u
.branch
.cond
= cond
;
4993 dsc
->u
.branch
.link
= link
;
4994 dsc
->u
.branch
.exchange
= exchange
;
4996 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4997 if (link
&& exchange
)
4998 /* For BLX, offset is computed from the Align (PC, 4). */
4999 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5002 dsc
->u
.branch
.dest
+= 4 + offset
;
5004 dsc
->u
.branch
.dest
+= 8 + offset
;
5006 dsc
->cleanup
= &cleanup_branch
;
5009 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5010 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5012 unsigned int cond
= bits (insn
, 28, 31);
5013 int exchange
= (cond
== 0xf);
5014 int link
= exchange
|| bit (insn
, 24);
5017 if (debug_displaced
)
5018 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5019 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5020 (unsigned long) insn
);
5022 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5023 then arrange the switch into Thumb mode. */
5024 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5026 offset
= bits (insn
, 0, 23) << 2;
5028 if (bit (offset
, 25))
5029 offset
= offset
| ~0x3ffffff;
5031 dsc
->modinsn
[0] = ARM_NOP
;
5033 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5038 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5039 uint16_t insn2
, struct regcache
*regs
,
5040 struct displaced_step_closure
*dsc
)
5042 int link
= bit (insn2
, 14);
5043 int exchange
= link
&& !bit (insn2
, 12);
5046 int j1
= bit (insn2
, 13);
5047 int j2
= bit (insn2
, 11);
5048 int s
= sbits (insn1
, 10, 10);
5049 int i1
= !(j1
^ bit (insn1
, 10));
5050 int i2
= !(j2
^ bit (insn1
, 10));
5052 if (!link
&& !exchange
) /* B */
5054 offset
= (bits (insn2
, 0, 10) << 1);
5055 if (bit (insn2
, 12)) /* Encoding T4 */
5057 offset
|= (bits (insn1
, 0, 9) << 12)
5063 else /* Encoding T3 */
5065 offset
|= (bits (insn1
, 0, 5) << 12)
5069 cond
= bits (insn1
, 6, 9);
5074 offset
= (bits (insn1
, 0, 9) << 12);
5075 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5076 offset
|= exchange
?
5077 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5080 if (debug_displaced
)
5081 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5082 "%.4x %.4x with offset %.8lx\n",
5083 link
? (exchange
) ? "blx" : "bl" : "b",
5084 insn1
, insn2
, offset
);
5086 dsc
->modinsn
[0] = THUMB_NOP
;
5088 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5092 /* Copy B Thumb instructions. */
5094 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5095 struct displaced_step_closure
*dsc
)
5097 unsigned int cond
= 0;
5099 unsigned short bit_12_15
= bits (insn
, 12, 15);
5100 CORE_ADDR from
= dsc
->insn_addr
;
5102 if (bit_12_15
== 0xd)
5104 /* offset = SignExtend (imm8:0, 32) */
5105 offset
= sbits ((insn
<< 1), 0, 8);
5106 cond
= bits (insn
, 8, 11);
5108 else if (bit_12_15
== 0xe) /* Encoding T2 */
5110 offset
= sbits ((insn
<< 1), 0, 11);
5114 if (debug_displaced
)
5115 fprintf_unfiltered (gdb_stdlog
,
5116 "displaced: copying b immediate insn %.4x "
5117 "with offset %d\n", insn
, offset
);
5119 dsc
->u
.branch
.cond
= cond
;
5120 dsc
->u
.branch
.link
= 0;
5121 dsc
->u
.branch
.exchange
= 0;
5122 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5124 dsc
->modinsn
[0] = THUMB_NOP
;
5126 dsc
->cleanup
= &cleanup_branch
;
5131 /* Copy BX/BLX with register-specified destinations. */
5134 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5135 struct displaced_step_closure
*dsc
, int link
,
5136 unsigned int cond
, unsigned int rm
)
5138 /* Implement {BX,BLX}<cond> <reg>" as:
5140 Preparation: cond <- instruction condition
5141 Insn: mov r0, r0 (nop)
5142 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5144 Don't set r14 in cleanup for BX. */
5146 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5148 dsc
->u
.branch
.cond
= cond
;
5149 dsc
->u
.branch
.link
= link
;
5151 dsc
->u
.branch
.exchange
= 1;
5153 dsc
->cleanup
= &cleanup_branch
;
5157 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5158 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5160 unsigned int cond
= bits (insn
, 28, 31);
5163 int link
= bit (insn
, 5);
5164 unsigned int rm
= bits (insn
, 0, 3);
5166 if (debug_displaced
)
5167 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5168 (unsigned long) insn
);
5170 dsc
->modinsn
[0] = ARM_NOP
;
5172 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5177 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5178 struct regcache
*regs
,
5179 struct displaced_step_closure
*dsc
)
5181 int link
= bit (insn
, 7);
5182 unsigned int rm
= bits (insn
, 3, 6);
5184 if (debug_displaced
)
5185 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5186 (unsigned short) insn
);
5188 dsc
->modinsn
[0] = THUMB_NOP
;
5190 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5196 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5199 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5200 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5202 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5203 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5204 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5205 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5209 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5210 struct displaced_step_closure
*dsc
)
5212 unsigned int rn
= bits (insn
, 16, 19);
5213 unsigned int rd
= bits (insn
, 12, 15);
5214 unsigned int op
= bits (insn
, 21, 24);
5215 int is_mov
= (op
== 0xd);
5216 ULONGEST rd_val
, rn_val
;
5218 if (!insn_references_pc (insn
, 0x000ff000ul
))
5219 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5221 if (debug_displaced
)
5222 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5223 "%.8lx\n", is_mov
? "move" : "ALU",
5224 (unsigned long) insn
);
5226 /* Instruction is of form:
5228 <op><cond> rd, [rn,] #imm
5232 Preparation: tmp1, tmp2 <- r0, r1;
5234 Insn: <op><cond> r0, r1, #imm
5235 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5238 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5239 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5240 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5241 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5242 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5243 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5247 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5249 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5251 dsc
->cleanup
= &cleanup_alu_imm
;
5257 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5258 uint16_t insn2
, struct regcache
*regs
,
5259 struct displaced_step_closure
*dsc
)
5261 unsigned int op
= bits (insn1
, 5, 8);
5262 unsigned int rn
, rm
, rd
;
5263 ULONGEST rd_val
, rn_val
;
5265 rn
= bits (insn1
, 0, 3); /* Rn */
5266 rm
= bits (insn2
, 0, 3); /* Rm */
5267 rd
= bits (insn2
, 8, 11); /* Rd */
5269 /* This routine is only called for instruction MOV. */
5270 gdb_assert (op
== 0x2 && rn
== 0xf);
5272 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5273 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5275 if (debug_displaced
)
5276 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5277 "ALU", insn1
, insn2
);
5279 /* Instruction is of form:
5281 <op><cond> rd, [rn,] #imm
5285 Preparation: tmp1, tmp2 <- r0, r1;
5287 Insn: <op><cond> r0, r1, #imm
5288 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5291 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5292 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5293 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5294 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5295 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5296 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5299 dsc
->modinsn
[0] = insn1
;
5300 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5303 dsc
->cleanup
= &cleanup_alu_imm
;
5308 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5311 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5312 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5317 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5319 for (i
= 0; i
< 3; i
++)
5320 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5322 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5326 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5327 struct displaced_step_closure
*dsc
,
5328 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5330 ULONGEST rd_val
, rn_val
, rm_val
;
5332 /* Instruction is of form:
5334 <op><cond> rd, [rn,] rm [, <shift>]
5338 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5339 r0, r1, r2 <- rd, rn, rm
5340 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5341 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5344 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5345 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5346 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5347 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5348 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5349 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5350 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5351 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5352 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5355 dsc
->cleanup
= &cleanup_alu_reg
;
5359 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5360 struct displaced_step_closure
*dsc
)
5362 unsigned int op
= bits (insn
, 21, 24);
5363 int is_mov
= (op
== 0xd);
5365 if (!insn_references_pc (insn
, 0x000ff00ful
))
5366 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5368 if (debug_displaced
)
5369 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5370 is_mov
? "move" : "ALU", (unsigned long) insn
);
5373 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5375 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5377 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5383 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5384 struct regcache
*regs
,
5385 struct displaced_step_closure
*dsc
)
5389 rm
= bits (insn
, 3, 6);
5390 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5392 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5393 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5395 if (debug_displaced
)
5396 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5397 (unsigned short) insn
);
5399 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5401 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5406 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5409 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5410 struct regcache
*regs
,
5411 struct displaced_step_closure
*dsc
)
5413 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5416 for (i
= 0; i
< 4; i
++)
5417 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5419 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5423 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5424 struct displaced_step_closure
*dsc
,
5425 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5429 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5431 /* Instruction is of form:
5433 <op><cond> rd, [rn,] rm, <shift> rs
5437 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5438 r0, r1, r2, r3 <- rd, rn, rm, rs
5439 Insn: <op><cond> r0, r1, r2, <shift> r3
5441 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5445 for (i
= 0; i
< 4; i
++)
5446 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5448 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5449 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5450 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5451 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5452 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5453 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5454 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5455 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5457 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5461 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5462 struct regcache
*regs
,
5463 struct displaced_step_closure
*dsc
)
5465 unsigned int op
= bits (insn
, 21, 24);
5466 int is_mov
= (op
== 0xd);
5467 unsigned int rd
, rn
, rm
, rs
;
5469 if (!insn_references_pc (insn
, 0x000fff0ful
))
5470 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5472 if (debug_displaced
)
5473 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5474 "%.8lx\n", is_mov
? "move" : "ALU",
5475 (unsigned long) insn
);
5477 rn
= bits (insn
, 16, 19);
5478 rm
= bits (insn
, 0, 3);
5479 rs
= bits (insn
, 8, 11);
5480 rd
= bits (insn
, 12, 15);
5483 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5485 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5487 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5492 /* Clean up load instructions. */
5495 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5496 struct displaced_step_closure
*dsc
)
5498 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5500 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5501 if (dsc
->u
.ldst
.xfersize
== 8)
5502 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5503 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5505 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5506 if (dsc
->u
.ldst
.xfersize
> 4)
5507 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5508 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5509 if (!dsc
->u
.ldst
.immed
)
5510 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5512 /* Handle register writeback. */
5513 if (dsc
->u
.ldst
.writeback
)
5514 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5515 /* Put result in right place. */
5516 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5517 if (dsc
->u
.ldst
.xfersize
== 8)
5518 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5521 /* Clean up store instructions. */
5524 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5525 struct displaced_step_closure
*dsc
)
5527 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5529 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5530 if (dsc
->u
.ldst
.xfersize
> 4)
5531 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5532 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5533 if (!dsc
->u
.ldst
.immed
)
5534 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5535 if (!dsc
->u
.ldst
.restore_r4
)
5536 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5539 if (dsc
->u
.ldst
.writeback
)
5540 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5543 /* Copy "extra" load/store instructions. These are halfword/doubleword
5544 transfers, which have a different encoding to byte/word transfers. */
5547 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5548 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5550 unsigned int op1
= bits (insn
, 20, 24);
5551 unsigned int op2
= bits (insn
, 5, 6);
5552 unsigned int rt
= bits (insn
, 12, 15);
5553 unsigned int rn
= bits (insn
, 16, 19);
5554 unsigned int rm
= bits (insn
, 0, 3);
5555 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5556 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5557 int immed
= (op1
& 0x4) != 0;
5559 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5561 if (!insn_references_pc (insn
, 0x000ff00ful
))
5562 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5564 if (debug_displaced
)
5565 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5566 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5567 (unsigned long) insn
);
5569 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5572 internal_error (__FILE__
, __LINE__
,
5573 _("copy_extra_ld_st: instruction decode error"));
5575 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5576 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5577 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5579 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5581 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5582 if (bytesize
[opcode
] == 8)
5583 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5584 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5586 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5588 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5589 if (bytesize
[opcode
] == 8)
5590 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5591 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5593 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5596 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5597 dsc
->u
.ldst
.rn
= rn
;
5598 dsc
->u
.ldst
.immed
= immed
;
5599 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5600 dsc
->u
.ldst
.restore_r4
= 0;
5603 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5605 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5606 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5608 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5610 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5611 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5613 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5618 /* Copy byte/half word/word loads and stores. */
5621 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5622 struct displaced_step_closure
*dsc
, int load
,
5623 int immed
, int writeback
, int size
, int usermode
,
5624 int rt
, int rm
, int rn
)
5626 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5628 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5629 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5631 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5633 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5635 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5636 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5638 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5640 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5641 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5643 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5645 dsc
->u
.ldst
.xfersize
= size
;
5646 dsc
->u
.ldst
.rn
= rn
;
5647 dsc
->u
.ldst
.immed
= immed
;
5648 dsc
->u
.ldst
.writeback
= writeback
;
5650 /* To write PC we can do:
5652 Before this sequence of instructions:
5653 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5654 r2 is the Rn value got from dispalced_read_reg.
5656 Insn1: push {pc} Write address of STR instruction + offset on stack
5657 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5658 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5659 = addr(Insn1) + offset - addr(Insn3) - 8
5661 Insn4: add r4, r4, #8 r4 = offset - 8
5662 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5664 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5666 Otherwise we don't know what value to write for PC, since the offset is
5667 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5668 of this can be found in Section "Saving from r15" in
5669 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5671 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5676 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5677 uint16_t insn2
, struct regcache
*regs
,
5678 struct displaced_step_closure
*dsc
, int size
)
5680 unsigned int u_bit
= bit (insn1
, 7);
5681 unsigned int rt
= bits (insn2
, 12, 15);
5682 int imm12
= bits (insn2
, 0, 11);
5685 if (debug_displaced
)
5686 fprintf_unfiltered (gdb_stdlog
,
5687 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5688 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5694 /* Rewrite instruction LDR Rt imm12 into:
5696 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5700 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5703 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5704 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5705 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5707 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5709 pc_val
= pc_val
& 0xfffffffc;
5711 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5712 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5716 dsc
->u
.ldst
.xfersize
= size
;
5717 dsc
->u
.ldst
.immed
= 0;
5718 dsc
->u
.ldst
.writeback
= 0;
5719 dsc
->u
.ldst
.restore_r4
= 0;
5721 /* LDR R0, R2, R3 */
5722 dsc
->modinsn
[0] = 0xf852;
5723 dsc
->modinsn
[1] = 0x3;
5726 dsc
->cleanup
= &cleanup_load
;
5732 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5733 uint16_t insn2
, struct regcache
*regs
,
5734 struct displaced_step_closure
*dsc
,
5735 int writeback
, int immed
)
5737 unsigned int rt
= bits (insn2
, 12, 15);
5738 unsigned int rn
= bits (insn1
, 0, 3);
5739 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5740 /* In LDR (register), there is also a register Rm, which is not allowed to
5741 be PC, so we don't have to check it. */
5743 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5744 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5747 if (debug_displaced
)
5748 fprintf_unfiltered (gdb_stdlog
,
5749 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5750 rt
, rn
, insn1
, insn2
);
5752 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5755 dsc
->u
.ldst
.restore_r4
= 0;
5758 /* ldr[b]<cond> rt, [rn, #imm], etc.
5760 ldr[b]<cond> r0, [r2, #imm]. */
5762 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5763 dsc
->modinsn
[1] = insn2
& 0x0fff;
5766 /* ldr[b]<cond> rt, [rn, rm], etc.
5768 ldr[b]<cond> r0, [r2, r3]. */
5770 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5771 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5781 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5782 struct regcache
*regs
,
5783 struct displaced_step_closure
*dsc
,
5784 int load
, int size
, int usermode
)
5786 int immed
= !bit (insn
, 25);
5787 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5788 unsigned int rt
= bits (insn
, 12, 15);
5789 unsigned int rn
= bits (insn
, 16, 19);
5790 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5792 if (!insn_references_pc (insn
, 0x000ff00ful
))
5793 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5795 if (debug_displaced
)
5796 fprintf_unfiltered (gdb_stdlog
,
5797 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5798 load
? (size
== 1 ? "ldrb" : "ldr")
5799 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5801 (unsigned long) insn
);
5803 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5804 usermode
, rt
, rm
, rn
);
5806 if (load
|| rt
!= ARM_PC_REGNUM
)
5808 dsc
->u
.ldst
.restore_r4
= 0;
5811 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5813 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5814 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5816 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5818 {ldr,str}[b]<cond> r0, [r2, r3]. */
5819 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5823 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5824 dsc
->u
.ldst
.restore_r4
= 1;
5825 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5826 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5827 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5828 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5829 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5833 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5835 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5840 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5845 /* Cleanup LDM instructions with fully-populated register list. This is an
5846 unfortunate corner case: it's impossible to implement correctly by modifying
5847 the instruction. The issue is as follows: we have an instruction,
5851 which we must rewrite to avoid loading PC. A possible solution would be to
5852 do the load in two halves, something like (with suitable cleanup
5856 ldm[id][ab] r8!, {r0-r7}
5858 ldm[id][ab] r8, {r7-r14}
5861 but at present there's no suitable place for <temp>, since the scratch space
5862 is overwritten before the cleanup routine is called. For now, we simply
5863 emulate the instruction. */
5866 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5867 struct displaced_step_closure
*dsc
)
5869 int inc
= dsc
->u
.block
.increment
;
5870 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5871 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5872 uint32_t regmask
= dsc
->u
.block
.regmask
;
5873 int regno
= inc
? 0 : 15;
5874 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5875 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5876 && (regmask
& 0x8000) != 0;
5877 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5878 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5879 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5884 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5885 sensible we can do here. Complain loudly. */
5886 if (exception_return
)
5887 error (_("Cannot single-step exception return"));
5889 /* We don't handle any stores here for now. */
5890 gdb_assert (dsc
->u
.block
.load
!= 0);
5892 if (debug_displaced
)
5893 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5894 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5895 dsc
->u
.block
.increment
? "inc" : "dec",
5896 dsc
->u
.block
.before
? "before" : "after");
5903 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5906 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5909 xfer_addr
+= bump_before
;
5911 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5912 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5914 xfer_addr
+= bump_after
;
5916 regmask
&= ~(1 << regno
);
5919 if (dsc
->u
.block
.writeback
)
5920 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5924 /* Clean up an STM which included the PC in the register list. */
5927 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5928 struct displaced_step_closure
*dsc
)
5930 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5931 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5932 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5933 CORE_ADDR stm_insn_addr
;
5936 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5938 /* If condition code fails, there's nothing else to do. */
5939 if (!store_executed
)
5942 if (dsc
->u
.block
.increment
)
5944 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5946 if (dsc
->u
.block
.before
)
5951 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5953 if (dsc
->u
.block
.before
)
5957 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5958 stm_insn_addr
= dsc
->scratch_base
;
5959 offset
= pc_val
- stm_insn_addr
;
5961 if (debug_displaced
)
5962 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5963 "STM instruction\n", offset
);
5965 /* Rewrite the stored PC to the proper value for the non-displaced original
5967 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5968 dsc
->insn_addr
+ offset
);
5971 /* Clean up an LDM which includes the PC in the register list. We clumped all
5972 the registers in the transferred list into a contiguous range r0...rX (to
5973 avoid loading PC directly and losing control of the debugged program), so we
5974 must undo that here. */
5977 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5978 struct regcache
*regs
,
5979 struct displaced_step_closure
*dsc
)
5981 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5982 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5983 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5984 unsigned int regs_loaded
= bitcount (mask
);
5985 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5987 /* The method employed here will fail if the register list is fully populated
5988 (we need to avoid loading PC directly). */
5989 gdb_assert (num_to_shuffle
< 16);
5994 clobbered
= (1 << num_to_shuffle
) - 1;
5996 while (num_to_shuffle
> 0)
5998 if ((mask
& (1 << write_reg
)) != 0)
6000 unsigned int read_reg
= num_to_shuffle
- 1;
6002 if (read_reg
!= write_reg
)
6004 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6005 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6006 if (debug_displaced
)
6007 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6008 "loaded register r%d to r%d\n"), read_reg
,
6011 else if (debug_displaced
)
6012 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6013 "r%d already in the right place\n"),
6016 clobbered
&= ~(1 << write_reg
);
6024 /* Restore any registers we scribbled over. */
6025 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6027 if ((clobbered
& (1 << write_reg
)) != 0)
6029 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6031 if (debug_displaced
)
6032 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6033 "clobbered register r%d\n"), write_reg
);
6034 clobbered
&= ~(1 << write_reg
);
6038 /* Perform register writeback manually. */
6039 if (dsc
->u
.block
.writeback
)
6041 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6043 if (dsc
->u
.block
.increment
)
6044 new_rn_val
+= regs_loaded
* 4;
6046 new_rn_val
-= regs_loaded
* 4;
6048 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6053 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6054 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6057 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6058 struct regcache
*regs
,
6059 struct displaced_step_closure
*dsc
)
6061 int load
= bit (insn
, 20);
6062 int user
= bit (insn
, 22);
6063 int increment
= bit (insn
, 23);
6064 int before
= bit (insn
, 24);
6065 int writeback
= bit (insn
, 21);
6066 int rn
= bits (insn
, 16, 19);
6068 /* Block transfers which don't mention PC can be run directly
6070 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6071 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6073 if (rn
== ARM_PC_REGNUM
)
6075 warning (_("displaced: Unpredictable LDM or STM with "
6076 "base register r15"));
6077 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6080 if (debug_displaced
)
6081 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6082 "%.8lx\n", (unsigned long) insn
);
6084 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6085 dsc
->u
.block
.rn
= rn
;
6087 dsc
->u
.block
.load
= load
;
6088 dsc
->u
.block
.user
= user
;
6089 dsc
->u
.block
.increment
= increment
;
6090 dsc
->u
.block
.before
= before
;
6091 dsc
->u
.block
.writeback
= writeback
;
6092 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6094 dsc
->u
.block
.regmask
= insn
& 0xffff;
6098 if ((insn
& 0xffff) == 0xffff)
6100 /* LDM with a fully-populated register list. This case is
6101 particularly tricky. Implement for now by fully emulating the
6102 instruction (which might not behave perfectly in all cases, but
6103 these instructions should be rare enough for that not to matter
6105 dsc
->modinsn
[0] = ARM_NOP
;
6107 dsc
->cleanup
= &cleanup_block_load_all
;
6111 /* LDM of a list of registers which includes PC. Implement by
6112 rewriting the list of registers to be transferred into a
6113 contiguous chunk r0...rX before doing the transfer, then shuffling
6114 registers into the correct places in the cleanup routine. */
6115 unsigned int regmask
= insn
& 0xffff;
6116 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6119 for (i
= 0; i
< num_in_list
; i
++)
6120 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6122 /* Writeback makes things complicated. We need to avoid clobbering
6123 the base register with one of the registers in our modified
6124 register list, but just using a different register can't work in
6127 ldm r14!, {r0-r13,pc}
6129 which would need to be rewritten as:
6133 but that can't work, because there's no free register for N.
6135 Solve this by turning off the writeback bit, and emulating
6136 writeback manually in the cleanup routine. */
6141 new_regmask
= (1 << num_in_list
) - 1;
6143 if (debug_displaced
)
6144 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6145 "{..., pc}: original reg list %.4x, modified "
6146 "list %.4x\n"), rn
, writeback
? "!" : "",
6147 (int) insn
& 0xffff, new_regmask
);
6149 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6151 dsc
->cleanup
= &cleanup_block_load_pc
;
6156 /* STM of a list of registers which includes PC. Run the instruction
6157 as-is, but out of line: this will store the wrong value for the PC,
6158 so we must manually fix up the memory in the cleanup routine.
6159 Doing things this way has the advantage that we can auto-detect
6160 the offset of the PC write (which is architecture-dependent) in
6161 the cleanup routine. */
6162 dsc
->modinsn
[0] = insn
;
6164 dsc
->cleanup
= &cleanup_block_store_pc
;
6171 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6172 struct regcache
*regs
,
6173 struct displaced_step_closure
*dsc
)
6175 int rn
= bits (insn1
, 0, 3);
6176 int load
= bit (insn1
, 4);
6177 int writeback
= bit (insn1
, 5);
6179 /* Block transfers which don't mention PC can be run directly
6181 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6182 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6184 if (rn
== ARM_PC_REGNUM
)
6186 warning (_("displaced: Unpredictable LDM or STM with "
6187 "base register r15"));
6188 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6189 "unpredictable ldm/stm", dsc
);
6192 if (debug_displaced
)
6193 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6194 "%.4x%.4x\n", insn1
, insn2
);
6196 /* Clear bit 13, since it should be always zero. */
6197 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6198 dsc
->u
.block
.rn
= rn
;
6200 dsc
->u
.block
.load
= load
;
6201 dsc
->u
.block
.user
= 0;
6202 dsc
->u
.block
.increment
= bit (insn1
, 7);
6203 dsc
->u
.block
.before
= bit (insn1
, 8);
6204 dsc
->u
.block
.writeback
= writeback
;
6205 dsc
->u
.block
.cond
= INST_AL
;
6206 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6210 if (dsc
->u
.block
.regmask
== 0xffff)
6212 /* This branch is impossible to happen. */
6217 unsigned int regmask
= dsc
->u
.block
.regmask
;
6218 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6221 for (i
= 0; i
< num_in_list
; i
++)
6222 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6227 new_regmask
= (1 << num_in_list
) - 1;
6229 if (debug_displaced
)
6230 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6231 "{..., pc}: original reg list %.4x, modified "
6232 "list %.4x\n"), rn
, writeback
? "!" : "",
6233 (int) dsc
->u
.block
.regmask
, new_regmask
);
6235 dsc
->modinsn
[0] = insn1
;
6236 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6239 dsc
->cleanup
= &cleanup_block_load_pc
;
6244 dsc
->modinsn
[0] = insn1
;
6245 dsc
->modinsn
[1] = insn2
;
6247 dsc
->cleanup
= &cleanup_block_store_pc
;
6252 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6253 This is used to avoid a dependency on BFD's bfd_endian enum. */
6256 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6259 return read_memory_unsigned_integer (memaddr
, len
,
6260 (enum bfd_endian
) byte_order
);
6263 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6266 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6269 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6272 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6275 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6280 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6283 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6285 return arm_is_thumb (self
->regcache
);
6288 /* single_step() is called just before we want to resume the inferior,
6289 if we want to single-step it but there is no hardware or kernel
6290 single-step support. We find the target of the coming instructions
6291 and breakpoint them. */
6294 arm_software_single_step (struct regcache
*regcache
)
6296 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6297 struct arm_get_next_pcs next_pcs_ctx
;
6300 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6301 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6303 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6304 &arm_get_next_pcs_ops
,
6305 gdbarch_byte_order (gdbarch
),
6306 gdbarch_byte_order_for_code (gdbarch
),
6310 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6312 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6314 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
6315 VEC_replace (CORE_ADDR
, next_pcs
, i
, pc
);
6318 discard_cleanups (old_chain
);
6323 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6324 for Linux, where some SVC instructions must be treated specially. */
6327 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6328 struct displaced_step_closure
*dsc
)
6330 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6332 if (debug_displaced
)
6333 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6334 "%.8lx\n", (unsigned long) resume_addr
);
6336 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6340 /* Common copy routine for svc instruciton. */
6343 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6344 struct displaced_step_closure
*dsc
)
6346 /* Preparation: none.
6347 Insn: unmodified svc.
6348 Cleanup: pc <- insn_addr + insn_size. */
6350 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6352 dsc
->wrote_to_pc
= 1;
6354 /* Allow OS-specific code to override SVC handling. */
6355 if (dsc
->u
.svc
.copy_svc_os
)
6356 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6359 dsc
->cleanup
= &cleanup_svc
;
6365 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6366 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6369 if (debug_displaced
)
6370 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6371 (unsigned long) insn
);
6373 dsc
->modinsn
[0] = insn
;
6375 return install_svc (gdbarch
, regs
, dsc
);
6379 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6380 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6383 if (debug_displaced
)
6384 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6387 dsc
->modinsn
[0] = insn
;
6389 return install_svc (gdbarch
, regs
, dsc
);
6392 /* Copy undefined instructions. */
6395 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6396 struct displaced_step_closure
*dsc
)
6398 if (debug_displaced
)
6399 fprintf_unfiltered (gdb_stdlog
,
6400 "displaced: copying undefined insn %.8lx\n",
6401 (unsigned long) insn
);
6403 dsc
->modinsn
[0] = insn
;
6409 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6410 struct displaced_step_closure
*dsc
)
6413 if (debug_displaced
)
6414 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6415 "%.4x %.4x\n", (unsigned short) insn1
,
6416 (unsigned short) insn2
);
6418 dsc
->modinsn
[0] = insn1
;
6419 dsc
->modinsn
[1] = insn2
;
6425 /* Copy unpredictable instructions. */
6428 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6429 struct displaced_step_closure
*dsc
)
6431 if (debug_displaced
)
6432 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6433 "%.8lx\n", (unsigned long) insn
);
6435 dsc
->modinsn
[0] = insn
;
6440 /* The decode_* functions are instruction decoding helpers. They mostly follow
6441 the presentation in the ARM ARM. */
6444 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6445 struct regcache
*regs
,
6446 struct displaced_step_closure
*dsc
)
6448 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6449 unsigned int rn
= bits (insn
, 16, 19);
6451 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6452 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6453 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6454 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6455 else if ((op1
& 0x60) == 0x20)
6456 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6457 else if ((op1
& 0x71) == 0x40)
6458 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6460 else if ((op1
& 0x77) == 0x41)
6461 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6462 else if ((op1
& 0x77) == 0x45)
6463 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6464 else if ((op1
& 0x77) == 0x51)
6467 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6469 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6471 else if ((op1
& 0x77) == 0x55)
6472 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6473 else if (op1
== 0x57)
6476 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6477 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6478 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6479 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6480 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6482 else if ((op1
& 0x63) == 0x43)
6483 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6484 else if ((op2
& 0x1) == 0x0)
6485 switch (op1
& ~0x80)
6488 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6490 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6491 case 0x71: case 0x75:
6493 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6494 case 0x63: case 0x67: case 0x73: case 0x77:
6495 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6497 return arm_copy_undef (gdbarch
, insn
, dsc
);
6500 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6504 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6505 struct regcache
*regs
,
6506 struct displaced_step_closure
*dsc
)
6508 if (bit (insn
, 27) == 0)
6509 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6510 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6511 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6514 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6517 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6519 case 0x4: case 0x5: case 0x6: case 0x7:
6520 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6523 switch ((insn
& 0xe00000) >> 21)
6525 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6527 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6530 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6533 return arm_copy_undef (gdbarch
, insn
, dsc
);
6538 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6539 switch ((insn
& 0xe00000) >> 21)
6542 /* ldc/ldc2 imm (undefined for rn == pc). */
6543 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6544 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6547 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6549 case 0x4: case 0x5: case 0x6: case 0x7:
6550 /* ldc/ldc2 lit (undefined for rn != pc). */
6551 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6552 : arm_copy_undef (gdbarch
, insn
, dsc
);
6555 return arm_copy_undef (gdbarch
, insn
, dsc
);
6560 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6563 if (bits (insn
, 16, 19) == 0xf)
6565 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6567 return arm_copy_undef (gdbarch
, insn
, dsc
);
6571 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6573 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6577 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6579 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6582 return arm_copy_undef (gdbarch
, insn
, dsc
);
6586 /* Decode miscellaneous instructions in dp/misc encoding space. */
6589 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6590 struct regcache
*regs
,
6591 struct displaced_step_closure
*dsc
)
6593 unsigned int op2
= bits (insn
, 4, 6);
6594 unsigned int op
= bits (insn
, 21, 22);
6599 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6602 if (op
== 0x1) /* bx. */
6603 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6605 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6607 return arm_copy_undef (gdbarch
, insn
, dsc
);
6611 /* Not really supported. */
6612 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6614 return arm_copy_undef (gdbarch
, insn
, dsc
);
6618 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6619 regs
, dsc
); /* blx register. */
6621 return arm_copy_undef (gdbarch
, insn
, dsc
);
6624 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6628 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6630 /* Not really supported. */
6631 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6634 return arm_copy_undef (gdbarch
, insn
, dsc
);
6639 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6640 struct regcache
*regs
,
6641 struct displaced_step_closure
*dsc
)
6644 switch (bits (insn
, 20, 24))
6647 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6650 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6652 case 0x12: case 0x16:
6653 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6656 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6660 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6662 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6663 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6664 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6665 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6666 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6667 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6668 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6669 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6670 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6671 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6672 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6673 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6674 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6675 /* 2nd arg means "unprivileged". */
6676 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6680 /* Should be unreachable. */
6685 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6686 struct regcache
*regs
,
6687 struct displaced_step_closure
*dsc
)
6689 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6690 uint32_t op1
= bits (insn
, 20, 24);
6692 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6693 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6694 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6695 else if ((!a
&& (op1
& 0x17) == 0x02)
6696 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6697 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6698 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6699 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6700 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6701 else if ((!a
&& (op1
& 0x17) == 0x03)
6702 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6703 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6704 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6705 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6706 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6707 else if ((!a
&& (op1
& 0x17) == 0x06)
6708 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6709 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6710 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6711 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6712 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6713 else if ((!a
&& (op1
& 0x17) == 0x07)
6714 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6715 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6717 /* Should be unreachable. */
6722 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6723 struct displaced_step_closure
*dsc
)
6725 switch (bits (insn
, 20, 24))
6727 case 0x00: case 0x01: case 0x02: case 0x03:
6728 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6730 case 0x04: case 0x05: case 0x06: case 0x07:
6731 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6733 case 0x08: case 0x09: case 0x0a: case 0x0b:
6734 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6735 return arm_copy_unmodified (gdbarch
, insn
,
6736 "decode/pack/unpack/saturate/reverse", dsc
);
6739 if (bits (insn
, 5, 7) == 0) /* op2. */
6741 if (bits (insn
, 12, 15) == 0xf)
6742 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6744 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6747 return arm_copy_undef (gdbarch
, insn
, dsc
);
6749 case 0x1a: case 0x1b:
6750 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6751 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6753 return arm_copy_undef (gdbarch
, insn
, dsc
);
6755 case 0x1c: case 0x1d:
6756 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6758 if (bits (insn
, 0, 3) == 0xf)
6759 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6761 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6764 return arm_copy_undef (gdbarch
, insn
, dsc
);
6766 case 0x1e: case 0x1f:
6767 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6768 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6770 return arm_copy_undef (gdbarch
, insn
, dsc
);
6773 /* Should be unreachable. */
6778 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6779 struct regcache
*regs
,
6780 struct displaced_step_closure
*dsc
)
6783 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6785 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6789 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6790 struct regcache
*regs
,
6791 struct displaced_step_closure
*dsc
)
6793 unsigned int opcode
= bits (insn
, 20, 24);
6797 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6798 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6800 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6801 case 0x12: case 0x16:
6802 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6804 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6805 case 0x13: case 0x17:
6806 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6808 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6809 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6810 /* Note: no writeback for these instructions. Bit 25 will always be
6811 zero though (via caller), so the following works OK. */
6812 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6815 /* Should be unreachable. */
6819 /* Decode shifted register instructions. */
6822 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6823 uint16_t insn2
, struct regcache
*regs
,
6824 struct displaced_step_closure
*dsc
)
6826 /* PC is only allowed to be used in instruction MOV. */
6828 unsigned int op
= bits (insn1
, 5, 8);
6829 unsigned int rn
= bits (insn1
, 0, 3);
6831 if (op
== 0x2 && rn
== 0xf) /* MOV */
6832 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6834 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6835 "dp (shift reg)", dsc
);
6839 /* Decode extension register load/store. Exactly the same as
6840 arm_decode_ext_reg_ld_st. */
6843 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6844 uint16_t insn2
, struct regcache
*regs
,
6845 struct displaced_step_closure
*dsc
)
6847 unsigned int opcode
= bits (insn1
, 4, 8);
6851 case 0x04: case 0x05:
6852 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6853 "vfp/neon vmov", dsc
);
6855 case 0x08: case 0x0c: /* 01x00 */
6856 case 0x0a: case 0x0e: /* 01x10 */
6857 case 0x12: case 0x16: /* 10x10 */
6858 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6859 "vfp/neon vstm/vpush", dsc
);
6861 case 0x09: case 0x0d: /* 01x01 */
6862 case 0x0b: case 0x0f: /* 01x11 */
6863 case 0x13: case 0x17: /* 10x11 */
6864 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6865 "vfp/neon vldm/vpop", dsc
);
6867 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6868 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6870 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6871 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6874 /* Should be unreachable. */
6879 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6880 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6882 unsigned int op1
= bits (insn
, 20, 25);
6883 int op
= bit (insn
, 4);
6884 unsigned int coproc
= bits (insn
, 8, 11);
6886 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6887 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6888 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6889 && (coproc
& 0xe) != 0xa)
6891 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6892 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6893 && (coproc
& 0xe) != 0xa)
6894 /* ldc/ldc2 imm/lit. */
6895 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6896 else if ((op1
& 0x3e) == 0x00)
6897 return arm_copy_undef (gdbarch
, insn
, dsc
);
6898 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6899 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6900 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6901 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6902 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6903 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6904 else if ((op1
& 0x30) == 0x20 && !op
)
6906 if ((coproc
& 0xe) == 0xa)
6907 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6909 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6911 else if ((op1
& 0x30) == 0x20 && op
)
6912 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6913 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6914 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6915 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6916 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6917 else if ((op1
& 0x30) == 0x30)
6918 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6920 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6924 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6925 uint16_t insn2
, struct regcache
*regs
,
6926 struct displaced_step_closure
*dsc
)
6928 unsigned int coproc
= bits (insn2
, 8, 11);
6929 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6930 unsigned int bit_9
= bit (insn1
, 9);
6931 unsigned int bit_4
= bit (insn1
, 4);
6936 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6937 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6939 else if (bit_5_8
== 0) /* UNDEFINED. */
6940 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6943 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6944 if ((coproc
& 0xe) == 0xa)
6945 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6947 else /* coproc is not 101x. */
6949 if (bit_4
== 0) /* STC/STC2. */
6950 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6952 else /* LDC/LDC2 {literal, immeidate}. */
6953 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6959 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6965 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6966 struct displaced_step_closure
*dsc
, int rd
)
6972 Preparation: Rd <- PC
6978 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6979 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6983 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6984 struct displaced_step_closure
*dsc
,
6985 int rd
, unsigned int imm
)
6988 /* Encoding T2: ADDS Rd, #imm */
6989 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6991 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6997 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6998 struct regcache
*regs
,
6999 struct displaced_step_closure
*dsc
)
7001 unsigned int rd
= bits (insn
, 8, 10);
7002 unsigned int imm8
= bits (insn
, 0, 7);
7004 if (debug_displaced
)
7005 fprintf_unfiltered (gdb_stdlog
,
7006 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7009 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7013 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7014 uint16_t insn2
, struct regcache
*regs
,
7015 struct displaced_step_closure
*dsc
)
7017 unsigned int rd
= bits (insn2
, 8, 11);
7018 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7019 extract raw immediate encoding rather than computing immediate. When
7020 generating ADD or SUB instruction, we can simply perform OR operation to
7021 set immediate into ADD. */
7022 unsigned int imm_3_8
= insn2
& 0x70ff;
7023 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7025 if (debug_displaced
)
7026 fprintf_unfiltered (gdb_stdlog
,
7027 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7028 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7030 if (bit (insn1
, 7)) /* Encoding T2 */
7032 /* Encoding T3: SUB Rd, Rd, #imm */
7033 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7034 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7036 else /* Encoding T3 */
7038 /* Encoding T3: ADD Rd, Rd, #imm */
7039 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7040 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7044 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7050 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7051 struct regcache
*regs
,
7052 struct displaced_step_closure
*dsc
)
7054 unsigned int rt
= bits (insn1
, 8, 10);
7056 int imm8
= (bits (insn1
, 0, 7) << 2);
7062 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7064 Insn: LDR R0, [R2, R3];
7065 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7067 if (debug_displaced
)
7068 fprintf_unfiltered (gdb_stdlog
,
7069 "displaced: copying thumb ldr r%d [pc #%d]\n"
7072 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7073 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7074 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7075 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7076 /* The assembler calculates the required value of the offset from the
7077 Align(PC,4) value of this instruction to the label. */
7078 pc
= pc
& 0xfffffffc;
7080 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7081 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7084 dsc
->u
.ldst
.xfersize
= 4;
7086 dsc
->u
.ldst
.immed
= 0;
7087 dsc
->u
.ldst
.writeback
= 0;
7088 dsc
->u
.ldst
.restore_r4
= 0;
7090 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7092 dsc
->cleanup
= &cleanup_load
;
7097 /* Copy Thumb cbnz/cbz insruction. */
7100 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7101 struct regcache
*regs
,
7102 struct displaced_step_closure
*dsc
)
7104 int non_zero
= bit (insn1
, 11);
7105 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7106 CORE_ADDR from
= dsc
->insn_addr
;
7107 int rn
= bits (insn1
, 0, 2);
7108 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7110 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7111 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7112 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7113 condition is false, let it be, cleanup_branch will do nothing. */
7114 if (dsc
->u
.branch
.cond
)
7116 dsc
->u
.branch
.cond
= INST_AL
;
7117 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7120 dsc
->u
.branch
.dest
= from
+ 2;
7122 dsc
->u
.branch
.link
= 0;
7123 dsc
->u
.branch
.exchange
= 0;
7125 if (debug_displaced
)
7126 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7127 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7128 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7130 dsc
->modinsn
[0] = THUMB_NOP
;
7132 dsc
->cleanup
= &cleanup_branch
;
7136 /* Copy Table Branch Byte/Halfword */
7138 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7139 uint16_t insn2
, struct regcache
*regs
,
7140 struct displaced_step_closure
*dsc
)
7142 ULONGEST rn_val
, rm_val
;
7143 int is_tbh
= bit (insn2
, 4);
7144 CORE_ADDR halfwords
= 0;
7145 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7147 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7148 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7154 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7155 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7161 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7162 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7165 if (debug_displaced
)
7166 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7167 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7168 (unsigned int) rn_val
, (unsigned int) rm_val
,
7169 (unsigned int) halfwords
);
7171 dsc
->u
.branch
.cond
= INST_AL
;
7172 dsc
->u
.branch
.link
= 0;
7173 dsc
->u
.branch
.exchange
= 0;
7174 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7176 dsc
->cleanup
= &cleanup_branch
;
7182 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7183 struct displaced_step_closure
*dsc
)
7186 int val
= displaced_read_reg (regs
, dsc
, 7);
7187 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7190 val
= displaced_read_reg (regs
, dsc
, 8);
7191 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7194 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7199 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7200 struct regcache
*regs
,
7201 struct displaced_step_closure
*dsc
)
7203 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7205 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7208 (1) register list is full, that is, r0-r7 are used.
7209 Prepare: tmp[0] <- r8
7211 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7212 MOV r8, r7; Move value of r7 to r8;
7213 POP {r7}; Store PC value into r7.
7215 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7217 (2) register list is not full, supposing there are N registers in
7218 register list (except PC, 0 <= N <= 7).
7219 Prepare: for each i, 0 - N, tmp[i] <- ri.
7221 POP {r0, r1, ...., rN};
7223 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7224 from tmp[] properly.
7226 if (debug_displaced
)
7227 fprintf_unfiltered (gdb_stdlog
,
7228 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7229 dsc
->u
.block
.regmask
, insn1
);
7231 if (dsc
->u
.block
.regmask
== 0xff)
7233 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7235 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7236 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7237 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7240 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7244 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7246 unsigned int new_regmask
;
7248 for (i
= 0; i
< num_in_list
+ 1; i
++)
7249 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7251 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7253 if (debug_displaced
)
7254 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7255 "{..., pc}: original reg list %.4x,"
7256 " modified list %.4x\n"),
7257 (int) dsc
->u
.block
.regmask
, new_regmask
);
7259 dsc
->u
.block
.regmask
|= 0x8000;
7260 dsc
->u
.block
.writeback
= 0;
7261 dsc
->u
.block
.cond
= INST_AL
;
7263 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7265 dsc
->cleanup
= &cleanup_block_load_pc
;
7272 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7273 struct regcache
*regs
,
7274 struct displaced_step_closure
*dsc
)
7276 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7277 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7280 /* 16-bit thumb instructions. */
7281 switch (op_bit_12_15
)
7283 /* Shift (imme), add, subtract, move and compare. */
7284 case 0: case 1: case 2: case 3:
7285 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7286 "shift/add/sub/mov/cmp",
7290 switch (op_bit_10_11
)
7292 case 0: /* Data-processing */
7293 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7297 case 1: /* Special data instructions and branch and exchange. */
7299 unsigned short op
= bits (insn1
, 7, 9);
7300 if (op
== 6 || op
== 7) /* BX or BLX */
7301 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7302 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7303 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7305 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7309 default: /* LDR (literal) */
7310 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7313 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7314 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7317 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7318 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7319 else /* Generate SP-relative address */
7320 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7322 case 11: /* Misc 16-bit instructions */
7324 switch (bits (insn1
, 8, 11))
7326 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7327 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7329 case 12: case 13: /* POP */
7330 if (bit (insn1
, 8)) /* PC is in register list. */
7331 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7333 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7335 case 15: /* If-Then, and hints */
7336 if (bits (insn1
, 0, 3))
7337 /* If-Then makes up to four following instructions conditional.
7338 IT instruction itself is not conditional, so handle it as a
7339 common unmodified instruction. */
7340 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7343 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7346 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7351 if (op_bit_10_11
< 2) /* Store multiple registers */
7352 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7353 else /* Load multiple registers */
7354 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7356 case 13: /* Conditional branch and supervisor call */
7357 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7358 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7360 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7362 case 14: /* Unconditional branch */
7363 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7370 internal_error (__FILE__
, __LINE__
,
7371 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7375 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7376 uint16_t insn1
, uint16_t insn2
,
7377 struct regcache
*regs
,
7378 struct displaced_step_closure
*dsc
)
7380 int rt
= bits (insn2
, 12, 15);
7381 int rn
= bits (insn1
, 0, 3);
7382 int op1
= bits (insn1
, 7, 8);
7384 switch (bits (insn1
, 5, 6))
7386 case 0: /* Load byte and memory hints */
7387 if (rt
== 0xf) /* PLD/PLI */
7390 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7391 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7393 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7398 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7399 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7402 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7403 "ldrb{reg, immediate}/ldrbt",
7408 case 1: /* Load halfword and memory hints. */
7409 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7410 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7411 "pld/unalloc memhint", dsc
);
7415 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7418 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7422 case 2: /* Load word */
7424 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7427 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7428 else if (op1
== 0x1) /* Encoding T3 */
7429 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7431 else /* op1 == 0x0 */
7433 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7434 /* LDR (immediate) */
7435 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7436 dsc
, bit (insn2
, 8), 1);
7437 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7438 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7441 /* LDR (register) */
7442 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7448 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7455 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7456 uint16_t insn2
, struct regcache
*regs
,
7457 struct displaced_step_closure
*dsc
)
7460 unsigned short op
= bit (insn2
, 15);
7461 unsigned int op1
= bits (insn1
, 11, 12);
7467 switch (bits (insn1
, 9, 10))
7472 /* Load/store {dual, execlusive}, table branch. */
7473 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7474 && bits (insn2
, 5, 7) == 0)
7475 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7478 /* PC is not allowed to use in load/store {dual, exclusive}
7480 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7481 "load/store dual/ex", dsc
);
7483 else /* load/store multiple */
7485 switch (bits (insn1
, 7, 8))
7487 case 0: case 3: /* SRS, RFE */
7488 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7491 case 1: case 2: /* LDM/STM/PUSH/POP */
7492 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7499 /* Data-processing (shift register). */
7500 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7503 default: /* Coprocessor instructions. */
7504 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7509 case 2: /* op1 = 2 */
7510 if (op
) /* Branch and misc control. */
7512 if (bit (insn2
, 14) /* BLX/BL */
7513 || bit (insn2
, 12) /* Unconditional branch */
7514 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7515 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7517 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7522 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7524 int op
= bits (insn1
, 4, 8);
7525 int rn
= bits (insn1
, 0, 3);
7526 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7527 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7530 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7533 else /* Data processing (modified immeidate) */
7534 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7538 case 3: /* op1 = 3 */
7539 switch (bits (insn1
, 9, 10))
7543 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7545 else /* NEON Load/Store and Store single data item */
7546 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7547 "neon elt/struct load/store",
7550 case 1: /* op1 = 3, bits (9, 10) == 1 */
7551 switch (bits (insn1
, 7, 8))
7553 case 0: case 1: /* Data processing (register) */
7554 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7557 case 2: /* Multiply and absolute difference */
7558 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7559 "mul/mua/diff", dsc
);
7561 case 3: /* Long multiply and divide */
7562 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7567 default: /* Coprocessor instructions */
7568 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7577 internal_error (__FILE__
, __LINE__
,
7578 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7583 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7584 struct regcache
*regs
,
7585 struct displaced_step_closure
*dsc
)
7587 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7589 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7591 if (debug_displaced
)
7592 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7593 "at %.8lx\n", insn1
, (unsigned long) from
);
7596 dsc
->insn_size
= thumb_insn_size (insn1
);
7597 if (thumb_insn_size (insn1
) == 4)
7600 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7601 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7604 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7608 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7609 CORE_ADDR to
, struct regcache
*regs
,
7610 struct displaced_step_closure
*dsc
)
7613 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7616 /* Most displaced instructions use a 1-instruction scratch space, so set this
7617 here and override below if/when necessary. */
7619 dsc
->insn_addr
= from
;
7620 dsc
->scratch_base
= to
;
7621 dsc
->cleanup
= NULL
;
7622 dsc
->wrote_to_pc
= 0;
7624 if (!displaced_in_arm_mode (regs
))
7625 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7629 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7630 if (debug_displaced
)
7631 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7632 "at %.8lx\n", (unsigned long) insn
,
7633 (unsigned long) from
);
7635 if ((insn
& 0xf0000000) == 0xf0000000)
7636 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7637 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7639 case 0x0: case 0x1: case 0x2: case 0x3:
7640 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7643 case 0x4: case 0x5: case 0x6:
7644 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7648 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7651 case 0x8: case 0x9: case 0xa: case 0xb:
7652 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7655 case 0xc: case 0xd: case 0xe: case 0xf:
7656 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7661 internal_error (__FILE__
, __LINE__
,
7662 _("arm_process_displaced_insn: Instruction decode error"));
7665 /* Actually set up the scratch space for a displaced instruction. */
7668 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7669 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7671 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7672 unsigned int i
, len
, offset
;
7673 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7674 int size
= dsc
->is_thumb
? 2 : 4;
7675 const gdb_byte
*bkp_insn
;
7678 /* Poke modified instruction(s). */
7679 for (i
= 0; i
< dsc
->numinsns
; i
++)
7681 if (debug_displaced
)
7683 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7685 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7688 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7689 (unsigned short)dsc
->modinsn
[i
]);
7691 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7692 (unsigned long) to
+ offset
);
7695 write_memory_unsigned_integer (to
+ offset
, size
,
7696 byte_order_for_code
,
7701 /* Choose the correct breakpoint instruction. */
7704 bkp_insn
= tdep
->thumb_breakpoint
;
7705 len
= tdep
->thumb_breakpoint_size
;
7709 bkp_insn
= tdep
->arm_breakpoint
;
7710 len
= tdep
->arm_breakpoint_size
;
7713 /* Put breakpoint afterwards. */
7714 write_memory (to
+ offset
, bkp_insn
, len
);
7716 if (debug_displaced
)
7717 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7718 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7721 /* Entry point for cleaning things up after a displaced instruction has been
7725 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7726 struct displaced_step_closure
*dsc
,
7727 CORE_ADDR from
, CORE_ADDR to
,
7728 struct regcache
*regs
)
7731 dsc
->cleanup (gdbarch
, regs
, dsc
);
7733 if (!dsc
->wrote_to_pc
)
7734 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7735 dsc
->insn_addr
+ dsc
->insn_size
);
7739 #include "bfd-in2.h"
7740 #include "libcoff.h"
7743 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7745 gdb_disassembler
*di
7746 = static_cast<gdb_disassembler
*>(info
->application_data
);
7747 struct gdbarch
*gdbarch
= di
->arch ();
7749 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7751 static asymbol
*asym
;
7752 static combined_entry_type ce
;
7753 static struct coff_symbol_struct csym
;
7754 static struct bfd fake_bfd
;
7755 static bfd_target fake_target
;
7757 if (csym
.native
== NULL
)
7759 /* Create a fake symbol vector containing a Thumb symbol.
7760 This is solely so that the code in print_insn_little_arm()
7761 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7762 the presence of a Thumb symbol and switch to decoding
7763 Thumb instructions. */
7765 fake_target
.flavour
= bfd_target_coff_flavour
;
7766 fake_bfd
.xvec
= &fake_target
;
7767 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7769 csym
.symbol
.the_bfd
= &fake_bfd
;
7770 csym
.symbol
.name
= "fake";
7771 asym
= (asymbol
*) & csym
;
7774 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7775 info
->symbols
= &asym
;
7778 info
->symbols
= NULL
;
7780 if (info
->endian
== BFD_ENDIAN_BIG
)
7781 return print_insn_big_arm (memaddr
, info
);
7783 return print_insn_little_arm (memaddr
, info
);
7786 /* The following define instruction sequences that will cause ARM
7787 cpu's to take an undefined instruction trap. These are used to
7788 signal a breakpoint to GDB.
7790 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7791 modes. A different instruction is required for each mode. The ARM
7792 cpu's can also be big or little endian. Thus four different
7793 instructions are needed to support all cases.
7795 Note: ARMv4 defines several new instructions that will take the
7796 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7797 not in fact add the new instructions. The new undefined
7798 instructions in ARMv4 are all instructions that had no defined
7799 behaviour in earlier chips. There is no guarantee that they will
7800 raise an exception, but may be treated as NOP's. In practice, it
7801 may only safe to rely on instructions matching:
7803 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7804 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7805 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7807 Even this may only true if the condition predicate is true. The
7808 following use a condition predicate of ALWAYS so it is always TRUE.
7810 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7811 and NetBSD all use a software interrupt rather than an undefined
7812 instruction to force a trap. This can be handled by by the
7813 abi-specific code during establishment of the gdbarch vector. */
7815 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7816 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7817 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7818 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7820 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7821 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7822 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7823 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7825 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7828 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7830 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7831 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7833 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7835 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7837 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7838 check whether we are replacing a 32-bit instruction. */
7839 if (tdep
->thumb2_breakpoint
!= NULL
)
7843 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7845 unsigned short inst1
;
7847 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7848 if (thumb_insn_size (inst1
) == 4)
7849 return ARM_BP_KIND_THUMB2
;
7853 return ARM_BP_KIND_THUMB
;
7856 return ARM_BP_KIND_ARM
;
7860 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7862 static const gdb_byte
*
7863 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7865 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7869 case ARM_BP_KIND_ARM
:
7870 *size
= tdep
->arm_breakpoint_size
;
7871 return tdep
->arm_breakpoint
;
7872 case ARM_BP_KIND_THUMB
:
7873 *size
= tdep
->thumb_breakpoint_size
;
7874 return tdep
->thumb_breakpoint
;
7875 case ARM_BP_KIND_THUMB2
:
7876 *size
= tdep
->thumb2_breakpoint_size
;
7877 return tdep
->thumb2_breakpoint
;
7879 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7883 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7886 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7887 struct regcache
*regcache
,
7892 /* Check the memory pointed by PC is readable. */
7893 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7895 struct arm_get_next_pcs next_pcs_ctx
;
7898 VEC (CORE_ADDR
) *next_pcs
= NULL
;
7899 struct cleanup
*old_chain
7900 = make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
7902 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7903 &arm_get_next_pcs_ops
,
7904 gdbarch_byte_order (gdbarch
),
7905 gdbarch_byte_order_for_code (gdbarch
),
7909 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7911 /* If MEMADDR is the next instruction of current pc, do the
7912 software single step computation, and get the thumb mode by
7913 the destination address. */
7914 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
7916 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7918 do_cleanups (old_chain
);
7920 if (IS_THUMB_ADDR (pc
))
7922 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7923 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7926 return ARM_BP_KIND_ARM
;
7930 do_cleanups (old_chain
);
7933 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7936 /* Extract from an array REGBUF containing the (raw) register state a
7937 function return value of type TYPE, and copy that, in virtual
7938 format, into VALBUF. */
7941 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7944 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7945 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7947 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7949 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7953 /* The value is in register F0 in internal format. We need to
7954 extract the raw value and then convert it to the desired
7956 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7958 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7959 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7960 valbuf
, gdbarch_byte_order (gdbarch
));
7964 case ARM_FLOAT_SOFT_FPA
:
7965 case ARM_FLOAT_SOFT_VFP
:
7966 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7967 not using the VFP ABI code. */
7969 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7970 if (TYPE_LENGTH (type
) > 4)
7971 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7972 valbuf
+ INT_REGISTER_SIZE
);
7976 internal_error (__FILE__
, __LINE__
,
7977 _("arm_extract_return_value: "
7978 "Floating point model not supported"));
7982 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7983 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7984 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7985 || TYPE_CODE (type
) == TYPE_CODE_PTR
7986 || TYPE_CODE (type
) == TYPE_CODE_REF
7987 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7989 /* If the type is a plain integer, then the access is
7990 straight-forward. Otherwise we have to play around a bit
7992 int len
= TYPE_LENGTH (type
);
7993 int regno
= ARM_A1_REGNUM
;
7998 /* By using store_unsigned_integer we avoid having to do
7999 anything special for small big-endian values. */
8000 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8001 store_unsigned_integer (valbuf
,
8002 (len
> INT_REGISTER_SIZE
8003 ? INT_REGISTER_SIZE
: len
),
8005 len
-= INT_REGISTER_SIZE
;
8006 valbuf
+= INT_REGISTER_SIZE
;
8011 /* For a structure or union the behaviour is as if the value had
8012 been stored to word-aligned memory and then loaded into
8013 registers with 32-bit load instruction(s). */
8014 int len
= TYPE_LENGTH (type
);
8015 int regno
= ARM_A1_REGNUM
;
8016 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8020 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8021 memcpy (valbuf
, tmpbuf
,
8022 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8023 len
-= INT_REGISTER_SIZE
;
8024 valbuf
+= INT_REGISTER_SIZE
;
8030 /* Will a function return an aggregate type in memory or in a
8031 register? Return 0 if an aggregate type can be returned in a
8032 register, 1 if it must be returned in memory. */
8035 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8037 enum type_code code
;
8039 type
= check_typedef (type
);
8041 /* Simple, non-aggregate types (ie not including vectors and
8042 complex) are always returned in a register (or registers). */
8043 code
= TYPE_CODE (type
);
8044 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8045 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8048 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
8050 /* Vector values should be returned using ARM registers if they
8051 are not over 16 bytes. */
8052 return (TYPE_LENGTH (type
) > 16);
8055 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8057 /* The AAPCS says all aggregates not larger than a word are returned
8059 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
8068 /* All aggregate types that won't fit in a register must be returned
8070 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8073 /* In the ARM ABI, "integer" like aggregate types are returned in
8074 registers. For an aggregate type to be integer like, its size
8075 must be less than or equal to INT_REGISTER_SIZE and the
8076 offset of each addressable subfield must be zero. Note that bit
8077 fields are not addressable, and all addressable subfields of
8078 unions always start at offset zero.
8080 This function is based on the behaviour of GCC 2.95.1.
8081 See: gcc/arm.c: arm_return_in_memory() for details.
8083 Note: All versions of GCC before GCC 2.95.2 do not set up the
8084 parameters correctly for a function returning the following
8085 structure: struct { float f;}; This should be returned in memory,
8086 not a register. Richard Earnshaw sent me a patch, but I do not
8087 know of any way to detect if a function like the above has been
8088 compiled with the correct calling convention. */
8090 /* Assume all other aggregate types can be returned in a register.
8091 Run a check for structures, unions and arrays. */
8094 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8097 /* Need to check if this struct/union is "integer" like. For
8098 this to be true, its size must be less than or equal to
8099 INT_REGISTER_SIZE and the offset of each addressable
8100 subfield must be zero. Note that bit fields are not
8101 addressable, and unions always start at offset zero. If any
8102 of the subfields is a floating point type, the struct/union
8103 cannot be an integer type. */
8105 /* For each field in the object, check:
8106 1) Is it FP? --> yes, nRc = 1;
8107 2) Is it addressable (bitpos != 0) and
8108 not packed (bitsize == 0)?
8112 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8114 enum type_code field_type_code
;
8117 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8120 /* Is it a floating point type field? */
8121 if (field_type_code
== TYPE_CODE_FLT
)
8127 /* If bitpos != 0, then we have to care about it. */
8128 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8130 /* Bitfields are not addressable. If the field bitsize is
8131 zero, then the field is not packed. Hence it cannot be
8132 a bitfield or any other packed type. */
8133 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8146 /* Write into appropriate registers a function return value of type
8147 TYPE, given in virtual format. */
8150 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8151 const gdb_byte
*valbuf
)
8153 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8154 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8156 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8158 gdb_byte buf
[MAX_REGISTER_SIZE
];
8160 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8164 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8165 gdbarch_byte_order (gdbarch
));
8166 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8169 case ARM_FLOAT_SOFT_FPA
:
8170 case ARM_FLOAT_SOFT_VFP
:
8171 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8172 not using the VFP ABI code. */
8174 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8175 if (TYPE_LENGTH (type
) > 4)
8176 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8177 valbuf
+ INT_REGISTER_SIZE
);
8181 internal_error (__FILE__
, __LINE__
,
8182 _("arm_store_return_value: Floating "
8183 "point model not supported"));
8187 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8188 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8189 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8190 || TYPE_CODE (type
) == TYPE_CODE_PTR
8191 || TYPE_CODE (type
) == TYPE_CODE_REF
8192 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8194 if (TYPE_LENGTH (type
) <= 4)
8196 /* Values of one word or less are zero/sign-extended and
8198 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8199 LONGEST val
= unpack_long (type
, valbuf
);
8201 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8202 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8206 /* Integral values greater than one word are stored in consecutive
8207 registers starting with r0. This will always be a multiple of
8208 the regiser size. */
8209 int len
= TYPE_LENGTH (type
);
8210 int regno
= ARM_A1_REGNUM
;
8214 regcache_cooked_write (regs
, regno
++, valbuf
);
8215 len
-= INT_REGISTER_SIZE
;
8216 valbuf
+= INT_REGISTER_SIZE
;
8222 /* For a structure or union the behaviour is as if the value had
8223 been stored to word-aligned memory and then loaded into
8224 registers with 32-bit load instruction(s). */
8225 int len
= TYPE_LENGTH (type
);
8226 int regno
= ARM_A1_REGNUM
;
8227 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8231 memcpy (tmpbuf
, valbuf
,
8232 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8233 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8234 len
-= INT_REGISTER_SIZE
;
8235 valbuf
+= INT_REGISTER_SIZE
;
8241 /* Handle function return values. */
8243 static enum return_value_convention
8244 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8245 struct type
*valtype
, struct regcache
*regcache
,
8246 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8249 struct type
*func_type
= function
? value_type (function
) : NULL
;
8250 enum arm_vfp_cprc_base_type vfp_base_type
;
8253 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8254 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8256 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8257 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8259 for (i
= 0; i
< vfp_base_count
; i
++)
8261 if (reg_char
== 'q')
8264 arm_neon_quad_write (gdbarch
, regcache
, i
,
8265 writebuf
+ i
* unit_length
);
8268 arm_neon_quad_read (gdbarch
, regcache
, i
,
8269 readbuf
+ i
* unit_length
);
8276 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8277 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8280 regcache_cooked_write (regcache
, regnum
,
8281 writebuf
+ i
* unit_length
);
8283 regcache_cooked_read (regcache
, regnum
,
8284 readbuf
+ i
* unit_length
);
8287 return RETURN_VALUE_REGISTER_CONVENTION
;
8290 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8291 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8292 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8294 if (tdep
->struct_return
== pcc_struct_return
8295 || arm_return_in_memory (gdbarch
, valtype
))
8296 return RETURN_VALUE_STRUCT_CONVENTION
;
8298 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8300 if (arm_return_in_memory (gdbarch
, valtype
))
8301 return RETURN_VALUE_STRUCT_CONVENTION
;
8305 arm_store_return_value (valtype
, regcache
, writebuf
);
8308 arm_extract_return_value (valtype
, regcache
, readbuf
);
8310 return RETURN_VALUE_REGISTER_CONVENTION
;
8315 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8317 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8319 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8321 gdb_byte buf
[INT_REGISTER_SIZE
];
8323 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8325 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8329 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8333 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8334 return the target PC. Otherwise return 0. */
8337 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8341 CORE_ADDR start_addr
;
8343 /* Find the starting address and name of the function containing the PC. */
8344 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8346 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8348 start_addr
= arm_skip_bx_reg (frame
, pc
);
8349 if (start_addr
!= 0)
8355 /* If PC is in a Thumb call or return stub, return the address of the
8356 target PC, which is in a register. The thunk functions are called
8357 _call_via_xx, where x is the register name. The possible names
8358 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8359 functions, named __ARM_call_via_r[0-7]. */
8360 if (startswith (name
, "_call_via_")
8361 || startswith (name
, "__ARM_call_via_"))
8363 /* Use the name suffix to determine which register contains the
8365 static char *table
[15] =
8366 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8367 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8370 int offset
= strlen (name
) - 2;
8372 for (regno
= 0; regno
<= 14; regno
++)
8373 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8374 return get_frame_register_unsigned (frame
, regno
);
8377 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8378 non-interworking calls to foo. We could decode the stubs
8379 to find the target but it's easier to use the symbol table. */
8380 namelen
= strlen (name
);
8381 if (name
[0] == '_' && name
[1] == '_'
8382 && ((namelen
> 2 + strlen ("_from_thumb")
8383 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8384 || (namelen
> 2 + strlen ("_from_arm")
8385 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8388 int target_len
= namelen
- 2;
8389 struct bound_minimal_symbol minsym
;
8390 struct objfile
*objfile
;
8391 struct obj_section
*sec
;
8393 if (name
[namelen
- 1] == 'b')
8394 target_len
-= strlen ("_from_thumb");
8396 target_len
-= strlen ("_from_arm");
8398 target_name
= (char *) alloca (target_len
+ 1);
8399 memcpy (target_name
, name
+ 2, target_len
);
8400 target_name
[target_len
] = '\0';
8402 sec
= find_pc_section (pc
);
8403 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8404 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8405 if (minsym
.minsym
!= NULL
)
8406 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8411 return 0; /* not a stub */
8415 set_arm_command (char *args
, int from_tty
)
8417 printf_unfiltered (_("\
8418 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8419 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8423 show_arm_command (char *args
, int from_tty
)
8425 cmd_show_list (showarmcmdlist
, from_tty
, "");
8429 arm_update_current_architecture (void)
8431 struct gdbarch_info info
;
8433 /* If the current architecture is not ARM, we have nothing to do. */
8434 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8437 /* Update the architecture. */
8438 gdbarch_info_init (&info
);
8440 if (!gdbarch_update_p (info
))
8441 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8445 set_fp_model_sfunc (char *args
, int from_tty
,
8446 struct cmd_list_element
*c
)
8450 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8451 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8453 arm_fp_model
= (enum arm_float_model
) fp_model
;
8457 if (fp_model
== ARM_FLOAT_LAST
)
8458 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8461 arm_update_current_architecture ();
8465 show_fp_model (struct ui_file
*file
, int from_tty
,
8466 struct cmd_list_element
*c
, const char *value
)
8468 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8470 if (arm_fp_model
== ARM_FLOAT_AUTO
8471 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8472 fprintf_filtered (file
, _("\
8473 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8474 fp_model_strings
[tdep
->fp_model
]);
8476 fprintf_filtered (file
, _("\
8477 The current ARM floating point model is \"%s\".\n"),
8478 fp_model_strings
[arm_fp_model
]);
8482 arm_set_abi (char *args
, int from_tty
,
8483 struct cmd_list_element
*c
)
8487 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8488 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8490 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8494 if (arm_abi
== ARM_ABI_LAST
)
8495 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8498 arm_update_current_architecture ();
8502 arm_show_abi (struct ui_file
*file
, int from_tty
,
8503 struct cmd_list_element
*c
, const char *value
)
8505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8507 if (arm_abi_global
== ARM_ABI_AUTO
8508 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8509 fprintf_filtered (file
, _("\
8510 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8511 arm_abi_strings
[tdep
->arm_abi
]);
8513 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8518 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8519 struct cmd_list_element
*c
, const char *value
)
8521 fprintf_filtered (file
,
8522 _("The current execution mode assumed "
8523 "(when symbols are unavailable) is \"%s\".\n"),
8524 arm_fallback_mode_string
);
8528 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8529 struct cmd_list_element
*c
, const char *value
)
8531 fprintf_filtered (file
,
8532 _("The current execution mode assumed "
8533 "(even when symbols are available) is \"%s\".\n"),
8534 arm_force_mode_string
);
8537 /* If the user changes the register disassembly style used for info
8538 register and other commands, we have to also switch the style used
8539 in opcodes for disassembly output. This function is run in the "set
8540 arm disassembly" command, and does that. */
8543 set_disassembly_style_sfunc (char *args
, int from_tty
,
8544 struct cmd_list_element
*c
)
8546 /* Convert the short style name into the long style name (eg, reg-names-*)
8547 before calling the generic set_disassembler_options() function. */
8548 std::string long_name
= std::string ("reg-names-") + disassembly_style
;
8549 set_disassembler_options (&long_name
[0]);
8553 show_disassembly_style_sfunc (struct ui_file
*file
, int from_tty
,
8554 struct cmd_list_element
*c
, const char *value
)
8556 struct gdbarch
*gdbarch
= get_current_arch ();
8557 char *options
= get_disassembler_options (gdbarch
);
8558 const char *style
= "";
8562 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
8563 if (CONST_STRNEQ (opt
, "reg-names-"))
8565 style
= &opt
[strlen ("reg-names-")];
8566 len
= strcspn (style
, ",");
8569 fprintf_unfiltered (file
, "The disassembly style is \"%.*s\".\n", len
, style
);
8572 /* Return the ARM register name corresponding to register I. */
8574 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8576 const int num_regs
= gdbarch_num_regs (gdbarch
);
8578 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8579 && i
>= num_regs
&& i
< num_regs
+ 32)
8581 static const char *const vfp_pseudo_names
[] = {
8582 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8583 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8584 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8585 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8588 return vfp_pseudo_names
[i
- num_regs
];
8591 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8592 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8594 static const char *const neon_pseudo_names
[] = {
8595 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8596 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8599 return neon_pseudo_names
[i
- num_regs
- 32];
8602 if (i
>= ARRAY_SIZE (arm_register_names
))
8603 /* These registers are only supported on targets which supply
8604 an XML description. */
8607 return arm_register_names
[i
];
8610 /* Test whether the coff symbol specific value corresponds to a Thumb
8614 coff_sym_is_thumb (int val
)
8616 return (val
== C_THUMBEXT
8617 || val
== C_THUMBSTAT
8618 || val
== C_THUMBEXTFUNC
8619 || val
== C_THUMBSTATFUNC
8620 || val
== C_THUMBLABEL
);
8623 /* arm_coff_make_msymbol_special()
8624 arm_elf_make_msymbol_special()
8626 These functions test whether the COFF or ELF symbol corresponds to
8627 an address in thumb code, and set a "special" bit in a minimal
8628 symbol to indicate that it does. */
8631 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8633 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8635 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8636 == ST_BRANCH_TO_THUMB
)
8637 MSYMBOL_SET_SPECIAL (msym
);
8641 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8643 if (coff_sym_is_thumb (val
))
8644 MSYMBOL_SET_SPECIAL (msym
);
8648 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8650 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8653 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8654 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8658 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8661 const char *name
= bfd_asymbol_name (sym
);
8662 struct arm_per_objfile
*data
;
8663 VEC(arm_mapping_symbol_s
) **map_p
;
8664 struct arm_mapping_symbol new_map_sym
;
8666 gdb_assert (name
[0] == '$');
8667 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8670 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8671 arm_objfile_data_key
);
8674 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8675 struct arm_per_objfile
);
8676 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8677 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8678 objfile
->obfd
->section_count
,
8679 VEC(arm_mapping_symbol_s
) *);
8681 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8683 new_map_sym
.value
= sym
->value
;
8684 new_map_sym
.type
= name
[1];
8686 /* Assume that most mapping symbols appear in order of increasing
8687 value. If they were randomly distributed, it would be faster to
8688 always push here and then sort at first use. */
8689 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8691 struct arm_mapping_symbol
*prev_map_sym
;
8693 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8694 if (prev_map_sym
->value
>= sym
->value
)
8697 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8698 arm_compare_mapping_symbols
);
8699 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8704 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8708 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8710 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8711 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8713 /* If necessary, set the T bit. */
8716 ULONGEST val
, t_bit
;
8717 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8718 t_bit
= arm_psr_thumb_bit (gdbarch
);
8719 if (arm_pc_is_thumb (gdbarch
, pc
))
8720 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8723 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8728 /* Read the contents of a NEON quad register, by reading from two
8729 double registers. This is used to implement the quad pseudo
8730 registers, and for argument passing in case the quad registers are
8731 missing; vectors are passed in quad registers when using the VFP
8732 ABI, even if a NEON unit is not present. REGNUM is the index of
8733 the quad register, in [0, 15]. */
8735 static enum register_status
8736 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8737 int regnum
, gdb_byte
*buf
)
8740 gdb_byte reg_buf
[8];
8741 int offset
, double_regnum
;
8742 enum register_status status
;
8744 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8745 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8748 /* d0 is always the least significant half of q0. */
8749 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8754 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8755 if (status
!= REG_VALID
)
8757 memcpy (buf
+ offset
, reg_buf
, 8);
8759 offset
= 8 - offset
;
8760 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8761 if (status
!= REG_VALID
)
8763 memcpy (buf
+ offset
, reg_buf
, 8);
8768 static enum register_status
8769 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8770 int regnum
, gdb_byte
*buf
)
8772 const int num_regs
= gdbarch_num_regs (gdbarch
);
8774 gdb_byte reg_buf
[8];
8775 int offset
, double_regnum
;
8777 gdb_assert (regnum
>= num_regs
);
8780 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8781 /* Quad-precision register. */
8782 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8785 enum register_status status
;
8787 /* Single-precision register. */
8788 gdb_assert (regnum
< 32);
8790 /* s0 is always the least significant half of d0. */
8791 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8792 offset
= (regnum
& 1) ? 0 : 4;
8794 offset
= (regnum
& 1) ? 4 : 0;
8796 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8797 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8800 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8801 if (status
== REG_VALID
)
8802 memcpy (buf
, reg_buf
+ offset
, 4);
8807 /* Store the contents of BUF to a NEON quad register, by writing to
8808 two double registers. This is used to implement the quad pseudo
8809 registers, and for argument passing in case the quad registers are
8810 missing; vectors are passed in quad registers when using the VFP
8811 ABI, even if a NEON unit is not present. REGNUM is the index
8812 of the quad register, in [0, 15]. */
8815 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8816 int regnum
, const gdb_byte
*buf
)
8819 int offset
, double_regnum
;
8821 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8822 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8825 /* d0 is always the least significant half of q0. */
8826 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8831 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8832 offset
= 8 - offset
;
8833 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8837 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8838 int regnum
, const gdb_byte
*buf
)
8840 const int num_regs
= gdbarch_num_regs (gdbarch
);
8842 gdb_byte reg_buf
[8];
8843 int offset
, double_regnum
;
8845 gdb_assert (regnum
>= num_regs
);
8848 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8849 /* Quad-precision register. */
8850 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8853 /* Single-precision register. */
8854 gdb_assert (regnum
< 32);
8856 /* s0 is always the least significant half of d0. */
8857 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8858 offset
= (regnum
& 1) ? 0 : 4;
8860 offset
= (regnum
& 1) ? 4 : 0;
8862 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8863 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8866 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8867 memcpy (reg_buf
+ offset
, buf
, 4);
8868 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8872 static struct value
*
8873 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8875 const int *reg_p
= (const int *) baton
;
8876 return value_of_register (*reg_p
, frame
);
8879 static enum gdb_osabi
8880 arm_elf_osabi_sniffer (bfd
*abfd
)
8882 unsigned int elfosabi
;
8883 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8885 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8887 if (elfosabi
== ELFOSABI_ARM
)
8888 /* GNU tools use this value. Check note sections in this case,
8890 bfd_map_over_sections (abfd
,
8891 generic_elf_osabi_sniff_abi_tag_sections
,
8894 /* Anything else will be handled by the generic ELF sniffer. */
8899 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8900 struct reggroup
*group
)
8902 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8903 this, FPS register belongs to save_regroup, restore_reggroup, and
8904 all_reggroup, of course. */
8905 if (regnum
== ARM_FPS_REGNUM
)
8906 return (group
== float_reggroup
8907 || group
== save_reggroup
8908 || group
== restore_reggroup
8909 || group
== all_reggroup
);
8911 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8915 /* For backward-compatibility we allow two 'g' packet lengths with
8916 the remote protocol depending on whether FPA registers are
8917 supplied. M-profile targets do not have FPA registers, but some
8918 stubs already exist in the wild which use a 'g' packet which
8919 supplies them albeit with dummy values. The packet format which
8920 includes FPA registers should be considered deprecated for
8921 M-profile targets. */
8924 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8926 if (gdbarch_tdep (gdbarch
)->is_m
)
8928 /* If we know from the executable this is an M-profile target,
8929 cater for remote targets whose register set layout is the
8930 same as the FPA layout. */
8931 register_remote_g_packet_guess (gdbarch
,
8932 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8933 (16 * INT_REGISTER_SIZE
)
8934 + (8 * FP_REGISTER_SIZE
)
8935 + (2 * INT_REGISTER_SIZE
),
8936 tdesc_arm_with_m_fpa_layout
);
8938 /* The regular M-profile layout. */
8939 register_remote_g_packet_guess (gdbarch
,
8940 /* r0-r12,sp,lr,pc; xpsr */
8941 (16 * INT_REGISTER_SIZE
)
8942 + INT_REGISTER_SIZE
,
8945 /* M-profile plus M4F VFP. */
8946 register_remote_g_packet_guess (gdbarch
,
8947 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8948 (16 * INT_REGISTER_SIZE
)
8949 + (16 * VFP_REGISTER_SIZE
)
8950 + (2 * INT_REGISTER_SIZE
),
8951 tdesc_arm_with_m_vfp_d16
);
8954 /* Otherwise we don't have a useful guess. */
8957 /* Implement the code_of_frame_writable gdbarch method. */
8960 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8962 if (gdbarch_tdep (gdbarch
)->is_m
8963 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8965 /* M-profile exception frames return to some magic PCs, where
8966 isn't writable at all. */
8974 /* Initialize the current architecture based on INFO. If possible,
8975 re-use an architecture from ARCHES, which is a list of
8976 architectures already created during this debugging session.
8978 Called e.g. at program startup, when reading a core file, and when
8979 reading a binary file. */
8981 static struct gdbarch
*
8982 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8984 struct gdbarch_tdep
*tdep
;
8985 struct gdbarch
*gdbarch
;
8986 struct gdbarch_list
*best_arch
;
8987 enum arm_abi_kind arm_abi
= arm_abi_global
;
8988 enum arm_float_model fp_model
= arm_fp_model
;
8989 struct tdesc_arch_data
*tdesc_data
= NULL
;
8991 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8992 int have_wmmx_registers
= 0;
8994 int have_fpa_registers
= 1;
8995 const struct target_desc
*tdesc
= info
.target_desc
;
8997 /* If we have an object to base this architecture on, try to determine
9000 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9002 int ei_osabi
, e_flags
;
9004 switch (bfd_get_flavour (info
.abfd
))
9006 case bfd_target_coff_flavour
:
9007 /* Assume it's an old APCS-style ABI. */
9009 arm_abi
= ARM_ABI_APCS
;
9012 case bfd_target_elf_flavour
:
9013 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9014 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9016 if (ei_osabi
== ELFOSABI_ARM
)
9018 /* GNU tools used to use this value, but do not for EABI
9019 objects. There's nowhere to tag an EABI version
9020 anyway, so assume APCS. */
9021 arm_abi
= ARM_ABI_APCS
;
9023 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9025 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9026 int attr_arch
, attr_profile
;
9030 case EF_ARM_EABI_UNKNOWN
:
9031 /* Assume GNU tools. */
9032 arm_abi
= ARM_ABI_APCS
;
9035 case EF_ARM_EABI_VER4
:
9036 case EF_ARM_EABI_VER5
:
9037 arm_abi
= ARM_ABI_AAPCS
;
9038 /* EABI binaries default to VFP float ordering.
9039 They may also contain build attributes that can
9040 be used to identify if the VFP argument-passing
9042 if (fp_model
== ARM_FLOAT_AUTO
)
9045 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9049 case AEABI_VFP_args_base
:
9050 /* "The user intended FP parameter/result
9051 passing to conform to AAPCS, base
9053 fp_model
= ARM_FLOAT_SOFT_VFP
;
9055 case AEABI_VFP_args_vfp
:
9056 /* "The user intended FP parameter/result
9057 passing to conform to AAPCS, VFP
9059 fp_model
= ARM_FLOAT_VFP
;
9061 case AEABI_VFP_args_toolchain
:
9062 /* "The user intended FP parameter/result
9063 passing to conform to tool chain-specific
9064 conventions" - we don't know any such
9065 conventions, so leave it as "auto". */
9067 case AEABI_VFP_args_compatible
:
9068 /* "Code is compatible with both the base
9069 and VFP variants; the user did not permit
9070 non-variadic functions to pass FP
9071 parameters/results" - leave it as
9075 /* Attribute value not mentioned in the
9076 November 2012 ABI, so leave it as
9081 fp_model
= ARM_FLOAT_SOFT_VFP
;
9087 /* Leave it as "auto". */
9088 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9093 /* Detect M-profile programs. This only works if the
9094 executable file includes build attributes; GCC does
9095 copy them to the executable, but e.g. RealView does
9097 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9099 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9101 Tag_CPU_arch_profile
);
9102 /* GCC specifies the profile for v6-M; RealView only
9103 specifies the profile for architectures starting with
9104 V7 (as opposed to architectures with a tag
9105 numerically greater than TAG_CPU_ARCH_V7). */
9106 if (!tdesc_has_registers (tdesc
)
9107 && (attr_arch
== TAG_CPU_ARCH_V6_M
9108 || attr_arch
== TAG_CPU_ARCH_V6S_M
9109 || attr_profile
== 'M'))
9114 if (fp_model
== ARM_FLOAT_AUTO
)
9116 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9118 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9121 /* Leave it as "auto". Strictly speaking this case
9122 means FPA, but almost nobody uses that now, and
9123 many toolchains fail to set the appropriate bits
9124 for the floating-point model they use. */
9126 case EF_ARM_SOFT_FLOAT
:
9127 fp_model
= ARM_FLOAT_SOFT_FPA
;
9129 case EF_ARM_VFP_FLOAT
:
9130 fp_model
= ARM_FLOAT_VFP
;
9132 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9133 fp_model
= ARM_FLOAT_SOFT_VFP
;
9138 if (e_flags
& EF_ARM_BE8
)
9139 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9144 /* Leave it as "auto". */
9149 /* Check any target description for validity. */
9150 if (tdesc_has_registers (tdesc
))
9152 /* For most registers we require GDB's default names; but also allow
9153 the numeric names for sp / lr / pc, as a convenience. */
9154 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9155 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9156 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9158 const struct tdesc_feature
*feature
;
9161 feature
= tdesc_find_feature (tdesc
,
9162 "org.gnu.gdb.arm.core");
9163 if (feature
== NULL
)
9165 feature
= tdesc_find_feature (tdesc
,
9166 "org.gnu.gdb.arm.m-profile");
9167 if (feature
== NULL
)
9173 tdesc_data
= tdesc_data_alloc ();
9176 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9177 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9178 arm_register_names
[i
]);
9179 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9182 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9185 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9189 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9190 ARM_PS_REGNUM
, "xpsr");
9192 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9193 ARM_PS_REGNUM
, "cpsr");
9197 tdesc_data_cleanup (tdesc_data
);
9201 feature
= tdesc_find_feature (tdesc
,
9202 "org.gnu.gdb.arm.fpa");
9203 if (feature
!= NULL
)
9206 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9207 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9208 arm_register_names
[i
]);
9211 tdesc_data_cleanup (tdesc_data
);
9216 have_fpa_registers
= 0;
9218 feature
= tdesc_find_feature (tdesc
,
9219 "org.gnu.gdb.xscale.iwmmxt");
9220 if (feature
!= NULL
)
9222 static const char *const iwmmxt_names
[] = {
9223 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9224 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9225 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9226 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9230 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9232 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9233 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9235 /* Check for the control registers, but do not fail if they
9237 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9238 tdesc_numbered_register (feature
, tdesc_data
, i
,
9239 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9241 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9243 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9244 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9248 tdesc_data_cleanup (tdesc_data
);
9252 have_wmmx_registers
= 1;
9255 /* If we have a VFP unit, check whether the single precision registers
9256 are present. If not, then we will synthesize them as pseudo
9258 feature
= tdesc_find_feature (tdesc
,
9259 "org.gnu.gdb.arm.vfp");
9260 if (feature
!= NULL
)
9262 static const char *const vfp_double_names
[] = {
9263 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9264 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9265 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9266 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9269 /* Require the double precision registers. There must be either
9272 for (i
= 0; i
< 32; i
++)
9274 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9276 vfp_double_names
[i
]);
9280 if (!valid_p
&& i
== 16)
9283 /* Also require FPSCR. */
9284 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9285 ARM_FPSCR_REGNUM
, "fpscr");
9288 tdesc_data_cleanup (tdesc_data
);
9292 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9293 have_vfp_pseudos
= 1;
9295 vfp_register_count
= i
;
9297 /* If we have VFP, also check for NEON. The architecture allows
9298 NEON without VFP (integer vector operations only), but GDB
9299 does not support that. */
9300 feature
= tdesc_find_feature (tdesc
,
9301 "org.gnu.gdb.arm.neon");
9302 if (feature
!= NULL
)
9304 /* NEON requires 32 double-precision registers. */
9307 tdesc_data_cleanup (tdesc_data
);
9311 /* If there are quad registers defined by the stub, use
9312 their type; otherwise (normally) provide them with
9313 the default type. */
9314 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9315 have_neon_pseudos
= 1;
9322 /* If there is already a candidate, use it. */
9323 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9325 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9327 if (arm_abi
!= ARM_ABI_AUTO
9328 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9331 if (fp_model
!= ARM_FLOAT_AUTO
9332 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9335 /* There are various other properties in tdep that we do not
9336 need to check here: those derived from a target description,
9337 since gdbarches with a different target description are
9338 automatically disqualified. */
9340 /* Do check is_m, though, since it might come from the binary. */
9341 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9344 /* Found a match. */
9348 if (best_arch
!= NULL
)
9350 if (tdesc_data
!= NULL
)
9351 tdesc_data_cleanup (tdesc_data
);
9352 return best_arch
->gdbarch
;
9355 tdep
= XCNEW (struct gdbarch_tdep
);
9356 gdbarch
= gdbarch_alloc (&info
, tdep
);
9358 /* Record additional information about the architecture we are defining.
9359 These are gdbarch discriminators, like the OSABI. */
9360 tdep
->arm_abi
= arm_abi
;
9361 tdep
->fp_model
= fp_model
;
9363 tdep
->have_fpa_registers
= have_fpa_registers
;
9364 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9365 gdb_assert (vfp_register_count
== 0
9366 || vfp_register_count
== 16
9367 || vfp_register_count
== 32);
9368 tdep
->vfp_register_count
= vfp_register_count
;
9369 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9370 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9371 tdep
->have_neon
= have_neon
;
9373 arm_register_g_packet_guesses (gdbarch
);
9376 switch (info
.byte_order_for_code
)
9378 case BFD_ENDIAN_BIG
:
9379 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9380 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9381 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9382 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9386 case BFD_ENDIAN_LITTLE
:
9387 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9388 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9389 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9390 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9395 internal_error (__FILE__
, __LINE__
,
9396 _("arm_gdbarch_init: bad byte order for float format"));
9399 /* On ARM targets char defaults to unsigned. */
9400 set_gdbarch_char_signed (gdbarch
, 0);
9402 /* Note: for displaced stepping, this includes the breakpoint, and one word
9403 of additional scratch space. This setting isn't used for anything beside
9404 displaced stepping at present. */
9405 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9407 /* This should be low enough for everything. */
9408 tdep
->lowest_pc
= 0x20;
9409 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9411 /* The default, for both APCS and AAPCS, is to return small
9412 structures in registers. */
9413 tdep
->struct_return
= reg_struct_return
;
9415 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9416 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9419 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9421 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9423 /* Frame handling. */
9424 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9425 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9426 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9428 frame_base_set_default (gdbarch
, &arm_normal_base
);
9430 /* Address manipulation. */
9431 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9433 /* Advance PC across function entry code. */
9434 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9436 /* Detect whether PC is at a point where the stack has been destroyed. */
9437 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9439 /* Skip trampolines. */
9440 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9442 /* The stack grows downward. */
9443 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9445 /* Breakpoint manipulation. */
9446 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
9447 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
9448 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9449 arm_breakpoint_kind_from_current_state
);
9451 /* Information about registers, etc. */
9452 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9453 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9454 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9455 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9456 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9458 /* This "info float" is FPA-specific. Use the generic version if we
9460 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9461 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9463 /* Internal <-> external register number maps. */
9464 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9465 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9467 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9469 /* Returning results. */
9470 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9473 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9475 /* Minsymbol frobbing. */
9476 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9477 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9478 arm_coff_make_msymbol_special
);
9479 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9481 /* Thumb-2 IT block support. */
9482 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9483 arm_adjust_breakpoint_address
);
9485 /* Virtual tables. */
9486 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9488 /* Hook in the ABI-specific overrides, if they have been registered. */
9489 gdbarch_init_osabi (info
, gdbarch
);
9491 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9493 /* Add some default predicates. */
9495 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9496 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9497 dwarf2_append_unwinders (gdbarch
);
9498 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9499 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9500 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9502 /* Now we have tuned the configuration, set a few final things,
9503 based on what the OS ABI has told us. */
9505 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9506 binaries are always marked. */
9507 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9508 tdep
->arm_abi
= ARM_ABI_APCS
;
9510 /* Watchpoints are not steppable. */
9511 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9513 /* We used to default to FPA for generic ARM, but almost nobody
9514 uses that now, and we now provide a way for the user to force
9515 the model. So default to the most useful variant. */
9516 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9517 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9519 if (tdep
->jb_pc
>= 0)
9520 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9522 /* Floating point sizes and format. */
9523 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9524 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9526 set_gdbarch_double_format
9527 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9528 set_gdbarch_long_double_format
9529 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9533 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9534 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9537 if (have_vfp_pseudos
)
9539 /* NOTE: These are the only pseudo registers used by
9540 the ARM target at the moment. If more are added, a
9541 little more care in numbering will be needed. */
9543 int num_pseudos
= 32;
9544 if (have_neon_pseudos
)
9546 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9547 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9548 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9553 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9555 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9557 /* Override tdesc_register_type to adjust the types of VFP
9558 registers for NEON. */
9559 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9562 /* Add standard register aliases. We add aliases even for those
9563 nanes which are used by the current architecture - it's simpler,
9564 and does no harm, since nothing ever lists user registers. */
9565 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9566 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9567 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9569 set_gdbarch_disassembler_options (gdbarch
, &arm_disassembler_options
);
9570 set_gdbarch_valid_disassembler_options (gdbarch
, disassembler_options_arm ());
9576 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9578 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9583 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9584 (unsigned long) tdep
->lowest_pc
);
9587 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9590 _initialize_arm_tdep (void)
9593 const char *setname
;
9594 const char *setdesc
;
9596 char regdesc
[1024], *rdptr
= regdesc
;
9597 size_t rest
= sizeof (regdesc
);
9599 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9601 arm_objfile_data_key
9602 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9604 /* Add ourselves to objfile event chain. */
9605 observer_attach_new_objfile (arm_exidx_new_objfile
);
9607 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9609 /* Register an ELF OS ABI sniffer for ARM binaries. */
9610 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9611 bfd_target_elf_flavour
,
9612 arm_elf_osabi_sniffer
);
9614 /* Initialize the standard target descriptions. */
9615 initialize_tdesc_arm_with_m ();
9616 initialize_tdesc_arm_with_m_fpa_layout ();
9617 initialize_tdesc_arm_with_m_vfp_d16 ();
9618 initialize_tdesc_arm_with_iwmmxt ();
9619 initialize_tdesc_arm_with_vfpv2 ();
9620 initialize_tdesc_arm_with_vfpv3 ();
9621 initialize_tdesc_arm_with_neon ();
9623 /* Add root prefix command for all "set arm"/"show arm" commands. */
9624 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9625 _("Various ARM-specific commands."),
9626 &setarmcmdlist
, "set arm ", 0, &setlist
);
9628 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9629 _("Various ARM-specific commands."),
9630 &showarmcmdlist
, "show arm ", 0, &showlist
);
9633 arm_disassembler_options
= xstrdup ("reg-names-std");
9634 const disasm_options_t
*disasm_options
= disassembler_options_arm ();
9635 int num_disassembly_styles
= 0;
9636 for (i
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9637 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9638 num_disassembly_styles
++;
9640 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
9641 valid_disassembly_styles
= XNEWVEC (const char *,
9642 num_disassembly_styles
+ 1);
9643 for (i
= j
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9644 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9646 size_t offset
= strlen ("reg-names-");
9647 const char *style
= disasm_options
->name
[i
];
9648 valid_disassembly_styles
[j
++] = &style
[offset
];
9649 length
= snprintf (rdptr
, rest
, "%s - %s\n", &style
[offset
],
9650 disasm_options
->description
[i
]);
9654 /* Mark the end of valid options. */
9655 valid_disassembly_styles
[num_disassembly_styles
] = NULL
;
9657 /* Create the help text. */
9658 std::string helptext
= string_printf ("%s%s%s",
9659 _("The valid values are:\n"),
9661 _("The default is \"std\"."));
9663 add_setshow_enum_cmd("disassembler", no_class
,
9664 valid_disassembly_styles
, &disassembly_style
,
9665 _("Set the disassembly style."),
9666 _("Show the disassembly style."),
9668 set_disassembly_style_sfunc
,
9669 show_disassembly_style_sfunc
,
9670 &setarmcmdlist
, &showarmcmdlist
);
9672 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9673 _("Set usage of ARM 32-bit mode."),
9674 _("Show usage of ARM 32-bit mode."),
9675 _("When off, a 26-bit PC will be used."),
9677 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9679 &setarmcmdlist
, &showarmcmdlist
);
9681 /* Add a command to allow the user to force the FPU model. */
9682 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9683 _("Set the floating point type."),
9684 _("Show the floating point type."),
9685 _("auto - Determine the FP typefrom the OS-ABI.\n\
9686 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9687 fpa - FPA co-processor (GCC compiled).\n\
9688 softvfp - Software FP with pure-endian doubles.\n\
9689 vfp - VFP co-processor."),
9690 set_fp_model_sfunc
, show_fp_model
,
9691 &setarmcmdlist
, &showarmcmdlist
);
9693 /* Add a command to allow the user to force the ABI. */
9694 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9697 NULL
, arm_set_abi
, arm_show_abi
,
9698 &setarmcmdlist
, &showarmcmdlist
);
9700 /* Add two commands to allow the user to force the assumed
9702 add_setshow_enum_cmd ("fallback-mode", class_support
,
9703 arm_mode_strings
, &arm_fallback_mode_string
,
9704 _("Set the mode assumed when symbols are unavailable."),
9705 _("Show the mode assumed when symbols are unavailable."),
9706 NULL
, NULL
, arm_show_fallback_mode
,
9707 &setarmcmdlist
, &showarmcmdlist
);
9708 add_setshow_enum_cmd ("force-mode", class_support
,
9709 arm_mode_strings
, &arm_force_mode_string
,
9710 _("Set the mode assumed even when symbols are available."),
9711 _("Show the mode assumed even when symbols are available."),
9712 NULL
, NULL
, arm_show_force_mode
,
9713 &setarmcmdlist
, &showarmcmdlist
);
9715 /* Debugging flag. */
9716 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9717 _("Set ARM debugging."),
9718 _("Show ARM debugging."),
9719 _("When on, arm-specific debugging is enabled."),
9721 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9722 &setdebuglist
, &showdebuglist
);
9725 /* ARM-reversible process record data structures. */
9727 #define ARM_INSN_SIZE_BYTES 4
9728 #define THUMB_INSN_SIZE_BYTES 2
9729 #define THUMB2_INSN_SIZE_BYTES 4
9732 /* Position of the bit within a 32-bit ARM instruction
9733 that defines whether the instruction is a load or store. */
9734 #define INSN_S_L_BIT_NUM 20
9736 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9739 unsigned int reg_len = LENGTH; \
9742 REGS = XNEWVEC (uint32_t, reg_len); \
9743 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9748 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9751 unsigned int mem_len = LENGTH; \
9754 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9755 memcpy(&MEMS->len, &RECORD_BUF[0], \
9756 sizeof(struct arm_mem_r) * LENGTH); \
9761 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9762 #define INSN_RECORDED(ARM_RECORD) \
9763 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9765 /* ARM memory record structure. */
9768 uint32_t len
; /* Record length. */
9769 uint32_t addr
; /* Memory address. */
9772 /* ARM instruction record contains opcode of current insn
9773 and execution state (before entry to decode_insn()),
9774 contains list of to-be-modified registers and
9775 memory blocks (on return from decode_insn()). */
9777 typedef struct insn_decode_record_t
9779 struct gdbarch
*gdbarch
;
9780 struct regcache
*regcache
;
9781 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9782 uint32_t arm_insn
; /* Should accommodate thumb. */
9783 uint32_t cond
; /* Condition code. */
9784 uint32_t opcode
; /* Insn opcode. */
9785 uint32_t decode
; /* Insn decode bits. */
9786 uint32_t mem_rec_count
; /* No of mem records. */
9787 uint32_t reg_rec_count
; /* No of reg records. */
9788 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9789 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9790 } insn_decode_record
;
9793 /* Checks ARM SBZ and SBO mandatory fields. */
9796 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9798 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9817 enum arm_record_result
9819 ARM_RECORD_SUCCESS
= 0,
9820 ARM_RECORD_FAILURE
= 1
9827 } arm_record_strx_t
;
9838 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9839 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9842 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9843 ULONGEST u_regval
[2]= {0};
9845 uint32_t reg_src1
= 0, reg_src2
= 0;
9846 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9848 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9849 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9851 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9853 /* 1) Handle misc store, immediate offset. */
9854 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9855 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9856 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9857 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9859 if (ARM_PC_REGNUM
== reg_src1
)
9861 /* If R15 was used as Rn, hence current PC+8. */
9862 u_regval
[0] = u_regval
[0] + 8;
9864 offset_8
= (immed_high
<< 4) | immed_low
;
9865 /* Calculate target store address. */
9866 if (14 == arm_insn_r
->opcode
)
9868 tgt_mem_addr
= u_regval
[0] + offset_8
;
9872 tgt_mem_addr
= u_regval
[0] - offset_8
;
9874 if (ARM_RECORD_STRH
== str_type
)
9876 record_buf_mem
[0] = 2;
9877 record_buf_mem
[1] = tgt_mem_addr
;
9878 arm_insn_r
->mem_rec_count
= 1;
9880 else if (ARM_RECORD_STRD
== str_type
)
9882 record_buf_mem
[0] = 4;
9883 record_buf_mem
[1] = tgt_mem_addr
;
9884 record_buf_mem
[2] = 4;
9885 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9886 arm_insn_r
->mem_rec_count
= 2;
9889 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9891 /* 2) Store, register offset. */
9893 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9895 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9896 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9897 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9900 /* If R15 was used as Rn, hence current PC+8. */
9901 u_regval
[0] = u_regval
[0] + 8;
9903 /* Calculate target store address, Rn +/- Rm, register offset. */
9904 if (12 == arm_insn_r
->opcode
)
9906 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9910 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9912 if (ARM_RECORD_STRH
== str_type
)
9914 record_buf_mem
[0] = 2;
9915 record_buf_mem
[1] = tgt_mem_addr
;
9916 arm_insn_r
->mem_rec_count
= 1;
9918 else if (ARM_RECORD_STRD
== str_type
)
9920 record_buf_mem
[0] = 4;
9921 record_buf_mem
[1] = tgt_mem_addr
;
9922 record_buf_mem
[2] = 4;
9923 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9924 arm_insn_r
->mem_rec_count
= 2;
9927 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9928 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9930 /* 3) Store, immediate pre-indexed. */
9931 /* 5) Store, immediate post-indexed. */
9932 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9933 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9934 offset_8
= (immed_high
<< 4) | immed_low
;
9935 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9936 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9937 /* Calculate target store address, Rn +/- Rm, register offset. */
9938 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9940 tgt_mem_addr
= u_regval
[0] + offset_8
;
9944 tgt_mem_addr
= u_regval
[0] - offset_8
;
9946 if (ARM_RECORD_STRH
== str_type
)
9948 record_buf_mem
[0] = 2;
9949 record_buf_mem
[1] = tgt_mem_addr
;
9950 arm_insn_r
->mem_rec_count
= 1;
9952 else if (ARM_RECORD_STRD
== str_type
)
9954 record_buf_mem
[0] = 4;
9955 record_buf_mem
[1] = tgt_mem_addr
;
9956 record_buf_mem
[2] = 4;
9957 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9958 arm_insn_r
->mem_rec_count
= 2;
9960 /* Record Rn also as it changes. */
9961 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9962 arm_insn_r
->reg_rec_count
= 1;
9964 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9965 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9967 /* 4) Store, register pre-indexed. */
9968 /* 6) Store, register post -indexed. */
9969 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9970 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9971 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9972 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9973 /* Calculate target store address, Rn +/- Rm, register offset. */
9974 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9976 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9980 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9982 if (ARM_RECORD_STRH
== str_type
)
9984 record_buf_mem
[0] = 2;
9985 record_buf_mem
[1] = tgt_mem_addr
;
9986 arm_insn_r
->mem_rec_count
= 1;
9988 else if (ARM_RECORD_STRD
== str_type
)
9990 record_buf_mem
[0] = 4;
9991 record_buf_mem
[1] = tgt_mem_addr
;
9992 record_buf_mem
[2] = 4;
9993 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9994 arm_insn_r
->mem_rec_count
= 2;
9996 /* Record Rn also as it changes. */
9997 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9998 arm_insn_r
->reg_rec_count
= 1;
10003 /* Handling ARM extension space insns. */
10006 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10008 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10009 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10010 uint32_t record_buf
[8], record_buf_mem
[8];
10011 uint32_t reg_src1
= 0;
10012 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10013 ULONGEST u_regval
= 0;
10015 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10016 /* Handle unconditional insn extension space. */
10018 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10019 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10020 if (arm_insn_r
->cond
)
10022 /* PLD has no affect on architectural state, it just affects
10024 if (5 == ((opcode1
& 0xE0) >> 5))
10027 record_buf
[0] = ARM_PS_REGNUM
;
10028 record_buf
[1] = ARM_LR_REGNUM
;
10029 arm_insn_r
->reg_rec_count
= 2;
10031 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10035 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10036 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10039 /* Undefined instruction on ARM V5; need to handle if later
10040 versions define it. */
10043 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10044 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10045 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10047 /* Handle arithmetic insn extension space. */
10048 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10049 && !INSN_RECORDED(arm_insn_r
))
10051 /* Handle MLA(S) and MUL(S). */
10052 if (0 <= insn_op1
&& 3 >= insn_op1
)
10054 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10055 record_buf
[1] = ARM_PS_REGNUM
;
10056 arm_insn_r
->reg_rec_count
= 2;
10058 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10060 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10061 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10062 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10063 record_buf
[2] = ARM_PS_REGNUM
;
10064 arm_insn_r
->reg_rec_count
= 3;
10068 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10069 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10070 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10072 /* Handle control insn extension space. */
10074 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10075 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10077 if (!bit (arm_insn_r
->arm_insn
,25))
10079 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10081 if ((0 == insn_op1
) || (2 == insn_op1
))
10084 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10085 arm_insn_r
->reg_rec_count
= 1;
10087 else if (1 == insn_op1
)
10089 /* CSPR is going to be changed. */
10090 record_buf
[0] = ARM_PS_REGNUM
;
10091 arm_insn_r
->reg_rec_count
= 1;
10093 else if (3 == insn_op1
)
10095 /* SPSR is going to be changed. */
10096 /* We need to get SPSR value, which is yet to be done. */
10100 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10105 record_buf
[0] = ARM_PS_REGNUM
;
10106 arm_insn_r
->reg_rec_count
= 1;
10108 else if (3 == insn_op1
)
10111 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10112 arm_insn_r
->reg_rec_count
= 1;
10115 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10118 record_buf
[0] = ARM_PS_REGNUM
;
10119 record_buf
[1] = ARM_LR_REGNUM
;
10120 arm_insn_r
->reg_rec_count
= 2;
10122 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10124 /* QADD, QSUB, QDADD, QDSUB */
10125 record_buf
[0] = ARM_PS_REGNUM
;
10126 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10127 arm_insn_r
->reg_rec_count
= 2;
10129 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10132 record_buf
[0] = ARM_PS_REGNUM
;
10133 record_buf
[1] = ARM_LR_REGNUM
;
10134 arm_insn_r
->reg_rec_count
= 2;
10136 /* Save SPSR also;how? */
10139 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10140 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10141 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10142 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10145 if (0 == insn_op1
|| 1 == insn_op1
)
10147 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10148 /* We dont do optimization for SMULW<y> where we
10150 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10151 record_buf
[1] = ARM_PS_REGNUM
;
10152 arm_insn_r
->reg_rec_count
= 2;
10154 else if (2 == insn_op1
)
10157 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10158 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10159 arm_insn_r
->reg_rec_count
= 2;
10161 else if (3 == insn_op1
)
10164 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10165 arm_insn_r
->reg_rec_count
= 1;
10171 /* MSR : immediate form. */
10174 /* CSPR is going to be changed. */
10175 record_buf
[0] = ARM_PS_REGNUM
;
10176 arm_insn_r
->reg_rec_count
= 1;
10178 else if (3 == insn_op1
)
10180 /* SPSR is going to be changed. */
10181 /* we need to get SPSR value, which is yet to be done */
10187 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10188 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10189 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10191 /* Handle load/store insn extension space. */
10193 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10194 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10195 && !INSN_RECORDED(arm_insn_r
))
10200 /* These insn, changes register and memory as well. */
10201 /* SWP or SWPB insn. */
10202 /* Get memory address given by Rn. */
10203 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10204 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10205 /* SWP insn ?, swaps word. */
10206 if (8 == arm_insn_r
->opcode
)
10208 record_buf_mem
[0] = 4;
10212 /* SWPB insn, swaps only byte. */
10213 record_buf_mem
[0] = 1;
10215 record_buf_mem
[1] = u_regval
;
10216 arm_insn_r
->mem_rec_count
= 1;
10217 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10218 arm_insn_r
->reg_rec_count
= 1;
10220 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10223 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10226 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10229 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10230 record_buf
[1] = record_buf
[0] + 1;
10231 arm_insn_r
->reg_rec_count
= 2;
10233 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10236 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10239 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10241 /* LDRH, LDRSB, LDRSH. */
10242 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10243 arm_insn_r
->reg_rec_count
= 1;
10248 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10249 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10250 && !INSN_RECORDED(arm_insn_r
))
10253 /* Handle coprocessor insn extension space. */
10256 /* To be done for ARMv5 and later; as of now we return -1. */
10260 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10261 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10266 /* Handling opcode 000 insns. */
10269 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10271 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10272 uint32_t record_buf
[8], record_buf_mem
[8];
10273 ULONGEST u_regval
[2] = {0};
10275 uint32_t reg_src1
= 0, reg_dest
= 0;
10276 uint32_t opcode1
= 0;
10278 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10279 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10280 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10282 /* Data processing insn /multiply insn. */
10283 if (9 == arm_insn_r
->decode
10284 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10285 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10287 /* Handle multiply instructions. */
10288 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10289 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10291 /* Handle MLA and MUL. */
10292 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10293 record_buf
[1] = ARM_PS_REGNUM
;
10294 arm_insn_r
->reg_rec_count
= 2;
10296 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10298 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10299 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10300 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10301 record_buf
[2] = ARM_PS_REGNUM
;
10302 arm_insn_r
->reg_rec_count
= 3;
10305 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10306 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10308 /* Handle misc load insns, as 20th bit (L = 1). */
10309 /* LDR insn has a capability to do branching, if
10310 MOV LR, PC is precceded by LDR insn having Rn as R15
10311 in that case, it emulates branch and link insn, and hence we
10312 need to save CSPR and PC as well. I am not sure this is right
10313 place; as opcode = 010 LDR insn make this happen, if R15 was
10315 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10316 if (15 != reg_dest
)
10318 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10319 arm_insn_r
->reg_rec_count
= 1;
10323 record_buf
[0] = reg_dest
;
10324 record_buf
[1] = ARM_PS_REGNUM
;
10325 arm_insn_r
->reg_rec_count
= 2;
10328 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10329 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10330 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10331 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10333 /* Handle MSR insn. */
10334 if (9 == arm_insn_r
->opcode
)
10336 /* CSPR is going to be changed. */
10337 record_buf
[0] = ARM_PS_REGNUM
;
10338 arm_insn_r
->reg_rec_count
= 1;
10342 /* SPSR is going to be changed. */
10343 /* How to read SPSR value? */
10347 else if (9 == arm_insn_r
->decode
10348 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10349 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10351 /* Handling SWP, SWPB. */
10352 /* These insn, changes register and memory as well. */
10353 /* SWP or SWPB insn. */
10355 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10356 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10357 /* SWP insn ?, swaps word. */
10358 if (8 == arm_insn_r
->opcode
)
10360 record_buf_mem
[0] = 4;
10364 /* SWPB insn, swaps only byte. */
10365 record_buf_mem
[0] = 1;
10367 record_buf_mem
[1] = u_regval
[0];
10368 arm_insn_r
->mem_rec_count
= 1;
10369 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10370 arm_insn_r
->reg_rec_count
= 1;
10372 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10373 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10375 /* Handle BLX, branch and link/exchange. */
10376 if (9 == arm_insn_r
->opcode
)
10378 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10379 and R14 stores the return address. */
10380 record_buf
[0] = ARM_PS_REGNUM
;
10381 record_buf
[1] = ARM_LR_REGNUM
;
10382 arm_insn_r
->reg_rec_count
= 2;
10385 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10387 /* Handle enhanced software breakpoint insn, BKPT. */
10388 /* CPSR is changed to be executed in ARM state, disabling normal
10389 interrupts, entering abort mode. */
10390 /* According to high vector configuration PC is set. */
10391 /* user hit breakpoint and type reverse, in
10392 that case, we need to go back with previous CPSR and
10393 Program Counter. */
10394 record_buf
[0] = ARM_PS_REGNUM
;
10395 record_buf
[1] = ARM_LR_REGNUM
;
10396 arm_insn_r
->reg_rec_count
= 2;
10398 /* Save SPSR also; how? */
10401 else if (11 == arm_insn_r
->decode
10402 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10404 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10406 /* Handle str(x) insn */
10407 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10410 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10411 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10413 /* Handle BX, branch and link/exchange. */
10414 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10415 record_buf
[0] = ARM_PS_REGNUM
;
10416 arm_insn_r
->reg_rec_count
= 1;
10418 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10419 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10420 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10422 /* Count leading zeros: CLZ. */
10423 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10424 arm_insn_r
->reg_rec_count
= 1;
10426 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10427 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10428 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10429 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10432 /* Handle MRS insn. */
10433 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10434 arm_insn_r
->reg_rec_count
= 1;
10436 else if (arm_insn_r
->opcode
<= 15)
10438 /* Normal data processing insns. */
10439 /* Out of 11 shifter operands mode, all the insn modifies destination
10440 register, which is specified by 13-16 decode. */
10441 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10442 record_buf
[1] = ARM_PS_REGNUM
;
10443 arm_insn_r
->reg_rec_count
= 2;
10450 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10451 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10455 /* Handling opcode 001 insns. */
10458 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10460 uint32_t record_buf
[8], record_buf_mem
[8];
10462 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10463 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10465 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10466 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10467 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10470 /* Handle MSR insn. */
10471 if (9 == arm_insn_r
->opcode
)
10473 /* CSPR is going to be changed. */
10474 record_buf
[0] = ARM_PS_REGNUM
;
10475 arm_insn_r
->reg_rec_count
= 1;
10479 /* SPSR is going to be changed. */
10482 else if (arm_insn_r
->opcode
<= 15)
10484 /* Normal data processing insns. */
10485 /* Out of 11 shifter operands mode, all the insn modifies destination
10486 register, which is specified by 13-16 decode. */
10487 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10488 record_buf
[1] = ARM_PS_REGNUM
;
10489 arm_insn_r
->reg_rec_count
= 2;
10496 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10497 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10502 arm_record_media (insn_decode_record
*arm_insn_r
)
10504 uint32_t record_buf
[8];
10506 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10509 /* Parallel addition and subtraction, signed */
10511 /* Parallel addition and subtraction, unsigned */
10514 /* Packing, unpacking, saturation and reversal */
10516 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10518 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10524 /* Signed multiplies */
10526 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10527 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10529 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10531 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10532 else if (op1
== 0x4)
10533 record_buf
[arm_insn_r
->reg_rec_count
++]
10534 = bits (arm_insn_r
->arm_insn
, 12, 15);
10540 if (bit (arm_insn_r
->arm_insn
, 21)
10541 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10544 record_buf
[arm_insn_r
->reg_rec_count
++]
10545 = bits (arm_insn_r
->arm_insn
, 12, 15);
10547 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10548 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10550 /* USAD8 and USADA8 */
10551 record_buf
[arm_insn_r
->reg_rec_count
++]
10552 = bits (arm_insn_r
->arm_insn
, 16, 19);
10559 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10560 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10562 /* Permanently UNDEFINED */
10567 /* BFC, BFI and UBFX */
10568 record_buf
[arm_insn_r
->reg_rec_count
++]
10569 = bits (arm_insn_r
->arm_insn
, 12, 15);
10578 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10583 /* Handle ARM mode instructions with opcode 010. */
10586 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10588 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10590 uint32_t reg_base
, reg_dest
;
10591 uint32_t offset_12
, tgt_mem_addr
;
10592 uint32_t record_buf
[8], record_buf_mem
[8];
10593 unsigned char wback
;
10596 /* Calculate wback. */
10597 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10598 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10600 arm_insn_r
->reg_rec_count
= 0;
10601 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10603 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10605 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10608 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10609 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10611 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10612 preceeds a LDR instruction having R15 as reg_base, it
10613 emulates a branch and link instruction, and hence we need to save
10614 CPSR and PC as well. */
10615 if (ARM_PC_REGNUM
== reg_dest
)
10616 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10618 /* If wback is true, also save the base register, which is going to be
10621 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10625 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10627 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10628 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10630 /* Handle bit U. */
10631 if (bit (arm_insn_r
->arm_insn
, 23))
10633 /* U == 1: Add the offset. */
10634 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10638 /* U == 0: subtract the offset. */
10639 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10642 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10644 if (bit (arm_insn_r
->arm_insn
, 22))
10646 /* STRB and STRBT: 1 byte. */
10647 record_buf_mem
[0] = 1;
10651 /* STR and STRT: 4 bytes. */
10652 record_buf_mem
[0] = 4;
10655 /* Handle bit P. */
10656 if (bit (arm_insn_r
->arm_insn
, 24))
10657 record_buf_mem
[1] = tgt_mem_addr
;
10659 record_buf_mem
[1] = (uint32_t) u_regval
;
10661 arm_insn_r
->mem_rec_count
= 1;
10663 /* If wback is true, also save the base register, which is going to be
10666 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10669 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10670 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10674 /* Handling opcode 011 insns. */
10677 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10679 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10681 uint32_t shift_imm
= 0;
10682 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10683 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10684 uint32_t record_buf
[8], record_buf_mem
[8];
10687 ULONGEST u_regval
[2];
10689 if (bit (arm_insn_r
->arm_insn
, 4))
10690 return arm_record_media (arm_insn_r
);
10692 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10693 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10695 /* Handle enhanced store insns and LDRD DSP insn,
10696 order begins according to addressing modes for store insns
10700 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10702 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10703 /* LDR insn has a capability to do branching, if
10704 MOV LR, PC is precedded by LDR insn having Rn as R15
10705 in that case, it emulates branch and link insn, and hence we
10706 need to save CSPR and PC as well. */
10707 if (15 != reg_dest
)
10709 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10710 arm_insn_r
->reg_rec_count
= 1;
10714 record_buf
[0] = reg_dest
;
10715 record_buf
[1] = ARM_PS_REGNUM
;
10716 arm_insn_r
->reg_rec_count
= 2;
10721 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10723 /* Store insn, register offset and register pre-indexed,
10724 register post-indexed. */
10726 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10728 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10729 regcache_raw_read_unsigned (reg_cache
, reg_src1
10731 regcache_raw_read_unsigned (reg_cache
, reg_src2
10733 if (15 == reg_src2
)
10735 /* If R15 was used as Rn, hence current PC+8. */
10736 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10737 u_regval
[0] = u_regval
[0] + 8;
10739 /* Calculate target store address, Rn +/- Rm, register offset. */
10741 if (bit (arm_insn_r
->arm_insn
, 23))
10743 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10747 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10750 switch (arm_insn_r
->opcode
)
10764 record_buf_mem
[0] = 4;
10779 record_buf_mem
[0] = 1;
10783 gdb_assert_not_reached ("no decoding pattern found");
10786 record_buf_mem
[1] = tgt_mem_addr
;
10787 arm_insn_r
->mem_rec_count
= 1;
10789 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10790 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10791 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10792 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10793 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10794 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10797 /* Rn is going to be changed in pre-indexed mode and
10798 post-indexed mode as well. */
10799 record_buf
[0] = reg_src2
;
10800 arm_insn_r
->reg_rec_count
= 1;
10805 /* Store insn, scaled register offset; scaled pre-indexed. */
10806 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10808 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10810 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10811 /* Get shift_imm. */
10812 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10813 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10814 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10815 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10816 /* Offset_12 used as shift. */
10820 /* Offset_12 used as index. */
10821 offset_12
= u_regval
[0] << shift_imm
;
10825 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10831 if (bit (u_regval
[0], 31))
10833 offset_12
= 0xFFFFFFFF;
10842 /* This is arithmetic shift. */
10843 offset_12
= s_word
>> shift_imm
;
10850 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10852 /* Get C flag value and shift it by 31. */
10853 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10854 | (u_regval
[0]) >> 1);
10858 offset_12
= (u_regval
[0] >> shift_imm
) \
10860 (sizeof(uint32_t) - shift_imm
));
10865 gdb_assert_not_reached ("no decoding pattern found");
10869 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10871 if (bit (arm_insn_r
->arm_insn
, 23))
10873 tgt_mem_addr
= u_regval
[1] + offset_12
;
10877 tgt_mem_addr
= u_regval
[1] - offset_12
;
10880 switch (arm_insn_r
->opcode
)
10894 record_buf_mem
[0] = 4;
10909 record_buf_mem
[0] = 1;
10913 gdb_assert_not_reached ("no decoding pattern found");
10916 record_buf_mem
[1] = tgt_mem_addr
;
10917 arm_insn_r
->mem_rec_count
= 1;
10919 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10920 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10921 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10922 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10923 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10924 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10927 /* Rn is going to be changed in register scaled pre-indexed
10928 mode,and scaled post indexed mode. */
10929 record_buf
[0] = reg_src2
;
10930 arm_insn_r
->reg_rec_count
= 1;
10935 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10936 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10940 /* Handle ARM mode instructions with opcode 100. */
10943 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10945 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10946 uint32_t register_count
= 0, register_bits
;
10947 uint32_t reg_base
, addr_mode
;
10948 uint32_t record_buf
[24], record_buf_mem
[48];
10952 /* Fetch the list of registers. */
10953 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10954 arm_insn_r
->reg_rec_count
= 0;
10956 /* Fetch the base register that contains the address we are loading data
10958 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10960 /* Calculate wback. */
10961 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10963 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10965 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10967 /* Find out which registers are going to be loaded from memory. */
10968 while (register_bits
)
10970 if (register_bits
& 0x00000001)
10971 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10972 register_bits
= register_bits
>> 1;
10977 /* If wback is true, also save the base register, which is going to be
10980 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10982 /* Save the CPSR register. */
10983 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10987 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10989 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10991 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10993 /* Find out how many registers are going to be stored to memory. */
10994 while (register_bits
)
10996 if (register_bits
& 0x00000001)
10998 register_bits
= register_bits
>> 1;
11003 /* STMDA (STMED): Decrement after. */
11005 record_buf_mem
[1] = (uint32_t) u_regval
11006 - register_count
* INT_REGISTER_SIZE
+ 4;
11008 /* STM (STMIA, STMEA): Increment after. */
11010 record_buf_mem
[1] = (uint32_t) u_regval
;
11012 /* STMDB (STMFD): Decrement before. */
11014 record_buf_mem
[1] = (uint32_t) u_regval
11015 - register_count
* INT_REGISTER_SIZE
;
11017 /* STMIB (STMFA): Increment before. */
11019 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11022 gdb_assert_not_reached ("no decoding pattern found");
11026 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11027 arm_insn_r
->mem_rec_count
= 1;
11029 /* If wback is true, also save the base register, which is going to be
11032 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11035 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11036 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11040 /* Handling opcode 101 insns. */
11043 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11045 uint32_t record_buf
[8];
11047 /* Handle B, BL, BLX(1) insns. */
11048 /* B simply branches so we do nothing here. */
11049 /* Note: BLX(1) doesnt fall here but instead it falls into
11050 extension space. */
11051 if (bit (arm_insn_r
->arm_insn
, 24))
11053 record_buf
[0] = ARM_LR_REGNUM
;
11054 arm_insn_r
->reg_rec_count
= 1;
11057 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11063 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11065 printf_unfiltered (_("Process record does not support instruction "
11066 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11067 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11072 /* Record handler for vector data transfer instructions. */
11075 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11077 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11078 uint32_t record_buf
[4];
11080 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11081 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11082 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11083 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11084 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11086 /* Handle VMOV instruction. */
11087 if (bit_l
&& bit_c
)
11089 record_buf
[0] = reg_t
;
11090 arm_insn_r
->reg_rec_count
= 1;
11092 else if (bit_l
&& !bit_c
)
11094 /* Handle VMOV instruction. */
11095 if (bits_a
== 0x00)
11097 record_buf
[0] = reg_t
;
11098 arm_insn_r
->reg_rec_count
= 1;
11100 /* Handle VMRS instruction. */
11101 else if (bits_a
== 0x07)
11104 reg_t
= ARM_PS_REGNUM
;
11106 record_buf
[0] = reg_t
;
11107 arm_insn_r
->reg_rec_count
= 1;
11110 else if (!bit_l
&& !bit_c
)
11112 /* Handle VMOV instruction. */
11113 if (bits_a
== 0x00)
11115 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11117 arm_insn_r
->reg_rec_count
= 1;
11119 /* Handle VMSR instruction. */
11120 else if (bits_a
== 0x07)
11122 record_buf
[0] = ARM_FPSCR_REGNUM
;
11123 arm_insn_r
->reg_rec_count
= 1;
11126 else if (!bit_l
&& bit_c
)
11128 /* Handle VMOV instruction. */
11129 if (!(bits_a
& 0x04))
11131 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11133 arm_insn_r
->reg_rec_count
= 1;
11135 /* Handle VDUP instruction. */
11138 if (bit (arm_insn_r
->arm_insn
, 21))
11140 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11141 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11142 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11143 arm_insn_r
->reg_rec_count
= 2;
11147 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11148 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11149 arm_insn_r
->reg_rec_count
= 1;
11154 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11158 /* Record handler for extension register load/store instructions. */
11161 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11163 uint32_t opcode
, single_reg
;
11164 uint8_t op_vldm_vstm
;
11165 uint32_t record_buf
[8], record_buf_mem
[128];
11166 ULONGEST u_regval
= 0;
11168 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11170 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11171 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11172 op_vldm_vstm
= opcode
& 0x1b;
11174 /* Handle VMOV instructions. */
11175 if ((opcode
& 0x1e) == 0x04)
11177 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11179 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11180 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11181 arm_insn_r
->reg_rec_count
= 2;
11185 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11186 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11190 /* The first S register number m is REG_M:M (M is bit 5),
11191 the corresponding D register number is REG_M:M / 2, which
11193 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11194 /* The second S register number is REG_M:M + 1, the
11195 corresponding D register number is (REG_M:M + 1) / 2.
11196 IOW, if bit M is 1, the first and second S registers
11197 are mapped to different D registers, otherwise, they are
11198 in the same D register. */
11201 record_buf
[arm_insn_r
->reg_rec_count
++]
11202 = ARM_D0_REGNUM
+ reg_m
+ 1;
11207 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11208 arm_insn_r
->reg_rec_count
= 1;
11212 /* Handle VSTM and VPUSH instructions. */
11213 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11214 || op_vldm_vstm
== 0x12)
11216 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11217 uint32_t memory_index
= 0;
11219 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11220 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11221 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11222 imm_off32
= imm_off8
<< 2;
11223 memory_count
= imm_off8
;
11225 if (bit (arm_insn_r
->arm_insn
, 23))
11226 start_address
= u_regval
;
11228 start_address
= u_regval
- imm_off32
;
11230 if (bit (arm_insn_r
->arm_insn
, 21))
11232 record_buf
[0] = reg_rn
;
11233 arm_insn_r
->reg_rec_count
= 1;
11236 while (memory_count
> 0)
11240 record_buf_mem
[memory_index
] = 4;
11241 record_buf_mem
[memory_index
+ 1] = start_address
;
11242 start_address
= start_address
+ 4;
11243 memory_index
= memory_index
+ 2;
11247 record_buf_mem
[memory_index
] = 4;
11248 record_buf_mem
[memory_index
+ 1] = start_address
;
11249 record_buf_mem
[memory_index
+ 2] = 4;
11250 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11251 start_address
= start_address
+ 8;
11252 memory_index
= memory_index
+ 4;
11256 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11258 /* Handle VLDM instructions. */
11259 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11260 || op_vldm_vstm
== 0x13)
11262 uint32_t reg_count
, reg_vd
;
11263 uint32_t reg_index
= 0;
11264 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11266 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11267 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11269 /* REG_VD is the first D register number. If the instruction
11270 loads memory to S registers (SINGLE_REG is TRUE), the register
11271 number is (REG_VD << 1 | bit D), so the corresponding D
11272 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11274 reg_vd
= reg_vd
| (bit_d
<< 4);
11276 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11277 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11279 /* If the instruction loads memory to D register, REG_COUNT should
11280 be divided by 2, according to the ARM Architecture Reference
11281 Manual. If the instruction loads memory to S register, divide by
11282 2 as well because two S registers are mapped to D register. */
11283 reg_count
= reg_count
/ 2;
11284 if (single_reg
&& bit_d
)
11286 /* Increase the register count if S register list starts from
11287 an odd number (bit d is one). */
11291 while (reg_count
> 0)
11293 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11296 arm_insn_r
->reg_rec_count
= reg_index
;
11298 /* VSTR Vector store register. */
11299 else if ((opcode
& 0x13) == 0x10)
11301 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11302 uint32_t memory_index
= 0;
11304 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11305 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11306 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11307 imm_off32
= imm_off8
<< 2;
11309 if (bit (arm_insn_r
->arm_insn
, 23))
11310 start_address
= u_regval
+ imm_off32
;
11312 start_address
= u_regval
- imm_off32
;
11316 record_buf_mem
[memory_index
] = 4;
11317 record_buf_mem
[memory_index
+ 1] = start_address
;
11318 arm_insn_r
->mem_rec_count
= 1;
11322 record_buf_mem
[memory_index
] = 4;
11323 record_buf_mem
[memory_index
+ 1] = start_address
;
11324 record_buf_mem
[memory_index
+ 2] = 4;
11325 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11326 arm_insn_r
->mem_rec_count
= 2;
11329 /* VLDR Vector load register. */
11330 else if ((opcode
& 0x13) == 0x11)
11332 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11336 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11337 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11341 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11342 /* Record register D rather than pseudo register S. */
11343 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11345 arm_insn_r
->reg_rec_count
= 1;
11348 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11349 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11353 /* Record handler for arm/thumb mode VFP data processing instructions. */
11356 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11358 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11359 uint32_t record_buf
[4];
11360 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11361 enum insn_types curr_insn_type
= INSN_INV
;
11363 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11364 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11365 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11366 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11367 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11368 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11369 opc1
= opc1
& 0x04;
11371 /* Handle VMLA, VMLS. */
11374 if (bit (arm_insn_r
->arm_insn
, 10))
11376 if (bit (arm_insn_r
->arm_insn
, 6))
11377 curr_insn_type
= INSN_T0
;
11379 curr_insn_type
= INSN_T1
;
11384 curr_insn_type
= INSN_T1
;
11386 curr_insn_type
= INSN_T2
;
11389 /* Handle VNMLA, VNMLS, VNMUL. */
11390 else if (opc1
== 0x01)
11393 curr_insn_type
= INSN_T1
;
11395 curr_insn_type
= INSN_T2
;
11398 else if (opc1
== 0x02 && !(opc3
& 0x01))
11400 if (bit (arm_insn_r
->arm_insn
, 10))
11402 if (bit (arm_insn_r
->arm_insn
, 6))
11403 curr_insn_type
= INSN_T0
;
11405 curr_insn_type
= INSN_T1
;
11410 curr_insn_type
= INSN_T1
;
11412 curr_insn_type
= INSN_T2
;
11415 /* Handle VADD, VSUB. */
11416 else if (opc1
== 0x03)
11418 if (!bit (arm_insn_r
->arm_insn
, 9))
11420 if (bit (arm_insn_r
->arm_insn
, 6))
11421 curr_insn_type
= INSN_T0
;
11423 curr_insn_type
= INSN_T1
;
11428 curr_insn_type
= INSN_T1
;
11430 curr_insn_type
= INSN_T2
;
11434 else if (opc1
== 0x0b)
11437 curr_insn_type
= INSN_T1
;
11439 curr_insn_type
= INSN_T2
;
11441 /* Handle all other vfp data processing instructions. */
11442 else if (opc1
== 0x0b)
11445 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11447 if (bit (arm_insn_r
->arm_insn
, 4))
11449 if (bit (arm_insn_r
->arm_insn
, 6))
11450 curr_insn_type
= INSN_T0
;
11452 curr_insn_type
= INSN_T1
;
11457 curr_insn_type
= INSN_T1
;
11459 curr_insn_type
= INSN_T2
;
11462 /* Handle VNEG and VABS. */
11463 else if ((opc2
== 0x01 && opc3
== 0x01)
11464 || (opc2
== 0x00 && opc3
== 0x03))
11466 if (!bit (arm_insn_r
->arm_insn
, 11))
11468 if (bit (arm_insn_r
->arm_insn
, 6))
11469 curr_insn_type
= INSN_T0
;
11471 curr_insn_type
= INSN_T1
;
11476 curr_insn_type
= INSN_T1
;
11478 curr_insn_type
= INSN_T2
;
11481 /* Handle VSQRT. */
11482 else if (opc2
== 0x01 && opc3
== 0x03)
11485 curr_insn_type
= INSN_T1
;
11487 curr_insn_type
= INSN_T2
;
11490 else if (opc2
== 0x07 && opc3
== 0x03)
11493 curr_insn_type
= INSN_T1
;
11495 curr_insn_type
= INSN_T2
;
11497 else if (opc3
& 0x01)
11500 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11502 if (!bit (arm_insn_r
->arm_insn
, 18))
11503 curr_insn_type
= INSN_T2
;
11507 curr_insn_type
= INSN_T1
;
11509 curr_insn_type
= INSN_T2
;
11513 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11516 curr_insn_type
= INSN_T1
;
11518 curr_insn_type
= INSN_T2
;
11520 /* Handle VCVTB, VCVTT. */
11521 else if ((opc2
& 0x0e) == 0x02)
11522 curr_insn_type
= INSN_T2
;
11523 /* Handle VCMP, VCMPE. */
11524 else if ((opc2
& 0x0e) == 0x04)
11525 curr_insn_type
= INSN_T3
;
11529 switch (curr_insn_type
)
11532 reg_vd
= reg_vd
| (bit_d
<< 4);
11533 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11534 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11535 arm_insn_r
->reg_rec_count
= 2;
11539 reg_vd
= reg_vd
| (bit_d
<< 4);
11540 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11541 arm_insn_r
->reg_rec_count
= 1;
11545 reg_vd
= (reg_vd
<< 1) | bit_d
;
11546 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11547 arm_insn_r
->reg_rec_count
= 1;
11551 record_buf
[0] = ARM_FPSCR_REGNUM
;
11552 arm_insn_r
->reg_rec_count
= 1;
11556 gdb_assert_not_reached ("no decoding pattern found");
11560 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11564 /* Handling opcode 110 insns. */
11567 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11569 uint32_t op1
, op1_ebit
, coproc
;
11571 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11572 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11573 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11575 if ((coproc
& 0x0e) == 0x0a)
11577 /* Handle extension register ld/st instructions. */
11579 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11581 /* 64-bit transfers between arm core and extension registers. */
11582 if ((op1
& 0x3e) == 0x04)
11583 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11587 /* Handle coprocessor ld/st instructions. */
11592 return arm_record_unsupported_insn (arm_insn_r
);
11595 return arm_record_unsupported_insn (arm_insn_r
);
11598 /* Move to coprocessor from two arm core registers. */
11600 return arm_record_unsupported_insn (arm_insn_r
);
11602 /* Move to two arm core registers from coprocessor. */
11607 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11608 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11609 arm_insn_r
->reg_rec_count
= 2;
11611 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11615 return arm_record_unsupported_insn (arm_insn_r
);
11618 /* Handling opcode 111 insns. */
11621 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11623 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11624 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11625 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11627 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11628 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11629 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11630 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11631 op
= bit (arm_insn_r
->arm_insn
, 4);
11633 /* Handle arm SWI/SVC system call instructions. */
11636 if (tdep
->arm_syscall_record
!= NULL
)
11638 ULONGEST svc_operand
, svc_number
;
11640 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11642 if (svc_operand
) /* OABI. */
11643 svc_number
= svc_operand
- 0x900000;
11645 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11647 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11651 printf_unfiltered (_("no syscall record support\n"));
11656 if ((coproc
& 0x0e) == 0x0a)
11658 /* VFP data-processing instructions. */
11659 if (!op1_sbit
&& !op
)
11660 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11662 /* Advanced SIMD, VFP instructions. */
11663 if (!op1_sbit
&& op
)
11664 return arm_record_vdata_transfer_insn (arm_insn_r
);
11668 /* Coprocessor data operations. */
11669 if (!op1_sbit
&& !op
)
11670 return arm_record_unsupported_insn (arm_insn_r
);
11672 /* Move to Coprocessor from ARM core register. */
11673 if (!op1_sbit
&& !op1_ebit
&& op
)
11674 return arm_record_unsupported_insn (arm_insn_r
);
11676 /* Move to arm core register from coprocessor. */
11677 if (!op1_sbit
&& op1_ebit
&& op
)
11679 uint32_t record_buf
[1];
11681 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11682 if (record_buf
[0] == 15)
11683 record_buf
[0] = ARM_PS_REGNUM
;
11685 arm_insn_r
->reg_rec_count
= 1;
11686 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11692 return arm_record_unsupported_insn (arm_insn_r
);
11695 /* Handling opcode 000 insns. */
11698 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11700 uint32_t record_buf
[8];
11701 uint32_t reg_src1
= 0;
11703 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11705 record_buf
[0] = ARM_PS_REGNUM
;
11706 record_buf
[1] = reg_src1
;
11707 thumb_insn_r
->reg_rec_count
= 2;
11709 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11715 /* Handling opcode 001 insns. */
11718 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11720 uint32_t record_buf
[8];
11721 uint32_t reg_src1
= 0;
11723 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11725 record_buf
[0] = ARM_PS_REGNUM
;
11726 record_buf
[1] = reg_src1
;
11727 thumb_insn_r
->reg_rec_count
= 2;
11729 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11734 /* Handling opcode 010 insns. */
11737 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11739 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11740 uint32_t record_buf
[8], record_buf_mem
[8];
11742 uint32_t reg_src1
= 0, reg_src2
= 0;
11743 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11745 ULONGEST u_regval
[2] = {0};
11747 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11749 if (bit (thumb_insn_r
->arm_insn
, 12))
11751 /* Handle load/store register offset. */
11752 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11753 if (opcode2
>= 12 && opcode2
<= 15)
11755 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11756 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11757 record_buf
[0] = reg_src1
;
11758 thumb_insn_r
->reg_rec_count
= 1;
11760 else if (opcode2
>= 8 && opcode2
<= 10)
11762 /* STR(2), STRB(2), STRH(2) . */
11763 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11764 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11765 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11766 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11768 record_buf_mem
[0] = 4; /* STR (2). */
11769 else if (10 == opcode2
)
11770 record_buf_mem
[0] = 1; /* STRB (2). */
11771 else if (9 == opcode2
)
11772 record_buf_mem
[0] = 2; /* STRH (2). */
11773 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11774 thumb_insn_r
->mem_rec_count
= 1;
11777 else if (bit (thumb_insn_r
->arm_insn
, 11))
11779 /* Handle load from literal pool. */
11781 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11782 record_buf
[0] = reg_src1
;
11783 thumb_insn_r
->reg_rec_count
= 1;
11787 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11788 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11789 if ((3 == opcode2
) && (!opcode3
))
11791 /* Branch with exchange. */
11792 record_buf
[0] = ARM_PS_REGNUM
;
11793 thumb_insn_r
->reg_rec_count
= 1;
11797 /* Format 8; special data processing insns. */
11798 record_buf
[0] = ARM_PS_REGNUM
;
11799 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11800 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11801 thumb_insn_r
->reg_rec_count
= 2;
11806 /* Format 5; data processing insns. */
11807 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11808 if (bit (thumb_insn_r
->arm_insn
, 7))
11810 reg_src1
= reg_src1
+ 8;
11812 record_buf
[0] = ARM_PS_REGNUM
;
11813 record_buf
[1] = reg_src1
;
11814 thumb_insn_r
->reg_rec_count
= 2;
11817 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11818 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11824 /* Handling opcode 001 insns. */
11827 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11829 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11830 uint32_t record_buf
[8], record_buf_mem
[8];
11832 uint32_t reg_src1
= 0;
11833 uint32_t opcode
= 0, immed_5
= 0;
11835 ULONGEST u_regval
= 0;
11837 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11842 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11843 record_buf
[0] = reg_src1
;
11844 thumb_insn_r
->reg_rec_count
= 1;
11849 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11850 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11851 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11852 record_buf_mem
[0] = 4;
11853 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11854 thumb_insn_r
->mem_rec_count
= 1;
11857 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11858 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11864 /* Handling opcode 100 insns. */
11867 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11869 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11870 uint32_t record_buf
[8], record_buf_mem
[8];
11872 uint32_t reg_src1
= 0;
11873 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11875 ULONGEST u_regval
= 0;
11877 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11882 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11883 record_buf
[0] = reg_src1
;
11884 thumb_insn_r
->reg_rec_count
= 1;
11886 else if (1 == opcode
)
11889 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11890 record_buf
[0] = reg_src1
;
11891 thumb_insn_r
->reg_rec_count
= 1;
11893 else if (2 == opcode
)
11896 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11897 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11898 record_buf_mem
[0] = 4;
11899 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11900 thumb_insn_r
->mem_rec_count
= 1;
11902 else if (0 == opcode
)
11905 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11906 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11907 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11908 record_buf_mem
[0] = 2;
11909 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11910 thumb_insn_r
->mem_rec_count
= 1;
11913 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11914 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11920 /* Handling opcode 101 insns. */
11923 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11925 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11927 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11928 uint32_t register_bits
= 0, register_count
= 0;
11929 uint32_t index
= 0, start_address
= 0;
11930 uint32_t record_buf
[24], record_buf_mem
[48];
11933 ULONGEST u_regval
= 0;
11935 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11936 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11937 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11942 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11943 while (register_bits
)
11945 if (register_bits
& 0x00000001)
11946 record_buf
[index
++] = register_count
;
11947 register_bits
= register_bits
>> 1;
11950 record_buf
[index
++] = ARM_PS_REGNUM
;
11951 record_buf
[index
++] = ARM_SP_REGNUM
;
11952 thumb_insn_r
->reg_rec_count
= index
;
11954 else if (10 == opcode2
)
11957 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11958 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11959 while (register_bits
)
11961 if (register_bits
& 0x00000001)
11963 register_bits
= register_bits
>> 1;
11965 start_address
= u_regval
- \
11966 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11967 thumb_insn_r
->mem_rec_count
= register_count
;
11968 while (register_count
)
11970 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11971 record_buf_mem
[(register_count
* 2) - 2] = 4;
11972 start_address
= start_address
+ 4;
11975 record_buf
[0] = ARM_SP_REGNUM
;
11976 thumb_insn_r
->reg_rec_count
= 1;
11978 else if (0x1E == opcode1
)
11981 /* Handle enhanced software breakpoint insn, BKPT. */
11982 /* CPSR is changed to be executed in ARM state, disabling normal
11983 interrupts, entering abort mode. */
11984 /* According to high vector configuration PC is set. */
11985 /* User hits breakpoint and type reverse, in that case, we need to go back with
11986 previous CPSR and Program Counter. */
11987 record_buf
[0] = ARM_PS_REGNUM
;
11988 record_buf
[1] = ARM_LR_REGNUM
;
11989 thumb_insn_r
->reg_rec_count
= 2;
11990 /* We need to save SPSR value, which is not yet done. */
11991 printf_unfiltered (_("Process record does not support instruction "
11992 "0x%0x at address %s.\n"),
11993 thumb_insn_r
->arm_insn
,
11994 paddress (thumb_insn_r
->gdbarch
,
11995 thumb_insn_r
->this_addr
));
11998 else if ((0 == opcode
) || (1 == opcode
))
12000 /* ADD(5), ADD(6). */
12001 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12002 record_buf
[0] = reg_src1
;
12003 thumb_insn_r
->reg_rec_count
= 1;
12005 else if (2 == opcode
)
12007 /* ADD(7), SUB(4). */
12008 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12009 record_buf
[0] = ARM_SP_REGNUM
;
12010 thumb_insn_r
->reg_rec_count
= 1;
12013 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12014 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12020 /* Handling opcode 110 insns. */
12023 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12025 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12026 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12028 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12029 uint32_t reg_src1
= 0;
12030 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12031 uint32_t index
= 0, start_address
= 0;
12032 uint32_t record_buf
[24], record_buf_mem
[48];
12034 ULONGEST u_regval
= 0;
12036 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12037 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12043 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12045 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12046 while (register_bits
)
12048 if (register_bits
& 0x00000001)
12049 record_buf
[index
++] = register_count
;
12050 register_bits
= register_bits
>> 1;
12053 record_buf
[index
++] = reg_src1
;
12054 thumb_insn_r
->reg_rec_count
= index
;
12056 else if (0 == opcode2
)
12058 /* It handles both STMIA. */
12059 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12061 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12062 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12063 while (register_bits
)
12065 if (register_bits
& 0x00000001)
12067 register_bits
= register_bits
>> 1;
12069 start_address
= u_regval
;
12070 thumb_insn_r
->mem_rec_count
= register_count
;
12071 while (register_count
)
12073 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12074 record_buf_mem
[(register_count
* 2) - 2] = 4;
12075 start_address
= start_address
+ 4;
12079 else if (0x1F == opcode1
)
12081 /* Handle arm syscall insn. */
12082 if (tdep
->arm_syscall_record
!= NULL
)
12084 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12085 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12089 printf_unfiltered (_("no syscall record support\n"));
12094 /* B (1), conditional branch is automatically taken care in process_record,
12095 as PC is saved there. */
12097 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12098 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12104 /* Handling opcode 111 insns. */
12107 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12109 uint32_t record_buf
[8];
12110 uint32_t bits_h
= 0;
12112 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12114 if (2 == bits_h
|| 3 == bits_h
)
12117 record_buf
[0] = ARM_LR_REGNUM
;
12118 thumb_insn_r
->reg_rec_count
= 1;
12120 else if (1 == bits_h
)
12123 record_buf
[0] = ARM_PS_REGNUM
;
12124 record_buf
[1] = ARM_LR_REGNUM
;
12125 thumb_insn_r
->reg_rec_count
= 2;
12128 /* B(2) is automatically taken care in process_record, as PC is
12131 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12136 /* Handler for thumb2 load/store multiple instructions. */
12139 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12141 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12143 uint32_t reg_rn
, op
;
12144 uint32_t register_bits
= 0, register_count
= 0;
12145 uint32_t index
= 0, start_address
= 0;
12146 uint32_t record_buf
[24], record_buf_mem
[48];
12148 ULONGEST u_regval
= 0;
12150 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12151 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12153 if (0 == op
|| 3 == op
)
12155 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12157 /* Handle RFE instruction. */
12158 record_buf
[0] = ARM_PS_REGNUM
;
12159 thumb2_insn_r
->reg_rec_count
= 1;
12163 /* Handle SRS instruction after reading banked SP. */
12164 return arm_record_unsupported_insn (thumb2_insn_r
);
12167 else if (1 == op
|| 2 == op
)
12169 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12171 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12172 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12173 while (register_bits
)
12175 if (register_bits
& 0x00000001)
12176 record_buf
[index
++] = register_count
;
12179 register_bits
= register_bits
>> 1;
12181 record_buf
[index
++] = reg_rn
;
12182 record_buf
[index
++] = ARM_PS_REGNUM
;
12183 thumb2_insn_r
->reg_rec_count
= index
;
12187 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12188 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12189 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12190 while (register_bits
)
12192 if (register_bits
& 0x00000001)
12195 register_bits
= register_bits
>> 1;
12200 /* Start address calculation for LDMDB/LDMEA. */
12201 start_address
= u_regval
;
12205 /* Start address calculation for LDMDB/LDMEA. */
12206 start_address
= u_regval
- register_count
* 4;
12209 thumb2_insn_r
->mem_rec_count
= register_count
;
12210 while (register_count
)
12212 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12213 record_buf_mem
[register_count
* 2 - 2] = 4;
12214 start_address
= start_address
+ 4;
12217 record_buf
[0] = reg_rn
;
12218 record_buf
[1] = ARM_PS_REGNUM
;
12219 thumb2_insn_r
->reg_rec_count
= 2;
12223 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12225 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12227 return ARM_RECORD_SUCCESS
;
12230 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12234 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12236 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12238 uint32_t reg_rd
, reg_rn
, offset_imm
;
12239 uint32_t reg_dest1
, reg_dest2
;
12240 uint32_t address
, offset_addr
;
12241 uint32_t record_buf
[8], record_buf_mem
[8];
12242 uint32_t op1
, op2
, op3
;
12244 ULONGEST u_regval
[2];
12246 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12247 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12248 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12250 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12252 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12254 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12255 record_buf
[0] = reg_dest1
;
12256 record_buf
[1] = ARM_PS_REGNUM
;
12257 thumb2_insn_r
->reg_rec_count
= 2;
12260 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12262 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12263 record_buf
[2] = reg_dest2
;
12264 thumb2_insn_r
->reg_rec_count
= 3;
12269 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12270 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12272 if (0 == op1
&& 0 == op2
)
12274 /* Handle STREX. */
12275 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12276 address
= u_regval
[0] + (offset_imm
* 4);
12277 record_buf_mem
[0] = 4;
12278 record_buf_mem
[1] = address
;
12279 thumb2_insn_r
->mem_rec_count
= 1;
12280 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12281 record_buf
[0] = reg_rd
;
12282 thumb2_insn_r
->reg_rec_count
= 1;
12284 else if (1 == op1
&& 0 == op2
)
12286 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12287 record_buf
[0] = reg_rd
;
12288 thumb2_insn_r
->reg_rec_count
= 1;
12289 address
= u_regval
[0];
12290 record_buf_mem
[1] = address
;
12294 /* Handle STREXB. */
12295 record_buf_mem
[0] = 1;
12296 thumb2_insn_r
->mem_rec_count
= 1;
12300 /* Handle STREXH. */
12301 record_buf_mem
[0] = 2 ;
12302 thumb2_insn_r
->mem_rec_count
= 1;
12306 /* Handle STREXD. */
12307 address
= u_regval
[0];
12308 record_buf_mem
[0] = 4;
12309 record_buf_mem
[2] = 4;
12310 record_buf_mem
[3] = address
+ 4;
12311 thumb2_insn_r
->mem_rec_count
= 2;
12316 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12318 if (bit (thumb2_insn_r
->arm_insn
, 24))
12320 if (bit (thumb2_insn_r
->arm_insn
, 23))
12321 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12323 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12325 address
= offset_addr
;
12328 address
= u_regval
[0];
12330 record_buf_mem
[0] = 4;
12331 record_buf_mem
[1] = address
;
12332 record_buf_mem
[2] = 4;
12333 record_buf_mem
[3] = address
+ 4;
12334 thumb2_insn_r
->mem_rec_count
= 2;
12335 record_buf
[0] = reg_rn
;
12336 thumb2_insn_r
->reg_rec_count
= 1;
12340 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12342 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12344 return ARM_RECORD_SUCCESS
;
12347 /* Handler for thumb2 data processing (shift register and modified immediate)
12351 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12353 uint32_t reg_rd
, op
;
12354 uint32_t record_buf
[8];
12356 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12357 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12359 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12361 record_buf
[0] = ARM_PS_REGNUM
;
12362 thumb2_insn_r
->reg_rec_count
= 1;
12366 record_buf
[0] = reg_rd
;
12367 record_buf
[1] = ARM_PS_REGNUM
;
12368 thumb2_insn_r
->reg_rec_count
= 2;
12371 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12373 return ARM_RECORD_SUCCESS
;
12376 /* Generic handler for thumb2 instructions which effect destination and PS
12380 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12383 uint32_t record_buf
[8];
12385 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12387 record_buf
[0] = reg_rd
;
12388 record_buf
[1] = ARM_PS_REGNUM
;
12389 thumb2_insn_r
->reg_rec_count
= 2;
12391 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12393 return ARM_RECORD_SUCCESS
;
12396 /* Handler for thumb2 branch and miscellaneous control instructions. */
12399 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12401 uint32_t op
, op1
, op2
;
12402 uint32_t record_buf
[8];
12404 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12405 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12406 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12408 /* Handle MSR insn. */
12409 if (!(op1
& 0x2) && 0x38 == op
)
12413 /* CPSR is going to be changed. */
12414 record_buf
[0] = ARM_PS_REGNUM
;
12415 thumb2_insn_r
->reg_rec_count
= 1;
12419 arm_record_unsupported_insn(thumb2_insn_r
);
12423 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12426 record_buf
[0] = ARM_PS_REGNUM
;
12427 record_buf
[1] = ARM_LR_REGNUM
;
12428 thumb2_insn_r
->reg_rec_count
= 2;
12431 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12433 return ARM_RECORD_SUCCESS
;
12436 /* Handler for thumb2 store single data item instructions. */
12439 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12441 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12443 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12444 uint32_t address
, offset_addr
;
12445 uint32_t record_buf
[8], record_buf_mem
[8];
12448 ULONGEST u_regval
[2];
12450 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12451 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12452 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12453 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12455 if (bit (thumb2_insn_r
->arm_insn
, 23))
12458 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12459 offset_addr
= u_regval
[0] + offset_imm
;
12460 address
= offset_addr
;
12465 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12467 /* Handle STRB (register). */
12468 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12469 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12470 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12471 offset_addr
= u_regval
[1] << shift_imm
;
12472 address
= u_regval
[0] + offset_addr
;
12476 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12477 if (bit (thumb2_insn_r
->arm_insn
, 10))
12479 if (bit (thumb2_insn_r
->arm_insn
, 9))
12480 offset_addr
= u_regval
[0] + offset_imm
;
12482 offset_addr
= u_regval
[0] - offset_imm
;
12484 address
= offset_addr
;
12487 address
= u_regval
[0];
12493 /* Store byte instructions. */
12496 record_buf_mem
[0] = 1;
12498 /* Store half word instructions. */
12501 record_buf_mem
[0] = 2;
12503 /* Store word instructions. */
12506 record_buf_mem
[0] = 4;
12510 gdb_assert_not_reached ("no decoding pattern found");
12514 record_buf_mem
[1] = address
;
12515 thumb2_insn_r
->mem_rec_count
= 1;
12516 record_buf
[0] = reg_rn
;
12517 thumb2_insn_r
->reg_rec_count
= 1;
12519 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12521 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12523 return ARM_RECORD_SUCCESS
;
12526 /* Handler for thumb2 load memory hints instructions. */
12529 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12531 uint32_t record_buf
[8];
12532 uint32_t reg_rt
, reg_rn
;
12534 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12535 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12537 if (ARM_PC_REGNUM
!= reg_rt
)
12539 record_buf
[0] = reg_rt
;
12540 record_buf
[1] = reg_rn
;
12541 record_buf
[2] = ARM_PS_REGNUM
;
12542 thumb2_insn_r
->reg_rec_count
= 3;
12544 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12546 return ARM_RECORD_SUCCESS
;
12549 return ARM_RECORD_FAILURE
;
12552 /* Handler for thumb2 load word instructions. */
12555 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12557 uint32_t record_buf
[8];
12559 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12560 record_buf
[1] = ARM_PS_REGNUM
;
12561 thumb2_insn_r
->reg_rec_count
= 2;
12563 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12565 return ARM_RECORD_SUCCESS
;
12568 /* Handler for thumb2 long multiply, long multiply accumulate, and
12569 divide instructions. */
12572 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12574 uint32_t opcode1
= 0, opcode2
= 0;
12575 uint32_t record_buf
[8];
12577 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12578 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12580 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12582 /* Handle SMULL, UMULL, SMULAL. */
12583 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12584 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12585 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12586 record_buf
[2] = ARM_PS_REGNUM
;
12587 thumb2_insn_r
->reg_rec_count
= 3;
12589 else if (1 == opcode1
|| 3 == opcode2
)
12591 /* Handle SDIV and UDIV. */
12592 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12593 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12594 record_buf
[2] = ARM_PS_REGNUM
;
12595 thumb2_insn_r
->reg_rec_count
= 3;
12598 return ARM_RECORD_FAILURE
;
12600 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12602 return ARM_RECORD_SUCCESS
;
12605 /* Record handler for thumb32 coprocessor instructions. */
12608 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12610 if (bit (thumb2_insn_r
->arm_insn
, 25))
12611 return arm_record_coproc_data_proc (thumb2_insn_r
);
12613 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12616 /* Record handler for advance SIMD structure load/store instructions. */
12619 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12621 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12622 uint32_t l_bit
, a_bit
, b_bits
;
12623 uint32_t record_buf
[128], record_buf_mem
[128];
12624 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12625 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12628 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12629 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12630 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12631 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12632 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12633 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12634 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12635 f_elem
= 8 / f_ebytes
;
12639 ULONGEST u_regval
= 0;
12640 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12641 address
= u_regval
;
12646 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12648 if (b_bits
== 0x07)
12650 else if (b_bits
== 0x0a)
12652 else if (b_bits
== 0x06)
12654 else if (b_bits
== 0x02)
12659 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12661 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12663 record_buf_mem
[index_m
++] = f_ebytes
;
12664 record_buf_mem
[index_m
++] = address
;
12665 address
= address
+ f_ebytes
;
12666 thumb2_insn_r
->mem_rec_count
+= 1;
12671 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12673 if (b_bits
== 0x09 || b_bits
== 0x08)
12675 else if (b_bits
== 0x03)
12680 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12681 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12683 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12685 record_buf_mem
[index_m
++] = f_ebytes
;
12686 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12687 thumb2_insn_r
->mem_rec_count
+= 1;
12689 address
= address
+ (2 * f_ebytes
);
12693 else if ((b_bits
& 0x0e) == 0x04)
12695 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12697 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12699 record_buf_mem
[index_m
++] = f_ebytes
;
12700 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12701 thumb2_insn_r
->mem_rec_count
+= 1;
12703 address
= address
+ (3 * f_ebytes
);
12707 else if (!(b_bits
& 0x0e))
12709 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12711 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12713 record_buf_mem
[index_m
++] = f_ebytes
;
12714 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12715 thumb2_insn_r
->mem_rec_count
+= 1;
12717 address
= address
+ (4 * f_ebytes
);
12723 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12725 if (bft_size
== 0x00)
12727 else if (bft_size
== 0x01)
12729 else if (bft_size
== 0x02)
12735 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12736 thumb2_insn_r
->mem_rec_count
= 1;
12738 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12739 thumb2_insn_r
->mem_rec_count
= 2;
12741 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12742 thumb2_insn_r
->mem_rec_count
= 3;
12744 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12745 thumb2_insn_r
->mem_rec_count
= 4;
12747 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12749 record_buf_mem
[index_m
] = f_ebytes
;
12750 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12759 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12760 thumb2_insn_r
->reg_rec_count
= 1;
12762 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12763 thumb2_insn_r
->reg_rec_count
= 2;
12765 else if ((b_bits
& 0x0e) == 0x04)
12766 thumb2_insn_r
->reg_rec_count
= 3;
12768 else if (!(b_bits
& 0x0e))
12769 thumb2_insn_r
->reg_rec_count
= 4;
12774 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12775 thumb2_insn_r
->reg_rec_count
= 1;
12777 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12778 thumb2_insn_r
->reg_rec_count
= 2;
12780 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12781 thumb2_insn_r
->reg_rec_count
= 3;
12783 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12784 thumb2_insn_r
->reg_rec_count
= 4;
12786 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12787 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12791 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12793 record_buf
[index_r
] = reg_rn
;
12794 thumb2_insn_r
->reg_rec_count
+= 1;
12797 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12799 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12804 /* Decodes thumb2 instruction type and invokes its record handler. */
12806 static unsigned int
12807 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12809 uint32_t op
, op1
, op2
;
12811 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12812 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12813 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12817 if (!(op2
& 0x64 ))
12819 /* Load/store multiple instruction. */
12820 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12822 else if (!((op2
& 0x64) ^ 0x04))
12824 /* Load/store (dual/exclusive) and table branch instruction. */
12825 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12827 else if (!((op2
& 0x20) ^ 0x20))
12829 /* Data-processing (shifted register). */
12830 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12832 else if (op2
& 0x40)
12834 /* Co-processor instructions. */
12835 return thumb2_record_coproc_insn (thumb2_insn_r
);
12838 else if (op1
== 0x02)
12842 /* Branches and miscellaneous control instructions. */
12843 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12845 else if (op2
& 0x20)
12847 /* Data-processing (plain binary immediate) instruction. */
12848 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12852 /* Data-processing (modified immediate). */
12853 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12856 else if (op1
== 0x03)
12858 if (!(op2
& 0x71 ))
12860 /* Store single data item. */
12861 return thumb2_record_str_single_data (thumb2_insn_r
);
12863 else if (!((op2
& 0x71) ^ 0x10))
12865 /* Advanced SIMD or structure load/store instructions. */
12866 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12868 else if (!((op2
& 0x67) ^ 0x01))
12870 /* Load byte, memory hints instruction. */
12871 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12873 else if (!((op2
& 0x67) ^ 0x03))
12875 /* Load halfword, memory hints instruction. */
12876 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12878 else if (!((op2
& 0x67) ^ 0x05))
12880 /* Load word instruction. */
12881 return thumb2_record_ld_word (thumb2_insn_r
);
12883 else if (!((op2
& 0x70) ^ 0x20))
12885 /* Data-processing (register) instruction. */
12886 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12888 else if (!((op2
& 0x78) ^ 0x30))
12890 /* Multiply, multiply accumulate, abs diff instruction. */
12891 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12893 else if (!((op2
& 0x78) ^ 0x38))
12895 /* Long multiply, long multiply accumulate, and divide. */
12896 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12898 else if (op2
& 0x40)
12900 /* Co-processor instructions. */
12901 return thumb2_record_coproc_insn (thumb2_insn_r
);
12908 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12909 and positive val on fauilure. */
12912 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12914 gdb_byte buf
[insn_size
];
12916 memset (&buf
[0], 0, insn_size
);
12918 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12920 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12922 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12926 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12928 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12932 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12933 uint32_t insn_size
)
12936 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12938 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12940 arm_record_data_proc_misc_ld_str
, /* 000. */
12941 arm_record_data_proc_imm
, /* 001. */
12942 arm_record_ld_st_imm_offset
, /* 010. */
12943 arm_record_ld_st_reg_offset
, /* 011. */
12944 arm_record_ld_st_multiple
, /* 100. */
12945 arm_record_b_bl
, /* 101. */
12946 arm_record_asimd_vfp_coproc
, /* 110. */
12947 arm_record_coproc_data_proc
/* 111. */
12950 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12952 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12954 thumb_record_shift_add_sub
, /* 000. */
12955 thumb_record_add_sub_cmp_mov
, /* 001. */
12956 thumb_record_ld_st_reg_offset
, /* 010. */
12957 thumb_record_ld_st_imm_offset
, /* 011. */
12958 thumb_record_ld_st_stack
, /* 100. */
12959 thumb_record_misc
, /* 101. */
12960 thumb_record_ldm_stm_swi
, /* 110. */
12961 thumb_record_branch
/* 111. */
12964 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12965 uint32_t insn_id
= 0;
12967 if (extract_arm_insn (arm_record
, insn_size
))
12971 printf_unfiltered (_("Process record: error reading memory at "
12972 "addr %s len = %d.\n"),
12973 paddress (arm_record
->gdbarch
,
12974 arm_record
->this_addr
), insn_size
);
12978 else if (ARM_RECORD
== record_type
)
12980 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12981 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12983 if (arm_record
->cond
== 0xf)
12984 ret
= arm_record_extension_space (arm_record
);
12987 /* If this insn has fallen into extension space
12988 then we need not decode it anymore. */
12989 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12991 if (ret
!= ARM_RECORD_SUCCESS
)
12993 arm_record_unsupported_insn (arm_record
);
12997 else if (THUMB_RECORD
== record_type
)
12999 /* As thumb does not have condition codes, we set negative. */
13000 arm_record
->cond
= -1;
13001 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13002 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13003 if (ret
!= ARM_RECORD_SUCCESS
)
13005 arm_record_unsupported_insn (arm_record
);
13009 else if (THUMB2_RECORD
== record_type
)
13011 /* As thumb does not have condition codes, we set negative. */
13012 arm_record
->cond
= -1;
13014 /* Swap first half of 32bit thumb instruction with second half. */
13015 arm_record
->arm_insn
13016 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13018 ret
= thumb2_record_decode_insn_handler (arm_record
);
13020 if (ret
!= ARM_RECORD_SUCCESS
)
13022 arm_record_unsupported_insn (arm_record
);
13028 /* Throw assertion. */
13029 gdb_assert_not_reached ("not a valid instruction, could not decode");
13036 /* Cleans up local record registers and memory allocations. */
13039 deallocate_reg_mem (insn_decode_record
*record
)
13041 xfree (record
->arm_regs
);
13042 xfree (record
->arm_mems
);
13046 /* Parse the current instruction and record the values of the registers and
13047 memory that will be changed in current instruction to record_arch_list".
13048 Return -1 if something is wrong. */
13051 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13052 CORE_ADDR insn_addr
)
13055 uint32_t no_of_rec
= 0;
13056 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13057 ULONGEST t_bit
= 0, insn_id
= 0;
13059 ULONGEST u_regval
= 0;
13061 insn_decode_record arm_record
;
13063 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13064 arm_record
.regcache
= regcache
;
13065 arm_record
.this_addr
= insn_addr
;
13066 arm_record
.gdbarch
= gdbarch
;
13069 if (record_debug
> 1)
13071 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13073 paddress (gdbarch
, arm_record
.this_addr
));
13076 if (extract_arm_insn (&arm_record
, 2))
13080 printf_unfiltered (_("Process record: error reading memory at "
13081 "addr %s len = %d.\n"),
13082 paddress (arm_record
.gdbarch
,
13083 arm_record
.this_addr
), 2);
13088 /* Check the insn, whether it is thumb or arm one. */
13090 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13091 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13094 if (!(u_regval
& t_bit
))
13096 /* We are decoding arm insn. */
13097 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13101 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13102 /* is it thumb2 insn? */
13103 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13105 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13106 THUMB2_INSN_SIZE_BYTES
);
13110 /* We are decoding thumb insn. */
13111 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13117 /* Record registers. */
13118 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13119 if (arm_record
.arm_regs
)
13121 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13123 if (record_full_arch_list_add_reg
13124 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13128 /* Record memories. */
13129 if (arm_record
.arm_mems
)
13131 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13133 if (record_full_arch_list_add_mem
13134 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13135 arm_record
.arm_mems
[no_of_rec
].len
))
13140 if (record_full_arch_list_add_end ())
13145 deallocate_reg_mem (&arm_record
);