1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h" /* For struct link_map_offsets. */
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 SP_REGNUM Contains address of top of stack.
76 PC_REGNUM Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs
[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes.*/
149 static unsigned int usr_cmd_cris_version
;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid
= 0;
154 /* Whether to make use of Dwarf-2 CFI (default on). */
155 static int usr_cmd_cris_dwarf2_cfi
= 1;
157 /* CRIS architecture specific information. */
160 unsigned int cris_version
;
164 /* Functions for accessing target dependent data. */
169 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
172 /* Sigtramp identification code copied from i386-linux-tdep.c. */
174 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
175 #define SIGTRAMP_OFFSET0 0
176 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
177 #define SIGTRAMP_OFFSET1 4
179 static const unsigned short sigtramp_code
[] =
181 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
182 SIGTRAMP_INSN1
/* break 13 */
185 #define SIGTRAMP_LEN (sizeof sigtramp_code)
187 /* Note: same length as normal sigtramp code. */
189 static const unsigned short rt_sigtramp_code
[] =
191 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
192 SIGTRAMP_INSN1
/* break 13 */
195 /* If PC is in a sigtramp routine, return the address of the start of
196 the routine. Otherwise, return 0. */
199 cris_sigtramp_start (struct frame_info
*next_frame
)
201 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
202 unsigned short buf
[SIGTRAMP_LEN
];
204 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
207 if (buf
[0] != SIGTRAMP_INSN0
)
209 if (buf
[0] != SIGTRAMP_INSN1
)
212 pc
-= SIGTRAMP_OFFSET1
;
213 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
217 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
223 /* If PC is in a RT sigtramp routine, return the address of the start of
224 the routine. Otherwise, return 0. */
227 cris_rt_sigtramp_start (struct frame_info
*next_frame
)
229 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
230 unsigned short buf
[SIGTRAMP_LEN
];
232 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
235 if (buf
[0] != SIGTRAMP_INSN0
)
237 if (buf
[0] != SIGTRAMP_INSN1
)
240 pc
-= SIGTRAMP_OFFSET1
;
241 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
245 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
251 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
252 routine, return the address of the associated sigcontext structure. */
255 cris_sigcontext_addr (struct frame_info
*next_frame
)
261 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
262 sp
= extract_unsigned_integer (buf
, 4);
264 /* Look for normal sigtramp frame first. */
265 pc
= cris_sigtramp_start (next_frame
);
268 /* struct signal_frame (arch/cris/kernel/signal.c) contains
269 struct sigcontext as its first member, meaning the SP points to
274 pc
= cris_rt_sigtramp_start (next_frame
);
277 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
278 a struct ucontext, which in turn contains a struct sigcontext.
280 4 + 4 + 128 to struct ucontext, then
281 4 + 4 + 12 to struct sigcontext. */
285 error ("Couldn't recognize signal trampoline.");
289 struct cris_unwind_cache
291 /* The previous frame's inner most stack address. Used as this
292 frame ID's stack_addr. */
294 /* The frame's base, optionally used by the high-level debug info. */
297 /* How far the SP and r8 (FP) have been offset from the start of
298 the stack frame (as defined by the previous frame's stack
304 /* From old frame_extra_info struct. */
308 /* Table indicating the location of each and every register. */
309 struct trad_frame_saved_reg
*saved_regs
;
312 static struct cris_unwind_cache
*
313 cris_sigtramp_frame_unwind_cache (struct frame_info
*next_frame
,
316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
317 struct cris_unwind_cache
*info
;
325 return (*this_cache
);
327 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
328 (*this_cache
) = info
;
329 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
331 /* Zero all fields. */
337 info
->uses_frame
= 0;
339 info
->leaf_function
= 0;
341 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
342 info
->base
= extract_unsigned_integer (buf
, 4);
344 addr
= cris_sigcontext_addr (next_frame
);
346 /* Layout of the sigcontext struct:
349 unsigned long oldmask;
353 if (tdep
->cris_version
== 10)
355 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
357 for (i
= 0; i
<= 13; i
++)
358 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
360 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
361 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
362 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
363 /* Note: IRP is off by 2 at this point. There's no point in correcting
364 it though since that will mean that the backtrace will show a PC
365 different from what is shown when stopped. */
366 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
367 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[IRP_REGNUM
];
368 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (24 * 4);
373 /* R0 to R13 are stored in order at offset (1 * 4) in
375 for (i
= 0; i
<= 13; i
++)
376 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
378 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
379 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
380 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
381 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
382 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
383 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
384 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
385 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
386 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
388 /* FIXME: If ERP is in a delay slot at this point then the PC will
389 be wrong at this point. This problem manifests itself in the
390 sigaltstack.exp test case, which occasionally generates FAILs when
391 the signal is received while in a delay slot.
393 This could be solved by a couple of read_memory_unsigned_integer and a
394 trad_frame_set_value. */
395 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[ERP_REGNUM
];
397 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (25 * 4);
404 cris_sigtramp_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
405 struct frame_id
*this_id
)
407 struct cris_unwind_cache
*cache
=
408 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
409 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
412 /* Forward declaration. */
414 static void cris_frame_prev_register (struct frame_info
*next_frame
,
415 void **this_prologue_cache
,
416 int regnum
, int *optimizedp
,
417 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
418 int *realnump
, void *bufferp
);
420 cris_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
422 int regnum
, int *optimizedp
,
423 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
424 int *realnump
, void *valuep
)
426 /* Make sure we've initialized the cache. */
427 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
428 cris_frame_prev_register (next_frame
, this_cache
, regnum
,
429 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
432 static const struct frame_unwind cris_sigtramp_frame_unwind
=
435 cris_sigtramp_frame_this_id
,
436 cris_sigtramp_frame_prev_register
439 static const struct frame_unwind
*
440 cris_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
442 if (cris_sigtramp_start (next_frame
)
443 || cris_rt_sigtramp_start (next_frame
))
444 return &cris_sigtramp_frame_unwind
;
450 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
451 struct frame_info
*this_frame
)
453 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
458 frame_unwind_register (this_frame
, ERP_REGNUM
, buf
);
459 erp
= extract_unsigned_integer (buf
, 4);
463 /* In delay slot - check if there's a breakpoint at the preceding
465 if (breakpoint_here_p (erp
& ~0x1))
471 /* Hardware watchpoint support. */
473 /* We support 6 hardware data watchpoints, but cannot trigger on execute
474 (any combination of read/write is fine). */
477 cris_can_use_hardware_watchpoint (int type
, int count
, int other
)
479 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
481 /* No bookkeeping is done here; it is handled by the remote debug agent. */
483 if (tdep
->cris_version
!= 32)
486 /* CRISv32: Six data watchpoints, one for instructions. */
487 return (((type
== bp_read_watchpoint
|| type
== bp_access_watchpoint
488 || type
== bp_hardware_watchpoint
) && count
<= 6)
489 || (type
== bp_hardware_breakpoint
&& count
<= 1));
492 /* The CRISv32 hardware data watchpoints work by specifying ranges,
493 which have no alignment or length restrictions. */
496 cris_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
501 /* If the inferior has some watchpoint that triggered, return the
502 address associated with that watchpoint. Otherwise, return
506 cris_stopped_data_address (void)
509 eda
= read_register (EDA_REGNUM
);
513 /* The instruction environment needed to find single-step breakpoints. */
516 struct instruction_environment
518 unsigned long reg
[NUM_GENREGS
];
519 unsigned long preg
[NUM_SPECREGS
];
520 unsigned long branch_break_address
;
521 unsigned long delay_slot_pc
;
522 unsigned long prefix_value
;
527 int delay_slot_pc_active
;
529 int disable_interrupt
;
532 /* Save old breakpoints in order to restore the state before a single_step.
533 At most, two breakpoints will have to be remembered. */
535 char binsn_quantum
[BREAKPOINT_MAX
];
536 static binsn_quantum break_mem
[2];
537 static CORE_ADDR next_pc
= 0;
538 static CORE_ADDR branch_target_address
= 0;
539 static unsigned char branch_break_inserted
= 0;
541 /* Machine-dependencies in CRIS for opcodes. */
543 /* Instruction sizes. */
544 enum cris_instruction_sizes
551 /* Addressing modes. */
552 enum cris_addressing_modes
559 /* Prefix addressing modes. */
560 enum cris_prefix_addressing_modes
562 PREFIX_INDEX_MODE
= 2,
563 PREFIX_ASSIGN_MODE
= 3,
565 /* Handle immediate byte offset addressing mode prefix format. */
566 PREFIX_OFFSET_MODE
= 2
569 /* Masks for opcodes. */
570 enum cris_opcode_masks
572 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
573 SIGNED_EXTEND_BIT_MASK
= 0x2,
574 SIGNED_BYTE_MASK
= 0x80,
575 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
576 SIGNED_WORD_MASK
= 0x8000,
577 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
578 SIGNED_DWORD_MASK
= 0x80000000,
579 SIGNED_QUICK_VALUE_MASK
= 0x20,
580 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
583 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
591 cris_get_operand2 (unsigned short insn
)
593 return ((insn
& 0xF000) >> 12);
597 cris_get_mode (unsigned short insn
)
599 return ((insn
& 0x0C00) >> 10);
603 cris_get_opcode (unsigned short insn
)
605 return ((insn
& 0x03C0) >> 6);
609 cris_get_size (unsigned short insn
)
611 return ((insn
& 0x0030) >> 4);
615 cris_get_operand1 (unsigned short insn
)
617 return (insn
& 0x000F);
620 /* Additional functions in order to handle opcodes. */
623 cris_get_quick_value (unsigned short insn
)
625 return (insn
& 0x003F);
629 cris_get_bdap_quick_offset (unsigned short insn
)
631 return (insn
& 0x00FF);
635 cris_get_branch_short_offset (unsigned short insn
)
637 return (insn
& 0x00FF);
641 cris_get_asr_shift_steps (unsigned long value
)
643 return (value
& 0x3F);
647 cris_get_clear_size (unsigned short insn
)
649 return ((insn
) & 0xC000);
653 cris_is_signed_extend_bit_on (unsigned short insn
)
655 return (((insn
) & 0x20) == 0x20);
659 cris_is_xflag_bit_on (unsigned short insn
)
661 return (((insn
) & 0x1000) == 0x1000);
665 cris_set_size_to_dword (unsigned short *insn
)
672 cris_get_signed_offset (unsigned short insn
)
674 return ((signed char) (insn
& 0x00FF));
677 /* Calls an op function given the op-type, working on the insn and the
679 static void cris_gdb_func (enum cris_op_type
, unsigned short, inst_env_type
*);
681 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
682 struct gdbarch_list
*);
684 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
686 static void set_cris_version (char *ignore_args
, int from_tty
,
687 struct cmd_list_element
*c
);
689 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
690 struct cmd_list_element
*c
);
692 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
693 struct frame_info
*next_frame
,
694 struct cris_unwind_cache
*info
);
696 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
697 struct frame_info
*next_frame
);
699 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
700 struct frame_info
*next_frame
);
702 /* When arguments must be pushed onto the stack, they go on in reverse
703 order. The below implements a FILO (stack) to do this.
704 Copied from d10v-tdep.c. */
709 struct stack_item
*prev
;
713 static struct stack_item
*
714 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
716 struct stack_item
*si
;
717 si
= xmalloc (sizeof (struct stack_item
));
718 si
->data
= xmalloc (len
);
721 memcpy (si
->data
, contents
, len
);
725 static struct stack_item
*
726 pop_stack_item (struct stack_item
*si
)
728 struct stack_item
*dead
= si
;
735 /* Put here the code to store, into fi->saved_regs, the addresses of
736 the saved registers of frame described by FRAME_INFO. This
737 includes special registers such as pc and fp saved in special ways
738 in the stack frame. sp is even more special: the address we return
739 for it IS the sp for the next frame. */
741 struct cris_unwind_cache
*
742 cris_frame_unwind_cache (struct frame_info
*next_frame
,
743 void **this_prologue_cache
)
746 struct cris_unwind_cache
*info
;
749 if ((*this_prologue_cache
))
750 return (*this_prologue_cache
);
752 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
753 (*this_prologue_cache
) = info
;
754 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
756 /* Zero all fields. */
762 info
->uses_frame
= 0;
764 info
->leaf_function
= 0;
766 /* Prologue analysis does the rest... */
767 cris_scan_prologue (frame_func_unwind (next_frame
), next_frame
, info
);
772 /* Given a GDB frame, determine the address of the calling function's
773 frame. This will be used to create a new GDB frame struct. */
776 cris_frame_this_id (struct frame_info
*next_frame
,
777 void **this_prologue_cache
,
778 struct frame_id
*this_id
)
780 struct cris_unwind_cache
*info
781 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
786 /* The FUNC is easy. */
787 func
= frame_func_unwind (next_frame
);
789 /* Hopefully the prologue analysis either correctly determined the
790 frame's base (which is the SP from the previous frame), or set
791 that base to "NULL". */
792 base
= info
->prev_sp
;
796 id
= frame_id_build (base
, func
);
802 cris_frame_prev_register (struct frame_info
*next_frame
,
803 void **this_prologue_cache
,
804 int regnum
, int *optimizedp
,
805 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
806 int *realnump
, void *bufferp
)
808 struct cris_unwind_cache
*info
809 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
810 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
811 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
814 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
815 dummy frame. The frame ID's base needs to match the TOS value
816 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
819 static struct frame_id
820 cris_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
822 return frame_id_build (cris_unwind_sp (gdbarch
, next_frame
),
823 frame_pc_unwind (next_frame
));
827 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
829 /* Align to the size of an instruction (so that they can safely be
830 pushed onto the stack). */
835 cris_push_dummy_code (struct gdbarch
*gdbarch
,
836 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
837 struct value
**args
, int nargs
,
838 struct type
*value_type
,
839 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
841 /* Allocate space sufficient for a breakpoint. */
843 /* Store the address of that breakpoint */
845 /* CRIS always starts the call at the callee's entry point. */
851 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
852 struct regcache
*regcache
, CORE_ADDR bp_addr
,
853 int nargs
, struct value
**args
, CORE_ADDR sp
,
854 int struct_return
, CORE_ADDR struct_addr
)
863 /* The function's arguments and memory allocated by gdb for the arguments to
864 point at reside in separate areas on the stack.
865 Both frame pointers grow toward higher addresses. */
869 struct stack_item
*si
= NULL
;
871 /* Push the return address. */
872 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
874 /* Are we returning a value using a structure return or a normal value
875 return? struct_addr is the address of the reserved space for the return
876 structure to be written on the stack. */
879 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
882 /* Now load as many as possible of the first arguments into registers,
883 and push the rest onto the stack. */
884 argreg
= ARG1_REGNUM
;
887 for (argnum
= 0; argnum
< nargs
; argnum
++)
894 len
= TYPE_LENGTH (value_type (args
[argnum
]));
895 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
897 /* How may registers worth of storage do we need for this argument? */
898 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
900 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
902 /* Data passed by value. Fits in available register(s). */
903 for (i
= 0; i
< reg_demand
; i
++)
905 regcache_cooked_write_unsigned (regcache
, argreg
,
906 *(unsigned long *) val
);
911 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
913 /* Data passed by value. Does not fit in available register(s).
914 Use the register(s) first, then the stack. */
915 for (i
= 0; i
< reg_demand
; i
++)
917 if (argreg
<= ARG4_REGNUM
)
919 regcache_cooked_write_unsigned (regcache
, argreg
,
920 *(unsigned long *) val
);
926 /* Push item for later so that pushed arguments
927 come in the right order. */
928 si
= push_stack_item (si
, val
, 4);
933 else if (len
> (2 * 4))
936 internal_error (__FILE__
, __LINE__
, "We don't do this");
940 /* Data passed by value. No available registers. Put it on
942 si
= push_stack_item (si
, val
, len
);
948 /* fp_arg must be word-aligned (i.e., don't += len) to match
949 the function prologue. */
950 sp
= (sp
- si
->len
) & ~3;
951 write_memory (sp
, si
->data
, si
->len
);
952 si
= pop_stack_item (si
);
955 /* Finally, update the SP register. */
956 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
961 static const struct frame_unwind cris_frame_unwind
= {
964 cris_frame_prev_register
967 const struct frame_unwind
*
968 cris_frame_sniffer (struct frame_info
*next_frame
)
970 return &cris_frame_unwind
;
974 cris_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
976 struct cris_unwind_cache
*info
977 = cris_frame_unwind_cache (next_frame
, this_cache
);
981 static const struct frame_base cris_frame_base
= {
983 cris_frame_base_address
,
984 cris_frame_base_address
,
985 cris_frame_base_address
988 /* Frames information. The definition of the struct frame_info is
992 enum frame_type type;
996 If the compilation option -fno-omit-frame-pointer is present the
997 variable frame will be set to the content of R8 which is the frame
1000 The variable pc contains the address where execution is performed
1001 in the present frame. The innermost frame contains the current content
1002 of the register PC. All other frames contain the content of the
1003 register PC in the next frame.
1005 The variable `type' indicates the frame's type: normal, SIGTRAMP
1006 (associated with a signal handler), dummy (associated with a dummy
1009 The variable return_pc contains the address where execution should be
1010 resumed when the present frame has finished, the return address.
1012 The variable leaf_function is 1 if the return address is in the register
1013 SRP, and 0 if it is on the stack.
1015 Prologue instructions C-code.
1016 The prologue may consist of (-fno-omit-frame-pointer)
1020 move.d sp,r8 move.d sp,r8
1022 movem rY,[sp] movem rY,[sp]
1023 move.S rZ,[r8-U] move.S rZ,[r8-U]
1025 where 1 is a non-terminal function, and 2 is a leaf-function.
1027 Note that this assumption is extremely brittle, and will break at the
1028 slightest change in GCC's prologue.
1030 If local variables are declared or register contents are saved on stack
1031 the subq-instruction will be present with X as the number of bytes
1032 needed for storage. The reshuffle with respect to r8 may be performed
1033 with any size S (b, w, d) and any of the general registers Z={0..13}.
1034 The offset U should be representable by a signed 8-bit value in all cases.
1035 Thus, the prefix word is assumed to be immediate byte offset mode followed
1036 by another word containing the instruction.
1045 Prologue instructions C++-code.
1046 Case 1) and 2) in the C-code may be followed by
1048 move.d r10,rS ; this
1052 move.S [r8+U],rZ ; P4
1054 if any of the call parameters are stored. The host expects these
1055 instructions to be executed in order to get the call parameters right. */
1057 /* Examine the prologue of a function. The variable ip is the address of
1058 the first instruction of the prologue. The variable limit is the address
1059 of the first instruction after the prologue. The variable fi contains the
1060 information in struct frame_info. The variable frameless_p controls whether
1061 the entire prologue is examined (0) or just enough instructions to
1062 determine that it is a prologue (1). */
1065 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1066 struct cris_unwind_cache
*info
)
1068 /* Present instruction. */
1069 unsigned short insn
;
1071 /* Next instruction, lookahead. */
1072 unsigned short insn_next
;
1075 /* Is there a push fp? */
1078 /* Number of byte on stack used for local variables and movem. */
1081 /* Highest register number in a movem. */
1084 /* move.d r<source_register>,rS */
1085 short source_register
;
1090 /* This frame is with respect to a leaf until a push srp is found. */
1093 info
->leaf_function
= 1;
1096 /* Assume nothing on stack. */
1100 /* If we were called without a next_frame, that means we were called
1101 from cris_skip_prologue which already tried to find the end of the
1102 prologue through the symbol information. 64 instructions past current
1103 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1104 limit
= next_frame
? frame_pc_unwind (next_frame
) : pc
+ 64;
1106 /* Find the prologue instructions. */
1107 while (pc
> 0 && pc
< limit
)
1109 insn
= read_memory_unsigned_integer (pc
, 2);
1113 /* push <reg> 32 bit instruction */
1114 insn_next
= read_memory_unsigned_integer (pc
, 2);
1116 regno
= cris_get_operand2 (insn_next
);
1119 info
->sp_offset
+= 4;
1121 /* This check, meant to recognize srp, used to be regno ==
1122 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1123 if (insn_next
== 0xBE7E)
1127 info
->leaf_function
= 0;
1130 else if (insn_next
== 0x8FEE)
1135 info
->r8_offset
= info
->sp_offset
;
1139 else if (insn
== 0x866E)
1144 info
->uses_frame
= 1;
1148 else if (cris_get_operand2 (insn
) == SP_REGNUM
1149 && cris_get_mode (insn
) == 0x0000
1150 && cris_get_opcode (insn
) == 0x000A)
1155 info
->sp_offset
+= cris_get_quick_value (insn
);
1158 else if (cris_get_mode (insn
) == 0x0002
1159 && cris_get_opcode (insn
) == 0x000F
1160 && cris_get_size (insn
) == 0x0003
1161 && cris_get_operand1 (insn
) == SP_REGNUM
)
1163 /* movem r<regsave>,[sp] */
1164 regsave
= cris_get_operand2 (insn
);
1166 else if (cris_get_operand2 (insn
) == SP_REGNUM
1167 && ((insn
& 0x0F00) >> 8) == 0x0001
1168 && (cris_get_signed_offset (insn
) < 0))
1170 /* Immediate byte offset addressing prefix word with sp as base
1171 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1172 is between 64 and 128.
1173 movem r<regsave>,[sp=sp-<val>] */
1176 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1178 insn_next
= read_memory_unsigned_integer (pc
, 2);
1180 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1181 && cris_get_opcode (insn_next
) == 0x000F
1182 && cris_get_size (insn_next
) == 0x0003
1183 && cris_get_operand1 (insn_next
) == SP_REGNUM
)
1185 regsave
= cris_get_operand2 (insn_next
);
1189 /* The prologue ended before the limit was reached. */
1194 else if (cris_get_mode (insn
) == 0x0001
1195 && cris_get_opcode (insn
) == 0x0009
1196 && cris_get_size (insn
) == 0x0002)
1198 /* move.d r<10..13>,r<0..15> */
1199 source_register
= cris_get_operand1 (insn
);
1201 /* FIXME? In the glibc solibs, the prologue might contain something
1202 like (this example taken from relocate_doit):
1204 sub.d 0xfffef426,$r0
1205 which isn't covered by the source_register check below. Question
1206 is whether to add a check for this combo, or make better use of
1207 the limit variable instead. */
1208 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1210 /* The prologue ended before the limit was reached. */
1215 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1216 /* The size is a fixed-size. */
1217 && ((insn
& 0x0F00) >> 8) == 0x0001
1218 /* A negative offset. */
1219 && (cris_get_signed_offset (insn
) < 0))
1221 /* move.S rZ,[r8-U] (?) */
1222 insn_next
= read_memory_unsigned_integer (pc
, 2);
1224 regno
= cris_get_operand2 (insn_next
);
1225 if ((regno
>= 0 && regno
< SP_REGNUM
)
1226 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1227 && cris_get_opcode (insn_next
) == 0x000F)
1229 /* move.S rZ,[r8-U] */
1234 /* The prologue ended before the limit was reached. */
1239 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1240 /* The size is a fixed-size. */
1241 && ((insn
& 0x0F00) >> 8) == 0x0001
1242 /* A positive offset. */
1243 && (cris_get_signed_offset (insn
) > 0))
1245 /* move.S [r8+U],rZ (?) */
1246 insn_next
= read_memory_unsigned_integer (pc
, 2);
1248 regno
= cris_get_operand2 (insn_next
);
1249 if ((regno
>= 0 && regno
< SP_REGNUM
)
1250 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1251 && cris_get_opcode (insn_next
) == 0x0009
1252 && cris_get_operand1 (insn_next
) == regno
)
1254 /* move.S [r8+U],rZ */
1259 /* The prologue ended before the limit was reached. */
1266 /* The prologue ended before the limit was reached. */
1272 /* We only want to know the end of the prologue when next_frame and info
1273 are NULL (called from cris_skip_prologue i.e.). */
1274 if (next_frame
== NULL
&& info
== NULL
)
1279 info
->size
= info
->sp_offset
;
1281 /* Compute the previous frame's stack pointer (which is also the
1282 frame's ID's stack address), and this frame's base pointer. */
1283 if (info
->uses_frame
)
1286 /* The SP was moved to the FP. This indicates that a new frame
1287 was created. Get THIS frame's FP value by unwinding it from
1289 frame_unwind_unsigned_register (next_frame
, CRIS_FP_REGNUM
,
1291 info
->base
= this_base
;
1292 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1294 /* The FP points at the last saved register. Adjust the FP back
1295 to before the first saved register giving the SP. */
1296 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1301 /* Assume that the FP is this frame's SP but with that pushed
1302 stack space added back. */
1303 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
1304 info
->base
= this_base
;
1305 info
->prev_sp
= info
->base
+ info
->size
;
1308 /* Calculate the addresses for the saved registers on the stack. */
1309 /* FIXME: The address calculation should really be done on the fly while
1310 we're analyzing the prologue (we only hold one regsave value as it is
1312 val
= info
->sp_offset
;
1314 for (regno
= regsave
; regno
>= 0; regno
--)
1316 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1320 /* The previous frame's SP needed to be computed. Save the computed
1322 trad_frame_set_value (info
->saved_regs
, SP_REGNUM
, info
->prev_sp
);
1324 if (!info
->leaf_function
)
1326 /* SRP saved on the stack. But where? */
1327 if (info
->r8_offset
== 0)
1329 /* R8 not pushed yet. */
1330 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1334 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1335 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1339 /* The PC is found in SRP (the actual register or located on the stack). */
1340 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1345 /* Advance pc beyond any function entry prologue instructions at pc
1346 to reach some "real" code. */
1348 /* Given a PC value corresponding to the start of a function, return the PC
1349 of the first instruction after the function prologue. */
1352 cris_skip_prologue (CORE_ADDR pc
)
1354 CORE_ADDR func_addr
, func_end
;
1355 struct symtab_and_line sal
;
1356 CORE_ADDR pc_after_prologue
;
1358 /* If we have line debugging information, then the end of the prologue
1359 should the first assembly instruction of the first source line. */
1360 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1362 sal
= find_pc_line (func_addr
, 0);
1363 if (sal
.end
> 0 && sal
.end
< func_end
)
1367 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1368 return pc_after_prologue
;
1372 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1375 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1380 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1383 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &sp
);
1387 /* Use the program counter to determine the contents and size of a breakpoint
1388 instruction. It returns a pointer to a string of bytes that encode a
1389 breakpoint instruction, stores the length of the string to *lenptr, and
1390 adjusts pcptr (if necessary) to point to the actual memory location where
1391 the breakpoint should be inserted. */
1393 static const unsigned char *
1394 cris_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1396 static unsigned char break_insn
[] = {0x38, 0xe9};
1402 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1406 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1408 int version
= cris_version ();
1410 switch (spec_reg
.applicable_version
)
1412 case cris_ver_version_all
:
1414 case cris_ver_warning
:
1415 /* Indeterminate/obsolete. */
1418 return (version
>= 0 && version
<= 3);
1420 return (version
>= 3);
1422 return (version
== 8 || version
== 9);
1424 return (version
>= 8);
1425 case cris_ver_v0_10
:
1426 return (version
>= 0 && version
<= 10);
1427 case cris_ver_v3_10
:
1428 return (version
>= 3 && version
<= 10);
1429 case cris_ver_v8_10
:
1430 return (version
>= 8 && version
<= 10);
1432 return (version
== 10);
1434 return (version
>= 10);
1436 return (version
>= 32);
1438 /* Invalid cris version. */
1443 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1444 register, -1 for an invalid register. */
1447 cris_register_size (int regno
)
1449 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1453 if (regno
>= 0 && regno
< NUM_GENREGS
)
1455 /* General registers (R0 - R15) are 32 bits. */
1458 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1460 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1461 Adjust regno accordingly. */
1462 spec_regno
= regno
- NUM_GENREGS
;
1464 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1466 if (cris_spec_regs
[i
].number
== spec_regno
1467 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1468 /* Go with the first applicable register. */
1469 return cris_spec_regs
[i
].reg_size
;
1471 /* Special register not applicable to this CRIS version. */
1474 else if (regno
>= PC_REGNUM
&& regno
< NUM_REGS
)
1476 /* This will apply to CRISv32 only where there are additional registers
1477 after the special registers (pseudo PC and support registers). */
1485 /* Nonzero if regno should not be fetched from the target. This is the case
1486 for unimplemented (size 0) and non-existant registers. */
1489 cris_cannot_fetch_register (int regno
)
1491 return ((regno
< 0 || regno
>= NUM_REGS
)
1492 || (cris_register_size (regno
) == 0));
1495 /* Nonzero if regno should not be written to the target, for various
1499 cris_cannot_store_register (int regno
)
1501 /* There are three kinds of registers we refuse to write to.
1502 1. Those that not implemented.
1503 2. Those that are read-only (depends on the processor mode).
1504 3. Those registers to which a write has no effect.
1507 if (regno
< 0 || regno
>= NUM_REGS
|| cris_register_size (regno
) == 0)
1508 /* Not implemented. */
1511 else if (regno
== VR_REGNUM
)
1515 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1516 /* Writing has no effect. */
1519 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1520 agent decide whether they are writable. */
1525 /* Nonzero if regno should not be fetched from the target. This is the case
1526 for unimplemented (size 0) and non-existant registers. */
1529 crisv32_cannot_fetch_register (int regno
)
1531 return ((regno
< 0 || regno
>= NUM_REGS
)
1532 || (cris_register_size (regno
) == 0));
1535 /* Nonzero if regno should not be written to the target, for various
1539 crisv32_cannot_store_register (int regno
)
1541 /* There are three kinds of registers we refuse to write to.
1542 1. Those that not implemented.
1543 2. Those that are read-only (depends on the processor mode).
1544 3. Those registers to which a write has no effect.
1547 if (regno
< 0 || regno
>= NUM_REGS
|| cris_register_size (regno
) == 0)
1548 /* Not implemented. */
1551 else if (regno
== VR_REGNUM
)
1555 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1556 /* Writing has no effect. */
1559 /* Many special registers are read-only in user mode. Let the debug
1560 agent decide whether they are writable. */
1565 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1566 of data in register regno. */
1568 static struct type
*
1569 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1571 if (regno
== PC_REGNUM
)
1572 return builtin_type_void_func_ptr
;
1573 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1574 return builtin_type_void_data_ptr
;
1575 else if ((regno
>= 0 && regno
< SP_REGNUM
)
1576 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1577 /* Note: R8 taken care of previous clause. */
1578 return builtin_type_uint32
;
1579 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1580 return builtin_type_uint16
;
1581 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1582 return builtin_type_uint8
;
1584 /* Invalid (unimplemented) register. */
1585 return builtin_type_int0
;
1588 static struct type
*
1589 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1591 if (regno
== PC_REGNUM
)
1592 return builtin_type_void_func_ptr
;
1593 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1594 return builtin_type_void_data_ptr
;
1595 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1596 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1597 || (regno
== PID_REGNUM
)
1598 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1599 /* Note: R8 and SP taken care of by previous clause. */
1600 return builtin_type_uint32
;
1601 else if (regno
== WZ_REGNUM
)
1602 return builtin_type_uint16
;
1603 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1604 return builtin_type_uint8
;
1607 /* Invalid (unimplemented) register. Should not happen as there are
1608 no unimplemented CRISv32 registers. */
1609 warning ("crisv32_register_type: unknown regno %d", regno
);
1610 return builtin_type_int0
;
1614 /* Stores a function return value of type type, where valbuf is the address
1615 of the value to be stored. */
1617 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1620 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1624 int len
= TYPE_LENGTH (type
);
1628 /* Put the return value in R10. */
1629 val
= extract_unsigned_integer (valbuf
, len
);
1630 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1634 /* Put the return value in R10 and R11. */
1635 val
= extract_unsigned_integer (valbuf
, 4);
1636 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1637 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1638 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1641 error ("cris_store_return_value: type length too large.");
1644 /* Return the name of register regno as a string. Return NULL for an invalid or
1645 unimplemented register. */
1648 cris_special_register_name (int regno
)
1653 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1654 Adjust regno accordingly. */
1655 spec_regno
= regno
- NUM_GENREGS
;
1657 /* Assume nothing about the layout of the cris_spec_regs struct
1659 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1661 if (cris_spec_regs
[i
].number
== spec_regno
1662 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1663 /* Go with the first applicable register. */
1664 return cris_spec_regs
[i
].name
;
1666 /* Special register not applicable to this CRIS version. */
1671 cris_register_name (int regno
)
1673 static char *cris_genreg_names
[] =
1674 { "r0", "r1", "r2", "r3", \
1675 "r4", "r5", "r6", "r7", \
1676 "r8", "r9", "r10", "r11", \
1677 "r12", "r13", "sp", "pc" };
1679 if (regno
>= 0 && regno
< NUM_GENREGS
)
1681 /* General register. */
1682 return cris_genreg_names
[regno
];
1684 else if (regno
>= NUM_GENREGS
&& regno
< NUM_REGS
)
1686 return cris_special_register_name (regno
);
1690 /* Invalid register. */
1696 crisv32_register_name (int regno
)
1698 static char *crisv32_genreg_names
[] =
1699 { "r0", "r1", "r2", "r3", \
1700 "r4", "r5", "r6", "r7", \
1701 "r8", "r9", "r10", "r11", \
1702 "r12", "r13", "sp", "acr"
1705 static char *crisv32_sreg_names
[] =
1706 { "s0", "s1", "s2", "s3", \
1707 "s4", "s5", "s6", "s7", \
1708 "s8", "s9", "s10", "s11", \
1709 "s12", "s13", "s14", "s15"
1712 if (regno
>= 0 && regno
< NUM_GENREGS
)
1714 /* General register. */
1715 return crisv32_genreg_names
[regno
];
1717 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1719 return cris_special_register_name (regno
);
1721 else if (regno
== PC_REGNUM
)
1725 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1727 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1731 /* Invalid register. */
1736 /* Convert DWARF register number REG to the appropriate register
1737 number used by GDB. */
1740 cris_dwarf2_reg_to_regnum (int reg
)
1742 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1743 numbering, MOF is 18).
1744 Adapted from gcc/config/cris/cris.h. */
1745 static int cris_dwarf_regmap
[] = {
1757 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1758 regnum
= cris_dwarf_regmap
[reg
];
1761 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
1766 /* DWARF-2 frame support. */
1769 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1770 struct dwarf2_frame_state_reg
*reg
)
1772 /* The return address column. */
1773 if (regnum
== PC_REGNUM
)
1774 reg
->how
= DWARF2_FRAME_REG_RA
;
1776 /* The call frame address. */
1777 else if (regnum
== SP_REGNUM
)
1778 reg
->how
= DWARF2_FRAME_REG_CFA
;
1781 /* Extract from an array regbuf containing the raw register state a function
1782 return value of type type, and copy that, in virtual format, into
1785 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1788 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1792 int len
= TYPE_LENGTH (type
);
1796 /* Get the return value from R10. */
1797 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1798 store_unsigned_integer (valbuf
, len
, val
);
1802 /* Get the return value from R10 and R11. */
1803 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1804 store_unsigned_integer (valbuf
, 4, val
);
1805 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1806 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1809 error ("cris_extract_return_value: type length too large");
1812 /* Handle the CRIS return value convention. */
1814 static enum return_value_convention
1815 cris_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1816 struct regcache
*regcache
, void *readbuf
,
1817 const void *writebuf
)
1819 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1820 || TYPE_CODE (type
) == TYPE_CODE_UNION
1821 || TYPE_LENGTH (type
) > 8)
1822 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1823 goes on the stack. */
1824 return RETURN_VALUE_STRUCT_CONVENTION
;
1827 cris_extract_return_value (type
, regcache
, readbuf
);
1829 cris_store_return_value (type
, regcache
, writebuf
);
1831 return RETURN_VALUE_REGISTER_CONVENTION
;
1834 /* Returns 1 if the given type will be passed by pointer rather than
1837 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1841 cris_reg_struct_has_addr (int gcc_p
, struct type
*type
)
1843 return (TYPE_LENGTH (type
) > 8);
1846 /* Calculates a value that measures how good inst_args constraints an
1847 instruction. It stems from cris_constraint, found in cris-dis.c. */
1850 constraint (unsigned int insn
, const signed char *inst_args
,
1851 inst_env_type
*inst_env
)
1856 const char *s
= inst_args
;
1862 if ((insn
& 0x30) == 0x30)
1867 /* A prefix operand. */
1868 if (inst_env
->prefix_found
)
1874 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1875 valid "push" size. In case of special register, it may be != 4. */
1876 if (inst_env
->prefix_found
)
1882 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1890 tmp
= (insn
>> 0xC) & 0xF;
1892 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1894 /* Since we match four bits, we will give a value of
1895 4 - 1 = 3 in a match. If there is a corresponding
1896 exact match of a special register in another pattern, it
1897 will get a value of 4, which will be higher. This should
1898 be correct in that an exact pattern would match better that
1900 Note that there is a reason for not returning zero; the
1901 pattern for "clear" is partly matched in the bit-pattern
1902 (the two lower bits must be zero), while the bit-pattern
1903 for a move from a special register is matched in the
1904 register constraint.
1905 This also means we will will have a race condition if
1906 there is a partly match in three bits in the bit pattern. */
1907 if (tmp
== cris_spec_regs
[i
].number
)
1914 if (cris_spec_regs
[i
].name
== NULL
)
1921 /* Returns the number of bits set in the variable value. */
1924 number_of_bits (unsigned int value
)
1926 int number_of_bits
= 0;
1930 number_of_bits
+= 1;
1931 value
&= (value
- 1);
1933 return number_of_bits
;
1936 /* Finds the address that should contain the single step breakpoint(s).
1937 It stems from code in cris-dis.c. */
1940 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
1943 int max_level_of_match
= -1;
1944 int max_matched
= -1;
1947 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
1949 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
1950 && ((cris_opcodes
[i
].lose
& insn
) == 0)
1951 /* Only CRISv10 instructions, please. */
1952 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
1954 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
1955 if (level_of_match
>= 0)
1958 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
1959 if (level_of_match
> max_level_of_match
)
1962 max_level_of_match
= level_of_match
;
1963 if (level_of_match
== 16)
1965 /* All bits matched, cannot find better. */
1975 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1976 actually an internal error. */
1979 find_step_target (inst_env_type
*inst_env
)
1983 unsigned short insn
;
1985 /* Create a local register image and set the initial state. */
1986 for (i
= 0; i
< NUM_GENREGS
; i
++)
1988 inst_env
->reg
[i
] = (unsigned long) read_register (i
);
1990 offset
= NUM_GENREGS
;
1991 for (i
= 0; i
< NUM_SPECREGS
; i
++)
1993 inst_env
->preg
[i
] = (unsigned long) read_register (offset
+ i
);
1995 inst_env
->branch_found
= 0;
1996 inst_env
->slot_needed
= 0;
1997 inst_env
->delay_slot_pc_active
= 0;
1998 inst_env
->prefix_found
= 0;
1999 inst_env
->invalid
= 0;
2000 inst_env
->xflag_found
= 0;
2001 inst_env
->disable_interrupt
= 0;
2003 /* Look for a step target. */
2006 /* Read an instruction from the client. */
2007 insn
= read_memory_unsigned_integer (inst_env
->reg
[PC_REGNUM
], 2);
2009 /* If the instruction is not in a delay slot the new content of the
2010 PC is [PC] + 2. If the instruction is in a delay slot it is not
2011 that simple. Since a instruction in a delay slot cannot change
2012 the content of the PC, it does not matter what value PC will have.
2013 Just make sure it is a valid instruction. */
2014 if (!inst_env
->delay_slot_pc_active
)
2016 inst_env
->reg
[PC_REGNUM
] += 2;
2020 inst_env
->delay_slot_pc_active
= 0;
2021 inst_env
->reg
[PC_REGNUM
] = inst_env
->delay_slot_pc
;
2023 /* Analyse the present instruction. */
2024 i
= find_cris_op (insn
, inst_env
);
2027 inst_env
->invalid
= 1;
2031 cris_gdb_func (cris_opcodes
[i
].op
, insn
, inst_env
);
2033 } while (!inst_env
->invalid
2034 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2035 || inst_env
->slot_needed
));
2039 /* There is no hardware single-step support. The function find_step_target
2040 digs through the opcodes in order to find all possible targets.
2041 Either one ordinary target or two targets for branches may be found. */
2044 cris_software_single_step (enum target_signal ignore
, int insert_breakpoints
)
2046 inst_env_type inst_env
;
2048 if (insert_breakpoints
)
2050 /* Analyse the present instruction environment and insert
2052 int status
= find_step_target (&inst_env
);
2055 /* Could not find a target. Things are likely to go downhill
2057 warning ("CRIS software single step could not find a step target.");
2061 /* Insert at most two breakpoints. One for the next PC content
2062 and possibly another one for a branch, jump, etc. */
2063 next_pc
= (CORE_ADDR
) inst_env
.reg
[PC_REGNUM
];
2064 target_insert_breakpoint (next_pc
, break_mem
[0]);
2065 if (inst_env
.branch_found
2066 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2068 branch_target_address
=
2069 (CORE_ADDR
) inst_env
.branch_break_address
;
2070 target_insert_breakpoint (branch_target_address
, break_mem
[1]);
2071 branch_break_inserted
= 1;
2077 /* Remove breakpoints. */
2078 target_remove_breakpoint (next_pc
, break_mem
[0]);
2079 if (branch_break_inserted
)
2081 target_remove_breakpoint (branch_target_address
, break_mem
[1]);
2082 branch_break_inserted
= 0;
2087 /* Calculates the prefix value for quick offset addressing mode. */
2090 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2092 /* It's invalid to be in a delay slot. You can't have a prefix to this
2093 instruction (not 100% sure). */
2094 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2096 inst_env
->invalid
= 1;
2100 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2101 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2103 /* A prefix doesn't change the xflag_found. But the rest of the flags
2105 inst_env
->slot_needed
= 0;
2106 inst_env
->prefix_found
= 1;
2109 /* Updates the autoincrement register. The size of the increment is derived
2110 from the size of the operation. The PC is always kept aligned on even
2114 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2116 if (size
== INST_BYTE_SIZE
)
2118 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2120 /* The PC must be word aligned, so increase the PC with one
2121 word even if the size is byte. */
2122 if (cris_get_operand1 (inst
) == REG_PC
)
2124 inst_env
->reg
[REG_PC
] += 1;
2127 else if (size
== INST_WORD_SIZE
)
2129 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2131 else if (size
== INST_DWORD_SIZE
)
2133 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2138 inst_env
->invalid
= 1;
2142 /* Just a forward declaration. */
2144 static unsigned long get_data_from_address (unsigned short *inst
,
2147 /* Calculates the prefix value for the general case of offset addressing
2151 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2156 /* It's invalid to be in a delay slot. */
2157 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2159 inst_env
->invalid
= 1;
2163 /* The calculation of prefix_value used to be after process_autoincrement,
2164 but that fails for an instruction such as jsr [$r0+12] which is encoded
2165 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2166 mustn't be incremented until we have read it and what it points at. */
2167 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2169 /* The offset is an indirection of the contents of the operand1 register. */
2170 inst_env
->prefix_value
+=
2171 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
2173 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2175 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2178 /* A prefix doesn't change the xflag_found. But the rest of the flags
2180 inst_env
->slot_needed
= 0;
2181 inst_env
->prefix_found
= 1;
2184 /* Calculates the prefix value for the index addressing mode. */
2187 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2189 /* It's invalid to be in a delay slot. I can't see that it's possible to
2190 have a prefix to this instruction. So I will treat this as invalid. */
2191 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2193 inst_env
->invalid
= 1;
2197 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2199 /* The offset is the operand2 value shifted the size of the instruction
2201 inst_env
->prefix_value
+=
2202 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2204 /* If the PC is operand1 (base) the address used is the address after
2205 the main instruction, i.e. address + 2 (the PC is already compensated
2206 for the prefix operation). */
2207 if (cris_get_operand1 (inst
) == REG_PC
)
2209 inst_env
->prefix_value
+= 2;
2212 /* A prefix doesn't change the xflag_found. But the rest of the flags
2214 inst_env
->slot_needed
= 0;
2215 inst_env
->xflag_found
= 0;
2216 inst_env
->prefix_found
= 1;
2219 /* Calculates the prefix value for the double indirect addressing mode. */
2222 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2227 /* It's invalid to be in a delay slot. */
2228 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2230 inst_env
->invalid
= 1;
2234 /* The prefix value is one dereference of the contents of the operand1
2236 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2237 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
2239 /* Check if the mode is autoincrement. */
2240 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2242 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2245 /* A prefix doesn't change the xflag_found. But the rest of the flags
2247 inst_env
->slot_needed
= 0;
2248 inst_env
->xflag_found
= 0;
2249 inst_env
->prefix_found
= 1;
2252 /* Finds the destination for a branch with 8-bits offset. */
2255 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2260 /* If we have a prefix or are in a delay slot it's bad. */
2261 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2263 inst_env
->invalid
= 1;
2267 /* We have a branch, find out where the branch will land. */
2268 offset
= cris_get_branch_short_offset (inst
);
2270 /* Check if the offset is signed. */
2271 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2276 /* The offset ends with the sign bit, set it to zero. The address
2277 should always be word aligned. */
2278 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2280 inst_env
->branch_found
= 1;
2281 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2283 inst_env
->slot_needed
= 1;
2284 inst_env
->prefix_found
= 0;
2285 inst_env
->xflag_found
= 0;
2286 inst_env
->disable_interrupt
= 1;
2289 /* Finds the destination for a branch with 16-bits offset. */
2292 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2296 /* If we have a prefix or is in a delay slot it's bad. */
2297 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2299 inst_env
->invalid
= 1;
2303 /* We have a branch, find out the offset for the branch. */
2304 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
2306 /* The instruction is one word longer than normal, so add one word
2308 inst_env
->reg
[REG_PC
] += 2;
2310 inst_env
->branch_found
= 1;
2311 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2314 inst_env
->slot_needed
= 1;
2315 inst_env
->prefix_found
= 0;
2316 inst_env
->xflag_found
= 0;
2317 inst_env
->disable_interrupt
= 1;
2320 /* Handles the ABS instruction. */
2323 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2328 /* ABS can't have a prefix, so it's bad if it does. */
2329 if (inst_env
->prefix_found
)
2331 inst_env
->invalid
= 1;
2335 /* Check if the operation affects the PC. */
2336 if (cris_get_operand2 (inst
) == REG_PC
)
2339 /* It's invalid to change to the PC if we are in a delay slot. */
2340 if (inst_env
->slot_needed
)
2342 inst_env
->invalid
= 1;
2346 value
= (long) inst_env
->reg
[REG_PC
];
2348 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2349 if (value
!= SIGNED_DWORD_MASK
)
2352 inst_env
->reg
[REG_PC
] = (long) value
;
2356 inst_env
->slot_needed
= 0;
2357 inst_env
->prefix_found
= 0;
2358 inst_env
->xflag_found
= 0;
2359 inst_env
->disable_interrupt
= 0;
2362 /* Handles the ADDI instruction. */
2365 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2367 /* It's invalid to have the PC as base register. And ADDI can't have
2369 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2371 inst_env
->invalid
= 1;
2375 inst_env
->slot_needed
= 0;
2376 inst_env
->prefix_found
= 0;
2377 inst_env
->xflag_found
= 0;
2378 inst_env
->disable_interrupt
= 0;
2381 /* Handles the ASR instruction. */
2384 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2387 unsigned long value
;
2388 unsigned long signed_extend_mask
= 0;
2390 /* ASR can't have a prefix, so check that it doesn't. */
2391 if (inst_env
->prefix_found
)
2393 inst_env
->invalid
= 1;
2397 /* Check if the PC is the target register. */
2398 if (cris_get_operand2 (inst
) == REG_PC
)
2400 /* It's invalid to change the PC in a delay slot. */
2401 if (inst_env
->slot_needed
)
2403 inst_env
->invalid
= 1;
2406 /* Get the number of bits to shift. */
2407 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2408 value
= inst_env
->reg
[REG_PC
];
2410 /* Find out how many bits the operation should apply to. */
2411 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2413 if (value
& SIGNED_BYTE_MASK
)
2415 signed_extend_mask
= 0xFF;
2416 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2417 signed_extend_mask
= ~signed_extend_mask
;
2419 value
= value
>> shift_steps
;
2420 value
|= signed_extend_mask
;
2422 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2423 inst_env
->reg
[REG_PC
] |= value
;
2425 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2427 if (value
& SIGNED_WORD_MASK
)
2429 signed_extend_mask
= 0xFFFF;
2430 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2431 signed_extend_mask
= ~signed_extend_mask
;
2433 value
= value
>> shift_steps
;
2434 value
|= signed_extend_mask
;
2436 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2437 inst_env
->reg
[REG_PC
] |= value
;
2439 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2441 if (value
& SIGNED_DWORD_MASK
)
2443 signed_extend_mask
= 0xFFFFFFFF;
2444 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2445 signed_extend_mask
= ~signed_extend_mask
;
2447 value
= value
>> shift_steps
;
2448 value
|= signed_extend_mask
;
2449 inst_env
->reg
[REG_PC
] = value
;
2452 inst_env
->slot_needed
= 0;
2453 inst_env
->prefix_found
= 0;
2454 inst_env
->xflag_found
= 0;
2455 inst_env
->disable_interrupt
= 0;
2458 /* Handles the ASRQ instruction. */
2461 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2465 unsigned long value
;
2466 unsigned long signed_extend_mask
= 0;
2468 /* ASRQ can't have a prefix, so check that it doesn't. */
2469 if (inst_env
->prefix_found
)
2471 inst_env
->invalid
= 1;
2475 /* Check if the PC is the target register. */
2476 if (cris_get_operand2 (inst
) == REG_PC
)
2479 /* It's invalid to change the PC in a delay slot. */
2480 if (inst_env
->slot_needed
)
2482 inst_env
->invalid
= 1;
2485 /* The shift size is given as a 5 bit quick value, i.e. we don't
2486 want the the sign bit of the quick value. */
2487 shift_steps
= cris_get_asr_shift_steps (inst
);
2488 value
= inst_env
->reg
[REG_PC
];
2489 if (value
& SIGNED_DWORD_MASK
)
2491 signed_extend_mask
= 0xFFFFFFFF;
2492 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2493 signed_extend_mask
= ~signed_extend_mask
;
2495 value
= value
>> shift_steps
;
2496 value
|= signed_extend_mask
;
2497 inst_env
->reg
[REG_PC
] = value
;
2499 inst_env
->slot_needed
= 0;
2500 inst_env
->prefix_found
= 0;
2501 inst_env
->xflag_found
= 0;
2502 inst_env
->disable_interrupt
= 0;
2505 /* Handles the AX, EI and SETF instruction. */
2508 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2510 if (inst_env
->prefix_found
)
2512 inst_env
->invalid
= 1;
2515 /* Check if the instruction is setting the X flag. */
2516 if (cris_is_xflag_bit_on (inst
))
2518 inst_env
->xflag_found
= 1;
2522 inst_env
->xflag_found
= 0;
2524 inst_env
->slot_needed
= 0;
2525 inst_env
->prefix_found
= 0;
2526 inst_env
->disable_interrupt
= 1;
2529 /* Checks if the instruction is in assign mode. If so, it updates the assign
2530 register. Note that check_assign assumes that the caller has checked that
2531 there is a prefix to this instruction. The mode check depends on this. */
2534 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2536 /* Check if it's an assign addressing mode. */
2537 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2539 /* Assign the prefix value to operand 1. */
2540 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2544 /* Handles the 2-operand BOUND instruction. */
2547 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2549 /* It's invalid to have the PC as the index operand. */
2550 if (cris_get_operand2 (inst
) == REG_PC
)
2552 inst_env
->invalid
= 1;
2555 /* Check if we have a prefix. */
2556 if (inst_env
->prefix_found
)
2558 check_assign (inst
, inst_env
);
2560 /* Check if this is an autoincrement mode. */
2561 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2563 /* It's invalid to change the PC in a delay slot. */
2564 if (inst_env
->slot_needed
)
2566 inst_env
->invalid
= 1;
2569 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2571 inst_env
->slot_needed
= 0;
2572 inst_env
->prefix_found
= 0;
2573 inst_env
->xflag_found
= 0;
2574 inst_env
->disable_interrupt
= 0;
2577 /* Handles the 3-operand BOUND instruction. */
2580 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2582 /* It's an error if we haven't got a prefix. And it's also an error
2583 if the PC is the destination register. */
2584 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2586 inst_env
->invalid
= 1;
2589 inst_env
->slot_needed
= 0;
2590 inst_env
->prefix_found
= 0;
2591 inst_env
->xflag_found
= 0;
2592 inst_env
->disable_interrupt
= 0;
2595 /* Clears the status flags in inst_env. */
2598 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2600 /* It's an error if we have got a prefix. */
2601 if (inst_env
->prefix_found
)
2603 inst_env
->invalid
= 1;
2607 inst_env
->slot_needed
= 0;
2608 inst_env
->prefix_found
= 0;
2609 inst_env
->xflag_found
= 0;
2610 inst_env
->disable_interrupt
= 0;
2613 /* Clears the status flags in inst_env. */
2616 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2618 /* It's an error if we have got a prefix. */
2619 if (inst_env
->prefix_found
)
2621 inst_env
->invalid
= 1;
2625 inst_env
->slot_needed
= 0;
2626 inst_env
->prefix_found
= 0;
2627 inst_env
->xflag_found
= 0;
2628 inst_env
->disable_interrupt
= 1;
2631 /* Handles the CLEAR instruction if it's in register mode. */
2634 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2636 /* Check if the target is the PC. */
2637 if (cris_get_operand2 (inst
) == REG_PC
)
2639 /* The instruction will clear the instruction's size bits. */
2640 int clear_size
= cris_get_clear_size (inst
);
2641 if (clear_size
== INST_BYTE_SIZE
)
2643 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2645 if (clear_size
== INST_WORD_SIZE
)
2647 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2649 if (clear_size
== INST_DWORD_SIZE
)
2651 inst_env
->delay_slot_pc
= 0x0;
2653 /* The jump will be delayed with one delay slot. So we need a delay
2655 inst_env
->slot_needed
= 1;
2656 inst_env
->delay_slot_pc_active
= 1;
2660 /* The PC will not change => no delay slot. */
2661 inst_env
->slot_needed
= 0;
2663 inst_env
->prefix_found
= 0;
2664 inst_env
->xflag_found
= 0;
2665 inst_env
->disable_interrupt
= 0;
2668 /* Handles the TEST instruction if it's in register mode. */
2671 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2673 /* It's an error if we have got a prefix. */
2674 if (inst_env
->prefix_found
)
2676 inst_env
->invalid
= 1;
2679 inst_env
->slot_needed
= 0;
2680 inst_env
->prefix_found
= 0;
2681 inst_env
->xflag_found
= 0;
2682 inst_env
->disable_interrupt
= 0;
2686 /* Handles the CLEAR and TEST instruction if the instruction isn't
2687 in register mode. */
2690 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2692 /* Check if we are in a prefix mode. */
2693 if (inst_env
->prefix_found
)
2695 /* The only way the PC can change is if this instruction is in
2696 assign addressing mode. */
2697 check_assign (inst
, inst_env
);
2699 /* Indirect mode can't change the PC so just check if the mode is
2701 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2703 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2705 inst_env
->slot_needed
= 0;
2706 inst_env
->prefix_found
= 0;
2707 inst_env
->xflag_found
= 0;
2708 inst_env
->disable_interrupt
= 0;
2711 /* Checks that the PC isn't the destination register or the instructions has
2715 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2717 /* It's invalid to have the PC as the destination. The instruction can't
2719 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2721 inst_env
->invalid
= 1;
2725 inst_env
->slot_needed
= 0;
2726 inst_env
->prefix_found
= 0;
2727 inst_env
->xflag_found
= 0;
2728 inst_env
->disable_interrupt
= 0;
2731 /* Checks that the instruction doesn't have a prefix. */
2734 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2736 /* The instruction can't have a prefix. */
2737 if (inst_env
->prefix_found
)
2739 inst_env
->invalid
= 1;
2743 inst_env
->slot_needed
= 0;
2744 inst_env
->prefix_found
= 0;
2745 inst_env
->xflag_found
= 0;
2746 inst_env
->disable_interrupt
= 1;
2749 /* Checks that the PC isn't the destination register and that the instruction
2750 doesn't have a prefix. */
2753 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2755 /* It's invalid to have the PC as the destination. The instruction can't
2757 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2759 inst_env
->invalid
= 1;
2763 inst_env
->slot_needed
= 0;
2764 inst_env
->prefix_found
= 0;
2765 inst_env
->xflag_found
= 0;
2766 inst_env
->disable_interrupt
= 1;
2769 /* Handles the register mode JUMP instruction. */
2772 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2774 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2775 you can't have a prefix. */
2776 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2778 inst_env
->invalid
= 1;
2782 /* Just change the PC. */
2783 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2784 inst_env
->slot_needed
= 0;
2785 inst_env
->prefix_found
= 0;
2786 inst_env
->xflag_found
= 0;
2787 inst_env
->disable_interrupt
= 1;
2790 /* Handles the JUMP instruction for all modes except register. */
2793 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2795 unsigned long newpc
;
2798 /* It's invalid to do a JUMP in a delay slot. */
2799 if (inst_env
->slot_needed
)
2801 inst_env
->invalid
= 1;
2805 /* Check if we have a prefix. */
2806 if (inst_env
->prefix_found
)
2808 check_assign (inst
, inst_env
);
2810 /* Get the new value for the the PC. */
2812 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2817 /* Get the new value for the PC. */
2818 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2819 newpc
= read_memory_unsigned_integer (address
, 4);
2821 /* Check if we should increment a register. */
2822 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2824 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2827 inst_env
->reg
[REG_PC
] = newpc
;
2829 inst_env
->slot_needed
= 0;
2830 inst_env
->prefix_found
= 0;
2831 inst_env
->xflag_found
= 0;
2832 inst_env
->disable_interrupt
= 1;
2835 /* Handles moves to special registers (aka P-register) for all modes. */
2838 move_to_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2840 if (inst_env
->prefix_found
)
2842 /* The instruction has a prefix that means we are only interested if
2843 the instruction is in assign mode. */
2844 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2846 /* The prefix handles the problem if we are in a delay slot. */
2847 if (cris_get_operand1 (inst
) == REG_PC
)
2849 /* Just take care of the assign. */
2850 check_assign (inst
, inst_env
);
2854 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2856 /* The instruction doesn't have a prefix, the only case left that we
2857 are interested in is the autoincrement mode. */
2858 if (cris_get_operand1 (inst
) == REG_PC
)
2860 /* If the PC is to be incremented it's invalid to be in a
2862 if (inst_env
->slot_needed
)
2864 inst_env
->invalid
= 1;
2868 /* The increment depends on the size of the special register. */
2869 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2871 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2873 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2875 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2879 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2883 inst_env
->slot_needed
= 0;
2884 inst_env
->prefix_found
= 0;
2885 inst_env
->xflag_found
= 0;
2886 inst_env
->disable_interrupt
= 1;
2889 /* Handles moves from special registers (aka P-register) for all modes
2893 none_reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2895 if (inst_env
->prefix_found
)
2897 /* The instruction has a prefix that means we are only interested if
2898 the instruction is in assign mode. */
2899 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2901 /* The prefix handles the problem if we are in a delay slot. */
2902 if (cris_get_operand1 (inst
) == REG_PC
)
2904 /* Just take care of the assign. */
2905 check_assign (inst
, inst_env
);
2909 /* The instruction doesn't have a prefix, the only case left that we
2910 are interested in is the autoincrement mode. */
2911 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2913 if (cris_get_operand1 (inst
) == REG_PC
)
2915 /* If the PC is to be incremented it's invalid to be in a
2917 if (inst_env
->slot_needed
)
2919 inst_env
->invalid
= 1;
2923 /* The increment depends on the size of the special register. */
2924 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2926 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2928 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2930 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2934 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2938 inst_env
->slot_needed
= 0;
2939 inst_env
->prefix_found
= 0;
2940 inst_env
->xflag_found
= 0;
2941 inst_env
->disable_interrupt
= 1;
2944 /* Handles moves from special registers (aka P-register) when the mode
2948 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2950 /* Register mode move from special register can't have a prefix. */
2951 if (inst_env
->prefix_found
)
2953 inst_env
->invalid
= 1;
2957 if (cris_get_operand1 (inst
) == REG_PC
)
2959 /* It's invalid to change the PC in a delay slot. */
2960 if (inst_env
->slot_needed
)
2962 inst_env
->invalid
= 1;
2965 /* The destination is the PC, the jump will have a delay slot. */
2966 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
2967 inst_env
->slot_needed
= 1;
2968 inst_env
->delay_slot_pc_active
= 1;
2972 /* If the destination isn't PC, there will be no jump. */
2973 inst_env
->slot_needed
= 0;
2975 inst_env
->prefix_found
= 0;
2976 inst_env
->xflag_found
= 0;
2977 inst_env
->disable_interrupt
= 1;
2980 /* Handles the MOVEM from memory to general register instruction. */
2983 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
2985 if (inst_env
->prefix_found
)
2987 /* The prefix handles the problem if we are in a delay slot. Is the
2988 MOVEM instruction going to change the PC? */
2989 if (cris_get_operand2 (inst
) >= REG_PC
)
2991 inst_env
->reg
[REG_PC
] =
2992 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
2994 /* The assign value is the value after the increment. Normally, the
2995 assign value is the value before the increment. */
2996 if ((cris_get_operand1 (inst
) == REG_PC
)
2997 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
2999 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3000 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3005 /* Is the MOVEM instruction going to change the PC? */
3006 if (cris_get_operand2 (inst
) == REG_PC
)
3008 /* It's invalid to change the PC in a delay slot. */
3009 if (inst_env
->slot_needed
)
3011 inst_env
->invalid
= 1;
3014 inst_env
->reg
[REG_PC
] =
3015 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3018 /* The increment is not depending on the size, instead it's depending
3019 on the number of registers loaded from memory. */
3020 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3022 /* It's invalid to change the PC in a delay slot. */
3023 if (inst_env
->slot_needed
)
3025 inst_env
->invalid
= 1;
3028 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3031 inst_env
->slot_needed
= 0;
3032 inst_env
->prefix_found
= 0;
3033 inst_env
->xflag_found
= 0;
3034 inst_env
->disable_interrupt
= 0;
3037 /* Handles the MOVEM to memory from general register instruction. */
3040 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3042 if (inst_env
->prefix_found
)
3044 /* The assign value is the value after the increment. Normally, the
3045 assign value is the value before the increment. */
3046 if ((cris_get_operand1 (inst
) == REG_PC
) &&
3047 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3049 /* The prefix handles the problem if we are in a delay slot. */
3050 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3051 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3056 /* The increment is not depending on the size, instead it's depending
3057 on the number of registers loaded to memory. */
3058 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3060 /* It's invalid to change the PC in a delay slot. */
3061 if (inst_env
->slot_needed
)
3063 inst_env
->invalid
= 1;
3066 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3069 inst_env
->slot_needed
= 0;
3070 inst_env
->prefix_found
= 0;
3071 inst_env
->xflag_found
= 0;
3072 inst_env
->disable_interrupt
= 0;
3075 /* Handles the intructions that's not yet implemented, by setting
3076 inst_env->invalid to true. */
3079 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3081 inst_env
->invalid
= 1;
3084 /* Handles the XOR instruction. */
3087 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3089 /* XOR can't have a prefix. */
3090 if (inst_env
->prefix_found
)
3092 inst_env
->invalid
= 1;
3096 /* Check if the PC is the target. */
3097 if (cris_get_operand2 (inst
) == REG_PC
)
3099 /* It's invalid to change the PC in a delay slot. */
3100 if (inst_env
->slot_needed
)
3102 inst_env
->invalid
= 1;
3105 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3107 inst_env
->slot_needed
= 0;
3108 inst_env
->prefix_found
= 0;
3109 inst_env
->xflag_found
= 0;
3110 inst_env
->disable_interrupt
= 0;
3113 /* Handles the MULS instruction. */
3116 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3118 /* MULS/U can't have a prefix. */
3119 if (inst_env
->prefix_found
)
3121 inst_env
->invalid
= 1;
3125 /* Consider it invalid if the PC is the target. */
3126 if (cris_get_operand2 (inst
) == REG_PC
)
3128 inst_env
->invalid
= 1;
3131 inst_env
->slot_needed
= 0;
3132 inst_env
->prefix_found
= 0;
3133 inst_env
->xflag_found
= 0;
3134 inst_env
->disable_interrupt
= 0;
3137 /* Handles the MULU instruction. */
3140 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3142 /* MULS/U can't have a prefix. */
3143 if (inst_env
->prefix_found
)
3145 inst_env
->invalid
= 1;
3149 /* Consider it invalid if the PC is the target. */
3150 if (cris_get_operand2 (inst
) == REG_PC
)
3152 inst_env
->invalid
= 1;
3155 inst_env
->slot_needed
= 0;
3156 inst_env
->prefix_found
= 0;
3157 inst_env
->xflag_found
= 0;
3158 inst_env
->disable_interrupt
= 0;
3161 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3162 The MOVE instruction is the move from source to register. */
3165 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3166 unsigned long source1
, unsigned long source2
)
3168 unsigned long pc_mask
;
3169 unsigned long operation_mask
;
3171 /* Find out how many bits the operation should apply to. */
3172 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3174 pc_mask
= 0xFFFFFF00;
3175 operation_mask
= 0xFF;
3177 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3179 pc_mask
= 0xFFFF0000;
3180 operation_mask
= 0xFFFF;
3182 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3185 operation_mask
= 0xFFFFFFFF;
3189 /* The size is out of range. */
3190 inst_env
->invalid
= 1;
3194 /* The instruction just works on uw_operation_mask bits. */
3195 source2
&= operation_mask
;
3196 source1
&= operation_mask
;
3198 /* Now calculate the result. The opcode's 3 first bits separates
3199 the different actions. */
3200 switch (cris_get_opcode (inst
) & 7)
3210 case 2: /* subtract */
3214 case 3: /* compare */
3226 inst_env
->invalid
= 1;
3232 /* Make sure that the result doesn't contain more than the instruction
3234 source2
&= operation_mask
;
3236 /* Calculate the new breakpoint address. */
3237 inst_env
->reg
[REG_PC
] &= pc_mask
;
3238 inst_env
->reg
[REG_PC
] |= source1
;
3242 /* Extends the value from either byte or word size to a dword. If the mode
3243 is zero extend then the value is extended with zero. If instead the mode
3244 is signed extend the sign bit of the value is taken into consideration. */
3246 static unsigned long
3247 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3249 /* The size can be either byte or word, check which one it is.
3250 Don't check the highest bit, it's indicating if it's a zero
3252 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3257 /* Check if the instruction is signed extend. If so, check if value has
3259 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3261 value
|= SIGNED_WORD_EXTEND_MASK
;
3269 /* Check if the instruction is signed extend. If so, check if value has
3271 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3273 value
|= SIGNED_BYTE_EXTEND_MASK
;
3276 /* The size should now be dword. */
3277 cris_set_size_to_dword (inst
);
3281 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3282 instruction. The MOVE instruction is the move from source to register. */
3285 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3286 inst_env_type
*inst_env
)
3288 unsigned long operand1
;
3289 unsigned long operand2
;
3291 /* It's invalid to have a prefix to the instruction. This is a register
3292 mode instruction and can't have a prefix. */
3293 if (inst_env
->prefix_found
)
3295 inst_env
->invalid
= 1;
3298 /* Check if the instruction has PC as its target. */
3299 if (cris_get_operand2 (inst
) == REG_PC
)
3301 if (inst_env
->slot_needed
)
3303 inst_env
->invalid
= 1;
3306 /* The instruction has the PC as its target register. */
3307 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3308 operand2
= inst_env
->reg
[REG_PC
];
3310 /* Check if it's a extend, signed or zero instruction. */
3311 if (cris_get_opcode (inst
) < 4)
3313 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3315 /* Calculate the PC value after the instruction, i.e. where the
3316 breakpoint should be. The order of the udw_operands is vital. */
3317 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3319 inst_env
->slot_needed
= 0;
3320 inst_env
->prefix_found
= 0;
3321 inst_env
->xflag_found
= 0;
3322 inst_env
->disable_interrupt
= 0;
3325 /* Returns the data contained at address. The size of the data is derived from
3326 the size of the operation. If the instruction is a zero or signed
3327 extend instruction, the size field is changed in instruction. */
3329 static unsigned long
3330 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
3332 int size
= cris_get_size (*inst
);
3333 unsigned long value
;
3335 /* If it's an extend instruction we don't want the signed extend bit,
3336 because it influences the size. */
3337 if (cris_get_opcode (*inst
) < 4)
3339 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3341 /* Is there a need for checking the size? Size should contain the number of
3344 value
= read_memory_unsigned_integer (address
, size
);
3346 /* Check if it's an extend, signed or zero instruction. */
3347 if (cris_get_opcode (*inst
) < 4)
3349 value
= do_sign_or_zero_extend (value
, inst
);
3354 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3355 instructions. The MOVE instruction is the move from source to register. */
3358 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3359 inst_env_type
*inst_env
)
3361 unsigned long operand2
;
3362 unsigned long operand3
;
3364 check_assign (inst
, inst_env
);
3365 if (cris_get_operand2 (inst
) == REG_PC
)
3367 operand2
= inst_env
->reg
[REG_PC
];
3369 /* Get the value of the third operand. */
3370 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3372 /* Calculate the PC value after the instruction, i.e. where the
3373 breakpoint should be. The order of the udw_operands is vital. */
3374 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3376 inst_env
->slot_needed
= 0;
3377 inst_env
->prefix_found
= 0;
3378 inst_env
->xflag_found
= 0;
3379 inst_env
->disable_interrupt
= 0;
3382 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3383 OR instructions. Note that for this to work as expected, the calling
3384 function must have made sure that there is a prefix to this instruction. */
3387 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3388 inst_env_type
*inst_env
)
3390 unsigned long operand2
;
3391 unsigned long operand3
;
3393 if (cris_get_operand1 (inst
) == REG_PC
)
3395 /* The PC will be changed by the instruction. */
3396 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3398 /* Get the value of the third operand. */
3399 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3401 /* Calculate the PC value after the instruction, i.e. where the
3402 breakpoint should be. */
3403 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3405 inst_env
->slot_needed
= 0;
3406 inst_env
->prefix_found
= 0;
3407 inst_env
->xflag_found
= 0;
3408 inst_env
->disable_interrupt
= 0;
3411 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3412 instructions. The MOVE instruction is the move from source to register. */
3415 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3416 inst_env_type
*inst_env
)
3418 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3420 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3421 SUB, AND or OR something weird is going on (if everything works these
3422 instructions should end up in the three operand version). */
3423 inst_env
->invalid
= 1;
3428 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3430 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3432 inst_env
->slot_needed
= 0;
3433 inst_env
->prefix_found
= 0;
3434 inst_env
->xflag_found
= 0;
3435 inst_env
->disable_interrupt
= 0;
3438 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3439 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3440 source to register. */
3443 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3444 inst_env_type
*inst_env
)
3446 unsigned long operand1
;
3447 unsigned long operand2
;
3448 unsigned long operand3
;
3451 /* The instruction is either an indirect or autoincrement addressing mode.
3452 Check if the destination register is the PC. */
3453 if (cris_get_operand2 (inst
) == REG_PC
)
3455 /* Must be done here, get_data_from_address may change the size
3457 size
= cris_get_size (inst
);
3458 operand2
= inst_env
->reg
[REG_PC
];
3460 /* Get the value of the third operand, i.e. the indirect operand. */
3461 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3462 operand3
= get_data_from_address (&inst
, operand1
);
3464 /* Calculate the PC value after the instruction, i.e. where the
3465 breakpoint should be. The order of the udw_operands is vital. */
3466 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3468 /* If this is an autoincrement addressing mode, check if the increment
3470 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3472 /* Get the size field. */
3473 size
= cris_get_size (inst
);
3475 /* If it's an extend instruction we don't want the signed extend bit,
3476 because it influences the size. */
3477 if (cris_get_opcode (inst
) < 4)
3479 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3481 process_autoincrement (size
, inst
, inst_env
);
3483 inst_env
->slot_needed
= 0;
3484 inst_env
->prefix_found
= 0;
3485 inst_env
->xflag_found
= 0;
3486 inst_env
->disable_interrupt
= 0;
3489 /* Handles the two-operand addressing mode, all modes except register, for
3490 the ADD, SUB CMP, AND and OR instruction. */
3493 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3494 inst_env_type
*inst_env
)
3496 if (inst_env
->prefix_found
)
3498 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3500 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3502 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3504 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3508 /* The mode is invalid for a prefixed base instruction. */
3509 inst_env
->invalid
= 1;
3515 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3519 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3522 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3524 unsigned long operand1
;
3525 unsigned long operand2
;
3527 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3528 instruction and can't have a prefix. */
3529 if (inst_env
->prefix_found
)
3531 inst_env
->invalid
= 1;
3535 /* Check if the instruction has PC as its target. */
3536 if (cris_get_operand2 (inst
) == REG_PC
)
3538 if (inst_env
->slot_needed
)
3540 inst_env
->invalid
= 1;
3543 operand1
= cris_get_quick_value (inst
);
3544 operand2
= inst_env
->reg
[REG_PC
];
3546 /* The size should now be dword. */
3547 cris_set_size_to_dword (&inst
);
3549 /* Calculate the PC value after the instruction, i.e. where the
3550 breakpoint should be. */
3551 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3553 inst_env
->slot_needed
= 0;
3554 inst_env
->prefix_found
= 0;
3555 inst_env
->xflag_found
= 0;
3556 inst_env
->disable_interrupt
= 0;
3559 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3562 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3564 unsigned long operand1
;
3565 unsigned long operand2
;
3567 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3568 instruction and can't have a prefix. */
3569 if (inst_env
->prefix_found
)
3571 inst_env
->invalid
= 1;
3574 /* Check if the instruction has PC as its target. */
3575 if (cris_get_operand2 (inst
) == REG_PC
)
3577 if (inst_env
->slot_needed
)
3579 inst_env
->invalid
= 1;
3582 /* The instruction has the PC as its target register. */
3583 operand1
= cris_get_quick_value (inst
);
3584 operand2
= inst_env
->reg
[REG_PC
];
3586 /* The quick value is signed, so check if we must do a signed extend. */
3587 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3590 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3592 /* The size should now be dword. */
3593 cris_set_size_to_dword (&inst
);
3595 /* Calculate the PC value after the instruction, i.e. where the
3596 breakpoint should be. */
3597 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3599 inst_env
->slot_needed
= 0;
3600 inst_env
->prefix_found
= 0;
3601 inst_env
->xflag_found
= 0;
3602 inst_env
->disable_interrupt
= 0;
3605 /* Translate op_type to a function and call it. */
3608 cris_gdb_func (enum cris_op_type op_type
, unsigned short inst
,
3609 inst_env_type
*inst_env
)
3613 case cris_not_implemented_op
:
3614 not_implemented_op (inst
, inst_env
);
3618 abs_op (inst
, inst_env
);
3622 addi_op (inst
, inst_env
);
3626 asr_op (inst
, inst_env
);
3630 asrq_op (inst
, inst_env
);
3633 case cris_ax_ei_setf_op
:
3634 ax_ei_setf_op (inst
, inst_env
);
3637 case cris_bdap_prefix
:
3638 bdap_prefix (inst
, inst_env
);
3641 case cris_biap_prefix
:
3642 biap_prefix (inst
, inst_env
);
3646 break_op (inst
, inst_env
);
3649 case cris_btst_nop_op
:
3650 btst_nop_op (inst
, inst_env
);
3653 case cris_clearf_di_op
:
3654 clearf_di_op (inst
, inst_env
);
3657 case cris_dip_prefix
:
3658 dip_prefix (inst
, inst_env
);
3661 case cris_dstep_logshift_mstep_neg_not_op
:
3662 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3665 case cris_eight_bit_offset_branch_op
:
3666 eight_bit_offset_branch_op (inst
, inst_env
);
3669 case cris_move_mem_to_reg_movem_op
:
3670 move_mem_to_reg_movem_op (inst
, inst_env
);
3673 case cris_move_reg_to_mem_movem_op
:
3674 move_reg_to_mem_movem_op (inst
, inst_env
);
3677 case cris_move_to_preg_op
:
3678 move_to_preg_op (inst
, inst_env
);
3682 muls_op (inst
, inst_env
);
3686 mulu_op (inst
, inst_env
);
3689 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3690 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3693 case cris_none_reg_mode_clear_test_op
:
3694 none_reg_mode_clear_test_op (inst
, inst_env
);
3697 case cris_none_reg_mode_jump_op
:
3698 none_reg_mode_jump_op (inst
, inst_env
);
3701 case cris_none_reg_mode_move_from_preg_op
:
3702 none_reg_mode_move_from_preg_op (inst
, inst_env
);
3705 case cris_quick_mode_add_sub_op
:
3706 quick_mode_add_sub_op (inst
, inst_env
);
3709 case cris_quick_mode_and_cmp_move_or_op
:
3710 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3713 case cris_quick_mode_bdap_prefix
:
3714 quick_mode_bdap_prefix (inst
, inst_env
);
3717 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3718 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3721 case cris_reg_mode_clear_op
:
3722 reg_mode_clear_op (inst
, inst_env
);
3725 case cris_reg_mode_jump_op
:
3726 reg_mode_jump_op (inst
, inst_env
);
3729 case cris_reg_mode_move_from_preg_op
:
3730 reg_mode_move_from_preg_op (inst
, inst_env
);
3733 case cris_reg_mode_test_op
:
3734 reg_mode_test_op (inst
, inst_env
);
3738 scc_op (inst
, inst_env
);
3741 case cris_sixteen_bit_offset_branch_op
:
3742 sixteen_bit_offset_branch_op (inst
, inst_env
);
3745 case cris_three_operand_add_sub_cmp_and_or_op
:
3746 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3749 case cris_three_operand_bound_op
:
3750 three_operand_bound_op (inst
, inst_env
);
3753 case cris_two_operand_bound_op
:
3754 two_operand_bound_op (inst
, inst_env
);
3758 xor_op (inst
, inst_env
);
3763 /* This wrapper is to avoid cris_get_assembler being called before
3764 exec_bfd has been set. */
3767 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3769 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3770 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3771 disassembler, even when there is no BFD. Does something like
3772 "gdb; target remote; disassmeble *0x123" work? */
3773 gdb_assert (exec_bfd
!= NULL
);
3774 print_insn
= cris_get_disassembler (exec_bfd
);
3775 gdb_assert (print_insn
!= NULL
);
3776 return print_insn (addr
, info
);
3779 /* Copied from <asm/elf.h>. */
3780 typedef unsigned long elf_greg_t
;
3782 /* Same as user_regs_struct struct in <asm/user.h>. */
3783 #define CRISV10_ELF_NGREG 35
3784 typedef elf_greg_t elf_gregset_t
[CRISV10_ELF_NGREG
];
3786 #define CRISV32_ELF_NGREG 32
3787 typedef elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3789 /* Unpack an elf_gregset_t into GDB's register cache. */
3792 supply_gregset (elf_gregset_t
*gregsetp
)
3794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3796 elf_greg_t
*regp
= *gregsetp
;
3797 static char zerobuf
[4] = {0};
3799 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3800 knows about the actual size of each register so that's no problem. */
3801 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3803 regcache_raw_supply (current_regcache
, i
, (char *)®p
[i
]);
3806 if (tdep
->cris_version
== 32)
3808 /* Needed to set pseudo-register PC for CRISv32. */
3809 /* FIXME: If ERP is in a delay slot at this point then the PC will
3810 be wrong. Issue a warning to alert the user. */
3811 regcache_raw_supply (current_regcache
, PC_REGNUM
,
3812 (char *)®p
[ERP_REGNUM
]);
3814 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3815 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3819 /* Use a local version of this function to get the correct types for
3820 regsets, until multi-arch core support is ready. */
3823 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
3824 int which
, CORE_ADDR reg_addr
)
3826 elf_gregset_t gregset
;
3831 if (core_reg_size
!= sizeof (elf_gregset_t
)
3832 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3834 warning ("wrong size gregset struct in core file");
3838 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3839 supply_gregset (&gregset
);
3843 /* We've covered all the kinds of registers we know about here,
3844 so this must be something we wouldn't know what to do with
3845 anyway. Just ignore it. */
3850 static struct core_fns cris_elf_core_fns
=
3852 bfd_target_elf_flavour
, /* core_flavour */
3853 default_check_format
, /* check_format */
3854 default_core_sniffer
, /* core_sniffer */
3855 fetch_core_registers
, /* core_read_registers */
3859 /* Fetch (and possibly build) an appropriate link_map_offsets
3860 structure for native GNU/Linux CRIS targets using the struct
3861 offsets defined in link.h (but without actual reference to that
3864 This makes it possible to access GNU/Linux CRIS shared libraries
3865 from a GDB that was not built on an GNU/Linux CRIS host (for cross
3868 See gdb/solib-svr4.h for an explanation of these fields. */
3870 static struct link_map_offsets
*
3871 cris_linux_svr4_fetch_link_map_offsets (void)
3873 static struct link_map_offsets lmo
;
3874 static struct link_map_offsets
*lmp
= NULL
;
3880 lmo
.r_debug_size
= 8; /* The actual size is 20 bytes, but
3881 this is all we need. */
3882 lmo
.r_map_offset
= 4;
3885 lmo
.link_map_size
= 20;
3887 lmo
.l_addr_offset
= 0;
3888 lmo
.l_addr_size
= 4;
3890 lmo
.l_name_offset
= 4;
3891 lmo
.l_name_size
= 4;
3893 lmo
.l_next_offset
= 12;
3894 lmo
.l_next_size
= 4;
3896 lmo
.l_prev_offset
= 16;
3897 lmo
.l_prev_size
= 4;
3903 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3906 _initialize_cris_tdep (void)
3908 static struct cmd_list_element
*cris_set_cmdlist
;
3909 static struct cmd_list_element
*cris_show_cmdlist
;
3911 struct cmd_list_element
*c
;
3913 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3915 /* CRIS-specific user-commands. */
3916 add_setshow_uinteger_cmd ("cris-version", class_support
,
3917 &usr_cmd_cris_version
,
3918 "Set the current CRIS version.",
3919 "Show the current CRIS version.",
3920 "Set if autodetection fails.",
3921 "Current CRIS version is %s.",
3922 set_cris_version
, NULL
,
3923 &setlist
, &showlist
);
3925 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3926 &usr_cmd_cris_dwarf2_cfi
,
3927 "Set the usage of Dwarf-2 CFI for CRIS.",
3928 "Show the usage of Dwarf-2 CFI for CRIS.",
3929 "Set to \"off\" if using gcc-cris < R59.",
3930 "Usage of Dwarf-2 CFI for CRIS is %d.",
3931 set_cris_dwarf2_cfi
, NULL
,
3932 &setlist
, &showlist
);
3934 deprecated_add_core_fns (&cris_elf_core_fns
);
3937 /* Prints out all target specific values. */
3940 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3942 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3945 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3946 tdep
->cris_version
);
3947 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3948 tdep
->cris_dwarf2_cfi
);
3953 set_cris_version (char *ignore_args
, int from_tty
,
3954 struct cmd_list_element
*c
)
3956 struct gdbarch_info info
;
3958 usr_cmd_cris_version_valid
= 1;
3960 /* Update the current architecture, if needed. */
3961 gdbarch_info_init (&info
);
3962 if (!gdbarch_update_p (info
))
3963 internal_error (__FILE__
, __LINE__
,
3964 "cris_gdbarch_update: failed to update architecture.");
3968 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
3969 struct cmd_list_element
*c
)
3971 struct gdbarch_info info
;
3973 /* Update the current architecture, if needed. */
3974 gdbarch_info_init (&info
);
3975 if (!gdbarch_update_p (info
))
3976 internal_error (__FILE__
, __LINE__
,
3977 "cris_gdbarch_update: failed to update architecture.");
3980 static struct gdbarch
*
3981 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3983 struct gdbarch
*gdbarch
;
3984 struct gdbarch_tdep
*tdep
;
3987 if (usr_cmd_cris_version_valid
)
3989 /* Trust the user's CRIS version setting. */
3990 cris_version
= usr_cmd_cris_version
;
3992 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
3998 /* Assume it's CRIS version 10. */
4002 /* Make the current settings visible to the user. */
4003 usr_cmd_cris_version
= cris_version
;
4005 /* Find a candidate among the list of pre-declared architectures. Both
4006 CRIS version and ABI must match. */
4007 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4009 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4011 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4012 == usr_cmd_cris_version
)
4013 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4014 == usr_cmd_cris_dwarf2_cfi
))
4015 return arches
->gdbarch
;
4018 /* No matching architecture was found. Create a new one. */
4019 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4020 gdbarch
= gdbarch_alloc (&info
, tdep
);
4022 tdep
->cris_version
= usr_cmd_cris_version
;
4023 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4025 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4026 switch (info
.byte_order
)
4028 case BFD_ENDIAN_LITTLE
:
4032 case BFD_ENDIAN_BIG
:
4033 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: big endian byte order in info");
4037 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: unknown byte order in info");
4040 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4041 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch
,
4042 cris_reg_struct_has_addr
);
4043 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
4045 set_gdbarch_sp_regnum (gdbarch
, 14);
4047 /* Length of ordinary registers used in push_word and a few other
4048 places. register_size() is the real way to know how big a
4051 set_gdbarch_double_bit (gdbarch
, 64);
4052 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
4053 which means we have to set this explicitly. */
4054 set_gdbarch_long_double_bit (gdbarch
, 64);
4056 /* The total amount of space needed to store (in an array called registers)
4057 GDB's copy of the machine's register state. Note: We can not use
4058 cris_register_size at this point, since it relies on current_gdbarch
4060 switch (tdep
->cris_version
)
4068 /* Old versions; not supported. */
4069 internal_error (__FILE__
, __LINE__
,
4070 "cris_gdbarch_init: unsupported CRIS version");
4075 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4076 P7 (32 bits), and P15 (32 bits) have been implemented. */
4077 set_gdbarch_pc_regnum (gdbarch
, 15);
4078 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4079 /* There are 32 registers (some of which may not be implemented). */
4080 set_gdbarch_num_regs (gdbarch
, 32);
4081 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4082 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4083 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4085 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4089 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4090 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4091 and pseudo-register PC (32 bits). */
4092 set_gdbarch_pc_regnum (gdbarch
, 32);
4093 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4094 /* 32 registers + pseudo-register PC + 16 support registers. */
4095 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4096 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4098 set_gdbarch_cannot_store_register
4099 (gdbarch
, crisv32_cannot_store_register
);
4100 set_gdbarch_cannot_fetch_register
4101 (gdbarch
, crisv32_cannot_fetch_register
);
4103 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4105 set_gdbarch_single_step_through_delay
4106 (gdbarch
, crisv32_single_step_through_delay
);
4111 internal_error (__FILE__
, __LINE__
,
4112 "cris_gdbarch_init: unknown CRIS version");
4115 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4116 have the same ABI). */
4117 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4118 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4119 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4120 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4122 /* The stack grows downward. */
4123 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4125 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4127 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4128 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4129 set_gdbarch_unwind_dummy_id (gdbarch
, cris_unwind_dummy_id
);
4131 if (tdep
->cris_dwarf2_cfi
== 1)
4133 /* Hook in the Dwarf-2 frame sniffer. */
4134 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4135 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4136 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
4139 frame_unwind_append_sniffer (gdbarch
, cris_sigtramp_frame_sniffer
);
4141 frame_unwind_append_sniffer (gdbarch
, cris_frame_sniffer
);
4142 frame_base_set_default (gdbarch
, &cris_frame_base
);
4144 /* Use target_specific function to define link map offsets. */
4145 set_solib_svr4_fetch_link_map_offsets
4146 (gdbarch
, cris_linux_svr4_fetch_link_map_offsets
);
4148 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4149 disassembler, even when there is no BFD. Does something like
4150 "gdb; target remote; disassmeble *0x123" work? */
4151 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);