gdb/gdbserver/linux-crisv32-low.c

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2015 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include <sys/ptrace.h>
  22
  23 /* Defined in auto-generated file reg-crisv32.c.  */
  24 void init_registers_crisv32 (void);
  25 extern const struct target_desc *tdesc_crisv32;
  26
  27 /* CRISv32 */
  28 #define cris_num_regs 49
  29
  30 #ifndef PTRACE_GET_THREAD_AREA
  31 #define PTRACE_GET_THREAD_AREA 25
  32 #endif
  33
  34 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
  35    without any significant gain).  */
  36
  37 /* Locations need to match <include/asm/arch/ptrace.h>.  */
  38 static int cris_regmap[] = {
  39   1*4, 2*4, 3*4, 4*4,
  40   5*4, 6*4, 7*4, 8*4,
  41   9*4, 10*4, 11*4, 12*4,
  42   13*4, 14*4, 24*4, 15*4,
  43
  44   -1, -1, -1, 16*4,
  45   -1, 22*4, 23*4, 17*4,
  46   -1, -1, 21*4, 20*4,
  47   -1, 19*4, -1, 18*4,
  48
  49   25*4,
  50
  51   26*4, -1,   -1,   29*4,
  52   30*4, 31*4, 32*4, 33*4,
  53   34*4, 35*4, 36*4, 37*4,
  54   38*4, 39*4, 40*4, -1
  55
  56 };
  57
  58 extern int debug_threads;
  59
  60 static CORE_ADDR
  61 cris_get_pc (struct regcache *regcache)
  62 {
  63   unsigned long pc;
  64   collect_register_by_name (regcache, "pc", &pc);
  65   if (debug_threads)
  66     debug_printf ("stop pc is %08lx\n", pc);
  67   return pc;
  68 }
  69
  70 static void
  71 cris_set_pc (struct regcache *regcache, CORE_ADDR pc)
  72 {
  73   unsigned long newpc = pc;
  74   supply_register_by_name (regcache, "pc", &newpc);
  75 }
  76
  77 static const unsigned short cris_breakpoint = 0xe938;
  78 #define cris_breakpoint_len 2
  79
  80 static int
  81 cris_breakpoint_at (CORE_ADDR where)
  82 {
  83   unsigned short insn;
  84
  85   (*the_target->read_memory) (where, (unsigned char *) &insn,
  86                               cris_breakpoint_len);
  87   if (insn == cris_breakpoint)
  88     return 1;
  89
  90   /* If necessary, recognize more trap instructions here.  GDB only uses the
  91      one.  */
  92   return 0;
  93 }
  94
  95 /* We only place breakpoints in empty marker functions, and thread locking
  96    is outside of the function.  So rather than importing software single-step,
  97    we can just run until exit.  */
  98
  99 /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
 100    for CRISv32.  Without it, td_ta_event_getmsg in thread_db_create_event
 101    will fail when debugging multi-threaded applications.  */
 102
 103 static CORE_ADDR
 104 cris_reinsert_addr (void)
 105 {
 106   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 107   unsigned long pc;
 108   collect_register_by_name (regcache, "srp", &pc);
 109   return pc;
 110 }
 111
 112 static void
 113 cris_write_data_breakpoint (struct regcache *regcache,
 114                             int bp, unsigned long start, unsigned long end)
 115 {
 116   switch (bp)
 117     {
 118     case 0:
 119       supply_register_by_name (regcache, "s3", &start);
 120       supply_register_by_name (regcache, "s4", &end);
 121       break;
 122     case 1:
 123       supply_register_by_name (regcache, "s5", &start);
 124       supply_register_by_name (regcache, "s6", &end);
 125       break;
 126     case 2:
 127       supply_register_by_name (regcache, "s7", &start);
 128       supply_register_by_name (regcache, "s8", &end);
 129       break;
 130     case 3:
 131       supply_register_by_name (regcache, "s9", &start);
 132       supply_register_by_name (regcache, "s10", &end);
 133       break;
 134     case 4:
 135       supply_register_by_name (regcache, "s11", &start);
 136       supply_register_by_name (regcache, "s12", &end);
 137       break;
 138     case 5:
 139       supply_register_by_name (regcache, "s13", &start);
 140       supply_register_by_name (regcache, "s14", &end);
 141       break;
 142     }
 143 }
 144
 145 static int
 146 cris_supports_z_point_type (char z_type)
 147 {
 148   switch (z_type)
 149     {
 150     case Z_PACKET_WRITE_WP:
 151     case Z_PACKET_READ_WP:
 152     case Z_PACKET_ACCESS_WP:
 153       return 1;
 154     default:
 155       return 0;
 156     }
 157 }
 158
 159 static int
 160 cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 161                    int len, struct raw_breakpoint *bp)
 162 {
 163   int bp;
 164   unsigned long bp_ctrl;
 165   unsigned long start, end;
 166   unsigned long ccs;
 167   struct regcache *regcache;
 168
 169   regcache = get_thread_regcache (current_thread, 1);
 170
 171   /* Read watchpoints are set as access watchpoints, because of GDB's
 172      inability to deal with pure read watchpoints.  */
 173   if (type == raw_bkpt_type_read_wp)
 174     type = raw_bkpt_type_access_wp;
 175
 176   /* Get the configuration register.  */
 177   collect_register_by_name (regcache, "s0", &bp_ctrl);
 178
 179   /* The watchpoint allocation scheme is the simplest possible.
 180      For example, if a region is watched for read and
 181      a write watch is requested, a new watchpoint will
 182      be used.  Also, if a watch for a region that is already
 183      covered by one or more existing watchpoints, a new
 184      watchpoint will be used.  */
 185
 186   /* First, find a free data watchpoint.  */
 187   for (bp = 0; bp < 6; bp++)
 188     {
 189       /* Each data watchpoint's control registers occupy 2 bits
 190          (hence the 3), starting at bit 2 for D0 (hence the 2)
 191          with 4 bits between for each watchpoint (yes, the 4).  */
 192       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 193         break;
 194     }
 195
 196   if (bp > 5)
 197     {
 198       /* We're out of watchpoints.  */
 199       return -1;
 200     }
 201
 202   /* Configure the control register first.  */
 203   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 204     {
 205       /* Trigger on read.  */
 206       bp_ctrl |= (1 << (2 + bp * 4));
 207     }
 208   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 209     {
 210       /* Trigger on write.  */
 211       bp_ctrl |= (2 << (2 + bp * 4));
 212     }
 213
 214   /* Setup the configuration register.  */
 215   supply_register_by_name (regcache, "s0", &bp_ctrl);
 216
 217   /* Setup the range.  */
 218   start = addr;
 219   end = addr + len - 1;
 220
 221   /* Configure the watchpoint register.  */
 222   cris_write_data_breakpoint (regcache, bp, start, end);
 223
 224   collect_register_by_name (regcache, "ccs", &ccs);
 225   /* Set the S1 flag to enable watchpoints.  */
 226   ccs |= (1 << 19);
 227   supply_register_by_name (regcache, "ccs", &ccs);
 228
 229   return 0;
 230 }
 231
 232 static int
 233 cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len,
 234                    struct raw_breakpoint *bp)
 235 {
 236   int bp;
 237   unsigned long bp_ctrl;
 238   unsigned long start, end;
 239   struct regcache *regcache;
 240   unsigned long bp_d_regs[12];
 241
 242   regcache = get_thread_regcache (current_thread, 1);
 243
 244   /* Read watchpoints are set as access watchpoints, because of GDB's
 245      inability to deal with pure read watchpoints.  */
 246   if (type == raw_bkpt_type_read_wp)
 247     type = raw_bkpt_type_access_wp;
 248
 249   /* Get the configuration register.  */
 250   collect_register_by_name (regcache, "s0", &bp_ctrl);
 251
 252   /* Try to find a watchpoint that is configured for the
 253      specified range, then check that read/write also matches.  */
 254
 255   /* Ugly pointer arithmetic, since I cannot rely on a
 256      single switch (addr) as there may be several watchpoints with
 257      the same start address for example.  */
 258
 259   /* Get all range registers to simplify search.  */
 260   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 261   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 262   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 263   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 264   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 265   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 266   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 267   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 268   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 269   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 270   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 271   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 272
 273   for (bp = 0; bp < 6; bp++)
 274     {
 275       if (bp_d_regs[bp * 2] == addr
 276           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 277         /* Matching range.  */
 278         int bitpos = 2 + bp * 4;
 279         int rw_bits;
 280
 281         /* Read/write bits for this BP.  */
 282         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 283
 284         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 285             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 286             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 287           {
 288             /* Read/write matched.  */
 289             break;
 290           }
 291       }
 292     }
 293
 294   if (bp > 5)
 295     {
 296       /* No watchpoint matched.  */
 297       return -1;
 298     }
 299
 300   /* Found a matching watchpoint.  Now, deconfigure it by
 301      both disabling read/write in bp_ctrl and zeroing its
 302      start/end addresses.  */
 303   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 304   /* Setup the configuration register.  */
 305   supply_register_by_name (regcache, "s0", &bp_ctrl);
 306
 307   start = end = 0;
 308   /* Configure the watchpoint register.  */
 309   cris_write_data_breakpoint (regcache, bp, start, end);
 310
 311   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 312   return 0;
 313 }
 314
 315 static int
 316 cris_stopped_by_watchpoint (void)
 317 {
 318   unsigned long exs;
 319   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 320
 321   collect_register_by_name (regcache, "exs", &exs);
 322
 323   return (((exs & 0xff00) >> 8) == 0xc);
 324 }
 325
 326 static CORE_ADDR
 327 cris_stopped_data_address (void)
 328 {
 329   unsigned long eda;
 330   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 331
 332   collect_register_by_name (regcache, "eda", &eda);
 333
 334   /* FIXME: Possibly adjust to match watched range.  */
 335   return eda;
 336 }
 337
 338 ps_err_e
 339 ps_get_thread_area (const struct ps_prochandle *ph,
 340                     lwpid_t lwpid, int idx, void **base)
 341 {
 342   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 343     return PS_ERR;
 344
 345   /* IDX is the bias from the thread pointer to the beginning of the
 346      thread descriptor.  It has to be subtracted due to implementation
 347      quirks in libthread_db.  */
 348   *base = (void *) ((char *) *base - idx);
 349   return PS_OK;
 350 }
 351
 352 static void
 353 cris_fill_gregset (struct regcache *regcache, void *buf)
 354 {
 355   int i;
 356
 357   for (i = 0; i < cris_num_regs; i++)
 358     {
 359       if (cris_regmap[i] != -1)
 360         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 361     }
 362 }
 363
 364 static void
 365 cris_store_gregset (struct regcache *regcache, const void *buf)
 366 {
 367   int i;
 368
 369   for (i = 0; i < cris_num_regs; i++)
 370     {
 371       if (cris_regmap[i] != -1)
 372         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 373     }
 374 }
 375
 376 static void
 377 cris_arch_setup (void)
 378 {
 379   current_process ()->tdesc = tdesc_crisv32;
 380 }
 381
 382 static struct regset_info cris_regsets[] = {
 383   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 384     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 385   { 0, 0, 0, -1, -1, NULL, NULL }
 386 };
 387
 388
 389 static struct regsets_info cris_regsets_info =
 390   {
 391     cris_regsets, /* regsets */
 392     0, /* num_regsets */
 393     NULL, /* disabled_regsets */
 394   };
 395
 396 static struct usrregs_info cris_usrregs_info =
 397   {
 398     cris_num_regs,
 399     cris_regmap,
 400   };
 401
 402 static struct regs_info regs_info =
 403   {
 404     NULL, /* regset_bitmap */
 405     &cris_usrregs_info,
 406     &cris_regsets_info
 407   };
 408
 409 static const struct regs_info *
 410 cris_regs_info (void)
 411 {
 412   return &regs_info;
 413 }
 414
 415 struct linux_target_ops the_low_target = {
 416   cris_arch_setup,
 417   cris_regs_info,
 418   NULL,
 419   NULL,
 420   NULL, /* fetch_register */
 421   cris_get_pc,
 422   cris_set_pc,
 423   (const unsigned char *) &cris_breakpoint,
 424   cris_breakpoint_len,
 425   cris_reinsert_addr,
 426   0,
 427   cris_breakpoint_at,
 428   cris_supports_z_point_type,
 429   cris_insert_point,
 430   cris_remove_point,
 431   cris_stopped_by_watchpoint,
 432   cris_stopped_data_address,
 433 };
 434
 435 void
 436 initialize_low_arch (void)
 437 {
 438   init_registers_crisv32 ();
 439
 440   initialize_regsets_info (&cris_regsets_info);
 441 }