gdb/gdbserver/linux-ppc-low.c

   1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
   2    GDB.
   3    Copyright (C) 1995-2015 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "server.h"
  21 #include "linux-low.h"
  22
  23 #include <elf.h>
  24 #include <asm/ptrace.h>
  25
  26 #include "nat/ppc-linux.h"
  27
  28 static unsigned long ppc_hwcap;
  29
  30
  31 /* Defined in auto-generated file powerpc-32l.c.  */
  32 void init_registers_powerpc_32l (void);
  33 extern const struct target_desc *tdesc_powerpc_32l;
  34
  35 /* Defined in auto-generated file powerpc-altivec32l.c.  */
  36 void init_registers_powerpc_altivec32l (void);
  37 extern const struct target_desc *tdesc_powerpc_altivec32l;
  38
  39 /* Defined in auto-generated file powerpc-cell32l.c.  */
  40 void init_registers_powerpc_cell32l (void);
  41 extern const struct target_desc *tdesc_powerpc_cell32l;
  42
  43 /* Defined in auto-generated file powerpc-vsx32l.c.  */
  44 void init_registers_powerpc_vsx32l (void);
  45 extern const struct target_desc *tdesc_powerpc_vsx32l;
  46
  47 /* Defined in auto-generated file powerpc-isa205-32l.c.  */
  48 void init_registers_powerpc_isa205_32l (void);
  49 extern const struct target_desc *tdesc_powerpc_isa205_32l;
  50
  51 /* Defined in auto-generated file powerpc-isa205-altivec32l.c.  */
  52 void init_registers_powerpc_isa205_altivec32l (void);
  53 extern const struct target_desc *tdesc_powerpc_isa205_altivec32l;
  54
  55 /* Defined in auto-generated file powerpc-isa205-vsx32l.c.  */
  56 void init_registers_powerpc_isa205_vsx32l (void);
  57 extern const struct target_desc *tdesc_powerpc_isa205_vsx32l;
  58
  59 /* Defined in auto-generated file powerpc-e500l.c.  */
  60 void init_registers_powerpc_e500l (void);
  61 extern const struct target_desc *tdesc_powerpc_e500l;
  62
  63 /* Defined in auto-generated file powerpc-64l.c.  */
  64 void init_registers_powerpc_64l (void);
  65 extern const struct target_desc *tdesc_powerpc_64l;
  66
  67 /* Defined in auto-generated file powerpc-altivec64l.c.  */
  68 void init_registers_powerpc_altivec64l (void);
  69 extern const struct target_desc *tdesc_powerpc_altivec64l;
  70
  71 /* Defined in auto-generated file powerpc-cell64l.c.  */
  72 void init_registers_powerpc_cell64l (void);
  73 extern const struct target_desc *tdesc_powerpc_cell64l;
  74
  75 /* Defined in auto-generated file powerpc-vsx64l.c.  */
  76 void init_registers_powerpc_vsx64l (void);
  77 extern const struct target_desc *tdesc_powerpc_vsx64l;
  78
  79 /* Defined in auto-generated file powerpc-isa205-64l.c.  */
  80 void init_registers_powerpc_isa205_64l (void);
  81 extern const struct target_desc *tdesc_powerpc_isa205_64l;
  82
  83 /* Defined in auto-generated file powerpc-isa205-altivec64l.c.  */
  84 void init_registers_powerpc_isa205_altivec64l (void);
  85 extern const struct target_desc *tdesc_powerpc_isa205_altivec64l;
  86
  87 /* Defined in auto-generated file powerpc-isa205-vsx64l.c.  */
  88 void init_registers_powerpc_isa205_vsx64l (void);
  89 extern const struct target_desc *tdesc_powerpc_isa205_vsx64l;
  90
  91 #define ppc_num_regs 73
  92
  93 #ifdef __powerpc64__
  94 /* We use a constant for FPSCR instead of PT_FPSCR, because
  95    many shipped PPC64 kernels had the wrong value in ptrace.h.  */
  96 static int ppc_regmap[] =
  97  {PT_R0 * 8,     PT_R1 * 8,     PT_R2 * 8,     PT_R3 * 8,
  98   PT_R4 * 8,     PT_R5 * 8,     PT_R6 * 8,     PT_R7 * 8,
  99   PT_R8 * 8,     PT_R9 * 8,     PT_R10 * 8,    PT_R11 * 8,
 100   PT_R12 * 8,    PT_R13 * 8,    PT_R14 * 8,    PT_R15 * 8,
 101   PT_R16 * 8,    PT_R17 * 8,    PT_R18 * 8,    PT_R19 * 8,
 102   PT_R20 * 8,    PT_R21 * 8,    PT_R22 * 8,    PT_R23 * 8,
 103   PT_R24 * 8,    PT_R25 * 8,    PT_R26 * 8,    PT_R27 * 8,
 104   PT_R28 * 8,    PT_R29 * 8,    PT_R30 * 8,    PT_R31 * 8,
 105   PT_FPR0*8,     PT_FPR0*8 + 8, PT_FPR0*8+16,  PT_FPR0*8+24,
 106   PT_FPR0*8+32,  PT_FPR0*8+40,  PT_FPR0*8+48,  PT_FPR0*8+56,
 107   PT_FPR0*8+64,  PT_FPR0*8+72,  PT_FPR0*8+80,  PT_FPR0*8+88,
 108   PT_FPR0*8+96,  PT_FPR0*8+104,  PT_FPR0*8+112,  PT_FPR0*8+120,
 109   PT_FPR0*8+128, PT_FPR0*8+136,  PT_FPR0*8+144,  PT_FPR0*8+152,
 110   PT_FPR0*8+160,  PT_FPR0*8+168,  PT_FPR0*8+176,  PT_FPR0*8+184,
 111   PT_FPR0*8+192,  PT_FPR0*8+200,  PT_FPR0*8+208,  PT_FPR0*8+216,
 112   PT_FPR0*8+224,  PT_FPR0*8+232,  PT_FPR0*8+240,  PT_FPR0*8+248,
 113   PT_NIP * 8,    PT_MSR * 8,    PT_CCR * 8,    PT_LNK * 8,
 114   PT_CTR * 8,    PT_XER * 8,    PT_FPR0*8 + 256,
 115   PT_ORIG_R3 * 8, PT_TRAP * 8 };
 116 #else
 117 /* Currently, don't check/send MQ.  */
 118 static int ppc_regmap[] =
 119  {PT_R0 * 4,     PT_R1 * 4,     PT_R2 * 4,     PT_R3 * 4,
 120   PT_R4 * 4,     PT_R5 * 4,     PT_R6 * 4,     PT_R7 * 4,
 121   PT_R8 * 4,     PT_R9 * 4,     PT_R10 * 4,    PT_R11 * 4,
 122   PT_R12 * 4,    PT_R13 * 4,    PT_R14 * 4,    PT_R15 * 4,
 123   PT_R16 * 4,    PT_R17 * 4,    PT_R18 * 4,    PT_R19 * 4,
 124   PT_R20 * 4,    PT_R21 * 4,    PT_R22 * 4,    PT_R23 * 4,
 125   PT_R24 * 4,    PT_R25 * 4,    PT_R26 * 4,    PT_R27 * 4,
 126   PT_R28 * 4,    PT_R29 * 4,    PT_R30 * 4,    PT_R31 * 4,
 127   PT_FPR0*4,     PT_FPR0*4 + 8, PT_FPR0*4+16,  PT_FPR0*4+24,
 128   PT_FPR0*4+32,  PT_FPR0*4+40,  PT_FPR0*4+48,  PT_FPR0*4+56,
 129   PT_FPR0*4+64,  PT_FPR0*4+72,  PT_FPR0*4+80,  PT_FPR0*4+88,
 130   PT_FPR0*4+96,  PT_FPR0*4+104,  PT_FPR0*4+112,  PT_FPR0*4+120,
 131   PT_FPR0*4+128, PT_FPR0*4+136,  PT_FPR0*4+144,  PT_FPR0*4+152,
 132   PT_FPR0*4+160,  PT_FPR0*4+168,  PT_FPR0*4+176,  PT_FPR0*4+184,
 133   PT_FPR0*4+192,  PT_FPR0*4+200,  PT_FPR0*4+208,  PT_FPR0*4+216,
 134   PT_FPR0*4+224,  PT_FPR0*4+232,  PT_FPR0*4+240,  PT_FPR0*4+248,
 135   PT_NIP * 4,    PT_MSR * 4,    PT_CCR * 4,    PT_LNK * 4,
 136   PT_CTR * 4,    PT_XER * 4,    PT_FPSCR * 4,
 137   PT_ORIG_R3 * 4, PT_TRAP * 4
 138  };
 139
 140 static int ppc_regmap_e500[] =
 141  {PT_R0 * 4,     PT_R1 * 4,     PT_R2 * 4,     PT_R3 * 4,
 142   PT_R4 * 4,     PT_R5 * 4,     PT_R6 * 4,     PT_R7 * 4,
 143   PT_R8 * 4,     PT_R9 * 4,     PT_R10 * 4,    PT_R11 * 4,
 144   PT_R12 * 4,    PT_R13 * 4,    PT_R14 * 4,    PT_R15 * 4,
 145   PT_R16 * 4,    PT_R17 * 4,    PT_R18 * 4,    PT_R19 * 4,
 146   PT_R20 * 4,    PT_R21 * 4,    PT_R22 * 4,    PT_R23 * 4,
 147   PT_R24 * 4,    PT_R25 * 4,    PT_R26 * 4,    PT_R27 * 4,
 148   PT_R28 * 4,    PT_R29 * 4,    PT_R30 * 4,    PT_R31 * 4,
 149   -1,            -1,            -1,            -1,
 150   -1,            -1,            -1,            -1,
 151   -1,            -1,            -1,            -1,
 152   -1,            -1,            -1,            -1,
 153   -1,            -1,            -1,            -1,
 154   -1,            -1,            -1,            -1,
 155   -1,            -1,            -1,            -1,
 156   -1,            -1,            -1,            -1,
 157   PT_NIP * 4,    PT_MSR * 4,    PT_CCR * 4,    PT_LNK * 4,
 158   PT_CTR * 4,    PT_XER * 4,    -1,
 159   PT_ORIG_R3 * 4, PT_TRAP * 4
 160  };
 161 #endif
 162
 163 static int
 164 ppc_cannot_store_register (int regno)
 165 {
 166   const struct target_desc *tdesc = current_process ()->tdesc;
 167
 168 #ifndef __powerpc64__
 169   /* Some kernels do not allow us to store fpscr.  */
 170   if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
 171       && regno == find_regno (tdesc, "fpscr"))
 172     return 2;
 173 #endif
 174
 175   /* Some kernels do not allow us to store orig_r3 or trap.  */
 176   if (regno == find_regno (tdesc, "orig_r3")
 177       || regno == find_regno (tdesc, "trap"))
 178     return 2;
 179
 180   return 0;
 181 }
 182
 183 static int
 184 ppc_cannot_fetch_register (int regno)
 185 {
 186   return 0;
 187 }
 188
 189 static void
 190 ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
 191 {
 192   memset (buf, 0, sizeof (long));
 193
 194   if (__BYTE_ORDER == __LITTLE_ENDIAN)
 195     {
 196       /* Little-endian values always sit at the left end of the buffer.  */
 197       collect_register (regcache, regno, buf);
 198     }
 199   else if (__BYTE_ORDER == __BIG_ENDIAN)
 200     {
 201       /* Big-endian values sit at the right end of the buffer.  In case of
 202          registers whose sizes are smaller than sizeof (long), we must use a
 203          padding to access them correctly.  */
 204       int size = register_size (regcache->tdesc, regno);
 205
 206       if (size < sizeof (long))
 207         collect_register (regcache, regno, buf + sizeof (long) - size);
 208       else
 209         collect_register (regcache, regno, buf);
 210     }
 211   else
 212     perror_with_name ("Unexpected byte order");
 213 }
 214
 215 static void
 216 ppc_supply_ptrace_register (struct regcache *regcache,
 217                             int regno, const char *buf)
 218 {
 219   if (__BYTE_ORDER == __LITTLE_ENDIAN)
 220     {
 221       /* Little-endian values always sit at the left end of the buffer.  */
 222       supply_register (regcache, regno, buf);
 223     }
 224   else if (__BYTE_ORDER == __BIG_ENDIAN)
 225     {
 226       /* Big-endian values sit at the right end of the buffer.  In case of
 227          registers whose sizes are smaller than sizeof (long), we must use a
 228          padding to access them correctly.  */
 229       int size = register_size (regcache->tdesc, regno);
 230
 231       if (size < sizeof (long))
 232         supply_register (regcache, regno, buf + sizeof (long) - size);
 233       else
 234         supply_register (regcache, regno, buf);
 235     }
 236   else
 237     perror_with_name ("Unexpected byte order");
 238 }
 239
 240
 241 #define INSTR_SC        0x44000002
 242 #define NR_spu_run      0x0116
 243
 244 /* If the PPU thread is currently stopped on a spu_run system call,
 245    return to FD and ADDR the file handle and NPC parameter address
 246    used with the system call.  Return non-zero if successful.  */
 247 static int
 248 parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
 249 {
 250   CORE_ADDR curr_pc;
 251   int curr_insn;
 252   int curr_r0;
 253
 254   if (register_size (regcache->tdesc, 0) == 4)
 255     {
 256       unsigned int pc, r0, r3, r4;
 257       collect_register_by_name (regcache, "pc", &pc);
 258       collect_register_by_name (regcache, "r0", &r0);
 259       collect_register_by_name (regcache, "orig_r3", &r3);
 260       collect_register_by_name (regcache, "r4", &r4);
 261       curr_pc = (CORE_ADDR) pc;
 262       curr_r0 = (int) r0;
 263       *fd = (int) r3;
 264       *addr = (CORE_ADDR) r4;
 265     }
 266   else
 267     {
 268       unsigned long pc, r0, r3, r4;
 269       collect_register_by_name (regcache, "pc", &pc);
 270       collect_register_by_name (regcache, "r0", &r0);
 271       collect_register_by_name (regcache, "orig_r3", &r3);
 272       collect_register_by_name (regcache, "r4", &r4);
 273       curr_pc = (CORE_ADDR) pc;
 274       curr_r0 = (int) r0;
 275       *fd = (int) r3;
 276       *addr = (CORE_ADDR) r4;
 277     }
 278
 279   /* Fetch instruction preceding current NIP.  */
 280   if ((*the_target->read_memory) (curr_pc - 4,
 281                                   (unsigned char *) &curr_insn, 4) != 0)
 282     return 0;
 283   /* It should be a "sc" instruction.  */
 284   if (curr_insn != INSTR_SC)
 285     return 0;
 286   /* System call number should be NR_spu_run.  */
 287   if (curr_r0 != NR_spu_run)
 288     return 0;
 289
 290   return 1;
 291 }
 292
 293 static CORE_ADDR
 294 ppc_get_pc (struct regcache *regcache)
 295 {
 296   CORE_ADDR addr;
 297   int fd;
 298
 299   if (parse_spufs_run (regcache, &fd, &addr))
 300     {
 301       unsigned int pc;
 302       (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
 303       return ((CORE_ADDR)1 << 63)
 304         | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
 305     }
 306   else if (register_size (regcache->tdesc, 0) == 4)
 307     {
 308       unsigned int pc;
 309       collect_register_by_name (regcache, "pc", &pc);
 310       return (CORE_ADDR) pc;
 311     }
 312   else
 313     {
 314       unsigned long pc;
 315       collect_register_by_name (regcache, "pc", &pc);
 316       return (CORE_ADDR) pc;
 317     }
 318 }
 319
 320 static void
 321 ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
 322 {
 323   CORE_ADDR addr;
 324   int fd;
 325
 326   if (parse_spufs_run (regcache, &fd, &addr))
 327     {
 328       unsigned int newpc = pc;
 329       (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
 330     }
 331   else if (register_size (regcache->tdesc, 0) == 4)
 332     {
 333       unsigned int newpc = pc;
 334       supply_register_by_name (regcache, "pc", &newpc);
 335     }
 336   else
 337     {
 338       unsigned long newpc = pc;
 339       supply_register_by_name (regcache, "pc", &newpc);
 340     }
 341 }
 342
 343
 344 static int
 345 ppc_get_hwcap (unsigned long *valp)
 346 {
 347   const struct target_desc *tdesc = current_process ()->tdesc;
 348   int wordsize = register_size (tdesc, 0);
 349   unsigned char *data = alloca (2 * wordsize);
 350   int offset = 0;
 351
 352   while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
 353     {
 354       if (wordsize == 4)
 355         {
 356           unsigned int *data_p = (unsigned int *)data;
 357           if (data_p[0] == AT_HWCAP)
 358             {
 359               *valp = data_p[1];
 360               return 1;
 361             }
 362         }
 363       else
 364         {
 365           unsigned long *data_p = (unsigned long *)data;
 366           if (data_p[0] == AT_HWCAP)
 367             {
 368               *valp = data_p[1];
 369               return 1;
 370             }
 371         }
 372
 373       offset += 2 * wordsize;
 374     }
 375
 376   *valp = 0;
 377   return 0;
 378 }
 379
 380 /* Forward declaration.  */
 381 static struct usrregs_info ppc_usrregs_info;
 382 #ifndef __powerpc64__
 383 static int ppc_regmap_adjusted;
 384 #endif
 385
 386 static void
 387 ppc_arch_setup (void)
 388 {
 389   const struct target_desc *tdesc;
 390 #ifdef __powerpc64__
 391   long msr;
 392   struct regcache *regcache;
 393
 394   /* On a 64-bit host, assume 64-bit inferior process with no
 395      AltiVec registers.  Reset ppc_hwcap to ensure that the
 396      collect_register call below does not fail.  */
 397   tdesc = tdesc_powerpc_64l;
 398   current_process ()->tdesc = tdesc;
 399   ppc_hwcap = 0;
 400
 401   regcache = new_register_cache (tdesc);
 402   fetch_inferior_registers (regcache, find_regno (tdesc, "msr"));
 403   collect_register_by_name (regcache, "msr", &msr);
 404   free_register_cache (regcache);
 405   if (ppc64_64bit_inferior_p (msr))
 406     {
 407       ppc_get_hwcap (&ppc_hwcap);
 408       if (ppc_hwcap & PPC_FEATURE_CELL)
 409         tdesc = tdesc_powerpc_cell64l;
 410       else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
 411         {
 412           /* Power ISA 2.05 (implemented by Power 6 and newer processors)
 413              increases the FPSCR from 32 bits to 64 bits. Even though Power 7
 414              supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05
 415              set, only PPC_FEATURE_ARCH_2_06.  Since for now the only bits
 416              used in the higher half of the register are for Decimal Floating
 417              Point, we check if that feature is available to decide the size
 418              of the FPSCR.  */
 419           if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 420             tdesc = tdesc_powerpc_isa205_vsx64l;
 421           else
 422             tdesc = tdesc_powerpc_vsx64l;
 423         }
 424       else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
 425         {
 426           if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 427             tdesc = tdesc_powerpc_isa205_altivec64l;
 428           else
 429             tdesc = tdesc_powerpc_altivec64l;
 430         }
 431
 432       current_process ()->tdesc = tdesc;
 433       return;
 434     }
 435 #endif
 436
 437   /* OK, we have a 32-bit inferior.  */
 438   tdesc = tdesc_powerpc_32l;
 439   current_process ()->tdesc = tdesc;
 440
 441   ppc_get_hwcap (&ppc_hwcap);
 442   if (ppc_hwcap & PPC_FEATURE_CELL)
 443     tdesc = tdesc_powerpc_cell32l;
 444   else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
 445     {
 446       if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 447         tdesc = tdesc_powerpc_isa205_vsx32l;
 448       else
 449         tdesc = tdesc_powerpc_vsx32l;
 450     }
 451   else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
 452     {
 453       if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 454         tdesc = tdesc_powerpc_isa205_altivec32l;
 455       else
 456         tdesc = tdesc_powerpc_altivec32l;
 457     }
 458
 459   /* On 32-bit machines, check for SPE registers.
 460      Set the low target's regmap field as appropriately.  */
 461 #ifndef __powerpc64__
 462   if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
 463     tdesc = tdesc_powerpc_e500l;
 464
 465   if (!ppc_regmap_adjusted)
 466     {
 467       if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
 468         ppc_usrregs_info.regmap = ppc_regmap_e500;
 469
 470       /* If the FPSCR is 64-bit wide, we need to fetch the whole
 471          64-bit slot and not just its second word.  The PT_FPSCR
 472          supplied in a 32-bit GDB compilation doesn't reflect
 473          this.  */
 474       if (register_size (tdesc, 70) == 8)
 475         ppc_regmap[70] = (48 + 2*32) * sizeof (long);
 476
 477       ppc_regmap_adjusted = 1;
 478    }
 479 #endif
 480   current_process ()->tdesc = tdesc;
 481 }
 482
 483 /* Correct in either endianness.
 484    This instruction is "twge r2, r2", which GDB uses as a software
 485    breakpoint.  */
 486 static const unsigned int ppc_breakpoint = 0x7d821008;
 487 #define ppc_breakpoint_len 4
 488
 489 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
 490
 491 static const gdb_byte *
 492 ppc_sw_breakpoint_from_kind (int kind, int *size)
 493 {
 494   *size = ppc_breakpoint_len;
 495   return (const gdb_byte *) &ppc_breakpoint;
 496 }
 497
 498 static int
 499 ppc_breakpoint_at (CORE_ADDR where)
 500 {
 501   unsigned int insn;
 502
 503   if (where & ((CORE_ADDR)1 << 63))
 504     {
 505       char mem_annex[32];
 506       sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
 507       (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
 508                                 NULL, where & 0xffffffff, 4);
 509       if (insn == 0x3fff)
 510         return 1;
 511     }
 512   else
 513     {
 514       (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
 515       if (insn == ppc_breakpoint)
 516         return 1;
 517       /* If necessary, recognize more trap instructions here.  GDB only uses
 518          the one.  */
 519     }
 520
 521   return 0;
 522 }
 523
 524 /* Provide only a fill function for the general register set.  ps_lgetregs
 525    will use this for NPTL support.  */
 526
 527 static void ppc_fill_gregset (struct regcache *regcache, void *buf)
 528 {
 529   int i;
 530
 531   for (i = 0; i < 32; i++)
 532     ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
 533
 534   for (i = 64; i < 70; i++)
 535     ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
 536
 537   for (i = 71; i < 73; i++)
 538     ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
 539 }
 540
 541 #define SIZEOF_VSXREGS 32*8
 542
 543 static void
 544 ppc_fill_vsxregset (struct regcache *regcache, void *buf)
 545 {
 546   int i, base;
 547   char *regset = buf;
 548
 549   if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
 550     return;
 551
 552   base = find_regno (regcache->tdesc, "vs0h");
 553   for (i = 0; i < 32; i++)
 554     collect_register (regcache, base + i, &regset[i * 8]);
 555 }
 556
 557 static void
 558 ppc_store_vsxregset (struct regcache *regcache, const void *buf)
 559 {
 560   int i, base;
 561   const char *regset = buf;
 562
 563   if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
 564     return;
 565
 566   base = find_regno (regcache->tdesc, "vs0h");
 567   for (i = 0; i < 32; i++)
 568     supply_register (regcache, base + i, &regset[i * 8]);
 569 }
 570
 571 #define SIZEOF_VRREGS 33*16+4
 572
 573 static void
 574 ppc_fill_vrregset (struct regcache *regcache, void *buf)
 575 {
 576   int i, base;
 577   char *regset = buf;
 578
 579   if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
 580     return;
 581
 582   base = find_regno (regcache->tdesc, "vr0");
 583   for (i = 0; i < 32; i++)
 584     collect_register (regcache, base + i, &regset[i * 16]);
 585
 586   collect_register_by_name (regcache, "vscr", &regset[32 * 16 + 12]);
 587   collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
 588 }
 589
 590 static void
 591 ppc_store_vrregset (struct regcache *regcache, const void *buf)
 592 {
 593   int i, base;
 594   const char *regset = buf;
 595
 596   if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
 597     return;
 598
 599   base = find_regno (regcache->tdesc, "vr0");
 600   for (i = 0; i < 32; i++)
 601     supply_register (regcache, base + i, &regset[i * 16]);
 602
 603   supply_register_by_name (regcache, "vscr", &regset[32 * 16 + 12]);
 604   supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
 605 }
 606
 607 struct gdb_evrregset_t
 608 {
 609   unsigned long evr[32];
 610   unsigned long long acc;
 611   unsigned long spefscr;
 612 };
 613
 614 static void
 615 ppc_fill_evrregset (struct regcache *regcache, void *buf)
 616 {
 617   int i, ev0;
 618   struct gdb_evrregset_t *regset = buf;
 619
 620   if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
 621     return;
 622
 623   ev0 = find_regno (regcache->tdesc, "ev0h");
 624   for (i = 0; i < 32; i++)
 625     collect_register (regcache, ev0 + i, &regset->evr[i]);
 626
 627   collect_register_by_name (regcache, "acc", &regset->acc);
 628   collect_register_by_name (regcache, "spefscr", &regset->spefscr);
 629 }
 630
 631 static void
 632 ppc_store_evrregset (struct regcache *regcache, const void *buf)
 633 {
 634   int i, ev0;
 635   const struct gdb_evrregset_t *regset = buf;
 636
 637   if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
 638     return;
 639
 640   ev0 = find_regno (regcache->tdesc, "ev0h");
 641   for (i = 0; i < 32; i++)
 642     supply_register (regcache, ev0 + i, &regset->evr[i]);
 643
 644   supply_register_by_name (regcache, "acc", &regset->acc);
 645   supply_register_by_name (regcache, "spefscr", &regset->spefscr);
 646 }
 647
 648 static struct regset_info ppc_regsets[] = {
 649   /* List the extra register sets before GENERAL_REGS.  That way we will
 650      fetch them every time, but still fall back to PTRACE_PEEKUSER for the
 651      general registers.  Some kernels support these, but not the newer
 652      PPC_PTRACE_GETREGS.  */
 653   { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, SIZEOF_VSXREGS, EXTENDED_REGS,
 654   ppc_fill_vsxregset, ppc_store_vsxregset },
 655   { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, SIZEOF_VRREGS, EXTENDED_REGS,
 656     ppc_fill_vrregset, ppc_store_vrregset },
 657   { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 32 * 4 + 8 + 4, EXTENDED_REGS,
 658     ppc_fill_evrregset, ppc_store_evrregset },
 659   { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
 660   NULL_REGSET
 661 };
 662
 663 static struct usrregs_info ppc_usrregs_info =
 664   {
 665     ppc_num_regs,
 666     ppc_regmap,
 667   };
 668
 669 static struct regsets_info ppc_regsets_info =
 670   {
 671     ppc_regsets, /* regsets */
 672     0, /* num_regsets */
 673     NULL, /* disabled_regsets */
 674   };
 675
 676 static struct regs_info regs_info =
 677   {
 678     NULL, /* regset_bitmap */
 679     &ppc_usrregs_info,
 680     &ppc_regsets_info
 681   };
 682
 683 static const struct regs_info *
 684 ppc_regs_info (void)
 685 {
 686   return &regs_info;
 687 }
 688
 689 struct linux_target_ops the_low_target = {
 690   ppc_arch_setup,
 691   ppc_regs_info,
 692   ppc_cannot_fetch_register,
 693   ppc_cannot_store_register,
 694   NULL, /* fetch_register */
 695   ppc_get_pc,
 696   ppc_set_pc,
 697   NULL, /* breakpoint_kind_from_pc */
 698   ppc_sw_breakpoint_from_kind,
 699   NULL,
 700   0,
 701   ppc_breakpoint_at,
 702   NULL, /* supports_z_point_type */
 703   NULL,
 704   NULL,
 705   NULL,
 706   NULL,
 707   ppc_collect_ptrace_register,
 708   ppc_supply_ptrace_register,
 709 };
 710
 711 void
 712 initialize_low_arch (void)
 713 {
 714   /* Initialize the Linux target descriptions.  */
 715
 716   init_registers_powerpc_32l ();
 717   init_registers_powerpc_altivec32l ();
 718   init_registers_powerpc_cell32l ();
 719   init_registers_powerpc_vsx32l ();
 720   init_registers_powerpc_isa205_32l ();
 721   init_registers_powerpc_isa205_altivec32l ();
 722   init_registers_powerpc_isa205_vsx32l ();
 723   init_registers_powerpc_e500l ();
 724   init_registers_powerpc_64l ();
 725   init_registers_powerpc_altivec64l ();
 726   init_registers_powerpc_cell64l ();
 727   init_registers_powerpc_vsx64l ();
 728   init_registers_powerpc_isa205_64l ();
 729   init_registers_powerpc_isa205_altivec64l ();
 730   init_registers_powerpc_isa205_vsx64l ();
 731
 732   initialize_regsets_info (&ppc_regsets_info);
 733 }