1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx-mpx.c"
57 #include "features/i386/i386-avx-mpx-avx512.c"
58 #include "features/i386/i386-mmx.c"
63 #include "stap-probe.h"
64 #include "user-regs.h"
65 #include "cli/cli-utils.h"
66 #include "expression.h"
67 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names
[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names
[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names
[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names
[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names
[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names
[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names
[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names
[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names
[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names
[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs
= 16;
163 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
165 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
166 int mm0_regnum
= tdep
->mm0_regnum
;
171 regnum
-= mm0_regnum
;
172 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
178 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
182 regnum
-= tdep
->al_regnum
;
183 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
189 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
193 regnum
-= tdep
->ax_regnum
;
194 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
203 int eax_regnum
= tdep
->eax_regnum
;
208 regnum
-= eax_regnum
;
209 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
218 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
220 if (zmm0h_regnum
< 0)
223 regnum
-= zmm0h_regnum
;
224 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
228 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
231 int zmm0_regnum
= tdep
->zmm0_regnum
;
236 regnum
-= zmm0_regnum
;
237 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
241 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
244 int k0_regnum
= tdep
->k0_regnum
;
250 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
254 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
256 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
257 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
259 if (ymm0h_regnum
< 0)
262 regnum
-= ymm0h_regnum
;
263 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
269 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
271 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
272 int ymm0_regnum
= tdep
->ymm0_regnum
;
277 regnum
-= ymm0_regnum
;
278 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
282 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
284 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
285 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
287 if (ymm16h_regnum
< 0)
290 regnum
-= ymm16h_regnum
;
291 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
295 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
298 int ymm16_regnum
= tdep
->ymm16_regnum
;
300 if (ymm16_regnum
< 0)
303 regnum
-= ymm16_regnum
;
304 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
310 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
313 int bnd0_regnum
= tdep
->bnd0_regnum
;
318 regnum
-= bnd0_regnum
;
319 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
325 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
328 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
330 if (num_xmm_regs
== 0)
333 regnum
-= I387_XMM0_REGNUM (tdep
);
334 return regnum
>= 0 && regnum
< num_xmm_regs
;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
343 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
345 if (num_xmm_avx512_regs
== 0)
348 regnum
-= I387_XMM16_REGNUM (tdep
);
349 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
353 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 if (I387_NUM_XMM_REGS (tdep
) == 0)
360 return (regnum
== I387_MXCSR_REGNUM (tdep
));
366 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
370 if (I387_ST0_REGNUM (tdep
) < 0)
373 return (I387_ST0_REGNUM (tdep
) <= regnum
374 && regnum
< I387_FCTRL_REGNUM (tdep
));
378 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
380 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
382 if (I387_ST0_REGNUM (tdep
) < 0)
385 return (I387_FCTRL_REGNUM (tdep
) <= regnum
386 && regnum
< I387_XMM0_REGNUM (tdep
));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
394 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
396 if (I387_BND0R_REGNUM (tdep
) < 0)
399 regnum
-= tdep
->bnd0r_regnum
;
400 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
410 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
413 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
414 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
435 return tdesc_register_name (gdbarch
, regnum
);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
444 if (i386_bnd_regnum_p (gdbarch
, regnum
))
445 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
446 if (i386_mmx_regnum_p (gdbarch
, regnum
))
447 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
448 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
449 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
450 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
451 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
452 else if (i386_byte_regnum_p (gdbarch
, regnum
))
453 return i386_byte_names
[regnum
- tdep
->al_regnum
];
454 else if (i386_word_regnum_p (gdbarch
, regnum
))
455 return i386_word_names
[regnum
- tdep
->ax_regnum
];
457 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg
>= 0 && reg
<= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg
>= 12 && reg
<= 19)
483 /* Floating-point registers. */
484 return reg
- 12 + I387_ST0_REGNUM (tdep
);
486 else if (reg
>= 21 && reg
<= 28)
489 int ymm0_regnum
= tdep
->ymm0_regnum
;
492 && i386_xmm_regnum_p (gdbarch
, reg
))
493 return reg
- 21 + ymm0_regnum
;
495 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
497 else if (reg
>= 29 && reg
<= 36)
500 return reg
- 29 + I387_MM0_REGNUM (tdep
);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
507 /* Convert SVR4 DWARF register number REG to the appropriate register number
511 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg
>= 0 && reg
<= 9)
522 /* General-purpose registers. */
525 else if (reg
>= 11 && reg
<= 18)
527 /* Floating-point registers. */
528 return reg
- 11 + I387_ST0_REGNUM (tdep
);
530 else if (reg
>= 21 && reg
<= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
538 case 37: return I387_FCTRL_REGNUM (tdep
);
539 case 38: return I387_FSTAT_REGNUM (tdep
);
540 case 39: return I387_MXCSR_REGNUM (tdep
);
541 case 40: return I386_ES_REGNUM
;
542 case 41: return I386_CS_REGNUM
;
543 case 42: return I386_SS_REGNUM
;
544 case 43: return I386_DS_REGNUM
;
545 case 44: return I386_FS_REGNUM
;
546 case 45: return I386_GS_REGNUM
;
552 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
553 num_regs + num_pseudo_regs for other debug formats. */
556 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
558 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
561 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
567 /* This is the variable that is set with "set disassembly-flavor", and
568 its legitimate values. */
569 static const char att_flavor
[] = "att";
570 static const char intel_flavor
[] = "intel";
571 static const char *const valid_flavors
[] =
577 static const char *disassembly_flavor
= att_flavor
;
580 /* Use the program counter to determine the contents and size of a
581 breakpoint instruction. Return a pointer to a string of bytes that
582 encode a breakpoint instruction, store the length of the string in
583 *LEN and optionally adjust *PC to point to the correct memory
584 location for inserting the breakpoint.
586 On the i386 we have a single breakpoint that fits in a single byte
587 and can be inserted anywhere.
589 This function is 64-bit safe. */
591 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
593 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
596 /* Displaced instruction handling. */
598 /* Skip the legacy instruction prefixes in INSN.
599 Not all prefixes are valid for any particular insn
600 but we needn't care, the insn will fault if it's invalid.
601 The result is a pointer to the first opcode byte,
602 or NULL if we run off the end of the buffer. */
605 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
607 gdb_byte
*end
= insn
+ max_len
;
613 case DATA_PREFIX_OPCODE
:
614 case ADDR_PREFIX_OPCODE
:
615 case CS_PREFIX_OPCODE
:
616 case DS_PREFIX_OPCODE
:
617 case ES_PREFIX_OPCODE
:
618 case FS_PREFIX_OPCODE
:
619 case GS_PREFIX_OPCODE
:
620 case SS_PREFIX_OPCODE
:
621 case LOCK_PREFIX_OPCODE
:
622 case REPE_PREFIX_OPCODE
:
623 case REPNE_PREFIX_OPCODE
:
635 i386_absolute_jmp_p (const gdb_byte
*insn
)
637 /* jmp far (absolute address in operand). */
643 /* jump near, absolute indirect (/4). */
644 if ((insn
[1] & 0x38) == 0x20)
647 /* jump far, absolute indirect (/5). */
648 if ((insn
[1] & 0x38) == 0x28)
655 /* Return non-zero if INSN is a jump, zero otherwise. */
658 i386_jmp_p (const gdb_byte
*insn
)
660 /* jump short, relative. */
664 /* jump near, relative. */
668 return i386_absolute_jmp_p (insn
);
672 i386_absolute_call_p (const gdb_byte
*insn
)
674 /* call far, absolute. */
680 /* Call near, absolute indirect (/2). */
681 if ((insn
[1] & 0x38) == 0x10)
684 /* Call far, absolute indirect (/3). */
685 if ((insn
[1] & 0x38) == 0x18)
693 i386_ret_p (const gdb_byte
*insn
)
697 case 0xc2: /* ret near, pop N bytes. */
698 case 0xc3: /* ret near */
699 case 0xca: /* ret far, pop N bytes. */
700 case 0xcb: /* ret far */
701 case 0xcf: /* iret */
710 i386_call_p (const gdb_byte
*insn
)
712 if (i386_absolute_call_p (insn
))
715 /* call near, relative. */
722 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
723 length in bytes. Otherwise, return zero. */
726 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
728 /* Is it 'int $0x80'? */
729 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
730 /* Or is it 'sysenter'? */
731 || (insn
[0] == 0x0f && insn
[1] == 0x34)
732 /* Or is it 'syscall'? */
733 || (insn
[0] == 0x0f && insn
[1] == 0x05))
742 /* The gdbarch insn_is_call method. */
745 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
747 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
749 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
750 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
752 return i386_call_p (insn
);
755 /* The gdbarch insn_is_ret method. */
758 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
760 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
762 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
763 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
765 return i386_ret_p (insn
);
768 /* The gdbarch insn_is_jump method. */
771 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
773 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
775 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
776 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
778 return i386_jmp_p (insn
);
781 /* Some kernels may run one past a syscall insn, so we have to cope.
782 Otherwise this is just simple_displaced_step_copy_insn. */
784 struct displaced_step_closure
*
785 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
786 CORE_ADDR from
, CORE_ADDR to
,
787 struct regcache
*regs
)
789 size_t len
= gdbarch_max_insn_length (gdbarch
);
790 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
792 read_memory (from
, buf
, len
);
794 /* GDB may get control back after the insn after the syscall.
795 Presumably this is a kernel bug.
796 If this is a syscall, make sure there's a nop afterwards. */
801 insn
= i386_skip_prefixes (buf
, len
);
802 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
803 insn
[syscall_length
] = NOP_OPCODE
;
806 write_memory (to
, buf
, len
);
810 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
811 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
812 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
815 return (struct displaced_step_closure
*) buf
;
818 /* Fix up the state of registers and memory after having single-stepped
819 a displaced instruction. */
822 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
823 struct displaced_step_closure
*closure
,
824 CORE_ADDR from
, CORE_ADDR to
,
825 struct regcache
*regs
)
827 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
829 /* The offset we applied to the instruction's address.
830 This could well be negative (when viewed as a signed 32-bit
831 value), but ULONGEST won't reflect that, so take care when
833 ULONGEST insn_offset
= to
- from
;
835 /* Since we use simple_displaced_step_copy_insn, our closure is a
836 copy of the instruction. */
837 gdb_byte
*insn
= (gdb_byte
*) closure
;
838 /* The start of the insn, needed in case we see some prefixes. */
839 gdb_byte
*insn_start
= insn
;
842 fprintf_unfiltered (gdb_stdlog
,
843 "displaced: fixup (%s, %s), "
844 "insn = 0x%02x 0x%02x ...\n",
845 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
848 /* The list of issues to contend with here is taken from
849 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
850 Yay for Free Software! */
852 /* Relocate the %eip, if necessary. */
854 /* The instruction recognizers we use assume any leading prefixes
855 have been skipped. */
857 /* This is the size of the buffer in closure. */
858 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
859 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
860 /* If there are too many prefixes, just ignore the insn.
861 It will fault when run. */
866 /* Except in the case of absolute or indirect jump or call
867 instructions, or a return instruction, the new eip is relative to
868 the displaced instruction; make it relative. Well, signal
869 handler returns don't need relocation either, but we use the
870 value of %eip to recognize those; see below. */
871 if (! i386_absolute_jmp_p (insn
)
872 && ! i386_absolute_call_p (insn
)
873 && ! i386_ret_p (insn
))
878 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
880 /* A signal trampoline system call changes the %eip, resuming
881 execution of the main program after the signal handler has
882 returned. That makes them like 'return' instructions; we
883 shouldn't relocate %eip.
885 But most system calls don't, and we do need to relocate %eip.
887 Our heuristic for distinguishing these cases: if stepping
888 over the system call instruction left control directly after
889 the instruction, the we relocate --- control almost certainly
890 doesn't belong in the displaced copy. Otherwise, we assume
891 the instruction has put control where it belongs, and leave
892 it unrelocated. Goodness help us if there are PC-relative
894 if (i386_syscall_p (insn
, &insn_len
)
895 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
896 /* GDB can get control back after the insn after the syscall.
897 Presumably this is a kernel bug.
898 i386_displaced_step_copy_insn ensures its a nop,
899 we add one to the length for it. */
900 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
903 fprintf_unfiltered (gdb_stdlog
,
904 "displaced: syscall changed %%eip; "
909 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
911 /* If we just stepped over a breakpoint insn, we don't backup
912 the pc on purpose; this is to match behaviour without
915 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
918 fprintf_unfiltered (gdb_stdlog
,
920 "relocated %%eip from %s to %s\n",
921 paddress (gdbarch
, orig_eip
),
922 paddress (gdbarch
, eip
));
926 /* If the instruction was PUSHFL, then the TF bit will be set in the
927 pushed value, and should be cleared. We'll leave this for later,
928 since GDB already messes up the TF flag when stepping over a
931 /* If the instruction was a call, the return address now atop the
932 stack is the address following the copied instruction. We need
933 to make it the address following the original instruction. */
934 if (i386_call_p (insn
))
938 const ULONGEST retaddr_len
= 4;
940 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
941 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
942 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
943 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
946 fprintf_unfiltered (gdb_stdlog
,
947 "displaced: relocated return addr at %s to %s\n",
948 paddress (gdbarch
, esp
),
949 paddress (gdbarch
, retaddr
));
954 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
956 target_write_memory (*to
, buf
, len
);
961 i386_relocate_instruction (struct gdbarch
*gdbarch
,
962 CORE_ADDR
*to
, CORE_ADDR oldloc
)
964 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
965 gdb_byte buf
[I386_MAX_INSN_LEN
];
966 int offset
= 0, rel32
, newrel
;
968 gdb_byte
*insn
= buf
;
970 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
972 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
973 I386_MAX_INSN_LEN
, oldloc
);
975 /* Get past the prefixes. */
976 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
978 /* Adjust calls with 32-bit relative addresses as push/jump, with
979 the address pushed being the location where the original call in
980 the user program would return to. */
983 gdb_byte push_buf
[16];
984 unsigned int ret_addr
;
986 /* Where "ret" in the original code will return to. */
987 ret_addr
= oldloc
+ insn_length
;
988 push_buf
[0] = 0x68; /* pushq $... */
989 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
991 append_insns (to
, 5, push_buf
);
993 /* Convert the relative call to a relative jump. */
996 /* Adjust the destination offset. */
997 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
998 newrel
= (oldloc
- *to
) + rel32
;
999 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1001 if (debug_displaced
)
1002 fprintf_unfiltered (gdb_stdlog
,
1003 "Adjusted insn rel32=%s at %s to"
1004 " rel32=%s at %s\n",
1005 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1006 hex_string (newrel
), paddress (gdbarch
, *to
));
1008 /* Write the adjusted jump into its displaced location. */
1009 append_insns (to
, 5, insn
);
1013 /* Adjust jumps with 32-bit relative addresses. Calls are already
1015 if (insn
[0] == 0xe9)
1017 /* Adjust conditional jumps. */
1018 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1023 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1024 newrel
= (oldloc
- *to
) + rel32
;
1025 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1026 if (debug_displaced
)
1027 fprintf_unfiltered (gdb_stdlog
,
1028 "Adjusted insn rel32=%s at %s to"
1029 " rel32=%s at %s\n",
1030 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1031 hex_string (newrel
), paddress (gdbarch
, *to
));
1034 /* Write the adjusted instructions into their displaced
1036 append_insns (to
, insn_length
, buf
);
1040 #ifdef I386_REGNO_TO_SYMMETRY
1041 #error "The Sequent Symmetry is no longer supported."
1044 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1045 and %esp "belong" to the calling function. Therefore these
1046 registers should be saved if they're going to be modified. */
1048 /* The maximum number of saved registers. This should include all
1049 registers mentioned above, and %eip. */
1050 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1052 struct i386_frame_cache
1060 /* Saved registers. */
1061 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1066 /* Stack space reserved for local variables. */
1070 /* Allocate and initialize a frame cache. */
1072 static struct i386_frame_cache
*
1073 i386_alloc_frame_cache (void)
1075 struct i386_frame_cache
*cache
;
1078 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1083 cache
->sp_offset
= -4;
1086 /* Saved registers. We initialize these to -1 since zero is a valid
1087 offset (that's where %ebp is supposed to be stored). */
1088 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1089 cache
->saved_regs
[i
] = -1;
1090 cache
->saved_sp
= 0;
1091 cache
->saved_sp_reg
= -1;
1092 cache
->pc_in_eax
= 0;
1094 /* Frameless until proven otherwise. */
1100 /* If the instruction at PC is a jump, return the address of its
1101 target. Otherwise, return PC. */
1104 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1106 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1111 if (target_read_code (pc
, &op
, 1))
1118 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1124 /* Relative jump: if data16 == 0, disp32, else disp16. */
1127 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1129 /* Include the size of the jmp instruction (including the
1135 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1137 /* Include the size of the jmp instruction. */
1142 /* Relative jump, disp8 (ignore data16). */
1143 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1145 delta
+= data16
+ 2;
1152 /* Check whether PC points at a prologue for a function returning a
1153 structure or union. If so, it updates CACHE and returns the
1154 address of the first instruction after the code sequence that
1155 removes the "hidden" argument from the stack or CURRENT_PC,
1156 whichever is smaller. Otherwise, return PC. */
1159 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1160 struct i386_frame_cache
*cache
)
1162 /* Functions that return a structure or union start with:
1165 xchgl %eax, (%esp) 0x87 0x04 0x24
1166 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1168 (the System V compiler puts out the second `xchg' instruction,
1169 and the assembler doesn't try to optimize it, so the 'sib' form
1170 gets generated). This sequence is used to get the address of the
1171 return buffer for a function that returns a structure. */
1172 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1173 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1177 if (current_pc
<= pc
)
1180 if (target_read_code (pc
, &op
, 1))
1183 if (op
!= 0x58) /* popl %eax */
1186 if (target_read_code (pc
+ 1, buf
, 4))
1189 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1192 if (current_pc
== pc
)
1194 cache
->sp_offset
+= 4;
1198 if (current_pc
== pc
+ 1)
1200 cache
->pc_in_eax
= 1;
1204 if (buf
[1] == proto1
[1])
1211 i386_skip_probe (CORE_ADDR pc
)
1213 /* A function may start with
1227 if (target_read_code (pc
, &op
, 1))
1230 if (op
== 0x68 || op
== 0x6a)
1234 /* Skip past the `pushl' instruction; it has either a one-byte or a
1235 four-byte operand, depending on the opcode. */
1241 /* Read the following 8 bytes, which should be `call _probe' (6
1242 bytes) followed by `addl $4,%esp' (2 bytes). */
1243 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1244 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1245 pc
+= delta
+ sizeof (buf
);
1251 /* GCC 4.1 and later, can put code in the prologue to realign the
1252 stack pointer. Check whether PC points to such code, and update
1253 CACHE accordingly. Return the first instruction after the code
1254 sequence or CURRENT_PC, whichever is smaller. If we don't
1255 recognize the code, return PC. */
1258 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1259 struct i386_frame_cache
*cache
)
1261 /* There are 2 code sequences to re-align stack before the frame
1264 1. Use a caller-saved saved register:
1270 2. Use a callee-saved saved register:
1277 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1279 0x83 0xe4 0xf0 andl $-16, %esp
1280 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1285 int offset
, offset_and
;
1286 static int regnums
[8] = {
1287 I386_EAX_REGNUM
, /* %eax */
1288 I386_ECX_REGNUM
, /* %ecx */
1289 I386_EDX_REGNUM
, /* %edx */
1290 I386_EBX_REGNUM
, /* %ebx */
1291 I386_ESP_REGNUM
, /* %esp */
1292 I386_EBP_REGNUM
, /* %ebp */
1293 I386_ESI_REGNUM
, /* %esi */
1294 I386_EDI_REGNUM
/* %edi */
1297 if (target_read_code (pc
, buf
, sizeof buf
))
1300 /* Check caller-saved saved register. The first instruction has
1301 to be "leal 4(%esp), %reg". */
1302 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1304 /* MOD must be binary 10 and R/M must be binary 100. */
1305 if ((buf
[1] & 0xc7) != 0x44)
1308 /* REG has register number. */
1309 reg
= (buf
[1] >> 3) & 7;
1314 /* Check callee-saved saved register. The first instruction
1315 has to be "pushl %reg". */
1316 if ((buf
[0] & 0xf8) != 0x50)
1322 /* The next instruction has to be "leal 8(%esp), %reg". */
1323 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1326 /* MOD must be binary 10 and R/M must be binary 100. */
1327 if ((buf
[2] & 0xc7) != 0x44)
1330 /* REG has register number. Registers in pushl and leal have to
1332 if (reg
!= ((buf
[2] >> 3) & 7))
1338 /* Rigister can't be %esp nor %ebp. */
1339 if (reg
== 4 || reg
== 5)
1342 /* The next instruction has to be "andl $-XXX, %esp". */
1343 if (buf
[offset
+ 1] != 0xe4
1344 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1347 offset_and
= offset
;
1348 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1350 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1351 0xfc. REG must be binary 110 and MOD must be binary 01. */
1352 if (buf
[offset
] != 0xff
1353 || buf
[offset
+ 2] != 0xfc
1354 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1357 /* R/M has register. Registers in leal and pushl have to be the
1359 if (reg
!= (buf
[offset
+ 1] & 7))
1362 if (current_pc
> pc
+ offset_and
)
1363 cache
->saved_sp_reg
= regnums
[reg
];
1365 return std::min (pc
+ offset
+ 3, current_pc
);
1368 /* Maximum instruction length we need to handle. */
1369 #define I386_MAX_MATCHED_INSN_LEN 6
1371 /* Instruction description. */
1375 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1376 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1379 /* Return whether instruction at PC matches PATTERN. */
1382 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1386 if (target_read_code (pc
, &op
, 1))
1389 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1391 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1392 int insn_matched
= 1;
1395 gdb_assert (pattern
.len
> 1);
1396 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1398 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1401 for (i
= 1; i
< pattern
.len
; i
++)
1403 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1406 return insn_matched
;
1411 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1412 the first instruction description that matches. Otherwise, return
1415 static struct i386_insn
*
1416 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1418 struct i386_insn
*pattern
;
1420 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1422 if (i386_match_pattern (pc
, *pattern
))
1429 /* Return whether PC points inside a sequence of instructions that
1430 matches INSN_PATTERNS. */
1433 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1435 CORE_ADDR current_pc
;
1437 struct i386_insn
*insn
;
1439 insn
= i386_match_insn (pc
, insn_patterns
);
1444 ix
= insn
- insn_patterns
;
1445 for (i
= ix
- 1; i
>= 0; i
--)
1447 current_pc
-= insn_patterns
[i
].len
;
1449 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1453 current_pc
= pc
+ insn
->len
;
1454 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1456 if (!i386_match_pattern (current_pc
, *insn
))
1459 current_pc
+= insn
->len
;
1465 /* Some special instructions that might be migrated by GCC into the
1466 part of the prologue that sets up the new stack frame. Because the
1467 stack frame hasn't been setup yet, no registers have been saved
1468 yet, and only the scratch registers %eax, %ecx and %edx can be
1471 struct i386_insn i386_frame_setup_skip_insns
[] =
1473 /* Check for `movb imm8, r' and `movl imm32, r'.
1475 ??? Should we handle 16-bit operand-sizes here? */
1477 /* `movb imm8, %al' and `movb imm8, %ah' */
1478 /* `movb imm8, %cl' and `movb imm8, %ch' */
1479 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1480 /* `movb imm8, %dl' and `movb imm8, %dh' */
1481 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1482 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1483 { 5, { 0xb8 }, { 0xfe } },
1484 /* `movl imm32, %edx' */
1485 { 5, { 0xba }, { 0xff } },
1487 /* Check for `mov imm32, r32'. Note that there is an alternative
1488 encoding for `mov m32, %eax'.
1490 ??? Should we handle SIB adressing here?
1491 ??? Should we handle 16-bit operand-sizes here? */
1493 /* `movl m32, %eax' */
1494 { 5, { 0xa1 }, { 0xff } },
1495 /* `movl m32, %eax' and `mov; m32, %ecx' */
1496 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1497 /* `movl m32, %edx' */
1498 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1500 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1501 Because of the symmetry, there are actually two ways to encode
1502 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1503 opcode bytes 0x31 and 0x33 for `xorl'. */
1505 /* `subl %eax, %eax' */
1506 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1507 /* `subl %ecx, %ecx' */
1508 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1509 /* `subl %edx, %edx' */
1510 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1511 /* `xorl %eax, %eax' */
1512 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1513 /* `xorl %ecx, %ecx' */
1514 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1515 /* `xorl %edx, %edx' */
1516 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1521 /* Check whether PC points to a no-op instruction. */
1523 i386_skip_noop (CORE_ADDR pc
)
1528 if (target_read_code (pc
, &op
, 1))
1534 /* Ignore `nop' instruction. */
1538 if (target_read_code (pc
, &op
, 1))
1542 /* Ignore no-op instruction `mov %edi, %edi'.
1543 Microsoft system dlls often start with
1544 a `mov %edi,%edi' instruction.
1545 The 5 bytes before the function start are
1546 filled with `nop' instructions.
1547 This pattern can be used for hot-patching:
1548 The `mov %edi, %edi' instruction can be replaced by a
1549 near jump to the location of the 5 `nop' instructions
1550 which can be replaced by a 32-bit jump to anywhere
1551 in the 32-bit address space. */
1553 else if (op
== 0x8b)
1555 if (target_read_code (pc
+ 1, &op
, 1))
1561 if (target_read_code (pc
, &op
, 1))
1571 /* Check whether PC points at a code that sets up a new stack frame.
1572 If so, it updates CACHE and returns the address of the first
1573 instruction after the sequence that sets up the frame or LIMIT,
1574 whichever is smaller. If we don't recognize the code, return PC. */
1577 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1578 CORE_ADDR pc
, CORE_ADDR limit
,
1579 struct i386_frame_cache
*cache
)
1581 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1582 struct i386_insn
*insn
;
1589 if (target_read_code (pc
, &op
, 1))
1592 if (op
== 0x55) /* pushl %ebp */
1594 /* Take into account that we've executed the `pushl %ebp' that
1595 starts this instruction sequence. */
1596 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1597 cache
->sp_offset
+= 4;
1600 /* If that's all, return now. */
1604 /* Check for some special instructions that might be migrated by
1605 GCC into the prologue and skip them. At this point in the
1606 prologue, code should only touch the scratch registers %eax,
1607 %ecx and %edx, so while the number of posibilities is sheer,
1610 Make sure we only skip these instructions if we later see the
1611 `movl %esp, %ebp' that actually sets up the frame. */
1612 while (pc
+ skip
< limit
)
1614 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1621 /* If that's all, return now. */
1622 if (limit
<= pc
+ skip
)
1625 if (target_read_code (pc
+ skip
, &op
, 1))
1628 /* The i386 prologue looks like
1634 and a different prologue can be generated for atom.
1638 lea -0x10(%esp),%esp
1640 We handle both of them here. */
1644 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1646 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1652 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1657 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1658 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1667 /* OK, we actually have a frame. We just don't know how large
1668 it is yet. Set its size to zero. We'll adjust it if
1669 necessary. We also now commit to skipping the special
1670 instructions mentioned before. */
1673 /* If that's all, return now. */
1677 /* Check for stack adjustment
1683 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1684 reg, so we don't have to worry about a data16 prefix. */
1685 if (target_read_code (pc
, &op
, 1))
1689 /* `subl' with 8-bit immediate. */
1690 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1691 /* Some instruction starting with 0x83 other than `subl'. */
1694 /* `subl' with signed 8-bit immediate (though it wouldn't
1695 make sense to be negative). */
1696 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1699 else if (op
== 0x81)
1701 /* Maybe it is `subl' with a 32-bit immediate. */
1702 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1703 /* Some instruction starting with 0x81 other than `subl'. */
1706 /* It is `subl' with a 32-bit immediate. */
1707 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1710 else if (op
== 0x8d)
1712 /* The ModR/M byte is 0x64. */
1713 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1715 /* 'lea' with 8-bit displacement. */
1716 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1721 /* Some instruction other than `subl' nor 'lea'. */
1725 else if (op
== 0xc8) /* enter */
1727 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1734 /* Check whether PC points at code that saves registers on the stack.
1735 If so, it updates CACHE and returns the address of the first
1736 instruction after the register saves or CURRENT_PC, whichever is
1737 smaller. Otherwise, return PC. */
1740 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1741 struct i386_frame_cache
*cache
)
1743 CORE_ADDR offset
= 0;
1747 if (cache
->locals
> 0)
1748 offset
-= cache
->locals
;
1749 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1751 if (target_read_code (pc
, &op
, 1))
1753 if (op
< 0x50 || op
> 0x57)
1757 cache
->saved_regs
[op
- 0x50] = offset
;
1758 cache
->sp_offset
+= 4;
1765 /* Do a full analysis of the prologue at PC and update CACHE
1766 accordingly. Bail out early if CURRENT_PC is reached. Return the
1767 address where the analysis stopped.
1769 We handle these cases:
1771 The startup sequence can be at the start of the function, or the
1772 function can start with a branch to startup code at the end.
1774 %ebp can be set up with either the 'enter' instruction, or "pushl
1775 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1776 once used in the System V compiler).
1778 Local space is allocated just below the saved %ebp by either the
1779 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1780 16-bit unsigned argument for space to allocate, and the 'addl'
1781 instruction could have either a signed byte, or 32-bit immediate.
1783 Next, the registers used by this function are pushed. With the
1784 System V compiler they will always be in the order: %edi, %esi,
1785 %ebx (and sometimes a harmless bug causes it to also save but not
1786 restore %eax); however, the code below is willing to see the pushes
1787 in any order, and will handle up to 8 of them.
1789 If the setup sequence is at the end of the function, then the next
1790 instruction will be a branch back to the start. */
1793 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1794 CORE_ADDR pc
, CORE_ADDR current_pc
,
1795 struct i386_frame_cache
*cache
)
1797 pc
= i386_skip_noop (pc
);
1798 pc
= i386_follow_jump (gdbarch
, pc
);
1799 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1800 pc
= i386_skip_probe (pc
);
1801 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1802 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1803 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1806 /* Return PC of first real instruction. */
1809 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1811 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1813 static gdb_byte pic_pat
[6] =
1815 0xe8, 0, 0, 0, 0, /* call 0x0 */
1816 0x5b, /* popl %ebx */
1818 struct i386_frame_cache cache
;
1822 CORE_ADDR func_addr
;
1824 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1826 CORE_ADDR post_prologue_pc
1827 = skip_prologue_using_sal (gdbarch
, func_addr
);
1828 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1830 /* Clang always emits a line note before the prologue and another
1831 one after. We trust clang to emit usable line notes. */
1832 if (post_prologue_pc
1834 && COMPUNIT_PRODUCER (cust
) != NULL
1835 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1836 return std::max (start_pc
, post_prologue_pc
);
1840 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1841 if (cache
.locals
< 0)
1844 /* Found valid frame setup. */
1846 /* The native cc on SVR4 in -K PIC mode inserts the following code
1847 to get the address of the global offset table (GOT) into register
1852 movl %ebx,x(%ebp) (optional)
1855 This code is with the rest of the prologue (at the end of the
1856 function), so we have to skip it to get to the first real
1857 instruction at the start of the function. */
1859 for (i
= 0; i
< 6; i
++)
1861 if (target_read_code (pc
+ i
, &op
, 1))
1864 if (pic_pat
[i
] != op
)
1871 if (target_read_code (pc
+ delta
, &op
, 1))
1874 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1876 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1878 if (op
== 0x5d) /* One byte offset from %ebp. */
1880 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1882 else /* Unexpected instruction. */
1885 if (target_read_code (pc
+ delta
, &op
, 1))
1890 if (delta
> 0 && op
== 0x81
1891 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1898 /* If the function starts with a branch (to startup code at the end)
1899 the last instruction should bring us back to the first
1900 instruction of the real code. */
1901 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1902 pc
= i386_follow_jump (gdbarch
, pc
);
1907 /* Check that the code pointed to by PC corresponds to a call to
1908 __main, skip it if so. Return PC otherwise. */
1911 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1913 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1916 if (target_read_code (pc
, &op
, 1))
1922 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1924 /* Make sure address is computed correctly as a 32bit
1925 integer even if CORE_ADDR is 64 bit wide. */
1926 struct bound_minimal_symbol s
;
1927 CORE_ADDR call_dest
;
1929 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1930 call_dest
= call_dest
& 0xffffffffU
;
1931 s
= lookup_minimal_symbol_by_pc (call_dest
);
1932 if (s
.minsym
!= NULL
1933 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1934 && strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1942 /* This function is 64-bit safe. */
1945 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1949 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1950 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1954 /* Normal frames. */
1957 i386_frame_cache_1 (struct frame_info
*this_frame
,
1958 struct i386_frame_cache
*cache
)
1960 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1961 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1965 cache
->pc
= get_frame_func (this_frame
);
1967 /* In principle, for normal frames, %ebp holds the frame pointer,
1968 which holds the base address for the current stack frame.
1969 However, for functions that don't need it, the frame pointer is
1970 optional. For these "frameless" functions the frame pointer is
1971 actually the frame pointer of the calling frame. Signal
1972 trampolines are just a special case of a "frameless" function.
1973 They (usually) share their frame pointer with the frame that was
1974 in progress when the signal occurred. */
1976 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1977 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1978 if (cache
->base
== 0)
1984 /* For normal frames, %eip is stored at 4(%ebp). */
1985 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1988 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1991 if (cache
->locals
< 0)
1993 /* We didn't find a valid frame, which means that CACHE->base
1994 currently holds the frame pointer for our calling frame. If
1995 we're at the start of a function, or somewhere half-way its
1996 prologue, the function's frame probably hasn't been fully
1997 setup yet. Try to reconstruct the base address for the stack
1998 frame by looking at the stack pointer. For truly "frameless"
1999 functions this might work too. */
2001 if (cache
->saved_sp_reg
!= -1)
2003 /* Saved stack pointer has been saved. */
2004 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2005 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2007 /* We're halfway aligning the stack. */
2008 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2009 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2011 /* This will be added back below. */
2012 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2014 else if (cache
->pc
!= 0
2015 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2017 /* We're in a known function, but did not find a frame
2018 setup. Assume that the function does not use %ebp.
2019 Alternatively, we may have jumped to an invalid
2020 address; in that case there is definitely no new
2022 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2023 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2027 /* We're in an unknown function. We could not find the start
2028 of the function to analyze the prologue; our best option is
2029 to assume a typical frame layout with the caller's %ebp
2031 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2034 if (cache
->saved_sp_reg
!= -1)
2036 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2037 register may be unavailable). */
2038 if (cache
->saved_sp
== 0
2039 && deprecated_frame_register_read (this_frame
,
2040 cache
->saved_sp_reg
, buf
))
2041 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2043 /* Now that we have the base address for the stack frame we can
2044 calculate the value of %esp in the calling frame. */
2045 else if (cache
->saved_sp
== 0)
2046 cache
->saved_sp
= cache
->base
+ 8;
2048 /* Adjust all the saved registers such that they contain addresses
2049 instead of offsets. */
2050 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2051 if (cache
->saved_regs
[i
] != -1)
2052 cache
->saved_regs
[i
] += cache
->base
;
2057 static struct i386_frame_cache
*
2058 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2060 struct i386_frame_cache
*cache
;
2063 return (struct i386_frame_cache
*) *this_cache
;
2065 cache
= i386_alloc_frame_cache ();
2066 *this_cache
= cache
;
2070 i386_frame_cache_1 (this_frame
, cache
);
2072 CATCH (ex
, RETURN_MASK_ERROR
)
2074 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2075 throw_exception (ex
);
2083 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2084 struct frame_id
*this_id
)
2086 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2089 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2090 else if (cache
->base
== 0)
2092 /* This marks the outermost frame. */
2096 /* See the end of i386_push_dummy_call. */
2097 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2101 static enum unwind_stop_reason
2102 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2105 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2108 return UNWIND_UNAVAILABLE
;
2110 /* This marks the outermost frame. */
2111 if (cache
->base
== 0)
2112 return UNWIND_OUTERMOST
;
2114 return UNWIND_NO_REASON
;
2117 static struct value
*
2118 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2121 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2123 gdb_assert (regnum
>= 0);
2125 /* The System V ABI says that:
2127 "The flags register contains the system flags, such as the
2128 direction flag and the carry flag. The direction flag must be
2129 set to the forward (that is, zero) direction before entry and
2130 upon exit from a function. Other user flags have no specified
2131 role in the standard calling sequence and are not preserved."
2133 To guarantee the "upon exit" part of that statement we fake a
2134 saved flags register that has its direction flag cleared.
2136 Note that GCC doesn't seem to rely on the fact that the direction
2137 flag is cleared after a function return; it always explicitly
2138 clears the flag before operations where it matters.
2140 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2141 right thing to do. The way we fake the flags register here makes
2142 it impossible to change it. */
2144 if (regnum
== I386_EFLAGS_REGNUM
)
2148 val
= get_frame_register_unsigned (this_frame
, regnum
);
2150 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2153 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2154 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2156 if (regnum
== I386_ESP_REGNUM
2157 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2159 /* If the SP has been saved, but we don't know where, then this
2160 means that SAVED_SP_REG register was found unavailable back
2161 when we built the cache. */
2162 if (cache
->saved_sp
== 0)
2163 return frame_unwind_got_register (this_frame
, regnum
,
2164 cache
->saved_sp_reg
);
2166 return frame_unwind_got_constant (this_frame
, regnum
,
2170 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2171 return frame_unwind_got_memory (this_frame
, regnum
,
2172 cache
->saved_regs
[regnum
]);
2174 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2177 static const struct frame_unwind i386_frame_unwind
=
2180 i386_frame_unwind_stop_reason
,
2182 i386_frame_prev_register
,
2184 default_frame_sniffer
2187 /* Normal frames, but in a function epilogue. */
2189 /* Implement the stack_frame_destroyed_p gdbarch method.
2191 The epilogue is defined here as the 'ret' instruction, which will
2192 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2193 the function's stack frame. */
2196 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2199 struct compunit_symtab
*cust
;
2201 cust
= find_pc_compunit_symtab (pc
);
2202 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2205 if (target_read_memory (pc
, &insn
, 1))
2206 return 0; /* Can't read memory at pc. */
2208 if (insn
!= 0xc3) /* 'ret' instruction. */
2215 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2216 struct frame_info
*this_frame
,
2217 void **this_prologue_cache
)
2219 if (frame_relative_level (this_frame
) == 0)
2220 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2221 get_frame_pc (this_frame
));
2226 static struct i386_frame_cache
*
2227 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2229 struct i386_frame_cache
*cache
;
2233 return (struct i386_frame_cache
*) *this_cache
;
2235 cache
= i386_alloc_frame_cache ();
2236 *this_cache
= cache
;
2240 cache
->pc
= get_frame_func (this_frame
);
2242 /* At this point the stack looks as if we just entered the
2243 function, with the return address at the top of the
2245 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2246 cache
->base
= sp
+ cache
->sp_offset
;
2247 cache
->saved_sp
= cache
->base
+ 8;
2248 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2252 CATCH (ex
, RETURN_MASK_ERROR
)
2254 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2255 throw_exception (ex
);
2262 static enum unwind_stop_reason
2263 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2266 struct i386_frame_cache
*cache
=
2267 i386_epilogue_frame_cache (this_frame
, this_cache
);
2270 return UNWIND_UNAVAILABLE
;
2272 return UNWIND_NO_REASON
;
2276 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2278 struct frame_id
*this_id
)
2280 struct i386_frame_cache
*cache
=
2281 i386_epilogue_frame_cache (this_frame
, this_cache
);
2284 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2286 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2289 static struct value
*
2290 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2291 void **this_cache
, int regnum
)
2293 /* Make sure we've initialized the cache. */
2294 i386_epilogue_frame_cache (this_frame
, this_cache
);
2296 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2299 static const struct frame_unwind i386_epilogue_frame_unwind
=
2302 i386_epilogue_frame_unwind_stop_reason
,
2303 i386_epilogue_frame_this_id
,
2304 i386_epilogue_frame_prev_register
,
2306 i386_epilogue_frame_sniffer
2310 /* Stack-based trampolines. */
2312 /* These trampolines are used on cross x86 targets, when taking the
2313 address of a nested function. When executing these trampolines,
2314 no stack frame is set up, so we are in a similar situation as in
2315 epilogues and i386_epilogue_frame_this_id can be re-used. */
2317 /* Static chain passed in register. */
2319 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2321 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2322 { 5, { 0xb8 }, { 0xfe } },
2325 { 5, { 0xe9 }, { 0xff } },
2330 /* Static chain passed on stack (when regparm=3). */
2332 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2335 { 5, { 0x68 }, { 0xff } },
2338 { 5, { 0xe9 }, { 0xff } },
2343 /* Return whether PC points inside a stack trampoline. */
2346 i386_in_stack_tramp_p (CORE_ADDR pc
)
2351 /* A stack trampoline is detected if no name is associated
2352 to the current pc and if it points inside a trampoline
2355 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2359 if (target_read_memory (pc
, &insn
, 1))
2362 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2363 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2370 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2371 struct frame_info
*this_frame
,
2374 if (frame_relative_level (this_frame
) == 0)
2375 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2380 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2383 i386_epilogue_frame_unwind_stop_reason
,
2384 i386_epilogue_frame_this_id
,
2385 i386_epilogue_frame_prev_register
,
2387 i386_stack_tramp_frame_sniffer
2390 /* Generate a bytecode expression to get the value of the saved PC. */
2393 i386_gen_return_address (struct gdbarch
*gdbarch
,
2394 struct agent_expr
*ax
, struct axs_value
*value
,
2397 /* The following sequence assumes the traditional use of the base
2399 ax_reg (ax
, I386_EBP_REGNUM
);
2401 ax_simple (ax
, aop_add
);
2402 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2403 value
->kind
= axs_lvalue_memory
;
2407 /* Signal trampolines. */
2409 static struct i386_frame_cache
*
2410 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2412 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2413 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2414 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2415 struct i386_frame_cache
*cache
;
2420 return (struct i386_frame_cache
*) *this_cache
;
2422 cache
= i386_alloc_frame_cache ();
2426 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2427 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2429 addr
= tdep
->sigcontext_addr (this_frame
);
2430 if (tdep
->sc_reg_offset
)
2434 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2436 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2437 if (tdep
->sc_reg_offset
[i
] != -1)
2438 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2442 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2443 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2448 CATCH (ex
, RETURN_MASK_ERROR
)
2450 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2451 throw_exception (ex
);
2455 *this_cache
= cache
;
2459 static enum unwind_stop_reason
2460 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2463 struct i386_frame_cache
*cache
=
2464 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2467 return UNWIND_UNAVAILABLE
;
2469 return UNWIND_NO_REASON
;
2473 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2474 struct frame_id
*this_id
)
2476 struct i386_frame_cache
*cache
=
2477 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2480 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2483 /* See the end of i386_push_dummy_call. */
2484 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2488 static struct value
*
2489 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2490 void **this_cache
, int regnum
)
2492 /* Make sure we've initialized the cache. */
2493 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2495 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2499 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2500 struct frame_info
*this_frame
,
2501 void **this_prologue_cache
)
2503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2505 /* We shouldn't even bother if we don't have a sigcontext_addr
2507 if (tdep
->sigcontext_addr
== NULL
)
2510 if (tdep
->sigtramp_p
!= NULL
)
2512 if (tdep
->sigtramp_p (this_frame
))
2516 if (tdep
->sigtramp_start
!= 0)
2518 CORE_ADDR pc
= get_frame_pc (this_frame
);
2520 gdb_assert (tdep
->sigtramp_end
!= 0);
2521 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2528 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2531 i386_sigtramp_frame_unwind_stop_reason
,
2532 i386_sigtramp_frame_this_id
,
2533 i386_sigtramp_frame_prev_register
,
2535 i386_sigtramp_frame_sniffer
2540 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2542 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2547 static const struct frame_base i386_frame_base
=
2550 i386_frame_base_address
,
2551 i386_frame_base_address
,
2552 i386_frame_base_address
2555 static struct frame_id
2556 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2560 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2562 /* See the end of i386_push_dummy_call. */
2563 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2566 /* _Decimal128 function return values need 16-byte alignment on the
2570 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2572 return sp
& -(CORE_ADDR
)16;
2576 /* Figure out where the longjmp will land. Slurp the args out of the
2577 stack. We expect the first arg to be a pointer to the jmp_buf
2578 structure from which we extract the address that we will land at.
2579 This address is copied into PC. This routine returns non-zero on
2583 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2586 CORE_ADDR sp
, jb_addr
;
2587 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2588 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2589 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2591 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2592 longjmp will land. */
2593 if (jb_pc_offset
== -1)
2596 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2597 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2598 if (target_read_memory (sp
+ 4, buf
, 4))
2601 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2602 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2605 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2610 /* Check whether TYPE must be 16-byte-aligned when passed as a
2611 function argument. 16-byte vectors, _Decimal128 and structures or
2612 unions containing such types must be 16-byte-aligned; other
2613 arguments are 4-byte-aligned. */
2616 i386_16_byte_align_p (struct type
*type
)
2618 type
= check_typedef (type
);
2619 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2620 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2621 && TYPE_LENGTH (type
) == 16)
2623 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2624 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2625 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2626 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2629 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2631 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2638 /* Implementation for set_gdbarch_push_dummy_code. */
2641 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2642 struct value
**args
, int nargs
, struct type
*value_type
,
2643 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2644 struct regcache
*regcache
)
2646 /* Use 0xcc breakpoint - 1 byte. */
2650 /* Keep the stack aligned. */
2655 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2656 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2657 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2658 CORE_ADDR struct_addr
)
2660 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2666 /* Determine the total space required for arguments and struct
2667 return address in a first pass (allowing for 16-byte-aligned
2668 arguments), then push arguments in a second pass. */
2670 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2672 int args_space_used
= 0;
2678 /* Push value address. */
2679 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2680 write_memory (sp
, buf
, 4);
2681 args_space_used
+= 4;
2687 for (i
= 0; i
< nargs
; i
++)
2689 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2693 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2694 args_space_used
= align_up (args_space_used
, 16);
2696 write_memory (sp
+ args_space_used
,
2697 value_contents_all (args
[i
]), len
);
2698 /* The System V ABI says that:
2700 "An argument's size is increased, if necessary, to make it a
2701 multiple of [32-bit] words. This may require tail padding,
2702 depending on the size of the argument."
2704 This makes sure the stack stays word-aligned. */
2705 args_space_used
+= align_up (len
, 4);
2709 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2710 args_space
= align_up (args_space
, 16);
2711 args_space
+= align_up (len
, 4);
2719 /* The original System V ABI only requires word alignment,
2720 but modern incarnations need 16-byte alignment in order
2721 to support SSE. Since wasting a few bytes here isn't
2722 harmful we unconditionally enforce 16-byte alignment. */
2727 /* Store return address. */
2729 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2730 write_memory (sp
, buf
, 4);
2732 /* Finally, update the stack pointer... */
2733 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2734 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2736 /* ...and fake a frame pointer. */
2737 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2739 /* MarkK wrote: This "+ 8" is all over the place:
2740 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2741 i386_dummy_id). It's there, since all frame unwinders for
2742 a given target have to agree (within a certain margin) on the
2743 definition of the stack address of a frame. Otherwise frame id
2744 comparison might not work correctly. Since DWARF2/GCC uses the
2745 stack address *before* the function call as a frame's CFA. On
2746 the i386, when %ebp is used as a frame pointer, the offset
2747 between the contents %ebp and the CFA as defined by GCC. */
2751 /* These registers are used for returning integers (and on some
2752 targets also for returning `struct' and `union' values when their
2753 size and alignment match an integer type). */
2754 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2755 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2757 /* Read, for architecture GDBARCH, a function return value of TYPE
2758 from REGCACHE, and copy that into VALBUF. */
2761 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2762 struct regcache
*regcache
, gdb_byte
*valbuf
)
2764 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2765 int len
= TYPE_LENGTH (type
);
2766 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2768 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2770 if (tdep
->st0_regnum
< 0)
2772 warning (_("Cannot find floating-point return value."));
2773 memset (valbuf
, 0, len
);
2777 /* Floating-point return values can be found in %st(0). Convert
2778 its contents to the desired type. This is probably not
2779 exactly how it would happen on the target itself, but it is
2780 the best we can do. */
2781 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2782 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2786 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2787 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2789 if (len
<= low_size
)
2791 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2792 memcpy (valbuf
, buf
, len
);
2794 else if (len
<= (low_size
+ high_size
))
2796 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2797 memcpy (valbuf
, buf
, low_size
);
2798 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2799 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2802 internal_error (__FILE__
, __LINE__
,
2803 _("Cannot extract return value of %d bytes long."),
2808 /* Write, for architecture GDBARCH, a function return value of TYPE
2809 from VALBUF into REGCACHE. */
2812 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2813 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2815 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2816 int len
= TYPE_LENGTH (type
);
2818 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2821 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2823 if (tdep
->st0_regnum
< 0)
2825 warning (_("Cannot set floating-point return value."));
2829 /* Returning floating-point values is a bit tricky. Apart from
2830 storing the return value in %st(0), we have to simulate the
2831 state of the FPU at function return point. */
2833 /* Convert the value found in VALBUF to the extended
2834 floating-point format used by the FPU. This is probably
2835 not exactly how it would happen on the target itself, but
2836 it is the best we can do. */
2837 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2838 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2840 /* Set the top of the floating-point register stack to 7. The
2841 actual value doesn't really matter, but 7 is what a normal
2842 function return would end up with if the program started out
2843 with a freshly initialized FPU. */
2844 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2846 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2848 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2849 the floating-point register stack to 7, the appropriate value
2850 for the tag word is 0x3fff. */
2851 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2855 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2856 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2858 if (len
<= low_size
)
2859 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2860 else if (len
<= (low_size
+ high_size
))
2862 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2863 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2864 len
- low_size
, valbuf
+ low_size
);
2867 internal_error (__FILE__
, __LINE__
,
2868 _("Cannot store return value of %d bytes long."), len
);
2873 /* This is the variable that is set with "set struct-convention", and
2874 its legitimate values. */
2875 static const char default_struct_convention
[] = "default";
2876 static const char pcc_struct_convention
[] = "pcc";
2877 static const char reg_struct_convention
[] = "reg";
2878 static const char *const valid_conventions
[] =
2880 default_struct_convention
,
2881 pcc_struct_convention
,
2882 reg_struct_convention
,
2885 static const char *struct_convention
= default_struct_convention
;
2887 /* Return non-zero if TYPE, which is assumed to be a structure,
2888 a union type, or an array type, should be returned in registers
2889 for architecture GDBARCH. */
2892 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2894 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2895 enum type_code code
= TYPE_CODE (type
);
2896 int len
= TYPE_LENGTH (type
);
2898 gdb_assert (code
== TYPE_CODE_STRUCT
2899 || code
== TYPE_CODE_UNION
2900 || code
== TYPE_CODE_ARRAY
);
2902 if (struct_convention
== pcc_struct_convention
2903 || (struct_convention
== default_struct_convention
2904 && tdep
->struct_return
== pcc_struct_return
))
2907 /* Structures consisting of a single `float', `double' or 'long
2908 double' member are returned in %st(0). */
2909 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2911 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2912 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2913 return (len
== 4 || len
== 8 || len
== 12);
2916 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2919 /* Determine, for architecture GDBARCH, how a return value of TYPE
2920 should be returned. If it is supposed to be returned in registers,
2921 and READBUF is non-zero, read the appropriate value from REGCACHE,
2922 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2923 from WRITEBUF into REGCACHE. */
2925 static enum return_value_convention
2926 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2927 struct type
*type
, struct regcache
*regcache
,
2928 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2930 enum type_code code
= TYPE_CODE (type
);
2932 if (((code
== TYPE_CODE_STRUCT
2933 || code
== TYPE_CODE_UNION
2934 || code
== TYPE_CODE_ARRAY
)
2935 && !i386_reg_struct_return_p (gdbarch
, type
))
2936 /* Complex double and long double uses the struct return covention. */
2937 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2938 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2939 /* 128-bit decimal float uses the struct return convention. */
2940 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2942 /* The System V ABI says that:
2944 "A function that returns a structure or union also sets %eax
2945 to the value of the original address of the caller's area
2946 before it returns. Thus when the caller receives control
2947 again, the address of the returned object resides in register
2948 %eax and can be used to access the object."
2950 So the ABI guarantees that we can always find the return
2951 value just after the function has returned. */
2953 /* Note that the ABI doesn't mention functions returning arrays,
2954 which is something possible in certain languages such as Ada.
2955 In this case, the value is returned as if it was wrapped in
2956 a record, so the convention applied to records also applies
2963 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2964 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2967 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2970 /* This special case is for structures consisting of a single
2971 `float', `double' or 'long double' member. These structures are
2972 returned in %st(0). For these structures, we call ourselves
2973 recursively, changing TYPE into the type of the first member of
2974 the structure. Since that should work for all structures that
2975 have only one member, we don't bother to check the member's type
2977 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2979 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2980 return i386_return_value (gdbarch
, function
, type
, regcache
,
2985 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2987 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2989 return RETURN_VALUE_REGISTER_CONVENTION
;
2994 i387_ext_type (struct gdbarch
*gdbarch
)
2996 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2998 if (!tdep
->i387_ext_type
)
3000 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3001 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3004 return tdep
->i387_ext_type
;
3007 /* Construct type for pseudo BND registers. We can't use
3008 tdesc_find_type since a complement of one value has to be used
3009 to describe the upper bound. */
3011 static struct type
*
3012 i386_bnd_type (struct gdbarch
*gdbarch
)
3014 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3017 if (!tdep
->i386_bnd_type
)
3020 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3022 /* The type we're building is described bellow: */
3027 void *ubound
; /* One complement of raw ubound field. */
3031 t
= arch_composite_type (gdbarch
,
3032 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3034 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3035 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3037 TYPE_NAME (t
) = "builtin_type_bound128";
3038 tdep
->i386_bnd_type
= t
;
3041 return tdep
->i386_bnd_type
;
3044 /* Construct vector type for pseudo ZMM registers. We can't use
3045 tdesc_find_type since ZMM isn't described in target description. */
3047 static struct type
*
3048 i386_zmm_type (struct gdbarch
*gdbarch
)
3050 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3052 if (!tdep
->i386_zmm_type
)
3054 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3056 /* The type we're building is this: */
3058 union __gdb_builtin_type_vec512i
3060 int128_t uint128
[4];
3061 int64_t v4_int64
[8];
3062 int32_t v8_int32
[16];
3063 int16_t v16_int16
[32];
3064 int8_t v32_int8
[64];
3065 double v4_double
[8];
3072 t
= arch_composite_type (gdbarch
,
3073 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3074 append_composite_type_field (t
, "v16_float",
3075 init_vector_type (bt
->builtin_float
, 16));
3076 append_composite_type_field (t
, "v8_double",
3077 init_vector_type (bt
->builtin_double
, 8));
3078 append_composite_type_field (t
, "v64_int8",
3079 init_vector_type (bt
->builtin_int8
, 64));
3080 append_composite_type_field (t
, "v32_int16",
3081 init_vector_type (bt
->builtin_int16
, 32));
3082 append_composite_type_field (t
, "v16_int32",
3083 init_vector_type (bt
->builtin_int32
, 16));
3084 append_composite_type_field (t
, "v8_int64",
3085 init_vector_type (bt
->builtin_int64
, 8));
3086 append_composite_type_field (t
, "v4_int128",
3087 init_vector_type (bt
->builtin_int128
, 4));
3089 TYPE_VECTOR (t
) = 1;
3090 TYPE_NAME (t
) = "builtin_type_vec512i";
3091 tdep
->i386_zmm_type
= t
;
3094 return tdep
->i386_zmm_type
;
3097 /* Construct vector type for pseudo YMM registers. We can't use
3098 tdesc_find_type since YMM isn't described in target description. */
3100 static struct type
*
3101 i386_ymm_type (struct gdbarch
*gdbarch
)
3103 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3105 if (!tdep
->i386_ymm_type
)
3107 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3109 /* The type we're building is this: */
3111 union __gdb_builtin_type_vec256i
3113 int128_t uint128
[2];
3114 int64_t v2_int64
[4];
3115 int32_t v4_int32
[8];
3116 int16_t v8_int16
[16];
3117 int8_t v16_int8
[32];
3118 double v2_double
[4];
3125 t
= arch_composite_type (gdbarch
,
3126 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3127 append_composite_type_field (t
, "v8_float",
3128 init_vector_type (bt
->builtin_float
, 8));
3129 append_composite_type_field (t
, "v4_double",
3130 init_vector_type (bt
->builtin_double
, 4));
3131 append_composite_type_field (t
, "v32_int8",
3132 init_vector_type (bt
->builtin_int8
, 32));
3133 append_composite_type_field (t
, "v16_int16",
3134 init_vector_type (bt
->builtin_int16
, 16));
3135 append_composite_type_field (t
, "v8_int32",
3136 init_vector_type (bt
->builtin_int32
, 8));
3137 append_composite_type_field (t
, "v4_int64",
3138 init_vector_type (bt
->builtin_int64
, 4));
3139 append_composite_type_field (t
, "v2_int128",
3140 init_vector_type (bt
->builtin_int128
, 2));
3142 TYPE_VECTOR (t
) = 1;
3143 TYPE_NAME (t
) = "builtin_type_vec256i";
3144 tdep
->i386_ymm_type
= t
;
3147 return tdep
->i386_ymm_type
;
3150 /* Construct vector type for MMX registers. */
3151 static struct type
*
3152 i386_mmx_type (struct gdbarch
*gdbarch
)
3154 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3156 if (!tdep
->i386_mmx_type
)
3158 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3160 /* The type we're building is this: */
3162 union __gdb_builtin_type_vec64i
3165 int32_t v2_int32
[2];
3166 int16_t v4_int16
[4];
3173 t
= arch_composite_type (gdbarch
,
3174 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3176 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3177 append_composite_type_field (t
, "v2_int32",
3178 init_vector_type (bt
->builtin_int32
, 2));
3179 append_composite_type_field (t
, "v4_int16",
3180 init_vector_type (bt
->builtin_int16
, 4));
3181 append_composite_type_field (t
, "v8_int8",
3182 init_vector_type (bt
->builtin_int8
, 8));
3184 TYPE_VECTOR (t
) = 1;
3185 TYPE_NAME (t
) = "builtin_type_vec64i";
3186 tdep
->i386_mmx_type
= t
;
3189 return tdep
->i386_mmx_type
;
3192 /* Return the GDB type object for the "standard" data type of data in
3196 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3198 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3199 return i386_bnd_type (gdbarch
);
3200 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3201 return i386_mmx_type (gdbarch
);
3202 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3203 return i386_ymm_type (gdbarch
);
3204 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3205 return i386_ymm_type (gdbarch
);
3206 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3207 return i386_zmm_type (gdbarch
);
3210 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3211 if (i386_byte_regnum_p (gdbarch
, regnum
))
3212 return bt
->builtin_int8
;
3213 else if (i386_word_regnum_p (gdbarch
, regnum
))
3214 return bt
->builtin_int16
;
3215 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3216 return bt
->builtin_int32
;
3217 else if (i386_k_regnum_p (gdbarch
, regnum
))
3218 return bt
->builtin_int64
;
3221 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3224 /* Map a cooked register onto a raw register or memory. For the i386,
3225 the MMX registers need to be mapped onto floating point registers. */
3228 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
3230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
3235 mmxreg
= regnum
- tdep
->mm0_regnum
;
3236 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
3237 tos
= (fstat
>> 11) & 0x7;
3238 fpreg
= (mmxreg
+ tos
) % 8;
3240 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3243 /* A helper function for us by i386_pseudo_register_read_value and
3244 amd64_pseudo_register_read_value. It does all the work but reads
3245 the data into an already-allocated value. */
3248 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3249 struct regcache
*regcache
,
3251 struct value
*result_value
)
3253 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3254 enum register_status status
;
3255 gdb_byte
*buf
= value_contents_raw (result_value
);
3257 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3259 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3261 /* Extract (always little endian). */
3262 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3263 if (status
!= REG_VALID
)
3264 mark_value_bytes_unavailable (result_value
, 0,
3265 TYPE_LENGTH (value_type (result_value
)));
3267 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3271 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3272 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3274 regnum
-= tdep
->bnd0_regnum
;
3276 /* Extract (always little endian). Read lower 128bits. */
3277 status
= regcache_raw_read (regcache
,
3278 I387_BND0R_REGNUM (tdep
) + regnum
,
3280 if (status
!= REG_VALID
)
3281 mark_value_bytes_unavailable (result_value
, 0, 16);
3284 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3285 LONGEST upper
, lower
;
3286 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3288 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3289 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3292 memcpy (buf
, &lower
, size
);
3293 memcpy (buf
+ size
, &upper
, size
);
3296 else if (i386_k_regnum_p (gdbarch
, regnum
))
3298 regnum
-= tdep
->k0_regnum
;
3300 /* Extract (always little endian). */
3301 status
= regcache_raw_read (regcache
,
3302 tdep
->k0_regnum
+ regnum
,
3304 if (status
!= REG_VALID
)
3305 mark_value_bytes_unavailable (result_value
, 0, 8);
3307 memcpy (buf
, raw_buf
, 8);
3309 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3311 regnum
-= tdep
->zmm0_regnum
;
3313 if (regnum
< num_lower_zmm_regs
)
3315 /* Extract (always little endian). Read lower 128bits. */
3316 status
= regcache_raw_read (regcache
,
3317 I387_XMM0_REGNUM (tdep
) + regnum
,
3319 if (status
!= REG_VALID
)
3320 mark_value_bytes_unavailable (result_value
, 0, 16);
3322 memcpy (buf
, raw_buf
, 16);
3324 /* Extract (always little endian). Read upper 128bits. */
3325 status
= regcache_raw_read (regcache
,
3326 tdep
->ymm0h_regnum
+ regnum
,
3328 if (status
!= REG_VALID
)
3329 mark_value_bytes_unavailable (result_value
, 16, 16);
3331 memcpy (buf
+ 16, raw_buf
, 16);
3335 /* Extract (always little endian). Read lower 128bits. */
3336 status
= regcache_raw_read (regcache
,
3337 I387_XMM16_REGNUM (tdep
) + regnum
3338 - num_lower_zmm_regs
,
3340 if (status
!= REG_VALID
)
3341 mark_value_bytes_unavailable (result_value
, 0, 16);
3343 memcpy (buf
, raw_buf
, 16);
3345 /* Extract (always little endian). Read upper 128bits. */
3346 status
= regcache_raw_read (regcache
,
3347 I387_YMM16H_REGNUM (tdep
) + regnum
3348 - num_lower_zmm_regs
,
3350 if (status
!= REG_VALID
)
3351 mark_value_bytes_unavailable (result_value
, 16, 16);
3353 memcpy (buf
+ 16, raw_buf
, 16);
3356 /* Read upper 256bits. */
3357 status
= regcache_raw_read (regcache
,
3358 tdep
->zmm0h_regnum
+ regnum
,
3360 if (status
!= REG_VALID
)
3361 mark_value_bytes_unavailable (result_value
, 32, 32);
3363 memcpy (buf
+ 32, raw_buf
, 32);
3365 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3367 regnum
-= tdep
->ymm0_regnum
;
3369 /* Extract (always little endian). Read lower 128bits. */
3370 status
= regcache_raw_read (regcache
,
3371 I387_XMM0_REGNUM (tdep
) + regnum
,
3373 if (status
!= REG_VALID
)
3374 mark_value_bytes_unavailable (result_value
, 0, 16);
3376 memcpy (buf
, raw_buf
, 16);
3377 /* Read upper 128bits. */
3378 status
= regcache_raw_read (regcache
,
3379 tdep
->ymm0h_regnum
+ regnum
,
3381 if (status
!= REG_VALID
)
3382 mark_value_bytes_unavailable (result_value
, 16, 32);
3384 memcpy (buf
+ 16, raw_buf
, 16);
3386 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3388 regnum
-= tdep
->ymm16_regnum
;
3389 /* Extract (always little endian). Read lower 128bits. */
3390 status
= regcache_raw_read (regcache
,
3391 I387_XMM16_REGNUM (tdep
) + regnum
,
3393 if (status
!= REG_VALID
)
3394 mark_value_bytes_unavailable (result_value
, 0, 16);
3396 memcpy (buf
, raw_buf
, 16);
3397 /* Read upper 128bits. */
3398 status
= regcache_raw_read (regcache
,
3399 tdep
->ymm16h_regnum
+ regnum
,
3401 if (status
!= REG_VALID
)
3402 mark_value_bytes_unavailable (result_value
, 16, 16);
3404 memcpy (buf
+ 16, raw_buf
, 16);
3406 else if (i386_word_regnum_p (gdbarch
, regnum
))
3408 int gpnum
= regnum
- tdep
->ax_regnum
;
3410 /* Extract (always little endian). */
3411 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3412 if (status
!= REG_VALID
)
3413 mark_value_bytes_unavailable (result_value
, 0,
3414 TYPE_LENGTH (value_type (result_value
)));
3416 memcpy (buf
, raw_buf
, 2);
3418 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3420 int gpnum
= regnum
- tdep
->al_regnum
;
3422 /* Extract (always little endian). We read both lower and
3424 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3425 if (status
!= REG_VALID
)
3426 mark_value_bytes_unavailable (result_value
, 0,
3427 TYPE_LENGTH (value_type (result_value
)));
3428 else if (gpnum
>= 4)
3429 memcpy (buf
, raw_buf
+ 1, 1);
3431 memcpy (buf
, raw_buf
, 1);
3434 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3438 static struct value
*
3439 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3440 struct regcache
*regcache
,
3443 struct value
*result
;
3445 result
= allocate_value (register_type (gdbarch
, regnum
));
3446 VALUE_LVAL (result
) = lval_register
;
3447 VALUE_REGNUM (result
) = regnum
;
3449 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3455 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3456 int regnum
, const gdb_byte
*buf
)
3458 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3460 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3462 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3465 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3466 /* ... Modify ... (always little endian). */
3467 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3469 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3473 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3475 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3477 ULONGEST upper
, lower
;
3478 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3479 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3481 /* New values from input value. */
3482 regnum
-= tdep
->bnd0_regnum
;
3483 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3484 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3486 /* Fetching register buffer. */
3487 regcache_raw_read (regcache
,
3488 I387_BND0R_REGNUM (tdep
) + regnum
,
3493 /* Set register bits. */
3494 memcpy (raw_buf
, &lower
, 8);
3495 memcpy (raw_buf
+ 8, &upper
, 8);
3498 regcache_raw_write (regcache
,
3499 I387_BND0R_REGNUM (tdep
) + regnum
,
3502 else if (i386_k_regnum_p (gdbarch
, regnum
))
3504 regnum
-= tdep
->k0_regnum
;
3506 regcache_raw_write (regcache
,
3507 tdep
->k0_regnum
+ regnum
,
3510 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3512 regnum
-= tdep
->zmm0_regnum
;
3514 if (regnum
< num_lower_zmm_regs
)
3516 /* Write lower 128bits. */
3517 regcache_raw_write (regcache
,
3518 I387_XMM0_REGNUM (tdep
) + regnum
,
3520 /* Write upper 128bits. */
3521 regcache_raw_write (regcache
,
3522 I387_YMM0_REGNUM (tdep
) + regnum
,
3527 /* Write lower 128bits. */
3528 regcache_raw_write (regcache
,
3529 I387_XMM16_REGNUM (tdep
) + regnum
3530 - num_lower_zmm_regs
,
3532 /* Write upper 128bits. */
3533 regcache_raw_write (regcache
,
3534 I387_YMM16H_REGNUM (tdep
) + regnum
3535 - num_lower_zmm_regs
,
3538 /* Write upper 256bits. */
3539 regcache_raw_write (regcache
,
3540 tdep
->zmm0h_regnum
+ regnum
,
3543 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3545 regnum
-= tdep
->ymm0_regnum
;
3547 /* ... Write lower 128bits. */
3548 regcache_raw_write (regcache
,
3549 I387_XMM0_REGNUM (tdep
) + regnum
,
3551 /* ... Write upper 128bits. */
3552 regcache_raw_write (regcache
,
3553 tdep
->ymm0h_regnum
+ regnum
,
3556 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3558 regnum
-= tdep
->ymm16_regnum
;
3560 /* ... Write lower 128bits. */
3561 regcache_raw_write (regcache
,
3562 I387_XMM16_REGNUM (tdep
) + regnum
,
3564 /* ... Write upper 128bits. */
3565 regcache_raw_write (regcache
,
3566 tdep
->ymm16h_regnum
+ regnum
,
3569 else if (i386_word_regnum_p (gdbarch
, regnum
))
3571 int gpnum
= regnum
- tdep
->ax_regnum
;
3574 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3575 /* ... Modify ... (always little endian). */
3576 memcpy (raw_buf
, buf
, 2);
3578 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3580 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3582 int gpnum
= regnum
- tdep
->al_regnum
;
3584 /* Read ... We read both lower and upper registers. */
3585 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3586 /* ... Modify ... (always little endian). */
3588 memcpy (raw_buf
+ 1, buf
, 1);
3590 memcpy (raw_buf
, buf
, 1);
3592 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3595 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3599 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3602 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3603 struct agent_expr
*ax
, int regnum
)
3605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3607 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3609 /* MMX to FPU register mapping depends on current TOS. Let's just
3610 not care and collect everything... */
3613 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3614 for (i
= 0; i
< 8; i
++)
3615 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3618 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3620 regnum
-= tdep
->bnd0_regnum
;
3621 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3624 else if (i386_k_regnum_p (gdbarch
, regnum
))
3626 regnum
-= tdep
->k0_regnum
;
3627 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3630 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3632 regnum
-= tdep
->zmm0_regnum
;
3633 if (regnum
< num_lower_zmm_regs
)
3635 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3636 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3640 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3641 - num_lower_zmm_regs
);
3642 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3643 - num_lower_zmm_regs
);
3645 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3648 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3650 regnum
-= tdep
->ymm0_regnum
;
3651 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3652 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3655 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3657 regnum
-= tdep
->ymm16_regnum
;
3658 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3659 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3662 else if (i386_word_regnum_p (gdbarch
, regnum
))
3664 int gpnum
= regnum
- tdep
->ax_regnum
;
3666 ax_reg_mask (ax
, gpnum
);
3669 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3671 int gpnum
= regnum
- tdep
->al_regnum
;
3673 ax_reg_mask (ax
, gpnum
% 4);
3677 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3682 /* Return the register number of the register allocated by GCC after
3683 REGNUM, or -1 if there is no such register. */
3686 i386_next_regnum (int regnum
)
3688 /* GCC allocates the registers in the order:
3690 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3692 Since storing a variable in %esp doesn't make any sense we return
3693 -1 for %ebp and for %esp itself. */
3694 static int next_regnum
[] =
3696 I386_EDX_REGNUM
, /* Slot for %eax. */
3697 I386_EBX_REGNUM
, /* Slot for %ecx. */
3698 I386_ECX_REGNUM
, /* Slot for %edx. */
3699 I386_ESI_REGNUM
, /* Slot for %ebx. */
3700 -1, -1, /* Slots for %esp and %ebp. */
3701 I386_EDI_REGNUM
, /* Slot for %esi. */
3702 I386_EBP_REGNUM
/* Slot for %edi. */
3705 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3706 return next_regnum
[regnum
];
3711 /* Return nonzero if a value of type TYPE stored in register REGNUM
3712 needs any special handling. */
3715 i386_convert_register_p (struct gdbarch
*gdbarch
,
3716 int regnum
, struct type
*type
)
3718 int len
= TYPE_LENGTH (type
);
3720 /* Values may be spread across multiple registers. Most debugging
3721 formats aren't expressive enough to specify the locations, so
3722 some heuristics is involved. Right now we only handle types that
3723 have a length that is a multiple of the word size, since GCC
3724 doesn't seem to put any other types into registers. */
3725 if (len
> 4 && len
% 4 == 0)
3727 int last_regnum
= regnum
;
3731 last_regnum
= i386_next_regnum (last_regnum
);
3735 if (last_regnum
!= -1)
3739 return i387_convert_register_p (gdbarch
, regnum
, type
);
3742 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3743 return its contents in TO. */
3746 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3747 struct type
*type
, gdb_byte
*to
,
3748 int *optimizedp
, int *unavailablep
)
3750 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3751 int len
= TYPE_LENGTH (type
);
3753 if (i386_fp_regnum_p (gdbarch
, regnum
))
3754 return i387_register_to_value (frame
, regnum
, type
, to
,
3755 optimizedp
, unavailablep
);
3757 /* Read a value spread across multiple registers. */
3759 gdb_assert (len
> 4 && len
% 4 == 0);
3763 gdb_assert (regnum
!= -1);
3764 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3766 if (!get_frame_register_bytes (frame
, regnum
, 0,
3767 register_size (gdbarch
, regnum
),
3768 to
, optimizedp
, unavailablep
))
3771 regnum
= i386_next_regnum (regnum
);
3776 *optimizedp
= *unavailablep
= 0;
3780 /* Write the contents FROM of a value of type TYPE into register
3781 REGNUM in frame FRAME. */
3784 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3785 struct type
*type
, const gdb_byte
*from
)
3787 int len
= TYPE_LENGTH (type
);
3789 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3791 i387_value_to_register (frame
, regnum
, type
, from
);
3795 /* Write a value spread across multiple registers. */
3797 gdb_assert (len
> 4 && len
% 4 == 0);
3801 gdb_assert (regnum
!= -1);
3802 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3804 put_frame_register (frame
, regnum
, from
);
3805 regnum
= i386_next_regnum (regnum
);
3811 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3812 in the general-purpose register set REGSET to register cache
3813 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3816 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3817 int regnum
, const void *gregs
, size_t len
)
3819 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3820 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3821 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3824 gdb_assert (len
>= tdep
->sizeof_gregset
);
3826 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3828 if ((regnum
== i
|| regnum
== -1)
3829 && tdep
->gregset_reg_offset
[i
] != -1)
3830 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3834 /* Collect register REGNUM from the register cache REGCACHE and store
3835 it in the buffer specified by GREGS and LEN as described by the
3836 general-purpose register set REGSET. If REGNUM is -1, do this for
3837 all registers in REGSET. */
3840 i386_collect_gregset (const struct regset
*regset
,
3841 const struct regcache
*regcache
,
3842 int regnum
, void *gregs
, size_t len
)
3844 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3845 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3846 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3849 gdb_assert (len
>= tdep
->sizeof_gregset
);
3851 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3853 if ((regnum
== i
|| regnum
== -1)
3854 && tdep
->gregset_reg_offset
[i
] != -1)
3855 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3859 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3860 in the floating-point register set REGSET to register cache
3861 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3864 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3865 int regnum
, const void *fpregs
, size_t len
)
3867 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3868 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3870 if (len
== I387_SIZEOF_FXSAVE
)
3872 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3876 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3877 i387_supply_fsave (regcache
, regnum
, fpregs
);
3880 /* Collect register REGNUM from the register cache REGCACHE and store
3881 it in the buffer specified by FPREGS and LEN as described by the
3882 floating-point register set REGSET. If REGNUM is -1, do this for
3883 all registers in REGSET. */
3886 i386_collect_fpregset (const struct regset
*regset
,
3887 const struct regcache
*regcache
,
3888 int regnum
, void *fpregs
, size_t len
)
3890 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3891 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3893 if (len
== I387_SIZEOF_FXSAVE
)
3895 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3899 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3900 i387_collect_fsave (regcache
, regnum
, fpregs
);
3903 /* Register set definitions. */
3905 const struct regset i386_gregset
=
3907 NULL
, i386_supply_gregset
, i386_collect_gregset
3910 const struct regset i386_fpregset
=
3912 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3915 /* Default iterator over core file register note sections. */
3918 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3919 iterate_over_regset_sections_cb
*cb
,
3921 const struct regcache
*regcache
)
3923 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3925 cb (".reg", tdep
->sizeof_gregset
, &i386_gregset
, NULL
, cb_data
);
3926 if (tdep
->sizeof_fpregset
)
3927 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
3931 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3934 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3935 CORE_ADDR pc
, char *name
)
3937 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3938 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3941 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3943 unsigned long indirect
=
3944 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3945 struct minimal_symbol
*indsym
=
3946 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3947 const char *symname
= indsym
? MSYMBOL_LINKAGE_NAME (indsym
) : 0;
3951 if (startswith (symname
, "__imp_")
3952 || startswith (symname
, "_imp_"))
3954 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3957 return 0; /* Not a trampoline. */
3961 /* Return whether the THIS_FRAME corresponds to a sigtramp
3965 i386_sigtramp_p (struct frame_info
*this_frame
)
3967 CORE_ADDR pc
= get_frame_pc (this_frame
);
3970 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3971 return (name
&& strcmp ("_sigtramp", name
) == 0);
3975 /* We have two flavours of disassembly. The machinery on this page
3976 deals with switching between those. */
3979 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3981 gdb_assert (disassembly_flavor
== att_flavor
3982 || disassembly_flavor
== intel_flavor
);
3984 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3985 constified, cast to prevent a compiler warning. */
3986 info
->disassembler_options
= (char *) disassembly_flavor
;
3988 return print_insn_i386 (pc
, info
);
3992 /* There are a few i386 architecture variants that differ only
3993 slightly from the generic i386 target. For now, we don't give them
3994 their own source file, but include them here. As a consequence,
3995 they'll always be included. */
3997 /* System V Release 4 (SVR4). */
3999 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4003 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4005 CORE_ADDR pc
= get_frame_pc (this_frame
);
4008 /* The origin of these symbols is currently unknown. */
4009 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4010 return (name
&& (strcmp ("_sigreturn", name
) == 0
4011 || strcmp ("sigvechandler", name
) == 0));
4014 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4015 address of the associated sigcontext (ucontext) structure. */
4018 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4020 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4021 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4025 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4026 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4028 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4033 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4037 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4039 return (*s
== '$' /* Literal number. */
4040 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4041 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4042 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4045 /* Helper function for i386_stap_parse_special_token.
4047 This function parses operands of the form `-8+3+1(%rbp)', which
4048 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4050 Return 1 if the operand was parsed successfully, zero
4054 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4055 struct stap_parse_info
*p
)
4057 const char *s
= p
->arg
;
4059 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4063 long displacements
[3];
4079 if (!isdigit ((unsigned char) *s
))
4082 displacements
[0] = strtol (s
, &endp
, 10);
4085 if (*s
!= '+' && *s
!= '-')
4087 /* We are not dealing with a triplet. */
4100 if (!isdigit ((unsigned char) *s
))
4103 displacements
[1] = strtol (s
, &endp
, 10);
4106 if (*s
!= '+' && *s
!= '-')
4108 /* We are not dealing with a triplet. */
4121 if (!isdigit ((unsigned char) *s
))
4124 displacements
[2] = strtol (s
, &endp
, 10);
4127 if (*s
!= '(' || s
[1] != '%')
4133 while (isalnum (*s
))
4139 len
= s
- start
- 1;
4140 regname
= (char *) alloca (len
+ 1);
4142 strncpy (regname
, start
, len
);
4143 regname
[len
] = '\0';
4145 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4146 error (_("Invalid register name `%s' on expression `%s'."),
4147 regname
, p
->saved_arg
);
4149 for (i
= 0; i
< 3; i
++)
4151 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4153 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4154 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4155 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4157 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4160 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4163 write_exp_string (&p
->pstate
, str
);
4164 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4166 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4167 write_exp_elt_type (&p
->pstate
,
4168 builtin_type (gdbarch
)->builtin_data_ptr
);
4169 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4171 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4172 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4173 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4175 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4176 write_exp_elt_type (&p
->pstate
,
4177 lookup_pointer_type (p
->arg_type
));
4178 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4180 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4190 /* Helper function for i386_stap_parse_special_token.
4192 This function parses operands of the form `register base +
4193 (register index * size) + offset', as represented in
4194 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4196 Return 1 if the operand was parsed successfully, zero
4200 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4201 struct stap_parse_info
*p
)
4203 const char *s
= p
->arg
;
4205 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4207 int offset_minus
= 0;
4216 struct stoken base_token
, index_token
;
4226 if (offset_minus
&& !isdigit (*s
))
4233 offset
= strtol (s
, &endp
, 10);
4237 if (*s
!= '(' || s
[1] != '%')
4243 while (isalnum (*s
))
4246 if (*s
!= ',' || s
[1] != '%')
4249 len_base
= s
- start
;
4250 base
= (char *) alloca (len_base
+ 1);
4251 strncpy (base
, start
, len_base
);
4252 base
[len_base
] = '\0';
4254 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4255 error (_("Invalid register name `%s' on expression `%s'."),
4256 base
, p
->saved_arg
);
4261 while (isalnum (*s
))
4264 len_index
= s
- start
;
4265 index
= (char *) alloca (len_index
+ 1);
4266 strncpy (index
, start
, len_index
);
4267 index
[len_index
] = '\0';
4269 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4270 error (_("Invalid register name `%s' on expression `%s'."),
4271 index
, p
->saved_arg
);
4273 if (*s
!= ',' && *s
!= ')')
4289 size
= strtol (s
, &endp
, 10);
4300 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4301 write_exp_elt_type (&p
->pstate
,
4302 builtin_type (gdbarch
)->builtin_long
);
4303 write_exp_elt_longcst (&p
->pstate
, offset
);
4304 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4306 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4309 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4310 base_token
.ptr
= base
;
4311 base_token
.length
= len_base
;
4312 write_exp_string (&p
->pstate
, base_token
);
4313 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4316 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4318 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4319 index_token
.ptr
= index
;
4320 index_token
.length
= len_index
;
4321 write_exp_string (&p
->pstate
, index_token
);
4322 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4326 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4327 write_exp_elt_type (&p
->pstate
,
4328 builtin_type (gdbarch
)->builtin_long
);
4329 write_exp_elt_longcst (&p
->pstate
, size
);
4330 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4332 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4333 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4336 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4338 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4339 write_exp_elt_type (&p
->pstate
,
4340 lookup_pointer_type (p
->arg_type
));
4341 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4343 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4353 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4357 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4358 struct stap_parse_info
*p
)
4360 /* In order to parse special tokens, we use a state-machine that go
4361 through every known token and try to get a match. */
4365 THREE_ARG_DISPLACEMENT
,
4370 current_state
= TRIPLET
;
4372 /* The special tokens to be parsed here are:
4374 - `register base + (register index * size) + offset', as represented
4375 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4377 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4378 `*(-8 + 3 - 1 + (void *) $eax)'. */
4380 while (current_state
!= DONE
)
4382 switch (current_state
)
4385 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4389 case THREE_ARG_DISPLACEMENT
:
4390 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4395 /* Advancing to the next state. */
4404 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4405 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4408 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4410 return "(x86_64|i.86)";
4418 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4420 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4421 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4422 static const char *const stap_register_indirection_prefixes
[] = { "(",
4424 static const char *const stap_register_indirection_suffixes
[] = { ")",
4427 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4428 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4430 /* Registering SystemTap handlers. */
4431 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4432 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4433 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4434 stap_register_indirection_prefixes
);
4435 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4436 stap_register_indirection_suffixes
);
4437 set_gdbarch_stap_is_single_operand (gdbarch
,
4438 i386_stap_is_single_operand
);
4439 set_gdbarch_stap_parse_special_token (gdbarch
,
4440 i386_stap_parse_special_token
);
4442 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
4445 /* System V Release 4 (SVR4). */
4448 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4450 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4452 /* System V Release 4 uses ELF. */
4453 i386_elf_init_abi (info
, gdbarch
);
4455 /* System V Release 4 has shared libraries. */
4456 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4458 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4459 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4460 tdep
->sc_pc_offset
= 36 + 14 * 4;
4461 tdep
->sc_sp_offset
= 36 + 17 * 4;
4463 tdep
->jb_pc_offset
= 20;
4469 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4471 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4473 /* DJGPP doesn't have any special frames for signal handlers. */
4474 tdep
->sigtramp_p
= NULL
;
4476 tdep
->jb_pc_offset
= 36;
4478 /* DJGPP does not support the SSE registers. */
4479 if (! tdesc_has_registers (info
.target_desc
))
4480 tdep
->tdesc
= tdesc_i386_mmx
;
4482 /* Native compiler is GCC, which uses the SVR4 register numbering
4483 even in COFF and STABS. See the comment in i386_gdbarch_init,
4484 before the calls to set_gdbarch_stab_reg_to_regnum and
4485 set_gdbarch_sdb_reg_to_regnum. */
4486 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4487 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4489 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
4491 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
4495 /* i386 register groups. In addition to the normal groups, add "mmx"
4498 static struct reggroup
*i386_sse_reggroup
;
4499 static struct reggroup
*i386_mmx_reggroup
;
4502 i386_init_reggroups (void)
4504 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4505 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4509 i386_add_reggroups (struct gdbarch
*gdbarch
)
4511 reggroup_add (gdbarch
, i386_sse_reggroup
);
4512 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4513 reggroup_add (gdbarch
, general_reggroup
);
4514 reggroup_add (gdbarch
, float_reggroup
);
4515 reggroup_add (gdbarch
, all_reggroup
);
4516 reggroup_add (gdbarch
, save_reggroup
);
4517 reggroup_add (gdbarch
, restore_reggroup
);
4518 reggroup_add (gdbarch
, vector_reggroup
);
4519 reggroup_add (gdbarch
, system_reggroup
);
4523 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4524 struct reggroup
*group
)
4526 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4527 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4528 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4529 bndr_regnum_p
, bnd_regnum_p
, k_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4530 zmm_avx512_regnum_p
, mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4531 avx512_p
, avx_p
, sse_p
;
4533 /* Don't include pseudo registers, except for MMX, in any register
4535 if (i386_byte_regnum_p (gdbarch
, regnum
))
4538 if (i386_word_regnum_p (gdbarch
, regnum
))
4541 if (i386_dword_regnum_p (gdbarch
, regnum
))
4544 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4545 if (group
== i386_mmx_reggroup
)
4546 return mmx_regnum_p
;
4548 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4549 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4550 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4551 if (group
== i386_sse_reggroup
)
4552 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4554 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4555 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4556 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4558 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4559 == X86_XSTATE_AVX_AVX512_MASK
);
4560 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4561 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4562 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4563 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4565 if (group
== vector_reggroup
)
4566 return (mmx_regnum_p
4567 || (zmm_regnum_p
&& avx512_p
)
4568 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4569 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4572 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4573 || i386_fpc_regnum_p (gdbarch
, regnum
));
4574 if (group
== float_reggroup
)
4577 /* For "info reg all", don't include upper YMM registers nor XMM
4578 registers when AVX is supported. */
4579 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4580 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4581 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4582 if (group
== all_reggroup
4583 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4584 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4586 || ymmh_avx512_regnum_p
4590 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4591 if (group
== all_reggroup
4592 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4593 return bnd_regnum_p
;
4595 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4596 if (group
== all_reggroup
4597 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4600 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4601 if (group
== all_reggroup
4602 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4603 return mpx_ctrl_regnum_p
;
4605 if (group
== general_reggroup
)
4606 return (!fp_regnum_p
4610 && !xmm_avx512_regnum_p
4613 && !ymm_avx512_regnum_p
4614 && !ymmh_avx512_regnum_p
4617 && !mpx_ctrl_regnum_p
4621 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4625 /* Get the ARGIth function argument for the current function. */
4628 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4631 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4632 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4633 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4634 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4637 #define PREFIX_REPZ 0x01
4638 #define PREFIX_REPNZ 0x02
4639 #define PREFIX_LOCK 0x04
4640 #define PREFIX_DATA 0x08
4641 #define PREFIX_ADDR 0x10
4653 /* i386 arith/logic operations */
4666 struct i386_record_s
4668 struct gdbarch
*gdbarch
;
4669 struct regcache
*regcache
;
4670 CORE_ADDR orig_addr
;
4676 uint8_t mod
, reg
, rm
;
4685 /* Parse the "modrm" part of the memory address irp->addr points at.
4686 Returns -1 if something goes wrong, 0 otherwise. */
4689 i386_record_modrm (struct i386_record_s
*irp
)
4691 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4693 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4697 irp
->mod
= (irp
->modrm
>> 6) & 3;
4698 irp
->reg
= (irp
->modrm
>> 3) & 7;
4699 irp
->rm
= irp
->modrm
& 7;
4704 /* Extract the memory address that the current instruction writes to,
4705 and return it in *ADDR. Return -1 if something goes wrong. */
4708 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4710 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4711 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4716 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4723 uint8_t base
= irp
->rm
;
4728 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4731 scale
= (byte
>> 6) & 3;
4732 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4740 if ((base
& 7) == 5)
4743 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4746 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4747 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4748 *addr
+= irp
->addr
+ irp
->rip_offset
;
4752 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4755 *addr
= (int8_t) buf
[0];
4758 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4760 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4768 if (base
== 4 && irp
->popl_esp_hack
)
4769 *addr
+= irp
->popl_esp_hack
;
4770 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4773 if (irp
->aflag
== 2)
4778 *addr
= (uint32_t) (offset64
+ *addr
);
4780 if (havesib
&& (index
!= 4 || scale
!= 0))
4782 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4784 if (irp
->aflag
== 2)
4785 *addr
+= offset64
<< scale
;
4787 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4792 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4793 address from 32-bit to 64-bit. */
4794 *addr
= (uint32_t) *addr
;
4805 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4808 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4814 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4817 *addr
= (int8_t) buf
[0];
4820 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4823 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4830 regcache_raw_read_unsigned (irp
->regcache
,
4831 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4833 *addr
= (uint32_t) (*addr
+ offset64
);
4834 regcache_raw_read_unsigned (irp
->regcache
,
4835 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4837 *addr
= (uint32_t) (*addr
+ offset64
);
4840 regcache_raw_read_unsigned (irp
->regcache
,
4841 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4843 *addr
= (uint32_t) (*addr
+ offset64
);
4844 regcache_raw_read_unsigned (irp
->regcache
,
4845 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4847 *addr
= (uint32_t) (*addr
+ offset64
);
4850 regcache_raw_read_unsigned (irp
->regcache
,
4851 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4853 *addr
= (uint32_t) (*addr
+ offset64
);
4854 regcache_raw_read_unsigned (irp
->regcache
,
4855 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4857 *addr
= (uint32_t) (*addr
+ offset64
);
4860 regcache_raw_read_unsigned (irp
->regcache
,
4861 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4863 *addr
= (uint32_t) (*addr
+ offset64
);
4864 regcache_raw_read_unsigned (irp
->regcache
,
4865 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4867 *addr
= (uint32_t) (*addr
+ offset64
);
4870 regcache_raw_read_unsigned (irp
->regcache
,
4871 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4873 *addr
= (uint32_t) (*addr
+ offset64
);
4876 regcache_raw_read_unsigned (irp
->regcache
,
4877 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4879 *addr
= (uint32_t) (*addr
+ offset64
);
4882 regcache_raw_read_unsigned (irp
->regcache
,
4883 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4885 *addr
= (uint32_t) (*addr
+ offset64
);
4888 regcache_raw_read_unsigned (irp
->regcache
,
4889 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4891 *addr
= (uint32_t) (*addr
+ offset64
);
4901 /* Record the address and contents of the memory that will be changed
4902 by the current instruction. Return -1 if something goes wrong, 0
4906 i386_record_lea_modrm (struct i386_record_s
*irp
)
4908 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4911 if (irp
->override
>= 0)
4913 if (record_full_memory_query
)
4916 Process record ignores the memory change of instruction at address %s\n\
4917 because it can't get the value of the segment register.\n\
4918 Do you want to stop the program?"),
4919 paddress (gdbarch
, irp
->orig_addr
)))
4926 if (i386_record_lea_modrm_addr (irp
, &addr
))
4929 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4935 /* Record the effects of a push operation. Return -1 if something
4936 goes wrong, 0 otherwise. */
4939 i386_record_push (struct i386_record_s
*irp
, int size
)
4943 if (record_full_arch_list_add_reg (irp
->regcache
,
4944 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4946 regcache_raw_read_unsigned (irp
->regcache
,
4947 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4949 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4956 /* Defines contents to record. */
4957 #define I386_SAVE_FPU_REGS 0xfffd
4958 #define I386_SAVE_FPU_ENV 0xfffe
4959 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4961 /* Record the values of the floating point registers which will be
4962 changed by the current instruction. Returns -1 if something is
4963 wrong, 0 otherwise. */
4965 static int i386_record_floats (struct gdbarch
*gdbarch
,
4966 struct i386_record_s
*ir
,
4969 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4972 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4973 happen. Currently we store st0-st7 registers, but we need not store all
4974 registers all the time, in future we use ftag register and record only
4975 those who are not marked as an empty. */
4977 if (I386_SAVE_FPU_REGS
== iregnum
)
4979 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4981 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4985 else if (I386_SAVE_FPU_ENV
== iregnum
)
4987 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4989 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4993 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4995 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4997 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5001 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
5002 (iregnum
<= I387_FOP_REGNUM (tdep
)))
5004 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5009 /* Parameter error. */
5012 if(I386_SAVE_FPU_ENV
!= iregnum
)
5014 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5016 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5023 /* Parse the current instruction, and record the values of the
5024 registers and memory that will be changed by the current
5025 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5027 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5028 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5031 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5032 CORE_ADDR input_addr
)
5034 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5040 gdb_byte buf
[MAX_REGISTER_SIZE
];
5041 struct i386_record_s ir
;
5042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5046 memset (&ir
, 0, sizeof (struct i386_record_s
));
5047 ir
.regcache
= regcache
;
5048 ir
.addr
= input_addr
;
5049 ir
.orig_addr
= input_addr
;
5053 ir
.popl_esp_hack
= 0;
5054 ir
.regmap
= tdep
->record_regmap
;
5055 ir
.gdbarch
= gdbarch
;
5057 if (record_debug
> 1)
5058 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5060 paddress (gdbarch
, ir
.addr
));
5065 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5068 switch (opcode8
) /* Instruction prefixes */
5070 case REPE_PREFIX_OPCODE
:
5071 prefixes
|= PREFIX_REPZ
;
5073 case REPNE_PREFIX_OPCODE
:
5074 prefixes
|= PREFIX_REPNZ
;
5076 case LOCK_PREFIX_OPCODE
:
5077 prefixes
|= PREFIX_LOCK
;
5079 case CS_PREFIX_OPCODE
:
5080 ir
.override
= X86_RECORD_CS_REGNUM
;
5082 case SS_PREFIX_OPCODE
:
5083 ir
.override
= X86_RECORD_SS_REGNUM
;
5085 case DS_PREFIX_OPCODE
:
5086 ir
.override
= X86_RECORD_DS_REGNUM
;
5088 case ES_PREFIX_OPCODE
:
5089 ir
.override
= X86_RECORD_ES_REGNUM
;
5091 case FS_PREFIX_OPCODE
:
5092 ir
.override
= X86_RECORD_FS_REGNUM
;
5094 case GS_PREFIX_OPCODE
:
5095 ir
.override
= X86_RECORD_GS_REGNUM
;
5097 case DATA_PREFIX_OPCODE
:
5098 prefixes
|= PREFIX_DATA
;
5100 case ADDR_PREFIX_OPCODE
:
5101 prefixes
|= PREFIX_ADDR
;
5103 case 0x40: /* i386 inc %eax */
5104 case 0x41: /* i386 inc %ecx */
5105 case 0x42: /* i386 inc %edx */
5106 case 0x43: /* i386 inc %ebx */
5107 case 0x44: /* i386 inc %esp */
5108 case 0x45: /* i386 inc %ebp */
5109 case 0x46: /* i386 inc %esi */
5110 case 0x47: /* i386 inc %edi */
5111 case 0x48: /* i386 dec %eax */
5112 case 0x49: /* i386 dec %ecx */
5113 case 0x4a: /* i386 dec %edx */
5114 case 0x4b: /* i386 dec %ebx */
5115 case 0x4c: /* i386 dec %esp */
5116 case 0x4d: /* i386 dec %ebp */
5117 case 0x4e: /* i386 dec %esi */
5118 case 0x4f: /* i386 dec %edi */
5119 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5122 rex_w
= (opcode8
>> 3) & 1;
5123 rex_r
= (opcode8
& 0x4) << 1;
5124 ir
.rex_x
= (opcode8
& 0x2) << 2;
5125 ir
.rex_b
= (opcode8
& 0x1) << 3;
5127 else /* 32 bit target */
5136 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5142 if (prefixes
& PREFIX_DATA
)
5145 if (prefixes
& PREFIX_ADDR
)
5147 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5150 /* Now check op code. */
5151 opcode
= (uint32_t) opcode8
;
5156 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5159 opcode
= (uint32_t) opcode8
| 0x0f00;
5163 case 0x00: /* arith & logic */
5211 if (((opcode
>> 3) & 7) != OP_CMPL
)
5213 if ((opcode
& 1) == 0)
5216 ir
.ot
= ir
.dflag
+ OT_WORD
;
5218 switch ((opcode
>> 1) & 3)
5220 case 0: /* OP Ev, Gv */
5221 if (i386_record_modrm (&ir
))
5225 if (i386_record_lea_modrm (&ir
))
5231 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5233 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5236 case 1: /* OP Gv, Ev */
5237 if (i386_record_modrm (&ir
))
5240 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5244 case 2: /* OP A, Iv */
5245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5252 case 0x80: /* GRP1 */
5256 if (i386_record_modrm (&ir
))
5259 if (ir
.reg
!= OP_CMPL
)
5261 if ((opcode
& 1) == 0)
5264 ir
.ot
= ir
.dflag
+ OT_WORD
;
5271 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5272 if (i386_record_lea_modrm (&ir
))
5276 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5278 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5281 case 0x40: /* inc */
5290 case 0x48: /* dec */
5299 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5300 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5303 case 0xf6: /* GRP3 */
5305 if ((opcode
& 1) == 0)
5308 ir
.ot
= ir
.dflag
+ OT_WORD
;
5309 if (i386_record_modrm (&ir
))
5312 if (ir
.mod
!= 3 && ir
.reg
== 0)
5313 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5318 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5324 if (i386_record_lea_modrm (&ir
))
5330 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5334 if (ir
.reg
== 3) /* neg */
5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5342 if (ir
.ot
!= OT_BYTE
)
5343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5348 opcode
= opcode
<< 8 | ir
.modrm
;
5354 case 0xfe: /* GRP4 */
5355 case 0xff: /* GRP5 */
5356 if (i386_record_modrm (&ir
))
5358 if (ir
.reg
>= 2 && opcode
== 0xfe)
5361 opcode
= opcode
<< 8 | ir
.modrm
;
5368 if ((opcode
& 1) == 0)
5371 ir
.ot
= ir
.dflag
+ OT_WORD
;
5374 if (i386_record_lea_modrm (&ir
))
5380 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5387 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5389 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5395 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5404 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5406 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5411 opcode
= opcode
<< 8 | ir
.modrm
;
5417 case 0x84: /* test */
5421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5424 case 0x98: /* CWDE/CBW */
5425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5428 case 0x99: /* CDQ/CWD */
5429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5430 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5433 case 0x0faf: /* imul */
5436 ir
.ot
= ir
.dflag
+ OT_WORD
;
5437 if (i386_record_modrm (&ir
))
5440 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5441 else if (opcode
== 0x6b)
5444 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5446 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5450 case 0x0fc0: /* xadd */
5452 if ((opcode
& 1) == 0)
5455 ir
.ot
= ir
.dflag
+ OT_WORD
;
5456 if (i386_record_modrm (&ir
))
5461 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5463 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5464 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5470 if (i386_record_lea_modrm (&ir
))
5472 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5476 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5479 case 0x0fb0: /* cmpxchg */
5481 if ((opcode
& 1) == 0)
5484 ir
.ot
= ir
.dflag
+ OT_WORD
;
5485 if (i386_record_modrm (&ir
))
5490 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5491 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5498 if (i386_record_lea_modrm (&ir
))
5501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5504 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5505 if (i386_record_modrm (&ir
))
5509 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5510 an extended opcode. rdrand has bits 110 (/6) and rdseed
5511 has bits 111 (/7). */
5512 if (ir
.reg
== 6 || ir
.reg
== 7)
5514 /* The storage register is described by the 3 R/M bits, but the
5515 REX.B prefix may be used to give access to registers
5516 R8~R15. In this case ir.rex_b + R/M will give us the register
5517 in the range R8~R15.
5519 REX.W may also be used to access 64-bit registers, but we
5520 already record entire registers and not just partial bits
5522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5523 /* These instructions also set conditional bits. */
5524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5529 /* We don't handle this particular instruction yet. */
5531 opcode
= opcode
<< 8 | ir
.modrm
;
5535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5537 if (i386_record_lea_modrm (&ir
))
5539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5542 case 0x50: /* push */
5552 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5554 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5558 case 0x06: /* push es */
5559 case 0x0e: /* push cs */
5560 case 0x16: /* push ss */
5561 case 0x1e: /* push ds */
5562 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5567 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5571 case 0x0fa0: /* push fs */
5572 case 0x0fa8: /* push gs */
5573 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5578 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5582 case 0x60: /* pusha */
5583 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5588 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5592 case 0x58: /* pop */
5600 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5601 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5604 case 0x61: /* popa */
5605 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5610 for (regnum
= X86_RECORD_REAX_REGNUM
;
5611 regnum
<= X86_RECORD_REDI_REGNUM
;
5613 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5616 case 0x8f: /* pop */
5617 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5618 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5620 ir
.ot
= ir
.dflag
+ OT_WORD
;
5621 if (i386_record_modrm (&ir
))
5624 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5627 ir
.popl_esp_hack
= 1 << ir
.ot
;
5628 if (i386_record_lea_modrm (&ir
))
5631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5634 case 0xc8: /* enter */
5635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5636 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5638 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5642 case 0xc9: /* leave */
5643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5647 case 0x07: /* pop es */
5648 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5653 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5658 case 0x17: /* pop ss */
5659 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5664 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5669 case 0x1f: /* pop ds */
5670 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5680 case 0x0fa1: /* pop fs */
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5686 case 0x0fa9: /* pop gs */
5687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5689 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5692 case 0x88: /* mov */
5696 if ((opcode
& 1) == 0)
5699 ir
.ot
= ir
.dflag
+ OT_WORD
;
5701 if (i386_record_modrm (&ir
))
5706 if (opcode
== 0xc6 || opcode
== 0xc7)
5707 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5708 if (i386_record_lea_modrm (&ir
))
5713 if (opcode
== 0xc6 || opcode
== 0xc7)
5715 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5721 case 0x8a: /* mov */
5723 if ((opcode
& 1) == 0)
5726 ir
.ot
= ir
.dflag
+ OT_WORD
;
5727 if (i386_record_modrm (&ir
))
5730 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5732 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5735 case 0x8c: /* mov seg */
5736 if (i386_record_modrm (&ir
))
5741 opcode
= opcode
<< 8 | ir
.modrm
;
5746 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5750 if (i386_record_lea_modrm (&ir
))
5755 case 0x8e: /* mov seg */
5756 if (i386_record_modrm (&ir
))
5761 regnum
= X86_RECORD_ES_REGNUM
;
5764 regnum
= X86_RECORD_SS_REGNUM
;
5767 regnum
= X86_RECORD_DS_REGNUM
;
5770 regnum
= X86_RECORD_FS_REGNUM
;
5773 regnum
= X86_RECORD_GS_REGNUM
;
5777 opcode
= opcode
<< 8 | ir
.modrm
;
5781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5782 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5785 case 0x0fb6: /* movzbS */
5786 case 0x0fb7: /* movzwS */
5787 case 0x0fbe: /* movsbS */
5788 case 0x0fbf: /* movswS */
5789 if (i386_record_modrm (&ir
))
5791 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5794 case 0x8d: /* lea */
5795 if (i386_record_modrm (&ir
))
5800 opcode
= opcode
<< 8 | ir
.modrm
;
5805 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5807 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5810 case 0xa0: /* mov EAX */
5813 case 0xd7: /* xlat */
5814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5817 case 0xa2: /* mov EAX */
5819 if (ir
.override
>= 0)
5821 if (record_full_memory_query
)
5824 Process record ignores the memory change of instruction at address %s\n\
5825 because it can't get the value of the segment register.\n\
5826 Do you want to stop the program?"),
5827 paddress (gdbarch
, ir
.orig_addr
)))
5833 if ((opcode
& 1) == 0)
5836 ir
.ot
= ir
.dflag
+ OT_WORD
;
5839 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5842 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5846 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5849 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5853 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5856 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5858 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5863 case 0xb0: /* mov R, Ib */
5871 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5872 ? ((opcode
& 0x7) | ir
.rex_b
)
5873 : ((opcode
& 0x7) & 0x3));
5876 case 0xb8: /* mov R, Iv */
5884 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5887 case 0x91: /* xchg R, EAX */
5894 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5898 case 0x86: /* xchg Ev, Gv */
5900 if ((opcode
& 1) == 0)
5903 ir
.ot
= ir
.dflag
+ OT_WORD
;
5904 if (i386_record_modrm (&ir
))
5909 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5911 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5915 if (i386_record_lea_modrm (&ir
))
5919 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5921 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5924 case 0xc4: /* les Gv */
5925 case 0xc5: /* lds Gv */
5926 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5932 case 0x0fb2: /* lss Gv */
5933 case 0x0fb4: /* lfs Gv */
5934 case 0x0fb5: /* lgs Gv */
5935 if (i386_record_modrm (&ir
))
5943 opcode
= opcode
<< 8 | ir
.modrm
;
5948 case 0xc4: /* les Gv */
5949 regnum
= X86_RECORD_ES_REGNUM
;
5951 case 0xc5: /* lds Gv */
5952 regnum
= X86_RECORD_DS_REGNUM
;
5954 case 0x0fb2: /* lss Gv */
5955 regnum
= X86_RECORD_SS_REGNUM
;
5957 case 0x0fb4: /* lfs Gv */
5958 regnum
= X86_RECORD_FS_REGNUM
;
5960 case 0x0fb5: /* lgs Gv */
5961 regnum
= X86_RECORD_GS_REGNUM
;
5964 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5965 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5966 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5969 case 0xc0: /* shifts */
5975 if ((opcode
& 1) == 0)
5978 ir
.ot
= ir
.dflag
+ OT_WORD
;
5979 if (i386_record_modrm (&ir
))
5981 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5983 if (i386_record_lea_modrm (&ir
))
5989 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6000 if (i386_record_modrm (&ir
))
6004 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6009 if (i386_record_lea_modrm (&ir
))
6014 case 0xd8: /* Floats. */
6022 if (i386_record_modrm (&ir
))
6024 ir
.reg
|= ((opcode
& 7) << 3);
6030 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6038 /* For fcom, ficom nothing to do. */
6044 /* For fcomp, ficomp pop FPU stack, store all. */
6045 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6072 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6073 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6074 of code, always affects st(0) register. */
6075 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6099 /* Handling fld, fild. */
6100 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6104 switch (ir
.reg
>> 4)
6107 if (record_full_arch_list_add_mem (addr64
, 4))
6111 if (record_full_arch_list_add_mem (addr64
, 8))
6117 if (record_full_arch_list_add_mem (addr64
, 2))
6123 switch (ir
.reg
>> 4)
6126 if (record_full_arch_list_add_mem (addr64
, 4))
6128 if (3 == (ir
.reg
& 7))
6130 /* For fstp m32fp. */
6131 if (i386_record_floats (gdbarch
, &ir
,
6132 I386_SAVE_FPU_REGS
))
6137 if (record_full_arch_list_add_mem (addr64
, 4))
6139 if ((3 == (ir
.reg
& 7))
6140 || (5 == (ir
.reg
& 7))
6141 || (7 == (ir
.reg
& 7)))
6143 /* For fstp insn. */
6144 if (i386_record_floats (gdbarch
, &ir
,
6145 I386_SAVE_FPU_REGS
))
6150 if (record_full_arch_list_add_mem (addr64
, 8))
6152 if (3 == (ir
.reg
& 7))
6154 /* For fstp m64fp. */
6155 if (i386_record_floats (gdbarch
, &ir
,
6156 I386_SAVE_FPU_REGS
))
6161 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6163 /* For fistp, fbld, fild, fbstp. */
6164 if (i386_record_floats (gdbarch
, &ir
,
6165 I386_SAVE_FPU_REGS
))
6170 if (record_full_arch_list_add_mem (addr64
, 2))
6179 if (i386_record_floats (gdbarch
, &ir
,
6180 I386_SAVE_FPU_ENV_REG_STACK
))
6185 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6190 if (i386_record_floats (gdbarch
, &ir
,
6191 I386_SAVE_FPU_ENV_REG_STACK
))
6197 if (record_full_arch_list_add_mem (addr64
, 28))
6202 if (record_full_arch_list_add_mem (addr64
, 14))
6208 if (record_full_arch_list_add_mem (addr64
, 2))
6210 /* Insn fstp, fbstp. */
6211 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6216 if (record_full_arch_list_add_mem (addr64
, 10))
6222 if (record_full_arch_list_add_mem (addr64
, 28))
6228 if (record_full_arch_list_add_mem (addr64
, 14))
6232 if (record_full_arch_list_add_mem (addr64
, 80))
6235 if (i386_record_floats (gdbarch
, &ir
,
6236 I386_SAVE_FPU_ENV_REG_STACK
))
6240 if (record_full_arch_list_add_mem (addr64
, 8))
6243 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6248 opcode
= opcode
<< 8 | ir
.modrm
;
6253 /* Opcode is an extension of modR/M byte. */
6259 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6263 if (0x0c == (ir
.modrm
>> 4))
6265 if ((ir
.modrm
& 0x0f) <= 7)
6267 if (i386_record_floats (gdbarch
, &ir
,
6268 I386_SAVE_FPU_REGS
))
6273 if (i386_record_floats (gdbarch
, &ir
,
6274 I387_ST0_REGNUM (tdep
)))
6276 /* If only st(0) is changing, then we have already
6278 if ((ir
.modrm
& 0x0f) - 0x08)
6280 if (i386_record_floats (gdbarch
, &ir
,
6281 I387_ST0_REGNUM (tdep
) +
6282 ((ir
.modrm
& 0x0f) - 0x08)))
6300 if (i386_record_floats (gdbarch
, &ir
,
6301 I387_ST0_REGNUM (tdep
)))
6319 if (i386_record_floats (gdbarch
, &ir
,
6320 I386_SAVE_FPU_REGS
))
6324 if (i386_record_floats (gdbarch
, &ir
,
6325 I387_ST0_REGNUM (tdep
)))
6327 if (i386_record_floats (gdbarch
, &ir
,
6328 I387_ST0_REGNUM (tdep
) + 1))
6335 if (0xe9 == ir
.modrm
)
6337 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6340 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6342 if (i386_record_floats (gdbarch
, &ir
,
6343 I387_ST0_REGNUM (tdep
)))
6345 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6347 if (i386_record_floats (gdbarch
, &ir
,
6348 I387_ST0_REGNUM (tdep
) +
6352 else if ((ir
.modrm
& 0x0f) - 0x08)
6354 if (i386_record_floats (gdbarch
, &ir
,
6355 I387_ST0_REGNUM (tdep
) +
6356 ((ir
.modrm
& 0x0f) - 0x08)))
6362 if (0xe3 == ir
.modrm
)
6364 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6367 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6369 if (i386_record_floats (gdbarch
, &ir
,
6370 I387_ST0_REGNUM (tdep
)))
6372 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6374 if (i386_record_floats (gdbarch
, &ir
,
6375 I387_ST0_REGNUM (tdep
) +
6379 else if ((ir
.modrm
& 0x0f) - 0x08)
6381 if (i386_record_floats (gdbarch
, &ir
,
6382 I387_ST0_REGNUM (tdep
) +
6383 ((ir
.modrm
& 0x0f) - 0x08)))
6389 if ((0x0c == ir
.modrm
>> 4)
6390 || (0x0d == ir
.modrm
>> 4)
6391 || (0x0f == ir
.modrm
>> 4))
6393 if ((ir
.modrm
& 0x0f) <= 7)
6395 if (i386_record_floats (gdbarch
, &ir
,
6396 I387_ST0_REGNUM (tdep
) +
6402 if (i386_record_floats (gdbarch
, &ir
,
6403 I387_ST0_REGNUM (tdep
) +
6404 ((ir
.modrm
& 0x0f) - 0x08)))
6410 if (0x0c == ir
.modrm
>> 4)
6412 if (i386_record_floats (gdbarch
, &ir
,
6413 I387_FTAG_REGNUM (tdep
)))
6416 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6418 if ((ir
.modrm
& 0x0f) <= 7)
6420 if (i386_record_floats (gdbarch
, &ir
,
6421 I387_ST0_REGNUM (tdep
) +
6427 if (i386_record_floats (gdbarch
, &ir
,
6428 I386_SAVE_FPU_REGS
))
6434 if ((0x0c == ir
.modrm
>> 4)
6435 || (0x0e == ir
.modrm
>> 4)
6436 || (0x0f == ir
.modrm
>> 4)
6437 || (0xd9 == ir
.modrm
))
6439 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6444 if (0xe0 == ir
.modrm
)
6446 if (record_full_arch_list_add_reg (ir
.regcache
,
6450 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6452 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6460 case 0xa4: /* movsS */
6462 case 0xaa: /* stosS */
6464 case 0x6c: /* insS */
6466 regcache_raw_read_unsigned (ir
.regcache
,
6467 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6473 if ((opcode
& 1) == 0)
6476 ir
.ot
= ir
.dflag
+ OT_WORD
;
6477 regcache_raw_read_unsigned (ir
.regcache
,
6478 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6481 regcache_raw_read_unsigned (ir
.regcache
,
6482 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6484 regcache_raw_read_unsigned (ir
.regcache
,
6485 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6487 if (ir
.aflag
&& (es
!= ds
))
6489 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6490 if (record_full_memory_query
)
6493 Process record ignores the memory change of instruction at address %s\n\
6494 because it can't get the value of the segment register.\n\
6495 Do you want to stop the program?"),
6496 paddress (gdbarch
, ir
.orig_addr
)))
6502 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6506 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6507 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6508 if (opcode
== 0xa4 || opcode
== 0xa5)
6509 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6515 case 0xa6: /* cmpsS */
6517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6519 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6524 case 0xac: /* lodsS */
6526 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6528 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6533 case 0xae: /* scasS */
6535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6536 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6541 case 0x6e: /* outsS */
6543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6544 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6549 case 0xe4: /* port I/O */
6553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6564 case 0xc2: /* ret im */
6565 case 0xc3: /* ret */
6566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6570 case 0xca: /* lret im */
6571 case 0xcb: /* lret */
6572 case 0xcf: /* iret */
6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6578 case 0xe8: /* call im */
6579 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6581 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6585 case 0x9a: /* lcall im */
6586 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6591 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6592 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6596 case 0xe9: /* jmp im */
6597 case 0xea: /* ljmp im */
6598 case 0xeb: /* jmp Jb */
6599 case 0x70: /* jcc Jb */
6615 case 0x0f80: /* jcc Jv */
6633 case 0x0f90: /* setcc Gv */
6649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6651 if (i386_record_modrm (&ir
))
6654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6658 if (i386_record_lea_modrm (&ir
))
6663 case 0x0f40: /* cmov Gv, Ev */
6679 if (i386_record_modrm (&ir
))
6682 if (ir
.dflag
== OT_BYTE
)
6684 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6688 case 0x9c: /* pushf */
6689 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6690 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6692 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6696 case 0x9d: /* popf */
6697 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6698 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6701 case 0x9e: /* sahf */
6702 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6708 case 0xf5: /* cmc */
6709 case 0xf8: /* clc */
6710 case 0xf9: /* stc */
6711 case 0xfc: /* cld */
6712 case 0xfd: /* std */
6713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6716 case 0x9f: /* lahf */
6717 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6722 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6726 /* bit operations */
6727 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6728 ir
.ot
= ir
.dflag
+ OT_WORD
;
6729 if (i386_record_modrm (&ir
))
6734 opcode
= opcode
<< 8 | ir
.modrm
;
6740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6743 if (i386_record_lea_modrm (&ir
))
6747 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6750 case 0x0fa3: /* bt Gv, Ev */
6751 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6754 case 0x0fab: /* bts */
6755 case 0x0fb3: /* btr */
6756 case 0x0fbb: /* btc */
6757 ir
.ot
= ir
.dflag
+ OT_WORD
;
6758 if (i386_record_modrm (&ir
))
6761 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6765 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6767 regcache_raw_read_unsigned (ir
.regcache
,
6768 ir
.regmap
[ir
.reg
| rex_r
],
6773 addr64
+= ((int16_t) addr
>> 4) << 4;
6776 addr64
+= ((int32_t) addr
>> 5) << 5;
6779 addr64
+= ((int64_t) addr
>> 6) << 6;
6782 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6784 if (i386_record_lea_modrm (&ir
))
6787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6790 case 0x0fbc: /* bsf */
6791 case 0x0fbd: /* bsr */
6792 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6793 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6797 case 0x27: /* daa */
6798 case 0x2f: /* das */
6799 case 0x37: /* aaa */
6800 case 0x3f: /* aas */
6801 case 0xd4: /* aam */
6802 case 0xd5: /* aad */
6803 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6813 case 0x90: /* nop */
6814 if (prefixes
& PREFIX_LOCK
)
6821 case 0x9b: /* fwait */
6822 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6824 opcode
= (uint32_t) opcode8
;
6830 case 0xcc: /* int3 */
6831 printf_unfiltered (_("Process record does not support instruction "
6838 case 0xcd: /* int */
6842 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6845 if (interrupt
!= 0x80
6846 || tdep
->i386_intx80_record
== NULL
)
6848 printf_unfiltered (_("Process record does not support "
6849 "instruction int 0x%02x.\n"),
6854 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6861 case 0xce: /* into */
6862 printf_unfiltered (_("Process record does not support "
6863 "instruction into.\n"));
6868 case 0xfa: /* cli */
6869 case 0xfb: /* sti */
6872 case 0x62: /* bound */
6873 printf_unfiltered (_("Process record does not support "
6874 "instruction bound.\n"));
6879 case 0x0fc8: /* bswap reg */
6887 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6890 case 0xd6: /* salc */
6891 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6896 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6900 case 0xe0: /* loopnz */
6901 case 0xe1: /* loopz */
6902 case 0xe2: /* loop */
6903 case 0xe3: /* jecxz */
6904 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6908 case 0x0f30: /* wrmsr */
6909 printf_unfiltered (_("Process record does not support "
6910 "instruction wrmsr.\n"));
6915 case 0x0f32: /* rdmsr */
6916 printf_unfiltered (_("Process record does not support "
6917 "instruction rdmsr.\n"));
6922 case 0x0f31: /* rdtsc */
6923 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6927 case 0x0f34: /* sysenter */
6930 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6935 if (tdep
->i386_sysenter_record
== NULL
)
6937 printf_unfiltered (_("Process record does not support "
6938 "instruction sysenter.\n"));
6942 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6948 case 0x0f35: /* sysexit */
6949 printf_unfiltered (_("Process record does not support "
6950 "instruction sysexit.\n"));
6955 case 0x0f05: /* syscall */
6958 if (tdep
->i386_syscall_record
== NULL
)
6960 printf_unfiltered (_("Process record does not support "
6961 "instruction syscall.\n"));
6965 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6971 case 0x0f07: /* sysret */
6972 printf_unfiltered (_("Process record does not support "
6973 "instruction sysret.\n"));
6978 case 0x0fa2: /* cpuid */
6979 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6980 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6981 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6985 case 0xf4: /* hlt */
6986 printf_unfiltered (_("Process record does not support "
6987 "instruction hlt.\n"));
6993 if (i386_record_modrm (&ir
))
7000 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7004 if (i386_record_lea_modrm (&ir
))
7013 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7017 opcode
= opcode
<< 8 | ir
.modrm
;
7024 if (i386_record_modrm (&ir
))
7035 opcode
= opcode
<< 8 | ir
.modrm
;
7038 if (ir
.override
>= 0)
7040 if (record_full_memory_query
)
7043 Process record ignores the memory change of instruction at address %s\n\
7044 because it can't get the value of the segment register.\n\
7045 Do you want to stop the program?"),
7046 paddress (gdbarch
, ir
.orig_addr
)))
7052 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7054 if (record_full_arch_list_add_mem (addr64
, 2))
7057 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7059 if (record_full_arch_list_add_mem (addr64
, 8))
7064 if (record_full_arch_list_add_mem (addr64
, 4))
7075 case 0: /* monitor */
7078 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7082 opcode
= opcode
<< 8 | ir
.modrm
;
7090 if (ir
.override
>= 0)
7092 if (record_full_memory_query
)
7095 Process record ignores the memory change of instruction at address %s\n\
7096 because it can't get the value of the segment register.\n\
7097 Do you want to stop the program?"),
7098 paddress (gdbarch
, ir
.orig_addr
)))
7106 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7108 if (record_full_arch_list_add_mem (addr64
, 2))
7111 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7113 if (record_full_arch_list_add_mem (addr64
, 8))
7118 if (record_full_arch_list_add_mem (addr64
, 4))
7130 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7131 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7135 else if (ir
.rm
== 1)
7142 opcode
= opcode
<< 8 | ir
.modrm
;
7149 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7155 if (i386_record_lea_modrm (&ir
))
7158 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7161 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7163 case 7: /* invlpg */
7166 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7167 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7171 opcode
= opcode
<< 8 | ir
.modrm
;
7176 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7180 opcode
= opcode
<< 8 | ir
.modrm
;
7186 case 0x0f08: /* invd */
7187 case 0x0f09: /* wbinvd */
7190 case 0x63: /* arpl */
7191 if (i386_record_modrm (&ir
))
7193 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7196 ? (ir
.reg
| rex_r
) : ir
.rm
);
7200 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7201 if (i386_record_lea_modrm (&ir
))
7204 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7205 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7208 case 0x0f02: /* lar */
7209 case 0x0f03: /* lsl */
7210 if (i386_record_modrm (&ir
))
7212 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7213 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7217 if (i386_record_modrm (&ir
))
7219 if (ir
.mod
== 3 && ir
.reg
== 3)
7222 opcode
= opcode
<< 8 | ir
.modrm
;
7234 /* nop (multi byte) */
7237 case 0x0f20: /* mov reg, crN */
7238 case 0x0f22: /* mov crN, reg */
7239 if (i386_record_modrm (&ir
))
7241 if ((ir
.modrm
& 0xc0) != 0xc0)
7244 opcode
= opcode
<< 8 | ir
.modrm
;
7255 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7257 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7261 opcode
= opcode
<< 8 | ir
.modrm
;
7267 case 0x0f21: /* mov reg, drN */
7268 case 0x0f23: /* mov drN, reg */
7269 if (i386_record_modrm (&ir
))
7271 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7272 || ir
.reg
== 5 || ir
.reg
>= 8)
7275 opcode
= opcode
<< 8 | ir
.modrm
;
7279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7281 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7284 case 0x0f06: /* clts */
7285 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7288 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7290 case 0x0f0d: /* 3DNow! prefetch */
7293 case 0x0f0e: /* 3DNow! femms */
7294 case 0x0f77: /* emms */
7295 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7297 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7300 case 0x0f0f: /* 3DNow! data */
7301 if (i386_record_modrm (&ir
))
7303 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7308 case 0x0c: /* 3DNow! pi2fw */
7309 case 0x0d: /* 3DNow! pi2fd */
7310 case 0x1c: /* 3DNow! pf2iw */
7311 case 0x1d: /* 3DNow! pf2id */
7312 case 0x8a: /* 3DNow! pfnacc */
7313 case 0x8e: /* 3DNow! pfpnacc */
7314 case 0x90: /* 3DNow! pfcmpge */
7315 case 0x94: /* 3DNow! pfmin */
7316 case 0x96: /* 3DNow! pfrcp */
7317 case 0x97: /* 3DNow! pfrsqrt */
7318 case 0x9a: /* 3DNow! pfsub */
7319 case 0x9e: /* 3DNow! pfadd */
7320 case 0xa0: /* 3DNow! pfcmpgt */
7321 case 0xa4: /* 3DNow! pfmax */
7322 case 0xa6: /* 3DNow! pfrcpit1 */
7323 case 0xa7: /* 3DNow! pfrsqit1 */
7324 case 0xaa: /* 3DNow! pfsubr */
7325 case 0xae: /* 3DNow! pfacc */
7326 case 0xb0: /* 3DNow! pfcmpeq */
7327 case 0xb4: /* 3DNow! pfmul */
7328 case 0xb6: /* 3DNow! pfrcpit2 */
7329 case 0xb7: /* 3DNow! pmulhrw */
7330 case 0xbb: /* 3DNow! pswapd */
7331 case 0xbf: /* 3DNow! pavgusb */
7332 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7333 goto no_support_3dnow_data
;
7334 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7338 no_support_3dnow_data
:
7339 opcode
= (opcode
<< 8) | opcode8
;
7345 case 0x0faa: /* rsm */
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7349 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7350 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7351 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7352 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7353 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7354 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7358 if (i386_record_modrm (&ir
))
7362 case 0: /* fxsave */
7366 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7367 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7369 if (record_full_arch_list_add_mem (tmpu64
, 512))
7374 case 1: /* fxrstor */
7378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7380 for (i
= I387_MM0_REGNUM (tdep
);
7381 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7382 record_full_arch_list_add_reg (ir
.regcache
, i
);
7384 for (i
= I387_XMM0_REGNUM (tdep
);
7385 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7386 record_full_arch_list_add_reg (ir
.regcache
, i
);
7388 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7389 record_full_arch_list_add_reg (ir
.regcache
,
7390 I387_MXCSR_REGNUM(tdep
));
7392 for (i
= I387_ST0_REGNUM (tdep
);
7393 i386_fp_regnum_p (gdbarch
, i
); i
++)
7394 record_full_arch_list_add_reg (ir
.regcache
, i
);
7396 for (i
= I387_FCTRL_REGNUM (tdep
);
7397 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7398 record_full_arch_list_add_reg (ir
.regcache
, i
);
7402 case 2: /* ldmxcsr */
7403 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7405 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7408 case 3: /* stmxcsr */
7410 if (i386_record_lea_modrm (&ir
))
7414 case 5: /* lfence */
7415 case 6: /* mfence */
7416 case 7: /* sfence clflush */
7420 opcode
= (opcode
<< 8) | ir
.modrm
;
7426 case 0x0fc3: /* movnti */
7427 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7428 if (i386_record_modrm (&ir
))
7433 if (i386_record_lea_modrm (&ir
))
7437 /* Add prefix to opcode. */
7552 /* Mask out PREFIX_ADDR. */
7553 switch ((prefixes
& ~PREFIX_ADDR
))
7565 reswitch_prefix_add
:
7573 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7576 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7577 goto reswitch_prefix_add
;
7580 case 0x0f10: /* movups */
7581 case 0x660f10: /* movupd */
7582 case 0xf30f10: /* movss */
7583 case 0xf20f10: /* movsd */
7584 case 0x0f12: /* movlps */
7585 case 0x660f12: /* movlpd */
7586 case 0xf30f12: /* movsldup */
7587 case 0xf20f12: /* movddup */
7588 case 0x0f14: /* unpcklps */
7589 case 0x660f14: /* unpcklpd */
7590 case 0x0f15: /* unpckhps */
7591 case 0x660f15: /* unpckhpd */
7592 case 0x0f16: /* movhps */
7593 case 0x660f16: /* movhpd */
7594 case 0xf30f16: /* movshdup */
7595 case 0x0f28: /* movaps */
7596 case 0x660f28: /* movapd */
7597 case 0x0f2a: /* cvtpi2ps */
7598 case 0x660f2a: /* cvtpi2pd */
7599 case 0xf30f2a: /* cvtsi2ss */
7600 case 0xf20f2a: /* cvtsi2sd */
7601 case 0x0f2c: /* cvttps2pi */
7602 case 0x660f2c: /* cvttpd2pi */
7603 case 0x0f2d: /* cvtps2pi */
7604 case 0x660f2d: /* cvtpd2pi */
7605 case 0x660f3800: /* pshufb */
7606 case 0x660f3801: /* phaddw */
7607 case 0x660f3802: /* phaddd */
7608 case 0x660f3803: /* phaddsw */
7609 case 0x660f3804: /* pmaddubsw */
7610 case 0x660f3805: /* phsubw */
7611 case 0x660f3806: /* phsubd */
7612 case 0x660f3807: /* phsubsw */
7613 case 0x660f3808: /* psignb */
7614 case 0x660f3809: /* psignw */
7615 case 0x660f380a: /* psignd */
7616 case 0x660f380b: /* pmulhrsw */
7617 case 0x660f3810: /* pblendvb */
7618 case 0x660f3814: /* blendvps */
7619 case 0x660f3815: /* blendvpd */
7620 case 0x660f381c: /* pabsb */
7621 case 0x660f381d: /* pabsw */
7622 case 0x660f381e: /* pabsd */
7623 case 0x660f3820: /* pmovsxbw */
7624 case 0x660f3821: /* pmovsxbd */
7625 case 0x660f3822: /* pmovsxbq */
7626 case 0x660f3823: /* pmovsxwd */
7627 case 0x660f3824: /* pmovsxwq */
7628 case 0x660f3825: /* pmovsxdq */
7629 case 0x660f3828: /* pmuldq */
7630 case 0x660f3829: /* pcmpeqq */
7631 case 0x660f382a: /* movntdqa */
7632 case 0x660f3a08: /* roundps */
7633 case 0x660f3a09: /* roundpd */
7634 case 0x660f3a0a: /* roundss */
7635 case 0x660f3a0b: /* roundsd */
7636 case 0x660f3a0c: /* blendps */
7637 case 0x660f3a0d: /* blendpd */
7638 case 0x660f3a0e: /* pblendw */
7639 case 0x660f3a0f: /* palignr */
7640 case 0x660f3a20: /* pinsrb */
7641 case 0x660f3a21: /* insertps */
7642 case 0x660f3a22: /* pinsrd pinsrq */
7643 case 0x660f3a40: /* dpps */
7644 case 0x660f3a41: /* dppd */
7645 case 0x660f3a42: /* mpsadbw */
7646 case 0x660f3a60: /* pcmpestrm */
7647 case 0x660f3a61: /* pcmpestri */
7648 case 0x660f3a62: /* pcmpistrm */
7649 case 0x660f3a63: /* pcmpistri */
7650 case 0x0f51: /* sqrtps */
7651 case 0x660f51: /* sqrtpd */
7652 case 0xf20f51: /* sqrtsd */
7653 case 0xf30f51: /* sqrtss */
7654 case 0x0f52: /* rsqrtps */
7655 case 0xf30f52: /* rsqrtss */
7656 case 0x0f53: /* rcpps */
7657 case 0xf30f53: /* rcpss */
7658 case 0x0f54: /* andps */
7659 case 0x660f54: /* andpd */
7660 case 0x0f55: /* andnps */
7661 case 0x660f55: /* andnpd */
7662 case 0x0f56: /* orps */
7663 case 0x660f56: /* orpd */
7664 case 0x0f57: /* xorps */
7665 case 0x660f57: /* xorpd */
7666 case 0x0f58: /* addps */
7667 case 0x660f58: /* addpd */
7668 case 0xf20f58: /* addsd */
7669 case 0xf30f58: /* addss */
7670 case 0x0f59: /* mulps */
7671 case 0x660f59: /* mulpd */
7672 case 0xf20f59: /* mulsd */
7673 case 0xf30f59: /* mulss */
7674 case 0x0f5a: /* cvtps2pd */
7675 case 0x660f5a: /* cvtpd2ps */
7676 case 0xf20f5a: /* cvtsd2ss */
7677 case 0xf30f5a: /* cvtss2sd */
7678 case 0x0f5b: /* cvtdq2ps */
7679 case 0x660f5b: /* cvtps2dq */
7680 case 0xf30f5b: /* cvttps2dq */
7681 case 0x0f5c: /* subps */
7682 case 0x660f5c: /* subpd */
7683 case 0xf20f5c: /* subsd */
7684 case 0xf30f5c: /* subss */
7685 case 0x0f5d: /* minps */
7686 case 0x660f5d: /* minpd */
7687 case 0xf20f5d: /* minsd */
7688 case 0xf30f5d: /* minss */
7689 case 0x0f5e: /* divps */
7690 case 0x660f5e: /* divpd */
7691 case 0xf20f5e: /* divsd */
7692 case 0xf30f5e: /* divss */
7693 case 0x0f5f: /* maxps */
7694 case 0x660f5f: /* maxpd */
7695 case 0xf20f5f: /* maxsd */
7696 case 0xf30f5f: /* maxss */
7697 case 0x660f60: /* punpcklbw */
7698 case 0x660f61: /* punpcklwd */
7699 case 0x660f62: /* punpckldq */
7700 case 0x660f63: /* packsswb */
7701 case 0x660f64: /* pcmpgtb */
7702 case 0x660f65: /* pcmpgtw */
7703 case 0x660f66: /* pcmpgtd */
7704 case 0x660f67: /* packuswb */
7705 case 0x660f68: /* punpckhbw */
7706 case 0x660f69: /* punpckhwd */
7707 case 0x660f6a: /* punpckhdq */
7708 case 0x660f6b: /* packssdw */
7709 case 0x660f6c: /* punpcklqdq */
7710 case 0x660f6d: /* punpckhqdq */
7711 case 0x660f6e: /* movd */
7712 case 0x660f6f: /* movdqa */
7713 case 0xf30f6f: /* movdqu */
7714 case 0x660f70: /* pshufd */
7715 case 0xf20f70: /* pshuflw */
7716 case 0xf30f70: /* pshufhw */
7717 case 0x660f74: /* pcmpeqb */
7718 case 0x660f75: /* pcmpeqw */
7719 case 0x660f76: /* pcmpeqd */
7720 case 0x660f7c: /* haddpd */
7721 case 0xf20f7c: /* haddps */
7722 case 0x660f7d: /* hsubpd */
7723 case 0xf20f7d: /* hsubps */
7724 case 0xf30f7e: /* movq */
7725 case 0x0fc2: /* cmpps */
7726 case 0x660fc2: /* cmppd */
7727 case 0xf20fc2: /* cmpsd */
7728 case 0xf30fc2: /* cmpss */
7729 case 0x660fc4: /* pinsrw */
7730 case 0x0fc6: /* shufps */
7731 case 0x660fc6: /* shufpd */
7732 case 0x660fd0: /* addsubpd */
7733 case 0xf20fd0: /* addsubps */
7734 case 0x660fd1: /* psrlw */
7735 case 0x660fd2: /* psrld */
7736 case 0x660fd3: /* psrlq */
7737 case 0x660fd4: /* paddq */
7738 case 0x660fd5: /* pmullw */
7739 case 0xf30fd6: /* movq2dq */
7740 case 0x660fd8: /* psubusb */
7741 case 0x660fd9: /* psubusw */
7742 case 0x660fda: /* pminub */
7743 case 0x660fdb: /* pand */
7744 case 0x660fdc: /* paddusb */
7745 case 0x660fdd: /* paddusw */
7746 case 0x660fde: /* pmaxub */
7747 case 0x660fdf: /* pandn */
7748 case 0x660fe0: /* pavgb */
7749 case 0x660fe1: /* psraw */
7750 case 0x660fe2: /* psrad */
7751 case 0x660fe3: /* pavgw */
7752 case 0x660fe4: /* pmulhuw */
7753 case 0x660fe5: /* pmulhw */
7754 case 0x660fe6: /* cvttpd2dq */
7755 case 0xf20fe6: /* cvtpd2dq */
7756 case 0xf30fe6: /* cvtdq2pd */
7757 case 0x660fe8: /* psubsb */
7758 case 0x660fe9: /* psubsw */
7759 case 0x660fea: /* pminsw */
7760 case 0x660feb: /* por */
7761 case 0x660fec: /* paddsb */
7762 case 0x660fed: /* paddsw */
7763 case 0x660fee: /* pmaxsw */
7764 case 0x660fef: /* pxor */
7765 case 0xf20ff0: /* lddqu */
7766 case 0x660ff1: /* psllw */
7767 case 0x660ff2: /* pslld */
7768 case 0x660ff3: /* psllq */
7769 case 0x660ff4: /* pmuludq */
7770 case 0x660ff5: /* pmaddwd */
7771 case 0x660ff6: /* psadbw */
7772 case 0x660ff8: /* psubb */
7773 case 0x660ff9: /* psubw */
7774 case 0x660ffa: /* psubd */
7775 case 0x660ffb: /* psubq */
7776 case 0x660ffc: /* paddb */
7777 case 0x660ffd: /* paddw */
7778 case 0x660ffe: /* paddd */
7779 if (i386_record_modrm (&ir
))
7782 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7784 record_full_arch_list_add_reg (ir
.regcache
,
7785 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7786 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7790 case 0x0f11: /* movups */
7791 case 0x660f11: /* movupd */
7792 case 0xf30f11: /* movss */
7793 case 0xf20f11: /* movsd */
7794 case 0x0f13: /* movlps */
7795 case 0x660f13: /* movlpd */
7796 case 0x0f17: /* movhps */
7797 case 0x660f17: /* movhpd */
7798 case 0x0f29: /* movaps */
7799 case 0x660f29: /* movapd */
7800 case 0x660f3a14: /* pextrb */
7801 case 0x660f3a15: /* pextrw */
7802 case 0x660f3a16: /* pextrd pextrq */
7803 case 0x660f3a17: /* extractps */
7804 case 0x660f7f: /* movdqa */
7805 case 0xf30f7f: /* movdqu */
7806 if (i386_record_modrm (&ir
))
7810 if (opcode
== 0x0f13 || opcode
== 0x660f13
7811 || opcode
== 0x0f17 || opcode
== 0x660f17)
7814 if (!i386_xmm_regnum_p (gdbarch
,
7815 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7817 record_full_arch_list_add_reg (ir
.regcache
,
7818 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7840 if (i386_record_lea_modrm (&ir
))
7845 case 0x0f2b: /* movntps */
7846 case 0x660f2b: /* movntpd */
7847 case 0x0fe7: /* movntq */
7848 case 0x660fe7: /* movntdq */
7851 if (opcode
== 0x0fe7)
7855 if (i386_record_lea_modrm (&ir
))
7859 case 0xf30f2c: /* cvttss2si */
7860 case 0xf20f2c: /* cvttsd2si */
7861 case 0xf30f2d: /* cvtss2si */
7862 case 0xf20f2d: /* cvtsd2si */
7863 case 0xf20f38f0: /* crc32 */
7864 case 0xf20f38f1: /* crc32 */
7865 case 0x0f50: /* movmskps */
7866 case 0x660f50: /* movmskpd */
7867 case 0x0fc5: /* pextrw */
7868 case 0x660fc5: /* pextrw */
7869 case 0x0fd7: /* pmovmskb */
7870 case 0x660fd7: /* pmovmskb */
7871 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7874 case 0x0f3800: /* pshufb */
7875 case 0x0f3801: /* phaddw */
7876 case 0x0f3802: /* phaddd */
7877 case 0x0f3803: /* phaddsw */
7878 case 0x0f3804: /* pmaddubsw */
7879 case 0x0f3805: /* phsubw */
7880 case 0x0f3806: /* phsubd */
7881 case 0x0f3807: /* phsubsw */
7882 case 0x0f3808: /* psignb */
7883 case 0x0f3809: /* psignw */
7884 case 0x0f380a: /* psignd */
7885 case 0x0f380b: /* pmulhrsw */
7886 case 0x0f381c: /* pabsb */
7887 case 0x0f381d: /* pabsw */
7888 case 0x0f381e: /* pabsd */
7889 case 0x0f382b: /* packusdw */
7890 case 0x0f3830: /* pmovzxbw */
7891 case 0x0f3831: /* pmovzxbd */
7892 case 0x0f3832: /* pmovzxbq */
7893 case 0x0f3833: /* pmovzxwd */
7894 case 0x0f3834: /* pmovzxwq */
7895 case 0x0f3835: /* pmovzxdq */
7896 case 0x0f3837: /* pcmpgtq */
7897 case 0x0f3838: /* pminsb */
7898 case 0x0f3839: /* pminsd */
7899 case 0x0f383a: /* pminuw */
7900 case 0x0f383b: /* pminud */
7901 case 0x0f383c: /* pmaxsb */
7902 case 0x0f383d: /* pmaxsd */
7903 case 0x0f383e: /* pmaxuw */
7904 case 0x0f383f: /* pmaxud */
7905 case 0x0f3840: /* pmulld */
7906 case 0x0f3841: /* phminposuw */
7907 case 0x0f3a0f: /* palignr */
7908 case 0x0f60: /* punpcklbw */
7909 case 0x0f61: /* punpcklwd */
7910 case 0x0f62: /* punpckldq */
7911 case 0x0f63: /* packsswb */
7912 case 0x0f64: /* pcmpgtb */
7913 case 0x0f65: /* pcmpgtw */
7914 case 0x0f66: /* pcmpgtd */
7915 case 0x0f67: /* packuswb */
7916 case 0x0f68: /* punpckhbw */
7917 case 0x0f69: /* punpckhwd */
7918 case 0x0f6a: /* punpckhdq */
7919 case 0x0f6b: /* packssdw */
7920 case 0x0f6e: /* movd */
7921 case 0x0f6f: /* movq */
7922 case 0x0f70: /* pshufw */
7923 case 0x0f74: /* pcmpeqb */
7924 case 0x0f75: /* pcmpeqw */
7925 case 0x0f76: /* pcmpeqd */
7926 case 0x0fc4: /* pinsrw */
7927 case 0x0fd1: /* psrlw */
7928 case 0x0fd2: /* psrld */
7929 case 0x0fd3: /* psrlq */
7930 case 0x0fd4: /* paddq */
7931 case 0x0fd5: /* pmullw */
7932 case 0xf20fd6: /* movdq2q */
7933 case 0x0fd8: /* psubusb */
7934 case 0x0fd9: /* psubusw */
7935 case 0x0fda: /* pminub */
7936 case 0x0fdb: /* pand */
7937 case 0x0fdc: /* paddusb */
7938 case 0x0fdd: /* paddusw */
7939 case 0x0fde: /* pmaxub */
7940 case 0x0fdf: /* pandn */
7941 case 0x0fe0: /* pavgb */
7942 case 0x0fe1: /* psraw */
7943 case 0x0fe2: /* psrad */
7944 case 0x0fe3: /* pavgw */
7945 case 0x0fe4: /* pmulhuw */
7946 case 0x0fe5: /* pmulhw */
7947 case 0x0fe8: /* psubsb */
7948 case 0x0fe9: /* psubsw */
7949 case 0x0fea: /* pminsw */
7950 case 0x0feb: /* por */
7951 case 0x0fec: /* paddsb */
7952 case 0x0fed: /* paddsw */
7953 case 0x0fee: /* pmaxsw */
7954 case 0x0fef: /* pxor */
7955 case 0x0ff1: /* psllw */
7956 case 0x0ff2: /* pslld */
7957 case 0x0ff3: /* psllq */
7958 case 0x0ff4: /* pmuludq */
7959 case 0x0ff5: /* pmaddwd */
7960 case 0x0ff6: /* psadbw */
7961 case 0x0ff8: /* psubb */
7962 case 0x0ff9: /* psubw */
7963 case 0x0ffa: /* psubd */
7964 case 0x0ffb: /* psubq */
7965 case 0x0ffc: /* paddb */
7966 case 0x0ffd: /* paddw */
7967 case 0x0ffe: /* paddd */
7968 if (i386_record_modrm (&ir
))
7970 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7972 record_full_arch_list_add_reg (ir
.regcache
,
7973 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7976 case 0x0f71: /* psllw */
7977 case 0x0f72: /* pslld */
7978 case 0x0f73: /* psllq */
7979 if (i386_record_modrm (&ir
))
7981 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7983 record_full_arch_list_add_reg (ir
.regcache
,
7984 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7987 case 0x660f71: /* psllw */
7988 case 0x660f72: /* pslld */
7989 case 0x660f73: /* psllq */
7990 if (i386_record_modrm (&ir
))
7993 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7995 record_full_arch_list_add_reg (ir
.regcache
,
7996 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7999 case 0x0f7e: /* movd */
8000 case 0x660f7e: /* movd */
8001 if (i386_record_modrm (&ir
))
8004 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8011 if (i386_record_lea_modrm (&ir
))
8016 case 0x0f7f: /* movq */
8017 if (i386_record_modrm (&ir
))
8021 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8023 record_full_arch_list_add_reg (ir
.regcache
,
8024 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8029 if (i386_record_lea_modrm (&ir
))
8034 case 0xf30fb8: /* popcnt */
8035 if (i386_record_modrm (&ir
))
8037 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8038 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8041 case 0x660fd6: /* movq */
8042 if (i386_record_modrm (&ir
))
8047 if (!i386_xmm_regnum_p (gdbarch
,
8048 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8050 record_full_arch_list_add_reg (ir
.regcache
,
8051 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8056 if (i386_record_lea_modrm (&ir
))
8061 case 0x660f3817: /* ptest */
8062 case 0x0f2e: /* ucomiss */
8063 case 0x660f2e: /* ucomisd */
8064 case 0x0f2f: /* comiss */
8065 case 0x660f2f: /* comisd */
8066 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8069 case 0x0ff7: /* maskmovq */
8070 regcache_raw_read_unsigned (ir
.regcache
,
8071 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8073 if (record_full_arch_list_add_mem (addr
, 64))
8077 case 0x660ff7: /* maskmovdqu */
8078 regcache_raw_read_unsigned (ir
.regcache
,
8079 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8081 if (record_full_arch_list_add_mem (addr
, 128))
8096 /* In the future, maybe still need to deal with need_dasm. */
8097 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8098 if (record_full_arch_list_add_end ())
8104 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8105 "at address %s.\n"),
8106 (unsigned int) (opcode
),
8107 paddress (gdbarch
, ir
.orig_addr
));
8111 static const int i386_record_regmap
[] =
8113 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8114 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8115 0, 0, 0, 0, 0, 0, 0, 0,
8116 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8117 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8120 /* Check that the given address appears suitable for a fast
8121 tracepoint, which on x86-64 means that we need an instruction of at
8122 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8123 jump and not have to worry about program jumps to an address in the
8124 middle of the tracepoint jump. On x86, it may be possible to use
8125 4-byte jumps with a 2-byte offset to a trampoline located in the
8126 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8127 of instruction to replace, and 0 if not, plus an explanatory
8131 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8136 /* Ask the target for the minimum instruction length supported. */
8137 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8141 /* If the target does not support the get_min_fast_tracepoint_insn_len
8142 operation, assume that fast tracepoints will always be implemented
8143 using 4-byte relative jumps on both x86 and x86-64. */
8146 else if (jumplen
== 0)
8148 /* If the target does support get_min_fast_tracepoint_insn_len but
8149 returns zero, then the IPA has not loaded yet. In this case,
8150 we optimistically assume that truncated 2-byte relative jumps
8151 will be available on x86, and compensate later if this assumption
8152 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8153 jumps will always be used. */
8154 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8157 /* Check for fit. */
8158 len
= gdb_insn_length (gdbarch
, addr
);
8162 /* Return a bit of target-specific detail to add to the caller's
8163 generic failure message. */
8165 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
8166 "need at least %d bytes for the jump"),
8178 /* Return a floating-point format for a floating-point variable of
8179 length LEN in bits. If non-NULL, NAME is the name of its type.
8180 If no suitable type is found, return NULL. */
8182 const struct floatformat
**
8183 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8184 const char *name
, int len
)
8186 if (len
== 128 && name
)
8187 if (strcmp (name
, "__float128") == 0
8188 || strcmp (name
, "_Float128") == 0
8189 || strcmp (name
, "complex _Float128") == 0)
8190 return floatformats_ia64_quad
;
8192 return default_floatformat_for_type (gdbarch
, name
, len
);
8196 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8197 struct tdesc_arch_data
*tdesc_data
)
8199 const struct target_desc
*tdesc
= tdep
->tdesc
;
8200 const struct tdesc_feature
*feature_core
;
8202 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8204 int i
, num_regs
, valid_p
;
8206 if (! tdesc_has_registers (tdesc
))
8209 /* Get core registers. */
8210 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8211 if (feature_core
== NULL
)
8214 /* Get SSE registers. */
8215 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8217 /* Try AVX registers. */
8218 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8220 /* Try MPX registers. */
8221 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8223 /* Try AVX512 registers. */
8224 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8228 /* The XCR0 bits. */
8231 /* AVX512 register description requires AVX register description. */
8235 tdep
->xcr0
= X86_XSTATE_AVX_MPX_AVX512_MASK
;
8237 /* It may have been set by OSABI initialization function. */
8238 if (tdep
->k0_regnum
< 0)
8240 tdep
->k_register_names
= i386_k_names
;
8241 tdep
->k0_regnum
= I386_K0_REGNUM
;
8244 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8245 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8246 tdep
->k0_regnum
+ i
,
8249 if (tdep
->num_zmm_regs
== 0)
8251 tdep
->zmmh_register_names
= i386_zmmh_names
;
8252 tdep
->num_zmm_regs
= 8;
8253 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8256 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8257 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8258 tdep
->zmm0h_regnum
+ i
,
8259 tdep
->zmmh_register_names
[i
]);
8261 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8262 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8263 tdep
->xmm16_regnum
+ i
,
8264 tdep
->xmm_avx512_register_names
[i
]);
8266 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8267 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8268 tdep
->ymm16h_regnum
+ i
,
8269 tdep
->ymm16h_register_names
[i
]);
8273 /* AVX register description requires SSE register description. */
8277 if (!feature_avx512
)
8278 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8280 /* It may have been set by OSABI initialization function. */
8281 if (tdep
->num_ymm_regs
== 0)
8283 tdep
->ymmh_register_names
= i386_ymmh_names
;
8284 tdep
->num_ymm_regs
= 8;
8285 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8288 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8289 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8290 tdep
->ymm0h_regnum
+ i
,
8291 tdep
->ymmh_register_names
[i
]);
8293 else if (feature_sse
)
8294 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8297 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8298 tdep
->num_xmm_regs
= 0;
8301 num_regs
= tdep
->num_core_regs
;
8302 for (i
= 0; i
< num_regs
; i
++)
8303 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8304 tdep
->register_names
[i
]);
8308 /* Need to include %mxcsr, so add one. */
8309 num_regs
+= tdep
->num_xmm_regs
+ 1;
8310 for (; i
< num_regs
; i
++)
8311 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8312 tdep
->register_names
[i
]);
8317 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8319 if (tdep
->bnd0r_regnum
< 0)
8321 tdep
->mpx_register_names
= i386_mpx_names
;
8322 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8323 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8326 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8327 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8328 I387_BND0R_REGNUM (tdep
) + i
,
8329 tdep
->mpx_register_names
[i
]);
8336 /* Note: This is called for both i386 and amd64. */
8338 static struct gdbarch
*
8339 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8341 struct gdbarch_tdep
*tdep
;
8342 struct gdbarch
*gdbarch
;
8343 struct tdesc_arch_data
*tdesc_data
;
8344 const struct target_desc
*tdesc
;
8350 /* If there is already a candidate, use it. */
8351 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8353 return arches
->gdbarch
;
8355 /* Allocate space for the new architecture. Assume i386 for now. */
8356 tdep
= XCNEW (struct gdbarch_tdep
);
8357 gdbarch
= gdbarch_alloc (&info
, tdep
);
8359 /* General-purpose registers. */
8360 tdep
->gregset_reg_offset
= NULL
;
8361 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8362 tdep
->sizeof_gregset
= 0;
8364 /* Floating-point registers. */
8365 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8366 tdep
->fpregset
= &i386_fpregset
;
8368 /* The default settings include the FPU registers, the MMX registers
8369 and the SSE registers. This can be overridden for a specific ABI
8370 by adjusting the members `st0_regnum', `mm0_regnum' and
8371 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8372 will show up in the output of "info all-registers". */
8374 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8376 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8377 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8379 tdep
->jb_pc_offset
= -1;
8380 tdep
->struct_return
= pcc_struct_return
;
8381 tdep
->sigtramp_start
= 0;
8382 tdep
->sigtramp_end
= 0;
8383 tdep
->sigtramp_p
= i386_sigtramp_p
;
8384 tdep
->sigcontext_addr
= NULL
;
8385 tdep
->sc_reg_offset
= NULL
;
8386 tdep
->sc_pc_offset
= -1;
8387 tdep
->sc_sp_offset
= -1;
8389 tdep
->xsave_xcr0_offset
= -1;
8391 tdep
->record_regmap
= i386_record_regmap
;
8393 set_gdbarch_long_long_align_bit (gdbarch
, 32);
8395 /* The format used for `long double' on almost all i386 targets is
8396 the i387 extended floating-point format. In fact, of all targets
8397 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8398 on having a `long double' that's not `long' at all. */
8399 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8401 /* Although the i387 extended floating-point has only 80 significant
8402 bits, a `long double' actually takes up 96, probably to enforce
8404 set_gdbarch_long_double_bit (gdbarch
, 96);
8406 /* Support for floating-point data type variants. */
8407 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8409 /* Register numbers of various important registers. */
8410 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8411 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8412 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8413 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8415 /* NOTE: kettenis/20040418: GCC does have two possible register
8416 numbering schemes on the i386: dbx and SVR4. These schemes
8417 differ in how they number %ebp, %esp, %eflags, and the
8418 floating-point registers, and are implemented by the arrays
8419 dbx_register_map[] and svr4_dbx_register_map in
8420 gcc/config/i386.c. GCC also defines a third numbering scheme in
8421 gcc/config/i386.c, which it designates as the "default" register
8422 map used in 64bit mode. This last register numbering scheme is
8423 implemented in dbx64_register_map, and is used for AMD64; see
8426 Currently, each GCC i386 target always uses the same register
8427 numbering scheme across all its supported debugging formats
8428 i.e. SDB (COFF), stabs and DWARF 2. This is because
8429 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8430 DBX_REGISTER_NUMBER macro which is defined by each target's
8431 respective config header in a manner independent of the requested
8432 output debugging format.
8434 This does not match the arrangement below, which presumes that
8435 the SDB and stabs numbering schemes differ from the DWARF and
8436 DWARF 2 ones. The reason for this arrangement is that it is
8437 likely to get the numbering scheme for the target's
8438 default/native debug format right. For targets where GCC is the
8439 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8440 targets where the native toolchain uses a different numbering
8441 scheme for a particular debug format (stabs-in-ELF on Solaris)
8442 the defaults below will have to be overridden, like
8443 i386_elf_init_abi() does. */
8445 /* Use the dbx register numbering scheme for stabs and COFF. */
8446 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8447 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8449 /* Use the SVR4 register numbering scheme for DWARF 2. */
8450 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8452 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8453 be in use on any of the supported i386 targets. */
8455 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8457 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8459 /* Call dummy code. */
8460 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8461 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8462 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8463 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8465 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8466 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8467 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8469 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8471 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8473 /* Stack grows downward. */
8474 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8476 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8477 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8479 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8480 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8482 set_gdbarch_frame_args_skip (gdbarch
, 8);
8484 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8486 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8488 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8490 /* Add the i386 register groups. */
8491 i386_add_reggroups (gdbarch
);
8492 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8494 /* Helper for function argument information. */
8495 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8497 /* Hook the function epilogue frame unwinder. This unwinder is
8498 appended to the list first, so that it supercedes the DWARF
8499 unwinder in function epilogues (where the DWARF unwinder
8500 currently fails). */
8501 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8503 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8504 to the list before the prologue-based unwinders, so that DWARF
8505 CFI info will be used if it is available. */
8506 dwarf2_append_unwinders (gdbarch
);
8508 frame_base_set_default (gdbarch
, &i386_frame_base
);
8510 /* Pseudo registers may be changed by amd64_init_abi. */
8511 set_gdbarch_pseudo_register_read_value (gdbarch
,
8512 i386_pseudo_register_read_value
);
8513 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8514 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8515 i386_ax_pseudo_register_collect
);
8517 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8518 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8520 /* Override the normal target description method to make the AVX
8521 upper halves anonymous. */
8522 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8524 /* Even though the default ABI only includes general-purpose registers,
8525 floating-point registers and the SSE registers, we have to leave a
8526 gap for the upper AVX, MPX and AVX512 registers. */
8527 set_gdbarch_num_regs (gdbarch
, I386_AVX512_NUM_REGS
);
8529 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8531 /* Get the x86 target description from INFO. */
8532 tdesc
= info
.target_desc
;
8533 if (! tdesc_has_registers (tdesc
))
8535 tdep
->tdesc
= tdesc
;
8537 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8538 tdep
->register_names
= i386_register_names
;
8540 /* No upper YMM registers. */
8541 tdep
->ymmh_register_names
= NULL
;
8542 tdep
->ymm0h_regnum
= -1;
8544 /* No upper ZMM registers. */
8545 tdep
->zmmh_register_names
= NULL
;
8546 tdep
->zmm0h_regnum
= -1;
8548 /* No high XMM registers. */
8549 tdep
->xmm_avx512_register_names
= NULL
;
8550 tdep
->xmm16_regnum
= -1;
8552 /* No upper YMM16-31 registers. */
8553 tdep
->ymm16h_register_names
= NULL
;
8554 tdep
->ymm16h_regnum
= -1;
8556 tdep
->num_byte_regs
= 8;
8557 tdep
->num_word_regs
= 8;
8558 tdep
->num_dword_regs
= 0;
8559 tdep
->num_mmx_regs
= 8;
8560 tdep
->num_ymm_regs
= 0;
8562 /* No MPX registers. */
8563 tdep
->bnd0r_regnum
= -1;
8564 tdep
->bndcfgu_regnum
= -1;
8566 /* No AVX512 registers. */
8567 tdep
->k0_regnum
= -1;
8568 tdep
->num_zmm_regs
= 0;
8569 tdep
->num_ymm_avx512_regs
= 0;
8570 tdep
->num_xmm_avx512_regs
= 0;
8572 tdesc_data
= tdesc_data_alloc ();
8574 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8576 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8578 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8579 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8580 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8582 /* Hook in ABI-specific overrides, if they have been registered.
8583 Note: If INFO specifies a 64 bit arch, this is where we turn
8584 a 32-bit i386 into a 64-bit amd64. */
8585 info
.tdep_info
= tdesc_data
;
8586 gdbarch_init_osabi (info
, gdbarch
);
8588 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8590 tdesc_data_cleanup (tdesc_data
);
8592 gdbarch_free (gdbarch
);
8596 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8598 /* Wire in pseudo registers. Number of pseudo registers may be
8600 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8601 + tdep
->num_word_regs
8602 + tdep
->num_dword_regs
8603 + tdep
->num_mmx_regs
8604 + tdep
->num_ymm_regs
8606 + tdep
->num_ymm_avx512_regs
8607 + tdep
->num_zmm_regs
));
8609 /* Target description may be changed. */
8610 tdesc
= tdep
->tdesc
;
8612 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8614 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8615 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8617 /* Make %al the first pseudo-register. */
8618 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8619 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8621 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8622 if (tdep
->num_dword_regs
)
8624 /* Support dword pseudo-register if it hasn't been disabled. */
8625 tdep
->eax_regnum
= ymm0_regnum
;
8626 ymm0_regnum
+= tdep
->num_dword_regs
;
8629 tdep
->eax_regnum
= -1;
8631 mm0_regnum
= ymm0_regnum
;
8632 if (tdep
->num_ymm_regs
)
8634 /* Support YMM pseudo-register if it is available. */
8635 tdep
->ymm0_regnum
= ymm0_regnum
;
8636 mm0_regnum
+= tdep
->num_ymm_regs
;
8639 tdep
->ymm0_regnum
= -1;
8641 if (tdep
->num_ymm_avx512_regs
)
8643 /* Support YMM16-31 pseudo registers if available. */
8644 tdep
->ymm16_regnum
= mm0_regnum
;
8645 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8648 tdep
->ymm16_regnum
= -1;
8650 if (tdep
->num_zmm_regs
)
8652 /* Support ZMM pseudo-register if it is available. */
8653 tdep
->zmm0_regnum
= mm0_regnum
;
8654 mm0_regnum
+= tdep
->num_zmm_regs
;
8657 tdep
->zmm0_regnum
= -1;
8659 bnd0_regnum
= mm0_regnum
;
8660 if (tdep
->num_mmx_regs
!= 0)
8662 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8663 tdep
->mm0_regnum
= mm0_regnum
;
8664 bnd0_regnum
+= tdep
->num_mmx_regs
;
8667 tdep
->mm0_regnum
= -1;
8669 if (tdep
->bnd0r_regnum
> 0)
8670 tdep
->bnd0_regnum
= bnd0_regnum
;
8672 tdep
-> bnd0_regnum
= -1;
8674 /* Hook in the legacy prologue-based unwinders last (fallback). */
8675 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8676 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8677 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8679 /* If we have a register mapping, enable the generic core file
8680 support, unless it has already been enabled. */
8681 if (tdep
->gregset_reg_offset
8682 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8683 set_gdbarch_iterate_over_regset_sections
8684 (gdbarch
, i386_iterate_over_regset_sections
);
8686 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8687 i386_fast_tracepoint_valid_at
);
8692 static enum gdb_osabi
8693 i386_coff_osabi_sniffer (bfd
*abfd
)
8695 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
8696 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
8697 return GDB_OSABI_GO32
;
8699 return GDB_OSABI_UNKNOWN
;
8703 /* Return the target description for a specified XSAVE feature mask. */
8705 const struct target_desc
*
8706 i386_target_description (uint64_t xcr0
)
8708 switch (xcr0
& X86_XSTATE_ALL_MASK
)
8710 case X86_XSTATE_AVX_MPX_AVX512_MASK
:
8711 case X86_XSTATE_AVX_AVX512_MASK
:
8712 return tdesc_i386_avx_mpx_avx512
;
8713 case X86_XSTATE_AVX_MPX_MASK
:
8714 return tdesc_i386_avx_mpx
;
8715 case X86_XSTATE_MPX_MASK
:
8716 return tdesc_i386_mpx
;
8717 case X86_XSTATE_AVX_MASK
:
8718 return tdesc_i386_avx
;
8724 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8726 /* Find the bound directory base address. */
8728 static unsigned long
8729 i386_mpx_bd_base (void)
8731 struct regcache
*rcache
;
8732 struct gdbarch_tdep
*tdep
;
8734 enum register_status regstatus
;
8736 rcache
= get_current_regcache ();
8737 tdep
= gdbarch_tdep (get_regcache_arch (rcache
));
8739 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8741 if (regstatus
!= REG_VALID
)
8742 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8744 return ret
& MPX_BASE_MASK
;
8748 i386_mpx_enabled (void)
8750 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8751 const struct target_desc
*tdesc
= tdep
->tdesc
;
8753 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8756 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8757 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8758 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8759 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8761 /* Find the bound table entry given the pointer location and the base
8762 address of the table. */
8765 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8769 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8770 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8771 CORE_ADDR bd_entry_addr
;
8774 struct gdbarch
*gdbarch
= get_current_arch ();
8775 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8778 if (gdbarch_ptr_bit (gdbarch
) == 64)
8780 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8781 bd_ptr_r_shift
= 20;
8783 bt_select_r_shift
= 3;
8784 bt_select_l_shift
= 5;
8785 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8787 if ( sizeof (CORE_ADDR
) == 4)
8788 error (_("bound table examination not supported\
8789 for 64-bit process with 32-bit GDB"));
8793 mpx_bd_mask
= MPX_BD_MASK_32
;
8794 bd_ptr_r_shift
= 12;
8796 bt_select_r_shift
= 2;
8797 bt_select_l_shift
= 4;
8798 bt_mask
= MPX_BT_MASK_32
;
8801 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8802 bd_entry_addr
= bd_base
+ offset1
;
8803 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8805 if ((bd_entry
& 0x1) == 0)
8806 error (_("Invalid bounds directory entry at %s."),
8807 paddress (get_current_arch (), bd_entry_addr
));
8809 /* Clearing status bit. */
8811 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8812 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8814 return bt_addr
+ offset2
;
8817 /* Print routine for the mpx bounds. */
8820 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8822 struct ui_out
*uiout
= current_uiout
;
8824 struct gdbarch
*gdbarch
= get_current_arch ();
8825 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8826 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8828 if (bounds_in_map
== 1)
8830 uiout
->text ("Null bounds on map:");
8831 uiout
->text (" pointer value = ");
8832 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8838 uiout
->text ("{lbound = ");
8839 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8840 uiout
->text (", ubound = ");
8842 /* The upper bound is stored in 1's complement. */
8843 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8844 uiout
->text ("}: pointer value = ");
8845 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8847 if (gdbarch_ptr_bit (gdbarch
) == 64)
8848 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8850 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8852 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8853 -1 represents in this sense full memory access, and there is no need
8856 size
= (size
> -1 ? size
+ 1 : size
);
8857 uiout
->text (", size = ");
8858 uiout
->field_fmt ("size", "%s", plongest (size
));
8860 uiout
->text (", metadata = ");
8861 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8866 /* Implement the command "show mpx bound". */
8869 i386_mpx_info_bounds (char *args
, int from_tty
)
8871 CORE_ADDR bd_base
= 0;
8873 CORE_ADDR bt_entry_addr
= 0;
8874 CORE_ADDR bt_entry
[4];
8876 struct gdbarch
*gdbarch
= get_current_arch ();
8877 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8879 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8880 || !i386_mpx_enabled ())
8882 printf_unfiltered (_("Intel Memory Protection Extensions not "
8883 "supported on this target.\n"));
8889 printf_unfiltered (_("Address of pointer variable expected.\n"));
8893 addr
= parse_and_eval_address (args
);
8895 bd_base
= i386_mpx_bd_base ();
8896 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8898 memset (bt_entry
, 0, sizeof (bt_entry
));
8900 for (i
= 0; i
< 4; i
++)
8901 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8902 + i
* TYPE_LENGTH (data_ptr_type
),
8905 i386_mpx_print_bounds (bt_entry
);
8908 /* Implement the command "set mpx bound". */
8911 i386_mpx_set_bounds (char *args
, int from_tty
)
8913 CORE_ADDR bd_base
= 0;
8914 CORE_ADDR addr
, lower
, upper
;
8915 CORE_ADDR bt_entry_addr
= 0;
8916 CORE_ADDR bt_entry
[2];
8917 const char *input
= args
;
8919 struct gdbarch
*gdbarch
= get_current_arch ();
8920 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8921 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8923 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8924 || !i386_mpx_enabled ())
8925 error (_("Intel Memory Protection Extensions not supported\
8929 error (_("Pointer value expected."));
8931 addr
= value_as_address (parse_to_comma_and_eval (&input
));
8933 if (input
[0] == ',')
8935 if (input
[0] == '\0')
8936 error (_("wrong number of arguments: missing lower and upper bound."));
8937 lower
= value_as_address (parse_to_comma_and_eval (&input
));
8939 if (input
[0] == ',')
8941 if (input
[0] == '\0')
8942 error (_("Wrong number of arguments; Missing upper bound."));
8943 upper
= value_as_address (parse_to_comma_and_eval (&input
));
8945 bd_base
= i386_mpx_bd_base ();
8946 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8947 for (i
= 0; i
< 2; i
++)
8948 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8949 + i
* TYPE_LENGTH (data_ptr_type
),
8951 bt_entry
[0] = (uint64_t) lower
;
8952 bt_entry
[1] = ~(uint64_t) upper
;
8954 for (i
= 0; i
< 2; i
++)
8955 write_memory_unsigned_integer (bt_entry_addr
8956 + i
* TYPE_LENGTH (data_ptr_type
),
8957 TYPE_LENGTH (data_ptr_type
), byte_order
,
8961 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
8963 /* Helper function for the CLI commands. */
8966 set_mpx_cmd (char *args
, int from_tty
)
8968 help_list (mpx_set_cmdlist
, "set mpx ", all_commands
, gdb_stdout
);
8971 /* Helper function for the CLI commands. */
8974 show_mpx_cmd (char *args
, int from_tty
)
8976 cmd_show_list (mpx_show_cmdlist
, from_tty
, "");
8979 /* Provide a prototype to silence -Wmissing-prototypes. */
8980 void _initialize_i386_tdep (void);
8983 _initialize_i386_tdep (void)
8985 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8987 /* Add the variable that controls the disassembly flavor. */
8988 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8989 &disassembly_flavor
, _("\
8990 Set the disassembly flavor."), _("\
8991 Show the disassembly flavor."), _("\
8992 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8994 NULL
, /* FIXME: i18n: */
8995 &setlist
, &showlist
);
8997 /* Add the variable that controls the convention for returning
8999 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9000 &struct_convention
, _("\
9001 Set the convention for returning small structs."), _("\
9002 Show the convention for returning small structs."), _("\
9003 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9006 NULL
, /* FIXME: i18n: */
9007 &setlist
, &showlist
);
9009 /* Add "mpx" prefix for the set commands. */
9011 add_prefix_cmd ("mpx", class_support
, set_mpx_cmd
, _("\
9012 Set Intel Memory Protection Extensions specific variables."),
9013 &mpx_set_cmdlist
, "set mpx ",
9014 0 /* allow-unknown */, &setlist
);
9016 /* Add "mpx" prefix for the show commands. */
9018 add_prefix_cmd ("mpx", class_support
, show_mpx_cmd
, _("\
9019 Show Intel Memory Protection Extensions specific variables."),
9020 &mpx_show_cmdlist
, "show mpx ",
9021 0 /* allow-unknown */, &showlist
);
9023 /* Add "bound" command for the show mpx commands list. */
9025 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9026 "Show the memory bounds for a given array/pointer storage\
9027 in the bound table.",
9030 /* Add "bound" command for the set mpx commands list. */
9032 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9033 "Set the memory bounds for a given array/pointer storage\
9034 in the bound table.",
9037 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
9038 i386_coff_osabi_sniffer
);
9040 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9041 i386_svr4_init_abi
);
9042 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
9043 i386_go32_init_abi
);
9045 /* Initialize the i386-specific register groups. */
9046 i386_init_reggroups ();
9048 /* Initialize the standard target descriptions. */
9049 initialize_tdesc_i386 ();
9050 initialize_tdesc_i386_mmx ();
9051 initialize_tdesc_i386_avx ();
9052 initialize_tdesc_i386_mpx ();
9053 initialize_tdesc_i386_avx_mpx ();
9054 initialize_tdesc_i386_avx_mpx_avx512 ();
9056 /* Tell remote stub that we support XML target description. */
9057 register_remote_support_xml ("i386");