1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 struct frame_extra_info
41 mips_extra_func_info_t proc_desc
;
45 /* Some MIPS boards don't support floating point while others only
46 support single-precision floating-point operations. See also
47 FP_REGISTER_DOUBLE. */
51 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
52 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
53 MIPS_FPU_NONE
/* No floating point. */
56 #ifndef MIPS_DEFAULT_FPU_TYPE
57 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
59 static int mips_fpu_type_auto
= 1;
60 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
61 #define MIPS_FPU_TYPE mips_fpu_type
63 #ifndef MIPS_SAVED_REGSIZE
64 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
67 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
68 #ifndef FP_REGISTER_DOUBLE
69 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
73 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
76 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
79 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
81 static void mips_print_register
PARAMS ((int, int));
83 static mips_extra_func_info_t
84 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
86 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
88 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
90 void mips_set_processor_type_command
PARAMS ((char *, int));
92 int mips_set_processor_type
PARAMS ((char *));
94 static void mips_show_processor_type_command
PARAMS ((char *, int));
96 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
97 struct cmd_list_element
*));
99 static mips_extra_func_info_t
100 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
102 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
103 mips_extra_func_info_t proc_desc
));
105 /* This value is the model of MIPS in use. It is derived from the value
106 of the PrID register. */
108 char *mips_processor_type
;
110 char *tmp_mips_processor_type
;
112 /* A set of original names, to be used when restoring back to generic
113 registers from a specific set. */
115 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
116 char **mips_processor_reg_names
= mips_generic_reg_names
;
119 mips_register_name (i
)
122 return mips_processor_reg_names
[i
];
127 /* Names of IDT R3041 registers. */
129 char *mips_r3041_reg_names
[] = {
130 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
131 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
132 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
133 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
134 "sr", "lo", "hi", "bad", "cause","pc",
135 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
136 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
137 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
138 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
139 "fsr", "fir", "fp", "",
140 "", "", "bus", "ccfg", "", "", "", "",
141 "", "", "port", "cmp", "", "", "epc", "prid",
144 /* Names of IDT R3051 registers. */
146 char *mips_r3051_reg_names
[] = {
147 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
148 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
149 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
150 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
151 "sr", "lo", "hi", "bad", "cause","pc",
152 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
153 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
154 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
155 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
156 "fsr", "fir", "fp", "",
157 "inx", "rand", "elo", "", "ctxt", "", "", "",
158 "", "", "ehi", "", "", "", "epc", "prid",
161 /* Names of IDT R3081 registers. */
163 char *mips_r3081_reg_names
[] = {
164 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
165 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
166 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
167 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
168 "sr", "lo", "hi", "bad", "cause","pc",
169 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
170 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
171 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
172 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
173 "fsr", "fir", "fp", "",
174 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
175 "", "", "ehi", "", "", "", "epc", "prid",
178 /* Names of LSI 33k registers. */
180 char *mips_lsi33k_reg_names
[] = {
181 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
182 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
183 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
184 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
185 "epc", "hi", "lo", "sr", "cause","badvaddr",
186 "dcic", "bpc", "bda", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
198 } mips_processor_type_table
[] = {
199 { "generic", mips_generic_reg_names
},
200 { "r3041", mips_r3041_reg_names
},
201 { "r3051", mips_r3051_reg_names
},
202 { "r3071", mips_r3081_reg_names
},
203 { "r3081", mips_r3081_reg_names
},
204 { "lsi33k", mips_lsi33k_reg_names
},
209 /* Table to translate MIPS16 register field to actual register number. */
210 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
212 /* Heuristic_proc_start may hunt through the text section for a long
213 time across a 2400 baud serial line. Allows the user to limit this
216 static unsigned int heuristic_fence_post
= 0;
218 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
219 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
220 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
221 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
222 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
223 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
224 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
225 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
226 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
227 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
228 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
229 #define _PROC_MAGIC_ 0x0F0F0F0F
230 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
231 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
233 struct linked_proc_info
235 struct mips_extra_func_info info
;
236 struct linked_proc_info
*next
;
237 } *linked_proc_desc_table
= NULL
;
240 mips_print_extra_frame_info (fi
)
241 struct frame_info
*fi
;
245 && fi
->extra_info
->proc_desc
246 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
247 printf_filtered (" frame pointer is at %s+%d\n",
248 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
249 fi
->extra_info
->proc_desc
->pdr
.frameoffset
);
252 /* Should the upper word of 64-bit addresses be zeroed? */
253 static int mask_address_p
= 1;
255 /* Should call_function allocate stack space for a struct return? */
257 mips_use_struct_convention (gcc_p
, type
)
262 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
264 return 1; /* Structures are returned by ref in extra arg0 */
267 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
270 pc_is_mips16 (bfd_vma memaddr
)
272 struct minimal_symbol
*sym
;
274 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
275 if (IS_MIPS16_ADDR (memaddr
))
278 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
279 the high bit of the info field. Use this to decide if the function is
280 MIPS16 or normal MIPS. */
281 sym
= lookup_minimal_symbol_by_pc (memaddr
);
283 return MSYMBOL_IS_SPECIAL (sym
);
289 /* This returns the PC of the first inst after the prologue. If we can't
290 find the prologue, then return 0. */
293 after_prologue (pc
, proc_desc
)
295 mips_extra_func_info_t proc_desc
;
297 struct symtab_and_line sal
;
298 CORE_ADDR func_addr
, func_end
;
301 proc_desc
= find_proc_desc (pc
, NULL
);
305 /* If function is frameless, then we need to do it the hard way. I
306 strongly suspect that frameless always means prologueless... */
307 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
308 && PROC_FRAME_OFFSET (proc_desc
) == 0)
312 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
313 return 0; /* Unknown */
315 sal
= find_pc_line (func_addr
, 0);
317 if (sal
.end
< func_end
)
320 /* The line after the prologue is after the end of the function. In this
321 case, tell the caller to find the prologue the hard way. */
326 /* Decode a MIPS32 instruction that saves a register in the stack, and
327 set the appropriate bit in the general register mask or float register mask
328 to indicate which register is saved. This is a helper function
329 for mips_find_saved_regs. */
332 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
334 unsigned long *gen_mask
;
335 unsigned long *float_mask
;
339 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
340 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
341 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
343 /* It might be possible to use the instruction to
344 find the offset, rather than the code below which
345 is based on things being in a certain order in the
346 frame, but figuring out what the instruction's offset
347 is relative to might be a little tricky. */
348 reg
= (inst
& 0x001f0000) >> 16;
349 *gen_mask
|= (1 << reg
);
351 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
352 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
353 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
356 reg
= ((inst
& 0x001f0000) >> 16);
357 *float_mask
|= (1 << reg
);
361 /* Decode a MIPS16 instruction that saves a register in the stack, and
362 set the appropriate bit in the general register or float register mask
363 to indicate which register is saved. This is a helper function
364 for mips_find_saved_regs. */
367 mips16_decode_reg_save (inst
, gen_mask
)
369 unsigned long *gen_mask
;
371 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
373 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
374 *gen_mask
|= (1 << reg
);
376 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
378 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
379 *gen_mask
|= (1 << reg
);
381 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
382 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
383 *gen_mask
|= (1 << RA_REGNUM
);
387 /* Fetch and return instruction from the specified location. If the PC
388 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
391 mips_fetch_instruction (addr
)
394 char buf
[MIPS_INSTLEN
];
398 if (pc_is_mips16 (addr
))
400 instlen
= MIPS16_INSTLEN
;
401 addr
= UNMAKE_MIPS16_ADDR (addr
);
404 instlen
= MIPS_INSTLEN
;
405 status
= read_memory_nobpt (addr
, buf
, instlen
);
407 memory_error (status
, addr
);
408 return extract_unsigned_integer (buf
, instlen
);
412 /* These the fields of 32 bit mips instructions */
413 #define mips32_op(x) (x >> 25)
414 #define itype_op(x) (x >> 25)
415 #define itype_rs(x) ((x >> 21)& 0x1f)
416 #define itype_rt(x) ((x >> 16) & 0x1f)
417 #define itype_immediate(x) ( x & 0xffff)
419 #define jtype_op(x) (x >> 25)
420 #define jtype_target(x) ( x & 0x03fffff)
422 #define rtype_op(x) (x >>25)
423 #define rtype_rs(x) ((x>>21) & 0x1f)
424 #define rtype_rt(x) ((x>>16) & 0x1f)
425 #define rtype_rd(x) ((x>>11) & 0x1f)
426 #define rtype_shamt(x) ((x>>6) & 0x1f)
427 #define rtype_funct(x) (x & 0x3f )
430 mips32_relative_offset(unsigned long inst
)
432 x
= itype_immediate(inst
) ;
433 if (x
& 0x8000) /* sign bit set */
435 x
|= 0xffff0000 ; /* sign extension */
441 /* Determine whate to set a single step breakpoint while considering
444 mips32_next_pc(CORE_ADDR pc
)
448 inst
= mips_fetch_instruction(pc
) ;
449 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
450 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
451 { op
= ((inst
>> 25) & 0x03) ;
454 case 0 : goto equal_branch
; /* BEQL */
455 case 1 : goto neq_branch
; /* BNEZ */
456 case 2 : goto less_branch
; /* BLEZ */
457 case 3 : goto greater_branch
; /* BGTZ */
461 else pc
+= 4 ; /* Not a branch, next instruction is easy */
464 { /* This gets way messy */
466 /* Further subdivide into SPECIAL, REGIMM and other */
467 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
469 case 0 : /* SPECIAL */
470 op
= rtype_funct(inst
) ;
475 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
480 break ; /* end special */
481 case 1 : /* REGIMM */
483 op
= jtype_op(inst
) ; /* branch condition */
484 switch (jtype_op(inst
))
488 case 16 : /* BLTZALL */
489 case 18 : /* BLTZALL */
491 if (read_register(itype_rs(inst
)) < 0)
492 pc
+= mips32_relative_offset(inst
) + 4 ;
493 else pc
+= 8 ; /* after the delay slot */
497 case 17 : /* BGEZAL */
498 case 19 : /* BGEZALL */
499 greater_equal_branch
:
500 if (read_register(itype_rs(inst
)) >= 0)
501 pc
+= mips32_relative_offset(inst
) + 4 ;
502 else pc
+= 8 ; /* after the delay slot */
504 /* All of the other intructions in the REGIMM catagory */
508 break ; /* end REGIMM */
511 { unsigned long reg
;
512 reg
= jtype_target(inst
) << 2 ;
513 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
514 /* Whats this mysterious 0xf000000 adjustment ??? */
517 /* FIXME case JALX :*/
518 { unsigned long reg
;
519 reg
= jtype_target(inst
) << 2 ;
520 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
521 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
523 break ; /* The new PC will be alternate mode */
524 case 4 : /* BEQ , BEQL */
526 if (read_register(itype_rs(inst
)) ==
527 read_register(itype_rt(inst
)))
528 pc
+= mips32_relative_offset(inst
) + 4 ;
531 case 5 : /* BNE , BNEL */
533 if (read_register(itype_rs(inst
)) !=
534 read_register(itype_rs(inst
)))
535 pc
+= mips32_relative_offset(inst
) + 4 ;
538 case 6 : /* BLEZ , BLEZL */
540 if (read_register(itype_rs(inst
) <= 0))
541 pc
+= mips32_relative_offset(inst
) + 4 ;
545 greater_branch
: /* BGTZ BGTZL */
546 if (read_register(itype_rs(inst
) > 0))
547 pc
+= mips32_relative_offset(inst
) + 4 ;
554 } /* mips32_next_pc */
556 /* Decoding the next place to set a breakpoint is irregular for the
557 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
558 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
559 We dont want to set a single step instruction on the extend instruction
563 /* Lots of mips16 instruction formats */
564 /* Predicting jumps requires itype,ritype,i8type
565 and their extensions extItype,extritype,extI8type
567 enum mips16_inst_fmts
569 itype
, /* 0 immediate 5,10 */
570 ritype
, /* 1 5,3,8 */
571 rrtype
, /* 2 5,3,3,5 */
572 rritype
, /* 3 5,3,3,5 */
573 rrrtype
, /* 4 5,3,3,3,2 */
574 rriatype
, /* 5 5,3,3,1,4 */
575 shifttype
, /* 6 5,3,3,3,2 */
576 i8type
, /* 7 5,3,8 */
577 i8movtype
, /* 8 5,3,3,5 */
578 i8mov32rtype
, /* 9 5,3,5,3 */
579 i64type
, /* 10 5,3,8 */
580 ri64type
, /* 11 5,3,3,5 */
581 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
582 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
583 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
584 extRRItype
, /* 15 5,5,5,5,3,3,5 */
585 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
586 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
587 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
588 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
589 extRi64type
, /* 20 5,6,5,5,3,3,5 */
590 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
592 /* I am heaping all the fields of the formats into one structure and then,
593 only the fields which are involved in instruction extension */
596 unsigned short inst
;
597 enum mips16_inst_fmts fmt
;
598 unsigned long offset
;
599 unsigned int regx
; /* Function in i8 type */
605 static void print_unpack(char * comment
,
606 struct upk_mips16
* u
)
608 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
609 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
612 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
613 format for the bits which make up the immediatate extension.
616 extended_offset(unsigned long extension
)
618 unsigned long value
;
619 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
621 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
623 value
|= extension
& 0x01f ; /* extract 4:0 */
627 /* Only call this function if you know that this is an extendable
628 instruction, It wont malfunction, but why make excess remote memory references?
629 If the immediate operands get sign extended or somthing, do it after
630 the extension is performed.
632 /* FIXME: Every one of these cases needs to worry about sign extension
633 when the offset is to be used in relative addressing */
636 static unsigned short fetch_mips_16(CORE_ADDR pc
)
639 pc
&= 0xfffffffe ; /* clear the low order bit */
640 target_read_memory(pc
,buf
,2) ;
641 return extract_unsigned_integer(buf
,2) ;
645 unpack_mips16(CORE_ADDR pc
,
646 struct upk_mips16
* upk
)
649 unsigned long extension
;
651 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
652 /* Decrement to previous address and loose the 16bit mode flag */
653 /* return if the instruction was extendable, but not actually extended */
654 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
655 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
660 unsigned long value
;
662 { value
= extended_offset(extension
) ;
663 value
= value
<< 11 ; /* rom for the original value */
664 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
667 { value
= upk
->inst
& 0x7ff ;
668 /* FIXME : Consider sign extension */
670 upk
->offset
= value
;
675 { /* A register identifier and an offset */
676 /* Most of the fields are the same as I type but the
677 immediate value is of a different length */
678 unsigned long value
;
681 value
= extended_offset(extension
) ;
682 value
= value
<< 8 ; /* from the original instruction */
683 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
684 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
685 if (value
& 0x4000) /* test the sign bit , bit 26 */
686 { value
&= ~ 0x3fff ; /* remove the sign bit */
691 value
= upk
->inst
& 0xff ; /* 8 bits */
692 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
693 /* FIXME: Do sign extension , this format needs it */
694 if (value
& 0x80) /* THIS CONFUSES ME */
695 { value
&= 0xef ; /* remove the sign bit */
700 upk
->offset
= value
;
705 unsigned long value
;
706 unsigned short nexthalf
;
707 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
708 value
= value
<< 16 ;
709 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
711 upk
->offset
= value
;
715 printf_filtered("Decoding unimplemented instruction format type\n") ;
718 /* print_unpack("UPK",upk) ; */
722 #define mips16_op(x) (x >> 11)
724 /* This is a map of the opcodes which ae known to perform branches */
725 static unsigned char map16
[32] =
732 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
734 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
740 static struct upk_mips16 upk
;
742 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
746 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
747 inst
= fetch_mips_16(pc
) ;
749 op
= mips16_op(upk
.inst
) ;
755 case 2 : /* Branch */
757 unpack_mips16(pc
,&upk
) ;
759 offset
= upk
.offset
;
764 pc
+= (offset
<< 1) + 2 ;
767 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
769 unpack_mips16(pc
,&upk
) ;
770 pc
= add_offset_16(pc
,upk
.offset
) ;
771 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
772 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
777 unpack_mips16(pc
,&upk
) ;
778 reg
= read_register(upk
.regx
) ;
780 pc
+= (upk
.offset
<< 1) + 2 ;
785 unpack_mips16(pc
,&upk
) ;
786 reg
= read_register(upk
.regx
) ;
788 pc
+= (upk
.offset
<< 1) + 2 ;
791 case 12 : /* I8 Formats btez btnez */
793 unpack_mips16(pc
,&upk
) ;
794 /* upk.regx contains the opcode */
795 reg
= read_register(24) ; /* Test register is 24 */
796 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
797 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
798 /* pc = add_offset_16(pc,upk.offset) ; */
799 pc
+= (upk
.offset
<< 1) + 2 ;
802 case 29 : /* RR Formats JR, JALR, JALR-RA */
804 op
= upk
.inst
& 0x1f ;
807 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
808 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
811 case 0 : reg
= upk
.regx
; break ;
812 case 1 : reg
= 31 ; break ; /* Function return instruction*/
813 case 2 : reg
= upk
.regx
; break ;
814 default: reg
= 31 ; break ; /* BOGUS Guess */
816 pc
= read_register(reg
) ;
820 case 30 : /* This is an extend instruction */
821 pc
+= 4 ; /* Dont be setting breakpints on the second half */
824 printf("Filtered - next PC probably incorrrect due to jump inst\n");
829 else pc
+= 2 ; /* just a good old instruction */
830 /* See if we CAN actually break on the next instruction */
831 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
833 } /* mips16_next_pc */
835 /* The mips_next_pc function supports single_tep when the remote target monitor or
836 stub is not developed enough to so a single_step.
837 It works by decoding the current instruction and predicting where a branch
838 will go. This isnt hard because all the data is available.
839 The MIPS32 and MIPS16 variants are quite different
841 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
844 /* inst = mips_fetch_instruction(pc) ; */
845 /* if (pc_is_mips16) <----- This is failing */
847 return mips16_next_pc(pc
) ;
848 else return mips32_next_pc(pc
) ;
851 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
855 mips_find_saved_regs (fci
)
856 struct frame_info
*fci
;
859 CORE_ADDR reg_position
;
860 /* r0 bit means kernel trap */
862 /* What registers have been saved? Bitmasks. */
863 unsigned long gen_mask
, float_mask
;
864 mips_extra_func_info_t proc_desc
;
867 frame_saved_regs_zalloc (fci
);
869 /* If it is the frame for sigtramp, the saved registers are located
870 in a sigcontext structure somewhere on the stack.
871 If the stack layout for sigtramp changes we might have to change these
872 constants and the companion fixup_sigtramp in mdebugread.c */
873 #ifndef SIGFRAME_BASE
874 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
875 above the sigtramp frame. */
876 #define SIGFRAME_BASE MIPS_REGSIZE
877 /* FIXME! Are these correct?? */
878 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
879 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
880 #define SIGFRAME_FPREGSAVE_OFF \
881 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
883 #ifndef SIGFRAME_REG_SIZE
884 /* FIXME! Is this correct?? */
885 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
887 if (fci
->signal_handler_caller
)
889 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
891 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
892 + ireg
* SIGFRAME_REG_SIZE
;
893 fci
->saved_regs
[ireg
] = reg_position
;
895 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
897 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
898 + ireg
* SIGFRAME_REG_SIZE
;
899 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
901 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
905 proc_desc
= fci
->extra_info
->proc_desc
;
906 if (proc_desc
== NULL
)
907 /* I'm not sure how/whether this can happen. Normally when we can't
908 find a proc_desc, we "synthesize" one using heuristic_proc_desc
909 and set the saved_regs right away. */
912 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
913 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
914 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
916 if (/* In any frame other than the innermost or a frame interrupted by
917 a signal, we assume that all registers have been saved.
918 This assumes that all register saves in a function happen before
919 the first function call. */
920 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
922 /* In a dummy frame we know exactly where things are saved. */
923 && !PROC_DESC_IS_DUMMY (proc_desc
)
925 /* Don't bother unless we are inside a function prologue. Outside the
926 prologue, we know where everything is. */
928 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
930 /* Not sure exactly what kernel_trap means, but if it means
931 the kernel saves the registers without a prologue doing it,
932 we better not examine the prologue to see whether registers
933 have been saved yet. */
936 /* We need to figure out whether the registers that the proc_desc
937 claims are saved have been saved yet. */
941 /* Bitmasks; set if we have found a save for the register. */
942 unsigned long gen_save_found
= 0;
943 unsigned long float_save_found
= 0;
946 /* If the address is odd, assume this is MIPS16 code. */
947 addr
= PROC_LOW_ADDR (proc_desc
);
948 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
950 /* Scan through this function's instructions preceding the current
951 PC, and look for those that save registers. */
952 while (addr
< fci
->pc
)
954 inst
= mips_fetch_instruction (addr
);
955 if (pc_is_mips16 (addr
))
956 mips16_decode_reg_save (inst
, &gen_save_found
);
958 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
961 gen_mask
= gen_save_found
;
962 float_mask
= float_save_found
;
965 /* Fill in the offsets for the registers which gen_mask says
967 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
968 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
969 if (gen_mask
& 0x80000000)
971 fci
->saved_regs
[ireg
] = reg_position
;
972 reg_position
-= MIPS_SAVED_REGSIZE
;
975 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
976 of that normally used by gcc. Therefore, we have to fetch the first
977 instruction of the function, and if it's an entry instruction that
978 saves $s0 or $s1, correct their saved addresses. */
979 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
981 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
982 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
985 int sreg_count
= (inst
>> 6) & 3;
987 /* Check if the ra register was pushed on the stack. */
988 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
990 reg_position
-= MIPS_SAVED_REGSIZE
;
992 /* Check if the s0 and s1 registers were pushed on the stack. */
993 for (reg
= 16; reg
< sreg_count
+16; reg
++)
995 fci
->saved_regs
[reg
] = reg_position
;
996 reg_position
-= MIPS_SAVED_REGSIZE
;
1001 /* Fill in the offsets for the registers which float_mask says
1003 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1005 /* The freg_offset points to where the first *double* register
1006 is saved. So skip to the high-order word. */
1007 if (! GDB_TARGET_IS_MIPS64
)
1008 reg_position
+= MIPS_SAVED_REGSIZE
;
1010 /* Fill in the offsets for the float registers which float_mask says
1012 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
1013 if (float_mask
& 0x80000000)
1015 fci
->saved_regs
[FP0_REGNUM
+ireg
] = reg_position
;
1016 reg_position
-= MIPS_SAVED_REGSIZE
;
1019 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1023 read_next_frame_reg(fi
, regno
)
1024 struct frame_info
*fi
;
1027 for (; fi
; fi
= fi
->next
)
1029 /* We have to get the saved sp from the sigcontext
1030 if it is a signal handler frame. */
1031 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1035 if (fi
->saved_regs
== NULL
)
1036 mips_find_saved_regs (fi
);
1037 if (fi
->saved_regs
[regno
])
1038 return read_memory_integer(fi
->saved_regs
[regno
], MIPS_SAVED_REGSIZE
);
1041 return read_register (regno
);
1044 /* mips_addr_bits_remove - remove useless address bits */
1047 mips_addr_bits_remove (addr
)
1050 #if GDB_TARGET_IS_MIPS64
1051 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
)0xffffffff))
1053 /* This hack is a work-around for existing boards using PMON,
1054 the simulator, and any other 64-bit targets that doesn't have
1055 true 64-bit addressing. On these targets, the upper 32 bits
1056 of addresses are ignored by the hardware. Thus, the PC or SP
1057 are likely to have been sign extended to all 1s by instruction
1058 sequences that load 32-bit addresses. For example, a typical
1059 piece of code that loads an address is this:
1060 lui $r2, <upper 16 bits>
1061 ori $r2, <lower 16 bits>
1062 But the lui sign-extends the value such that the upper 32 bits
1063 may be all 1s. The workaround is simply to mask off these bits.
1064 In the future, gcc may be changed to support true 64-bit
1065 addressing, and this masking will have to be disabled. */
1066 addr
&= (CORE_ADDR
)0xffffffff;
1069 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1070 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1071 So we still have to mask off useless bits from addresses. */
1072 addr
&= (CORE_ADDR
)0xffffffff;
1079 mips_init_frame_pc_first (fromleaf
, prev
)
1081 struct frame_info
*prev
;
1085 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1086 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1087 tmp
= mips_skip_stub (pc
);
1088 prev
->pc
= tmp
? tmp
: pc
;
1093 mips_frame_saved_pc(frame
)
1094 struct frame_info
*frame
;
1097 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1098 /* We have to get the saved pc from the sigcontext
1099 if it is a signal handler frame. */
1100 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1101 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1103 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1104 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1106 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1108 return ADDR_BITS_REMOVE (saved_pc
);
1111 static struct mips_extra_func_info temp_proc_desc
;
1112 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1114 /* Set a register's saved stack address in temp_saved_regs. If an address
1115 has already been set for this register, do nothing; this way we will
1116 only recognize the first save of a given register in a function prologue.
1117 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1120 set_reg_offset (regno
, offset
)
1124 if (temp_saved_regs
[regno
] == 0)
1125 temp_saved_regs
[regno
] = offset
;
1129 /* Test whether the PC points to the return instruction at the
1130 end of a function. */
1133 mips_about_to_return (pc
)
1136 if (pc_is_mips16 (pc
))
1137 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1138 generates a "jr $ra"; other times it generates code to load
1139 the return address from the stack to an accessible register (such
1140 as $a3), then a "jr" using that register. This second case
1141 is almost impossible to distinguish from an indirect jump
1142 used for switch statements, so we don't even try. */
1143 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1145 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1149 /* This fencepost looks highly suspicious to me. Removing it also
1150 seems suspicious as it could affect remote debugging across serial
1154 heuristic_proc_start (pc
)
1162 pc
= ADDR_BITS_REMOVE (pc
);
1164 fence
= start_pc
- heuristic_fence_post
;
1165 if (start_pc
== 0) return 0;
1167 if (heuristic_fence_post
== UINT_MAX
1168 || fence
< VM_MIN_ADDRESS
)
1169 fence
= VM_MIN_ADDRESS
;
1171 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1173 /* search back for previous return */
1174 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1175 if (start_pc
< fence
)
1177 /* It's not clear to me why we reach this point when
1178 stop_soon_quietly, but with this test, at least we
1179 don't print out warnings for every child forked (eg, on
1180 decstation). 22apr93 rich@cygnus.com. */
1181 if (!stop_soon_quietly
)
1183 static int blurb_printed
= 0;
1185 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1190 /* This actually happens frequently in embedded
1191 development, when you first connect to a board
1192 and your stack pointer and pc are nowhere in
1193 particular. This message needs to give people
1194 in that situation enough information to
1195 determine that it's no big deal. */
1196 printf_filtered ("\n\
1197 GDB is unable to find the start of the function at 0x%s\n\
1198 and thus can't determine the size of that function's stack frame.\n\
1199 This means that GDB may be unable to access that stack frame, or\n\
1200 the frames below it.\n\
1201 This problem is most likely caused by an invalid program counter or\n\
1203 However, if you think GDB should simply search farther back\n\
1204 from 0x%s for code which looks like the beginning of a\n\
1205 function, you can increase the range of the search using the `set\n\
1206 heuristic-fence-post' command.\n",
1207 paddr_nz (pc
), paddr_nz (pc
));
1214 else if (pc_is_mips16 (start_pc
))
1216 unsigned short inst
;
1218 /* On MIPS16, any one of the following is likely to be the
1219 start of a function:
1223 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1224 inst
= mips_fetch_instruction (start_pc
);
1225 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1226 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1227 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1228 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1230 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1231 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1236 else if (mips_about_to_return (start_pc
))
1238 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1243 /* skip nops (usually 1) 0 - is this */
1244 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1245 start_pc
+= MIPS_INSTLEN
;
1250 /* Fetch the immediate value from a MIPS16 instruction.
1251 If the previous instruction was an EXTEND, use it to extend
1252 the upper bits of the immediate value. This is a helper function
1253 for mips16_heuristic_proc_desc. */
1256 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1257 unsigned short prev_inst
; /* previous instruction */
1258 unsigned short inst
; /* current instruction */
1259 int nbits
; /* number of bits in imm field */
1260 int scale
; /* scale factor to be applied to imm */
1261 int is_signed
; /* is the imm field signed? */
1265 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1267 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1268 if (offset
& 0x8000) /* check for negative extend */
1269 offset
= 0 - (0x10000 - (offset
& 0xffff));
1270 return offset
| (inst
& 0x1f);
1274 int max_imm
= 1 << nbits
;
1275 int mask
= max_imm
- 1;
1276 int sign_bit
= max_imm
>> 1;
1278 offset
= inst
& mask
;
1279 if (is_signed
&& (offset
& sign_bit
))
1280 offset
= 0 - (max_imm
- offset
);
1281 return offset
* scale
;
1286 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1287 stream from start_pc to limit_pc. */
1290 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1291 CORE_ADDR start_pc
, limit_pc
;
1292 struct frame_info
*next_frame
;
1296 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1297 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1298 unsigned inst
= 0; /* current instruction */
1299 unsigned entry_inst
= 0; /* the entry instruction */
1302 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1303 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1305 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1307 /* Save the previous instruction. If it's an EXTEND, we'll extract
1308 the immediate offset extension from it in mips16_get_imm. */
1311 /* Fetch and decode the instruction. */
1312 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1313 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1314 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1316 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1317 if (offset
< 0) /* negative stack adjustment? */
1318 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1320 /* Exit loop if a positive stack adjustment is found, which
1321 usually means that the stack cleanup code in the function
1322 epilogue is reached. */
1325 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1327 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1328 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1329 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1330 set_reg_offset (reg
, sp
+ offset
);
1332 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1334 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1335 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1336 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1337 set_reg_offset (reg
, sp
+ offset
);
1339 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1341 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1342 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1343 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1345 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1347 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1348 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1349 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1351 else if (inst
== 0x673d) /* move $s1, $sp */
1354 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1356 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1358 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1359 frame_addr
= sp
+ offset
;
1360 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1361 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1363 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1365 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1366 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1367 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1368 set_reg_offset (reg
, frame_addr
+ offset
);
1370 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1372 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1373 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1374 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1375 set_reg_offset (reg
, frame_addr
+ offset
);
1377 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1378 entry_inst
= inst
; /* save for later processing */
1379 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1380 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1383 /* The entry instruction is typically the first instruction in a function,
1384 and it stores registers at offsets relative to the value of the old SP
1385 (before the prologue). But the value of the sp parameter to this
1386 function is the new SP (after the prologue has been executed). So we
1387 can't calculate those offsets until we've seen the entire prologue,
1388 and can calculate what the old SP must have been. */
1389 if (entry_inst
!= 0)
1391 int areg_count
= (entry_inst
>> 8) & 7;
1392 int sreg_count
= (entry_inst
>> 6) & 3;
1394 /* The entry instruction always subtracts 32 from the SP. */
1395 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1397 /* Now we can calculate what the SP must have been at the
1398 start of the function prologue. */
1399 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1401 /* Check if a0-a3 were saved in the caller's argument save area. */
1402 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1404 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1405 set_reg_offset (reg
, sp
+ offset
);
1406 offset
+= MIPS_SAVED_REGSIZE
;
1409 /* Check if the ra register was pushed on the stack. */
1411 if (entry_inst
& 0x20)
1413 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1414 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1415 offset
-= MIPS_SAVED_REGSIZE
;
1418 /* Check if the s0 and s1 registers were pushed on the stack. */
1419 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1421 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1422 set_reg_offset (reg
, sp
+ offset
);
1423 offset
-= MIPS_SAVED_REGSIZE
;
1429 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1430 CORE_ADDR start_pc
, limit_pc
;
1431 struct frame_info
*next_frame
;
1435 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1437 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1438 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1439 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1440 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1442 unsigned long inst
, high_word
, low_word
;
1445 /* Fetch the instruction. */
1446 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1448 /* Save some code by pre-extracting some useful fields. */
1449 high_word
= (inst
>> 16) & 0xffff;
1450 low_word
= inst
& 0xffff;
1451 reg
= high_word
& 0x1f;
1453 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1454 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1455 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1457 if (low_word
& 0x8000) /* negative stack adjustment? */
1458 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1460 /* Exit loop if a positive stack adjustment is found, which
1461 usually means that the stack cleanup code in the function
1462 epilogue is reached. */
1465 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1467 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1468 set_reg_offset (reg
, sp
+ low_word
);
1470 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1472 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1473 but the register size used is only 32 bits. Make the address
1474 for the saved register point to the lower 32 bits. */
1475 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1476 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1478 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1480 /* Old gcc frame, r30 is virtual frame pointer. */
1481 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1482 frame_addr
= sp
+ low_word
;
1483 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1485 unsigned alloca_adjust
;
1486 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1487 frame_addr
= read_next_frame_reg(next_frame
, 30);
1488 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1489 if (alloca_adjust
> 0)
1491 /* FP > SP + frame_size. This may be because
1492 * of an alloca or somethings similar.
1493 * Fix sp to "pre-alloca" value, and try again.
1495 sp
+= alloca_adjust
;
1500 /* move $30,$sp. With different versions of gas this will be either
1501 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1502 Accept any one of these. */
1503 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1505 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1506 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1508 unsigned alloca_adjust
;
1509 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1510 frame_addr
= read_next_frame_reg(next_frame
, 30);
1511 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1512 if (alloca_adjust
> 0)
1514 /* FP > SP + frame_size. This may be because
1515 * of an alloca or somethings similar.
1516 * Fix sp to "pre-alloca" value, and try again.
1518 sp
+= alloca_adjust
;
1523 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1525 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1526 set_reg_offset (reg
, frame_addr
+ low_word
);
1531 static mips_extra_func_info_t
1532 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1533 CORE_ADDR start_pc
, limit_pc
;
1534 struct frame_info
*next_frame
;
1536 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1538 if (start_pc
== 0) return NULL
;
1539 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1540 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1541 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1542 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1543 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1545 if (start_pc
+ 200 < limit_pc
)
1546 limit_pc
= start_pc
+ 200;
1547 if (pc_is_mips16 (start_pc
))
1548 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1550 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1551 return &temp_proc_desc
;
1554 static mips_extra_func_info_t
1555 non_heuristic_proc_desc (pc
, addrptr
)
1559 CORE_ADDR startaddr
;
1560 mips_extra_func_info_t proc_desc
;
1561 struct block
*b
= block_for_pc(pc
);
1564 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1566 *addrptr
= startaddr
;
1567 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1571 if (startaddr
> BLOCK_START (b
))
1572 /* This is the "pathological" case referred to in a comment in
1573 print_frame_info. It might be better to move this check into
1577 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1580 /* If we never found a PDR for this function in symbol reading, then
1581 examine prologues to find the information. */
1584 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1585 if (PROC_FRAME_REG (proc_desc
) == -1)
1595 static mips_extra_func_info_t
1596 find_proc_desc (pc
, next_frame
)
1598 struct frame_info
*next_frame
;
1600 mips_extra_func_info_t proc_desc
;
1601 CORE_ADDR startaddr
;
1603 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1607 /* IF this is the topmost frame AND
1608 * (this proc does not have debugging information OR
1609 * the PC is in the procedure prologue)
1610 * THEN create a "heuristic" proc_desc (by analyzing
1611 * the actual code) to replace the "official" proc_desc.
1613 if (next_frame
== NULL
)
1615 struct symtab_and_line val
;
1616 struct symbol
*proc_symbol
=
1617 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1621 val
= find_pc_line (BLOCK_START
1622 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1624 val
.pc
= val
.end
? val
.end
: pc
;
1626 if (!proc_symbol
|| pc
< val
.pc
)
1628 mips_extra_func_info_t found_heuristic
=
1629 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1631 if (found_heuristic
)
1632 proc_desc
= found_heuristic
;
1638 /* Is linked_proc_desc_table really necessary? It only seems to be used
1639 by procedure call dummys. However, the procedures being called ought
1640 to have their own proc_descs, and even if they don't,
1641 heuristic_proc_desc knows how to create them! */
1643 register struct linked_proc_info
*link
;
1645 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1646 if (PROC_LOW_ADDR(&link
->info
) <= pc
1647 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1651 startaddr
= heuristic_proc_start (pc
);
1654 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1660 get_frame_pointer(frame
, proc_desc
)
1661 struct frame_info
*frame
;
1662 mips_extra_func_info_t proc_desc
;
1664 return ADDR_BITS_REMOVE (
1665 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1666 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1669 mips_extra_func_info_t cached_proc_desc
;
1672 mips_frame_chain(frame
)
1673 struct frame_info
*frame
;
1675 mips_extra_func_info_t proc_desc
;
1677 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1679 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1682 /* Check if the PC is inside a call stub. If it is, fetch the
1683 PC of the caller of that stub. */
1684 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1687 /* Look up the procedure descriptor for this PC. */
1688 proc_desc
= find_proc_desc(saved_pc
, frame
);
1692 cached_proc_desc
= proc_desc
;
1694 /* If no frame pointer and frame size is zero, we must be at end
1695 of stack (or otherwise hosed). If we don't check frame size,
1696 we loop forever if we see a zero size frame. */
1697 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1698 && PROC_FRAME_OFFSET (proc_desc
) == 0
1699 /* The previous frame from a sigtramp frame might be frameless
1700 and have frame size zero. */
1701 && !frame
->signal_handler_caller
)
1704 return get_frame_pointer (frame
, proc_desc
);
1708 mips_init_extra_frame_info(fromleaf
, fci
)
1710 struct frame_info
*fci
;
1714 /* Use proc_desc calculated in frame_chain */
1715 mips_extra_func_info_t proc_desc
=
1716 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1718 fci
->extra_info
= (struct frame_extra_info
*)
1719 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1721 fci
->saved_regs
= NULL
;
1722 fci
->extra_info
->proc_desc
=
1723 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1726 /* Fixup frame-pointer - only needed for top frame */
1727 /* This may not be quite right, if proc has a real frame register.
1728 Get the value of the frame relative sp, procedure might have been
1729 interrupted by a signal at it's very start. */
1730 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1731 && !PROC_DESC_IS_DUMMY (proc_desc
))
1732 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1734 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1736 if (proc_desc
== &temp_proc_desc
)
1740 /* Do not set the saved registers for a sigtramp frame,
1741 mips_find_saved_registers will do that for us.
1742 We can't use fci->signal_handler_caller, it is not yet set. */
1743 find_pc_partial_function (fci
->pc
, &name
,
1744 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1745 if (!IN_SIGTRAMP (fci
->pc
, name
))
1747 frame_saved_regs_zalloc (fci
);
1748 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1749 fci
->saved_regs
[PC_REGNUM
]
1750 = fci
->saved_regs
[RA_REGNUM
];
1754 /* hack: if argument regs are saved, guess these contain args */
1755 /* assume we can't tell how many args for now */
1756 fci
->extra_info
->num_args
= -1;
1757 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1759 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1761 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1768 /* MIPS stack frames are almost impenetrable. When execution stops,
1769 we basically have to look at symbol information for the function
1770 that we stopped in, which tells us *which* register (if any) is
1771 the base of the frame pointer, and what offset from that register
1772 the frame itself is at.
1774 This presents a problem when trying to examine a stack in memory
1775 (that isn't executing at the moment), using the "frame" command. We
1776 don't have a PC, nor do we have any registers except SP.
1778 This routine takes two arguments, SP and PC, and tries to make the
1779 cached frames look as if these two arguments defined a frame on the
1780 cache. This allows the rest of info frame to extract the important
1781 arguments without difficulty. */
1784 setup_arbitrary_frame (argc
, argv
)
1789 error ("MIPS frame specifications require two arguments: sp and pc");
1791 return create_new_frame (argv
[0], argv
[1]);
1795 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1797 * For n32 ABI, eight.
1798 * For all others, he same as the size of a general register.
1800 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1801 #define MIPS_NABI32 1
1802 #define STACK_ARGSIZE 8
1804 #define MIPS_NABI32 0
1805 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1809 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1814 CORE_ADDR struct_addr
;
1820 int stack_offset
= 0;
1822 /* Macros to round N up or down to the next A boundary; A must be
1824 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1825 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1827 /* First ensure that the stack and structure return address (if any)
1828 are properly aligned. The stack has to be at least 64-bit aligned
1829 even on 32-bit machines, because doubles must be 64-bit aligned.
1830 On at least one MIPS variant, stack frames need to be 128-bit
1831 aligned, so we round to this widest known alignment. */
1832 sp
= ROUND_DOWN (sp
, 16);
1833 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
1835 /* Now make space on the stack for the args. We allocate more
1836 than necessary for EABI, because the first few arguments are
1837 passed in registers, but that's OK. */
1838 for (argnum
= 0; argnum
< nargs
; argnum
++)
1839 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_SAVED_REGSIZE
);
1840 sp
-= ROUND_UP (len
, 16);
1842 /* Initialize the integer and float register pointers. */
1844 float_argreg
= FPA0_REGNUM
;
1846 /* the struct_return pointer occupies the first parameter-passing reg */
1848 write_register (argreg
++, struct_addr
);
1850 /* Now load as many as possible of the first arguments into
1851 registers, and push the rest onto the stack. Loop thru args
1852 from first to last. */
1853 for (argnum
= 0; argnum
< nargs
; argnum
++)
1856 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1857 value_ptr arg
= args
[argnum
];
1858 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1859 int len
= TYPE_LENGTH (arg_type
);
1860 enum type_code typecode
= TYPE_CODE (arg_type
);
1862 /* The EABI passes structures that do not fit in a register by
1863 reference. In all other cases, pass the structure by value. */
1864 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
1865 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1867 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
1868 typecode
= TYPE_CODE_PTR
;
1869 len
= MIPS_SAVED_REGSIZE
;
1873 val
= (char *)VALUE_CONTENTS (arg
);
1875 /* 32-bit ABIs always start floating point arguments in an
1876 even-numbered floating point register. */
1877 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1878 && (float_argreg
& 1))
1881 /* Floating point arguments passed in registers have to be
1882 treated specially. On 32-bit architectures, doubles
1883 are passed in register pairs; the even register gets
1884 the low word, and the odd register gets the high word.
1885 On non-EABI processors, the first two floating point arguments are
1886 also copied to general registers, because MIPS16 functions
1887 don't use float registers for arguments. This duplication of
1888 arguments in general registers can't hurt non-MIPS16 functions
1889 because those registers are normally skipped. */
1890 if (typecode
== TYPE_CODE_FLT
1891 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1892 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
1894 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1896 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1897 unsigned long regval
;
1899 /* Write the low word of the double to the even register(s). */
1900 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1901 write_register (float_argreg
++, regval
);
1903 write_register (argreg
+1, regval
);
1905 /* Write the high word of the double to the odd register(s). */
1906 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1907 write_register (float_argreg
++, regval
);
1910 write_register (argreg
, regval
);
1917 /* This is a floating point value that fits entirely
1918 in a single register. */
1919 CORE_ADDR regval
= extract_address (val
, len
);
1920 write_register (float_argreg
++, regval
);
1923 write_register (argreg
, regval
);
1924 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1930 /* Copy the argument to general registers or the stack in
1931 register-sized pieces. Large arguments are split between
1932 registers and stack. */
1933 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1934 are treated specially: Irix cc passes them in registers
1935 where gcc sometimes puts them on the stack. For maximum
1936 compatibility, we will put them in both places. */
1938 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
1939 (len
% MIPS_SAVED_REGSIZE
!= 0));
1942 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
1944 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1946 /* Write this portion of the argument to the stack. */
1947 /* Should shorter than int integer values be
1948 promoted to int before being stored? */
1950 int longword_offset
= 0;
1951 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1953 if (STACK_ARGSIZE
== 8 &&
1954 (typecode
== TYPE_CODE_INT
||
1955 typecode
== TYPE_CODE_PTR
||
1956 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1957 longword_offset
= STACK_ARGSIZE
- len
;
1958 else if ((typecode
== TYPE_CODE_STRUCT
||
1959 typecode
== TYPE_CODE_UNION
) &&
1960 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1961 longword_offset
= STACK_ARGSIZE
- len
;
1964 write_memory (sp
+ stack_offset
+ longword_offset
,
1968 /* Note!!! This is NOT an else clause.
1969 Odd sized structs may go thru BOTH paths. */
1970 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1972 CORE_ADDR regval
= extract_address (val
, partial_len
);
1974 /* A non-floating-point argument being passed in a
1975 general register. If a struct or union, and if
1976 the remaining length is smaller than the register
1977 size, we have to adjust the register value on
1980 It does not seem to be necessary to do the
1981 same for integral types.
1983 Also don't do this adjustment on EABI and O64
1987 && MIPS_SAVED_REGSIZE
< 8
1988 && TARGET_BYTE_ORDER
== BIG_ENDIAN
1989 && partial_len
< MIPS_SAVED_REGSIZE
1990 && (typecode
== TYPE_CODE_STRUCT
||
1991 typecode
== TYPE_CODE_UNION
))
1992 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
1995 write_register (argreg
, regval
);
1998 /* If this is the old ABI, prevent subsequent floating
1999 point arguments from being passed in floating point
2002 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2008 /* The offset onto the stack at which we will start
2009 copying parameters (after the registers are used up)
2010 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2011 leaves room for the "home" area for register parameters.
2013 In the new EABI (and the NABI32), the 8 register parameters
2014 do not have "home" stack space reserved for them, so the
2015 stack offset does not get incremented until after
2016 we have used up the 8 parameter registers. */
2018 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2020 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2025 /* Return adjusted stack pointer. */
2030 mips_push_return_address (pc
, sp
)
2034 /* Set the return address register to point to the entry
2035 point of the program, where a breakpoint lies in wait. */
2036 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
2041 mips_push_register (CORE_ADDR
*sp
, int regno
)
2043 char buffer
[MAX_REGISTER_RAW_SIZE
];
2046 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2048 regsize
= MIPS_SAVED_REGSIZE
;
2049 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2050 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2055 regsize
= REGISTER_RAW_SIZE (regno
);
2059 read_register_gen (regno
, buffer
);
2060 write_memory (*sp
, buffer
+ offset
, regsize
);
2063 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2064 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2067 mips_push_dummy_frame ()
2070 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2071 xmalloc(sizeof(struct linked_proc_info
));
2072 mips_extra_func_info_t proc_desc
= &link
->info
;
2073 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2074 CORE_ADDR old_sp
= sp
;
2075 link
->next
= linked_proc_desc_table
;
2076 linked_proc_desc_table
= link
;
2078 /* FIXME! are these correct ? */
2079 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2080 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2081 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2082 #define FLOAT_SINGLE_REG_SAVE_MASK \
2083 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2085 * The registers we must save are all those not preserved across
2086 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2087 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2088 * and FP Control/Status registers.
2091 * Dummy frame layout:
2094 * Saved MMHI, MMLO, FPC_CSR
2099 * Saved D18 (i.e. F19, F18)
2101 * Saved D0 (i.e. F1, F0)
2102 * Argument build area and stack arguments written via mips_push_arguments
2106 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2107 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2108 PROC_FRAME_OFFSET(proc_desc
) = 0;
2109 PROC_FRAME_ADJUST(proc_desc
) = 0;
2110 mips_push_register (&sp
, PC_REGNUM
);
2111 mips_push_register (&sp
, HI_REGNUM
);
2112 mips_push_register (&sp
, LO_REGNUM
);
2113 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2115 /* Save general CPU registers */
2116 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2117 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2118 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2119 for (ireg
= 32; --ireg
>= 0; )
2120 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2121 mips_push_register (&sp
, ireg
);
2123 /* Save floating point registers starting with high order word */
2124 PROC_FREG_MASK(proc_desc
) =
2125 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2126 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2127 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2129 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2130 for (ireg
= 32; --ireg
>= 0; )
2131 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2132 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2134 /* Update the frame pointer for the call dummy and the stack pointer.
2135 Set the procedure's starting and ending addresses to point to the
2136 call dummy address at the entry point. */
2137 write_register (PUSH_FP_REGNUM
, old_sp
);
2138 write_register (SP_REGNUM
, sp
);
2139 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2140 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2141 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2142 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2148 register int regnum
;
2149 struct frame_info
*frame
= get_current_frame ();
2150 CORE_ADDR new_sp
= FRAME_FP (frame
);
2152 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2154 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2155 if (frame
->saved_regs
== NULL
)
2156 mips_find_saved_regs (frame
);
2157 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2159 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2160 && frame
->saved_regs
[regnum
])
2161 write_register (regnum
,
2162 read_memory_integer (frame
->saved_regs
[regnum
],
2163 MIPS_SAVED_REGSIZE
));
2165 write_register (SP_REGNUM
, new_sp
);
2166 flush_cached_frames ();
2168 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2170 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2172 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2174 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2176 if (&pi_ptr
->info
== proc_desc
)
2181 error ("Can't locate dummy extra frame info\n");
2183 if (prev_ptr
!= NULL
)
2184 prev_ptr
->next
= pi_ptr
->next
;
2186 linked_proc_desc_table
= pi_ptr
->next
;
2190 write_register (HI_REGNUM
,
2191 read_memory_integer (new_sp
- 2*MIPS_SAVED_REGSIZE
,
2192 MIPS_SAVED_REGSIZE
));
2193 write_register (LO_REGNUM
,
2194 read_memory_integer (new_sp
- 3*MIPS_SAVED_REGSIZE
,
2195 MIPS_SAVED_REGSIZE
));
2196 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2197 write_register (FCRCS_REGNUM
,
2198 read_memory_integer (new_sp
- 4*MIPS_SAVED_REGSIZE
,
2199 MIPS_SAVED_REGSIZE
));
2204 mips_print_register (regnum
, all
)
2207 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2209 /* Get the data in raw format. */
2210 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2212 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2216 /* If an even floating point register, also print as double. */
2217 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2218 && !((regnum
-FP0_REGNUM
) & 1))
2219 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2221 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2223 read_relative_register_raw_bytes (regnum
, dbuffer
);
2224 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2225 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2227 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2228 val_print (builtin_type_double
, dbuffer
, 0, 0,
2229 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2230 printf_filtered ("); ");
2232 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2234 /* The problem with printing numeric register names (r26, etc.) is that
2235 the user can't use them on input. Probably the best solution is to
2236 fix it so that either the numeric or the funky (a2, etc.) names
2237 are accepted on input. */
2238 if (regnum
< MIPS_NUMREGS
)
2239 printf_filtered ("(r%d): ", regnum
);
2241 printf_filtered (": ");
2243 /* If virtual format is floating, print it that way. */
2244 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2245 if (FP_REGISTER_DOUBLE
)
2246 { /* show 8-byte floats as float AND double: */
2247 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2249 printf_filtered (" (float) ");
2250 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2251 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2252 printf_filtered (", (double) ");
2253 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2254 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2257 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2258 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2259 /* Else print as integer in hex. */
2261 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2262 'x', 0, gdb_stdout
);
2265 /* Replacement for generic do_registers_info.
2266 Print regs in pretty columns. */
2269 do_fp_register_row (regnum
)
2271 { /* do values for FP (float) regs */
2272 char *raw_buffer
[2];
2274 /* use HI and LO to control the order of combining two flt regs */
2275 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2276 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2277 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2278 int inv1
, inv2
, inv3
;
2280 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2281 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2282 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2284 /* Get the data in raw format. */
2285 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2286 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2287 if (REGISTER_RAW_SIZE(regnum
) == 4)
2289 /* 4-byte registers: we can fit two registers per row. */
2290 /* Also print every pair of 4-byte regs as an 8-byte double. */
2291 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2292 error ("can't read register %d (%s)",
2293 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2295 /* copy the two floats into one double, and unpack both */
2296 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2297 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2298 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2299 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2301 printf_filtered (inv1
? " %-5s: <invalid float>" :
2302 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2303 printf_filtered (inv2
? " %-5s: <invalid float>" :
2304 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2305 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2306 " dbl: %-24.17g\n", doub
);
2307 /* may want to do hex display here (future enhancement) */
2311 { /* eight byte registers: print each one as float AND as double. */
2312 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2314 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2315 flt1
= unpack_double (builtin_type_float
,
2316 &raw_buffer
[HI
][offset
], &inv1
);
2317 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2319 printf_filtered (inv1
? " %-5s: <invalid float>" :
2320 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2321 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2322 " dbl: %-24.17g\n", doub
);
2323 /* may want to do hex display here (future enhancement) */
2329 /* Print a row's worth of GP (int) registers, with name labels above */
2332 do_gp_register_row (regnum
)
2335 /* do values for GP (int) regs */
2336 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2337 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2339 int start_regnum
= regnum
;
2340 int numregs
= NUM_REGS
;
2343 /* For GP registers, we print a separate row of names above the vals */
2344 printf_filtered (" ");
2345 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2347 if (*REGISTER_NAME (regnum
) == '\0')
2348 continue; /* unused register */
2349 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2350 break; /* end the row: reached FP register */
2351 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2352 REGISTER_NAME (regnum
));
2355 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2356 start_regnum
); /* print the R0 to R31 names */
2358 regnum
= start_regnum
; /* go back to start of row */
2359 /* now print the values in hex, 4 or 8 to the row */
2360 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2362 if (*REGISTER_NAME (regnum
) == '\0')
2363 continue; /* unused register */
2364 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2365 break; /* end row: reached FP register */
2366 /* OK: get the data in raw format. */
2367 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2368 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2369 /* pad small registers */
2370 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2371 printf_filtered (" ");
2372 /* Now print the register value in hex, endian order. */
2373 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2374 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2375 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2377 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2378 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2379 printf_filtered (" ");
2382 if (col
> 0) /* ie. if we actually printed anything... */
2383 printf_filtered ("\n");
2388 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2391 mips_do_registers_info (regnum
, fpregs
)
2395 if (regnum
!= -1) /* do one specified register */
2397 if (*(REGISTER_NAME (regnum
)) == '\0')
2398 error ("Not a valid register for the current processor type");
2400 mips_print_register (regnum
, 0);
2401 printf_filtered ("\n");
2403 else /* do all (or most) registers */
2406 while (regnum
< NUM_REGS
)
2408 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2409 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2410 regnum
= do_fp_register_row (regnum
); /* FP regs */
2412 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2414 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2419 /* Return number of args passed to a frame. described by FIP.
2420 Can return -1, meaning no way to tell. */
2423 mips_frame_num_args (frame
)
2424 struct frame_info
*frame
;
2426 #if 0 /* FIXME Use or lose this! */
2427 struct chain_info_t
*p
;
2429 p
= mips_find_cached_frame (FRAME_FP (frame
));
2431 return p
->the_info
.numargs
;
2436 /* Is this a branch with a delay slot? */
2438 static int is_delayed
PARAMS ((unsigned long));
2445 for (i
= 0; i
< NUMOPCODES
; ++i
)
2446 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2447 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2449 return (i
< NUMOPCODES
2450 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2451 | INSN_COND_BRANCH_DELAY
2452 | INSN_COND_BRANCH_LIKELY
)));
2456 mips_step_skips_delay (pc
)
2459 char buf
[MIPS_INSTLEN
];
2461 /* There is no branch delay slot on MIPS16. */
2462 if (pc_is_mips16 (pc
))
2465 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2466 /* If error reading memory, guess that it is not a delayed branch. */
2468 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2472 /* Skip the PC past function prologue instructions (32-bit version).
2473 This is a helper function for mips_skip_prologue. */
2476 mips32_skip_prologue (pc
, lenient
)
2477 CORE_ADDR pc
; /* starting PC to search from */
2482 int seen_sp_adjust
= 0;
2483 int load_immediate_bytes
= 0;
2485 /* Skip the typical prologue instructions. These are the stack adjustment
2486 instruction and the instructions that save registers on the stack
2487 or in the gcc frame. */
2488 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2490 unsigned long high_word
;
2492 inst
= mips_fetch_instruction (pc
);
2493 high_word
= (inst
>> 16) & 0xffff;
2496 if (lenient
&& is_delayed (inst
))
2500 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2501 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2503 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2504 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2506 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2507 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2508 && (inst
& 0x001F0000)) /* reg != $zero */
2511 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2513 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2515 continue; /* reg != $zero */
2517 /* move $s8,$sp. With different versions of gas this will be either
2518 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2519 Accept any one of these. */
2520 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2523 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2525 else if (high_word
== 0x3c1c) /* lui $gp,n */
2527 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2529 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2530 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2532 /* The following instructions load $at or $t0 with an immediate
2533 value in preparation for a stack adjustment via
2534 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2535 a local variable, so we accept them only before a stack adjustment
2536 instruction was seen. */
2537 else if (!seen_sp_adjust
)
2539 if (high_word
== 0x3c01 || /* lui $at,n */
2540 high_word
== 0x3c08) /* lui $t0,n */
2542 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2545 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2546 high_word
== 0x3508 || /* ori $t0,$t0,n */
2547 high_word
== 0x3401 || /* ori $at,$zero,n */
2548 high_word
== 0x3408) /* ori $t0,$zero,n */
2550 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2560 /* In a frameless function, we might have incorrectly
2561 skipped some load immediate instructions. Undo the skipping
2562 if the load immediate was not followed by a stack adjustment. */
2563 if (load_immediate_bytes
&& !seen_sp_adjust
)
2564 pc
-= load_immediate_bytes
;
2568 /* Skip the PC past function prologue instructions (16-bit version).
2569 This is a helper function for mips_skip_prologue. */
2572 mips16_skip_prologue (pc
, lenient
)
2573 CORE_ADDR pc
; /* starting PC to search from */
2577 int extend_bytes
= 0;
2578 int prev_extend_bytes
;
2580 /* Table of instructions likely to be found in a function prologue. */
2583 unsigned short inst
;
2584 unsigned short mask
;
2587 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2588 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2589 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2590 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2591 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2592 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2593 { 0x673d, 0xffff }, /* move $s1,sp */
2594 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2595 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2596 { 0xe809, 0xf81f }, /* entry pseudo-op */
2597 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2598 { 0, 0 } /* end of table marker */
2601 /* Skip the typical prologue instructions. These are the stack adjustment
2602 instruction and the instructions that save registers on the stack
2603 or in the gcc frame. */
2604 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2606 unsigned short inst
;
2609 inst
= mips_fetch_instruction (pc
);
2611 /* Normally we ignore an extend instruction. However, if it is
2612 not followed by a valid prologue instruction, we must adjust
2613 the pc back over the extend so that it won't be considered
2614 part of the prologue. */
2615 if ((inst
& 0xf800) == 0xf000) /* extend */
2617 extend_bytes
= MIPS16_INSTLEN
;
2620 prev_extend_bytes
= extend_bytes
;
2623 /* Check for other valid prologue instructions besides extend. */
2624 for (i
= 0; table
[i
].mask
!= 0; i
++)
2625 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2627 if (table
[i
].mask
!= 0) /* it was in table? */
2628 continue; /* ignore it */
2629 else /* non-prologue */
2631 /* Return the current pc, adjusted backwards by 2 if
2632 the previous instruction was an extend. */
2633 return pc
- prev_extend_bytes
;
2639 /* To skip prologues, I use this predicate. Returns either PC itself
2640 if the code at PC does not look like a function prologue; otherwise
2641 returns an address that (if we're lucky) follows the prologue. If
2642 LENIENT, then we must skip everything which is involved in setting
2643 up the frame (it's OK to skip more, just so long as we don't skip
2644 anything which might clobber the registers which are being saved.
2645 We must skip more in the case where part of the prologue is in the
2646 delay slot of a non-prologue instruction). */
2649 mips_skip_prologue (pc
, lenient
)
2653 /* See if we can determine the end of the prologue via the symbol table.
2654 If so, then return either PC, or the PC after the prologue, whichever
2657 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2659 if (post_prologue_pc
!= 0)
2660 return max (pc
, post_prologue_pc
);
2662 /* Can't determine prologue from the symbol table, need to examine
2665 if (pc_is_mips16 (pc
))
2666 return mips16_skip_prologue (pc
, lenient
);
2668 return mips32_skip_prologue (pc
, lenient
);
2672 /* The lenient prologue stuff should be superseded by the code in
2673 init_extra_frame_info which looks to see whether the stores mentioned
2674 in the proc_desc have actually taken place. */
2676 /* Is address PC in the prologue (loosely defined) for function at
2680 mips_in_lenient_prologue (startaddr
, pc
)
2681 CORE_ADDR startaddr
;
2684 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2685 return pc
>= startaddr
&& pc
< end_prologue
;
2689 /* Determine how a return value is stored within the MIPS register
2690 file, given the return type `valtype'. */
2692 struct return_value_word
2700 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2703 return_value_location (valtype
, hi
, lo
)
2704 struct type
*valtype
;
2705 struct return_value_word
*hi
;
2706 struct return_value_word
*lo
;
2708 int len
= TYPE_LENGTH (valtype
);
2710 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2711 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2712 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2714 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2716 /* We need to break a 64bit float in two 32 bit halves and
2717 spread them across a floating-point register pair. */
2718 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2719 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2720 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2721 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2723 hi
->reg_offset
= lo
->reg_offset
;
2724 lo
->reg
= FP0_REGNUM
+ 0;
2725 hi
->reg
= FP0_REGNUM
+ 1;
2731 /* The floating point value fits in a single floating-point
2733 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2734 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2737 lo
->reg
= FP0_REGNUM
;
2748 /* Locate a result possibly spread across two registers. */
2750 lo
->reg
= regnum
+ 0;
2751 hi
->reg
= regnum
+ 1;
2752 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2753 && len
< MIPS_SAVED_REGSIZE
)
2755 /* "un-left-justify" the value in the low register */
2756 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2761 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2762 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2763 && len
< MIPS_SAVED_REGSIZE
* 2
2764 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2765 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2767 /* "un-left-justify" the value spread across two registers. */
2768 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2769 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2771 hi
->len
= len
- lo
->len
;
2775 /* Only perform a partial copy of the second register. */
2778 if (len
> MIPS_SAVED_REGSIZE
)
2780 lo
->len
= MIPS_SAVED_REGSIZE
;
2781 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
2789 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2790 && REGISTER_RAW_SIZE (regnum
) == 8
2791 && MIPS_SAVED_REGSIZE
== 4)
2793 /* Account for the fact that only the least-signficant part
2794 of the register is being used */
2795 lo
->reg_offset
+= 4;
2796 hi
->reg_offset
+= 4;
2799 hi
->buf_offset
= lo
->len
;
2803 /* Given a return value in `regbuf' with a type `valtype', extract and
2804 copy its value into `valbuf'. */
2807 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2808 struct type
*valtype
;
2809 char regbuf
[REGISTER_BYTES
];
2812 struct return_value_word lo
;
2813 struct return_value_word hi
;
2814 return_value_location (valtype
, &lo
, &hi
);
2816 memcpy (valbuf
+ lo
.buf_offset
,
2817 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
2821 memcpy (valbuf
+ hi
.buf_offset
,
2822 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
2828 int len
= TYPE_LENGTH (valtype
);
2831 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2832 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2833 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2834 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2835 regnum
= FP0_REGNUM
;
2837 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2838 { /* "un-left-justify" the value from the register */
2839 if (len
< REGISTER_RAW_SIZE (regnum
))
2840 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2841 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2842 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2843 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2844 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2845 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2847 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2848 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2852 /* Given a return value in `valbuf' with a type `valtype', write it's
2853 value into the appropriate register. */
2856 mips_store_return_value (valtype
, valbuf
)
2857 struct type
*valtype
;
2860 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2861 struct return_value_word lo
;
2862 struct return_value_word hi
;
2863 return_value_location (valtype
, &lo
, &hi
);
2865 memset (raw_buffer
, 0, sizeof (raw_buffer
));
2866 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
2867 write_register_bytes (REGISTER_BYTE (lo
.reg
),
2869 REGISTER_RAW_SIZE (lo
.reg
));
2873 memset (raw_buffer
, 0, sizeof (raw_buffer
));
2874 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
2875 write_register_bytes (REGISTER_BYTE (hi
.reg
),
2877 REGISTER_RAW_SIZE (hi
.reg
));
2883 int len
= TYPE_LENGTH (valtype
);
2884 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2887 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2888 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2889 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2890 && len
<= MIPS_REGSIZE
)))
2891 regnum
= FP0_REGNUM
;
2893 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2894 { /* "left-justify" the value in the register */
2895 if (len
< REGISTER_RAW_SIZE (regnum
))
2896 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2897 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2898 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2899 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2900 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2901 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2903 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2904 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2905 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2906 len
> REGISTER_RAW_SIZE (regnum
) ?
2907 len
: REGISTER_RAW_SIZE (regnum
));
2911 /* Exported procedure: Is PC in the signal trampoline code */
2914 in_sigtramp (pc
, ignore
)
2916 char *ignore
; /* function name */
2918 if (sigtramp_address
== 0)
2920 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2923 /* Commands to show/set the MIPS FPU type. */
2925 static void show_mipsfpu_command
PARAMS ((char *, int));
2927 show_mipsfpu_command (args
, from_tty
)
2933 switch (MIPS_FPU_TYPE
)
2935 case MIPS_FPU_SINGLE
:
2936 fpu
= "single-precision";
2938 case MIPS_FPU_DOUBLE
:
2939 fpu
= "double-precision";
2942 fpu
= "absent (none)";
2945 if (mips_fpu_type_auto
)
2946 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
2949 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
2954 static void set_mipsfpu_command
PARAMS ((char *, int));
2956 set_mipsfpu_command (args
, from_tty
)
2960 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
2961 show_mipsfpu_command (args
, from_tty
);
2964 static void set_mipsfpu_single_command
PARAMS ((char *, int));
2966 set_mipsfpu_single_command (args
, from_tty
)
2970 mips_fpu_type
= MIPS_FPU_SINGLE
;
2971 mips_fpu_type_auto
= 0;
2974 static void set_mipsfpu_double_command
PARAMS ((char *, int));
2976 set_mipsfpu_double_command (args
, from_tty
)
2980 mips_fpu_type
= MIPS_FPU_DOUBLE
;
2981 mips_fpu_type_auto
= 0;
2984 static void set_mipsfpu_none_command
PARAMS ((char *, int));
2986 set_mipsfpu_none_command (args
, from_tty
)
2990 mips_fpu_type
= MIPS_FPU_NONE
;
2991 mips_fpu_type_auto
= 0;
2994 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
2996 set_mipsfpu_auto_command (args
, from_tty
)
3000 mips_fpu_type_auto
= 1;
3003 /* Command to set the processor type. */
3006 mips_set_processor_type_command (args
, from_tty
)
3012 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3014 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3015 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3016 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3018 /* Restore the value. */
3019 tmp_mips_processor_type
= strsave (mips_processor_type
);
3024 if (!mips_set_processor_type (tmp_mips_processor_type
))
3026 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3027 /* Restore its value. */
3028 tmp_mips_processor_type
= strsave (mips_processor_type
);
3033 mips_show_processor_type_command (args
, from_tty
)
3039 /* Modify the actual processor type. */
3042 mips_set_processor_type (str
)
3050 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3052 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3054 mips_processor_type
= str
;
3055 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3057 /* FIXME tweak fpu flag too */
3064 /* Attempt to identify the particular processor model by reading the
3068 mips_read_processor_type ()
3072 prid
= read_register (PRID_REGNUM
);
3074 if ((prid
& ~0xf) == 0x700)
3075 return savestring ("r3041", strlen("r3041"));
3080 /* Just like reinit_frame_cache, but with the right arguments to be
3081 callable as an sfunc. */
3084 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3087 struct cmd_list_element
*c
;
3089 reinit_frame_cache ();
3093 gdb_print_insn_mips (memaddr
, info
)
3095 disassemble_info
*info
;
3097 mips_extra_func_info_t proc_desc
;
3099 /* Search for the function containing this address. Set the low bit
3100 of the address when searching, in case we were given an even address
3101 that is the start of a 16-bit function. If we didn't do this,
3102 the search would fail because the symbol table says the function
3103 starts at an odd address, i.e. 1 byte past the given address. */
3104 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3105 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3107 /* Make an attempt to determine if this is a 16-bit function. If
3108 the procedure descriptor exists and the address therein is odd,
3109 it's definitely a 16-bit function. Otherwise, we have to just
3110 guess that if the address passed in is odd, it's 16-bits. */
3112 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3114 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3116 /* Round down the instruction address to the appropriate boundary. */
3117 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3119 /* Call the appropriate disassembler based on the target endian-ness. */
3120 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3121 return print_insn_big_mips (memaddr
, info
);
3123 return print_insn_little_mips (memaddr
, info
);
3126 /* Old-style breakpoint macros.
3127 The IDT board uses an unusual breakpoint value, and sometimes gets
3128 confused when it sees the usual MIPS breakpoint instruction. */
3130 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3131 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3132 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3133 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3134 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3135 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3136 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3137 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3139 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3140 counter value to determine whether a 16- or 32-bit breakpoint should be
3141 used. It returns a pointer to a string of bytes that encode a breakpoint
3142 instruction, stores the length of the string to *lenptr, and adjusts pc
3143 (if necessary) to point to the actual memory location where the
3144 breakpoint should be inserted. */
3146 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
3150 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3152 if (pc_is_mips16 (*pcptr
))
3154 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3155 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3156 *lenptr
= sizeof(mips16_big_breakpoint
);
3157 return mips16_big_breakpoint
;
3161 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3162 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3163 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3165 *lenptr
= sizeof(big_breakpoint
);
3167 if (strcmp (target_shortname
, "mips") == 0)
3168 return idt_big_breakpoint
;
3169 else if (strcmp (target_shortname
, "ddb") == 0
3170 || strcmp (target_shortname
, "pmon") == 0
3171 || strcmp (target_shortname
, "lsi") == 0)
3172 return pmon_big_breakpoint
;
3174 return big_breakpoint
;
3179 if (pc_is_mips16 (*pcptr
))
3181 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3182 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3183 *lenptr
= sizeof(mips16_little_breakpoint
);
3184 return mips16_little_breakpoint
;
3188 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3189 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3190 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3192 *lenptr
= sizeof(little_breakpoint
);
3194 if (strcmp (target_shortname
, "mips") == 0)
3195 return idt_little_breakpoint
;
3196 else if (strcmp (target_shortname
, "ddb") == 0
3197 || strcmp (target_shortname
, "pmon") == 0
3198 || strcmp (target_shortname
, "lsi") == 0)
3199 return pmon_little_breakpoint
;
3201 return little_breakpoint
;
3206 /* If PC is in a mips16 call or return stub, return the address of the target
3207 PC, which is either the callee or the caller. There are several
3208 cases which must be handled:
3210 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3211 target PC is in $31 ($ra).
3212 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3213 and the target PC is in $2.
3214 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3215 before the jal instruction, this is effectively a call stub
3216 and the the target PC is in $2. Otherwise this is effectively
3217 a return stub and the target PC is in $18.
3219 See the source code for the stubs in gcc/config/mips/mips16.S for
3222 This function implements the SKIP_TRAMPOLINE_CODE macro.
3230 CORE_ADDR start_addr
;
3232 /* Find the starting address and name of the function containing the PC. */
3233 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3236 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3237 target PC is in $31 ($ra). */
3238 if (strcmp (name
, "__mips16_ret_sf") == 0
3239 || strcmp (name
, "__mips16_ret_df") == 0)
3240 return read_register (RA_REGNUM
);
3242 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3244 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3245 and the target PC is in $2. */
3246 if (name
[19] >= '0' && name
[19] <= '9')
3247 return read_register (2);
3249 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3250 before the jal instruction, this is effectively a call stub
3251 and the the target PC is in $2. Otherwise this is effectively
3252 a return stub and the target PC is in $18. */
3253 else if (name
[19] == 's' || name
[19] == 'd')
3255 if (pc
== start_addr
)
3257 /* Check if the target of the stub is a compiler-generated
3258 stub. Such a stub for a function bar might have a name
3259 like __fn_stub_bar, and might look like this:
3264 la $1,bar (becomes a lui/addiu pair)
3266 So scan down to the lui/addi and extract the target
3267 address from those two instructions. */
3269 CORE_ADDR target_pc
= read_register (2);
3273 /* See if the name of the target function is __fn_stub_*. */
3274 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3276 if (strncmp (name
, "__fn_stub_", 10) != 0
3277 && strcmp (name
, "etext") != 0
3278 && strcmp (name
, "_etext") != 0)
3281 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3282 The limit on the search is arbitrarily set to 20
3283 instructions. FIXME. */
3284 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3286 inst
= mips_fetch_instruction (target_pc
);
3287 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3288 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3289 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3290 return pc
| (inst
& 0xffff); /* low word */
3293 /* Couldn't find the lui/addui pair, so return stub address. */
3297 /* This is the 'return' part of a call stub. The return
3298 address is in $r18. */
3299 return read_register (18);
3302 return 0; /* not a stub */
3306 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3307 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3310 mips_in_call_stub (pc
, name
)
3314 CORE_ADDR start_addr
;
3316 /* Find the starting address of the function containing the PC. If the
3317 caller didn't give us a name, look it up at the same time. */
3318 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3321 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3323 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3324 if (name
[19] >= '0' && name
[19] <= '9')
3326 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3327 before the jal instruction, this is effectively a call stub. */
3328 else if (name
[19] == 's' || name
[19] == 'd')
3329 return pc
== start_addr
;
3332 return 0; /* not a stub */
3336 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3337 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3340 mips_in_return_stub (pc
, name
)
3344 CORE_ADDR start_addr
;
3346 /* Find the starting address of the function containing the PC. */
3347 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3350 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3351 if (strcmp (name
, "__mips16_ret_sf") == 0
3352 || strcmp (name
, "__mips16_ret_df") == 0)
3355 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3356 i.e. after the jal instruction, this is effectively a return stub. */
3357 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3358 && (name
[19] == 's' || name
[19] == 'd')
3359 && pc
!= start_addr
)
3362 return 0; /* not a stub */
3366 /* Return non-zero if the PC is in a library helper function that should
3367 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3370 mips_ignore_helper (pc
)
3375 /* Find the starting address and name of the function containing the PC. */
3376 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3379 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3380 that we want to ignore. */
3381 return (strcmp (name
, "__mips16_ret_sf") == 0
3382 || strcmp (name
, "__mips16_ret_df") == 0);
3386 /* Return a location where we can set a breakpoint that will be hit
3387 when an inferior function call returns. This is normally the
3388 program's entry point. Executables that don't have an entry
3389 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3390 whose address is the location where the breakpoint should be placed. */
3393 mips_call_dummy_address ()
3395 struct minimal_symbol
*sym
;
3397 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3399 return SYMBOL_VALUE_ADDRESS (sym
);
3401 return entry_point_address ();
3406 _initialize_mips_tdep ()
3408 static struct cmd_list_element
*mipsfpulist
= NULL
;
3409 struct cmd_list_element
*c
;
3411 if (!tm_print_insn
) /* Someone may have already set it */
3412 tm_print_insn
= gdb_print_insn_mips
;
3414 /* Let the user turn off floating point and set the fence post for
3415 heuristic_proc_start. */
3417 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3418 "Set use of MIPS floating-point coprocessor.",
3419 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3420 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3421 "Select single-precision MIPS floating-point coprocessor.",
3423 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3424 "Select double-precision MIPS floating-point coprocessor .",
3426 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3427 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3428 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3429 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3430 "Select no MIPS floating-point coprocessor.",
3432 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3433 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3434 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3435 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3436 "Select MIPS floating-point coprocessor automatically.",
3438 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3439 "Show current use of MIPS floating-point coprocessor target.",
3442 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3443 (char *) &tmp_mips_processor_type
,
3444 "Set the type of MIPS processor in use.\n\
3445 Set this to be able to access processor-type-specific registers.\n\
3448 c
->function
.cfunc
= mips_set_processor_type_command
;
3449 c
= add_show_from_set (c
, &showlist
);
3450 c
->function
.cfunc
= mips_show_processor_type_command
;
3452 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3453 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3455 /* We really would like to have both "0" and "unlimited" work, but
3456 command.c doesn't deal with that. So make it a var_zinteger
3457 because the user can always use "999999" or some such for unlimited. */
3458 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3459 (char *) &heuristic_fence_post
,
3461 Set the distance searched for the start of a function.\n\
3462 If you are debugging a stripped executable, GDB needs to search through the\n\
3463 program for the start of a function. This command sets the distance of the\n\
3464 search. The only need to set it is when debugging a stripped executable.",
3466 /* We need to throw away the frame cache when we set this, since it
3467 might change our ability to get backtraces. */
3468 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3469 add_show_from_set (c
, &showlist
);
3471 /* Allow the user to control whether the upper bits of 64-bit
3472 addresses should be zeroed. */
3474 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *)&mask_address_p
,
3475 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3476 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3477 Without an argument, zeroing of upper address bits is enabled.", &setlist
),