1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 #include "gdb_string.h"
38 #include "opcode/mips.h"
40 struct frame_extra_info
42 mips_extra_func_info_t proc_desc
;
46 /* Some MIPS boards don't support floating point while others only
47 support single-precision floating-point operations. See also
48 FP_REGISTER_DOUBLE. */
52 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
53 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
54 MIPS_FPU_NONE
/* No floating point. */
57 #ifndef MIPS_DEFAULT_FPU_TYPE
58 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
60 static int mips_fpu_type_auto
= 1;
61 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
62 #define MIPS_FPU_TYPE mips_fpu_type
64 #ifndef MIPS_SAVED_REGSIZE
65 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
68 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
69 #ifndef FP_REGISTER_DOUBLE
70 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
74 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
77 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
80 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
82 static void mips_print_register
PARAMS ((int, int));
84 static mips_extra_func_info_t
85 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
87 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
89 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
91 void mips_set_processor_type_command
PARAMS ((char *, int));
93 int mips_set_processor_type
PARAMS ((char *));
95 static void mips_show_processor_type_command
PARAMS ((char *, int));
97 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
98 struct cmd_list_element
*));
100 static mips_extra_func_info_t
101 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
103 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
104 mips_extra_func_info_t proc_desc
));
106 /* This value is the model of MIPS in use. It is derived from the value
107 of the PrID register. */
109 char *mips_processor_type
;
111 char *tmp_mips_processor_type
;
113 /* A set of original names, to be used when restoring back to generic
114 registers from a specific set. */
116 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
117 char **mips_processor_reg_names
= mips_generic_reg_names
;
120 mips_register_name (i
)
123 return mips_processor_reg_names
[i
];
126 /* Names of IDT R3041 registers. */
128 char *mips_r3041_reg_names
[] = {
129 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
132 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
133 "sr", "lo", "hi", "bad", "cause","pc",
134 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
135 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
136 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
137 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
138 "fsr", "fir", "fp", "",
139 "", "", "bus", "ccfg", "", "", "", "",
140 "", "", "port", "cmp", "", "", "epc", "prid",
143 /* Names of IDT R3051 registers. */
145 char *mips_r3051_reg_names
[] = {
146 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
147 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
148 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
149 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
150 "sr", "lo", "hi", "bad", "cause","pc",
151 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
152 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
153 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
154 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
155 "fsr", "fir", "fp", "",
156 "inx", "rand", "elo", "", "ctxt", "", "", "",
157 "", "", "ehi", "", "", "", "epc", "prid",
160 /* Names of IDT R3081 registers. */
162 char *mips_r3081_reg_names
[] = {
163 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
164 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
165 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
166 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
167 "sr", "lo", "hi", "bad", "cause","pc",
168 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
169 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
170 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
171 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
172 "fsr", "fir", "fp", "",
173 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
174 "", "", "ehi", "", "", "", "epc", "prid",
177 /* Names of LSI 33k registers. */
179 char *mips_lsi33k_reg_names
[] = {
180 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
181 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
182 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
183 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
184 "epc", "hi", "lo", "sr", "cause","badvaddr",
185 "dcic", "bpc", "bda", "", "", "", "", "",
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
197 } mips_processor_type_table
[] = {
198 { "generic", mips_generic_reg_names
},
199 { "r3041", mips_r3041_reg_names
},
200 { "r3051", mips_r3051_reg_names
},
201 { "r3071", mips_r3081_reg_names
},
202 { "r3081", mips_r3081_reg_names
},
203 { "lsi33k", mips_lsi33k_reg_names
},
211 /* Table to translate MIPS16 register field to actual register number. */
212 static int mips16_to_32_reg
[8] =
213 {16, 17, 2, 3, 4, 5, 6, 7};
215 /* Heuristic_proc_start may hunt through the text section for a long
216 time across a 2400 baud serial line. Allows the user to limit this
219 static unsigned int heuristic_fence_post
= 0;
221 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
222 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
223 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
224 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
225 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
226 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
227 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
228 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
229 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
230 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
231 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
232 #define _PROC_MAGIC_ 0x0F0F0F0F
233 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
234 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
236 struct linked_proc_info
238 struct mips_extra_func_info info
;
239 struct linked_proc_info
*next
;
241 *linked_proc_desc_table
= NULL
;
244 mips_print_extra_frame_info (fi
)
245 struct frame_info
*fi
;
249 && fi
->extra_info
->proc_desc
250 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
251 printf_filtered (" frame pointer is at %s+%d\n",
252 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
253 fi
->extra_info
->proc_desc
->pdr
.frameoffset
);
256 /* Should the upper word of 64-bit addresses be zeroed? */
257 static int mask_address_p
= 1;
259 /* Should call_function allocate stack space for a struct return? */
261 mips_use_struct_convention (gcc_p
, type
)
266 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
268 return 1; /* Structures are returned by ref in extra arg0 */
271 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
274 pc_is_mips16 (bfd_vma memaddr
)
276 struct minimal_symbol
*sym
;
278 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
279 if (IS_MIPS16_ADDR (memaddr
))
282 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
283 the high bit of the info field. Use this to decide if the function is
284 MIPS16 or normal MIPS. */
285 sym
= lookup_minimal_symbol_by_pc (memaddr
);
287 return MSYMBOL_IS_SPECIAL (sym
);
293 /* This returns the PC of the first inst after the prologue. If we can't
294 find the prologue, then return 0. */
297 after_prologue (pc
, proc_desc
)
299 mips_extra_func_info_t proc_desc
;
301 struct symtab_and_line sal
;
302 CORE_ADDR func_addr
, func_end
;
305 proc_desc
= find_proc_desc (pc
, NULL
);
309 /* If function is frameless, then we need to do it the hard way. I
310 strongly suspect that frameless always means prologueless... */
311 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
312 && PROC_FRAME_OFFSET (proc_desc
) == 0)
316 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
317 return 0; /* Unknown */
319 sal
= find_pc_line (func_addr
, 0);
321 if (sal
.end
< func_end
)
324 /* The line after the prologue is after the end of the function. In this
325 case, tell the caller to find the prologue the hard way. */
330 /* Decode a MIPS32 instruction that saves a register in the stack, and
331 set the appropriate bit in the general register mask or float register mask
332 to indicate which register is saved. This is a helper function
333 for mips_find_saved_regs. */
336 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
338 unsigned long *gen_mask
;
339 unsigned long *float_mask
;
343 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
344 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
345 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
347 /* It might be possible to use the instruction to
348 find the offset, rather than the code below which
349 is based on things being in a certain order in the
350 frame, but figuring out what the instruction's offset
351 is relative to might be a little tricky. */
352 reg
= (inst
& 0x001f0000) >> 16;
353 *gen_mask
|= (1 << reg
);
355 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
356 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
357 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
360 reg
= ((inst
& 0x001f0000) >> 16);
361 *float_mask
|= (1 << reg
);
365 /* Decode a MIPS16 instruction that saves a register in the stack, and
366 set the appropriate bit in the general register or float register mask
367 to indicate which register is saved. This is a helper function
368 for mips_find_saved_regs. */
371 mips16_decode_reg_save (inst
, gen_mask
)
373 unsigned long *gen_mask
;
375 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
377 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
378 *gen_mask
|= (1 << reg
);
380 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
382 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
383 *gen_mask
|= (1 << reg
);
385 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
386 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
387 *gen_mask
|= (1 << RA_REGNUM
);
391 /* Fetch and return instruction from the specified location. If the PC
392 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
395 mips_fetch_instruction (addr
)
398 char buf
[MIPS_INSTLEN
];
402 if (pc_is_mips16 (addr
))
404 instlen
= MIPS16_INSTLEN
;
405 addr
= UNMAKE_MIPS16_ADDR (addr
);
408 instlen
= MIPS_INSTLEN
;
409 status
= read_memory_nobpt (addr
, buf
, instlen
);
411 memory_error (status
, addr
);
412 return extract_unsigned_integer (buf
, instlen
);
416 /* These the fields of 32 bit mips instructions */
417 #define mips32_op(x) (x >> 25)
418 #define itype_op(x) (x >> 25)
419 #define itype_rs(x) ((x >> 21)& 0x1f)
420 #define itype_rt(x) ((x >> 16) & 0x1f)
421 #define itype_immediate(x) ( x & 0xffff)
423 #define jtype_op(x) (x >> 25)
424 #define jtype_target(x) ( x & 0x03fffff)
426 #define rtype_op(x) (x >>25)
427 #define rtype_rs(x) ((x>>21) & 0x1f)
428 #define rtype_rt(x) ((x>>16) & 0x1f)
429 #define rtype_rd(x) ((x>>11) & 0x1f)
430 #define rtype_shamt(x) ((x>>6) & 0x1f)
431 #define rtype_funct(x) (x & 0x3f )
434 mips32_relative_offset (unsigned long inst
)
437 x
= itype_immediate (inst
);
438 if (x
& 0x8000) /* sign bit set */
440 x
|= 0xffff0000; /* sign extension */
446 /* Determine whate to set a single step breakpoint while considering
449 mips32_next_pc (CORE_ADDR pc
)
453 inst
= mips_fetch_instruction (pc
);
454 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
456 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
458 op
= ((inst
>> 25) & 0x03);
462 goto equal_branch
; /* BEQL */
464 goto neq_branch
; /* BNEZ */
466 goto less_branch
; /* BLEZ */
468 goto greater_branch
; /* BGTZ */
474 pc
+= 4; /* Not a branch, next instruction is easy */
477 { /* This gets way messy */
479 /* Further subdivide into SPECIAL, REGIMM and other */
480 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
482 case 0: /* SPECIAL */
483 op
= rtype_funct (inst
);
488 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
494 break; /* end special */
497 op
= jtype_op (inst
); /* branch condition */
498 switch (jtype_op (inst
))
502 case 16: /* BLTZALL */
503 case 18: /* BLTZALL */
505 if (read_register (itype_rs (inst
)) < 0)
506 pc
+= mips32_relative_offset (inst
) + 4;
508 pc
+= 8; /* after the delay slot */
512 case 17: /* BGEZAL */
513 case 19: /* BGEZALL */
514 greater_equal_branch
:
515 if (read_register (itype_rs (inst
)) >= 0)
516 pc
+= mips32_relative_offset (inst
) + 4;
518 pc
+= 8; /* after the delay slot */
520 /* All of the other intructions in the REGIMM catagory */
525 break; /* end REGIMM */
530 reg
= jtype_target (inst
) << 2;
531 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
532 /* Whats this mysterious 0xf000000 adjustment ??? */
535 /* FIXME case JALX : */
538 reg
= jtype_target (inst
) << 2;
539 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
540 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
542 break; /* The new PC will be alternate mode */
543 case 4: /* BEQ , BEQL */
545 if (read_register (itype_rs (inst
)) ==
546 read_register (itype_rt (inst
)))
547 pc
+= mips32_relative_offset (inst
) + 4;
551 case 5: /* BNE , BNEL */
553 if (read_register (itype_rs (inst
)) !=
554 read_register (itype_rs (inst
)))
555 pc
+= mips32_relative_offset (inst
) + 4;
559 case 6: /* BLEZ , BLEZL */
561 if (read_register (itype_rs (inst
) <= 0))
562 pc
+= mips32_relative_offset (inst
) + 4;
567 greater_branch
: /* BGTZ BGTZL */
568 if (read_register (itype_rs (inst
) > 0))
569 pc
+= mips32_relative_offset (inst
) + 4;
578 } /* mips32_next_pc */
580 /* Decoding the next place to set a breakpoint is irregular for the
581 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
582 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
583 We dont want to set a single step instruction on the extend instruction
587 /* Lots of mips16 instruction formats */
588 /* Predicting jumps requires itype,ritype,i8type
589 and their extensions extItype,extritype,extI8type
591 enum mips16_inst_fmts
593 itype
, /* 0 immediate 5,10 */
594 ritype
, /* 1 5,3,8 */
595 rrtype
, /* 2 5,3,3,5 */
596 rritype
, /* 3 5,3,3,5 */
597 rrrtype
, /* 4 5,3,3,3,2 */
598 rriatype
, /* 5 5,3,3,1,4 */
599 shifttype
, /* 6 5,3,3,3,2 */
600 i8type
, /* 7 5,3,8 */
601 i8movtype
, /* 8 5,3,3,5 */
602 i8mov32rtype
, /* 9 5,3,5,3 */
603 i64type
, /* 10 5,3,8 */
604 ri64type
, /* 11 5,3,3,5 */
605 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
606 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
607 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
608 extRRItype
, /* 15 5,5,5,5,3,3,5 */
609 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
610 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
611 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
612 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
613 extRi64type
, /* 20 5,6,5,5,3,3,5 */
614 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
616 /* I am heaping all the fields of the formats into one structure and then,
617 only the fields which are involved in instruction extension */
621 enum mips16_inst_fmts fmt
;
622 unsigned long offset
;
623 unsigned int regx
; /* Function in i8 type */
630 print_unpack (char *comment
,
631 struct upk_mips16
*u
)
633 printf ("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
634 comment
, u
->inst
, u
->fmt
, u
->offset
, u
->regx
, u
->regy
);
637 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
638 format for the bits which make up the immediatate extension.
641 extended_offset (unsigned long extension
)
644 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
646 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
648 value
|= extension
& 0x01f; /* extract 4:0 */
652 /* Only call this function if you know that this is an extendable
653 instruction, It wont malfunction, but why make excess remote memory references?
654 If the immediate operands get sign extended or somthing, do it after
655 the extension is performed.
657 /* FIXME: Every one of these cases needs to worry about sign extension
658 when the offset is to be used in relative addressing */
661 static unsigned short
662 fetch_mips_16 (CORE_ADDR pc
)
665 pc
&= 0xfffffffe; /* clear the low order bit */
666 target_read_memory (pc
, buf
, 2);
667 return extract_unsigned_integer (buf
, 2);
671 unpack_mips16 (CORE_ADDR pc
,
672 struct upk_mips16
*upk
)
675 unsigned long extension
;
677 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
678 /* Decrement to previous address and loose the 16bit mode flag */
679 /* return if the instruction was extendable, but not actually extended */
680 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
683 extension
= mips_fetch_instruction (extpc
);
692 value
= extended_offset (extension
);
693 value
= value
<< 11; /* rom for the original value */
694 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
698 value
= upk
->inst
& 0x7ff;
699 /* FIXME : Consider sign extension */
706 { /* A register identifier and an offset */
707 /* Most of the fields are the same as I type but the
708 immediate value is of a different length */
712 value
= extended_offset (extension
);
713 value
= value
<< 8; /* from the original instruction */
714 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
715 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
716 if (value
& 0x4000) /* test the sign bit , bit 26 */
718 value
&= ~0x3fff; /* remove the sign bit */
724 value
= upk
->inst
& 0xff; /* 8 bits */
725 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
726 /* FIXME: Do sign extension , this format needs it */
727 if (value
& 0x80) /* THIS CONFUSES ME */
729 value
&= 0xef; /* remove the sign bit */
740 unsigned short nexthalf
;
741 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
743 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
749 printf_filtered ("Decoding unimplemented instruction format type\n");
752 /* print_unpack("UPK",upk) ; */
756 #define mips16_op(x) (x >> 11)
758 /* This is a map of the opcodes which ae known to perform branches */
759 static unsigned char map16
[32] =
760 {0, 0, 1, 1, 1, 1, 0, 0,
761 0, 0, 0, 0, 1, 0, 0, 0,
762 0, 0, 0, 0, 0, 0, 0, 0,
763 0, 0, 0, 0, 0, 1, 1, 0
767 add_offset_16 (CORE_ADDR pc
, int offset
)
769 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
775 static struct upk_mips16 upk
;
778 mips16_next_pc (CORE_ADDR pc
)
782 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
783 inst
= fetch_mips_16 (pc
);
785 op
= mips16_op (upk
.inst
);
793 unpack_mips16 (pc
, &upk
);
802 pc
+= (offset
<< 1) + 2;
805 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
807 unpack_mips16 (pc
, &upk
);
808 pc
= add_offset_16 (pc
, upk
.offset
);
809 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
810 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
816 unpack_mips16 (pc
, &upk
);
817 reg
= read_register (upk
.regx
);
819 pc
+= (upk
.offset
<< 1) + 2;
825 unpack_mips16 (pc
, &upk
);
826 reg
= read_register (upk
.regx
);
828 pc
+= (upk
.offset
<< 1) + 2;
832 case 12: /* I8 Formats btez btnez */
834 unpack_mips16 (pc
, &upk
);
835 /* upk.regx contains the opcode */
836 reg
= read_register (24); /* Test register is 24 */
837 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
838 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
839 /* pc = add_offset_16(pc,upk.offset) ; */
840 pc
+= (upk
.offset
<< 1) + 2;
844 case 29: /* RR Formats JR, JALR, JALR-RA */
846 op
= upk
.inst
& 0x1f;
849 upk
.regx
= (upk
.inst
>> 8) & 0x07;
850 upk
.regy
= (upk
.inst
>> 5) & 0x07;
858 break; /* Function return instruction */
864 break; /* BOGUS Guess */
866 pc
= read_register (reg
);
871 case 30: /* This is an extend instruction */
872 pc
+= 4; /* Dont be setting breakpints on the second half */
875 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
881 pc
+= 2; /* just a good old instruction */
882 /* See if we CAN actually break on the next instruction */
883 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
885 } /* mips16_next_pc */
887 /* The mips_next_pc function supports single_tep when the remote target monitor or
888 stub is not developed enough to so a single_step.
889 It works by decoding the current instruction and predicting where a branch
890 will go. This isnt hard because all the data is available.
891 The MIPS32 and MIPS16 variants are quite different
894 mips_next_pc (CORE_ADDR pc
)
897 /* inst = mips_fetch_instruction(pc) ; */
898 /* if (pc_is_mips16) <----- This is failing */
900 return mips16_next_pc (pc
);
902 return mips32_next_pc (pc
);
905 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
909 mips_find_saved_regs (fci
)
910 struct frame_info
*fci
;
913 CORE_ADDR reg_position
;
914 /* r0 bit means kernel trap */
916 /* What registers have been saved? Bitmasks. */
917 unsigned long gen_mask
, float_mask
;
918 mips_extra_func_info_t proc_desc
;
921 frame_saved_regs_zalloc (fci
);
923 /* If it is the frame for sigtramp, the saved registers are located
924 in a sigcontext structure somewhere on the stack.
925 If the stack layout for sigtramp changes we might have to change these
926 constants and the companion fixup_sigtramp in mdebugread.c */
927 #ifndef SIGFRAME_BASE
928 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
929 above the sigtramp frame. */
930 #define SIGFRAME_BASE MIPS_REGSIZE
931 /* FIXME! Are these correct?? */
932 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
933 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
934 #define SIGFRAME_FPREGSAVE_OFF \
935 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
937 #ifndef SIGFRAME_REG_SIZE
938 /* FIXME! Is this correct?? */
939 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
941 if (fci
->signal_handler_caller
)
943 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
945 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
946 + ireg
* SIGFRAME_REG_SIZE
;
947 fci
->saved_regs
[ireg
] = reg_position
;
949 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
951 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
952 + ireg
* SIGFRAME_REG_SIZE
;
953 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
955 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
959 proc_desc
= fci
->extra_info
->proc_desc
;
960 if (proc_desc
== NULL
)
961 /* I'm not sure how/whether this can happen. Normally when we can't
962 find a proc_desc, we "synthesize" one using heuristic_proc_desc
963 and set the saved_regs right away. */
966 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
967 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
968 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
970 if ( /* In any frame other than the innermost or a frame interrupted by
971 a signal, we assume that all registers have been saved.
972 This assumes that all register saves in a function happen before
973 the first function call. */
974 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
976 /* In a dummy frame we know exactly where things are saved. */
977 && !PROC_DESC_IS_DUMMY (proc_desc
)
979 /* Don't bother unless we are inside a function prologue. Outside the
980 prologue, we know where everything is. */
982 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
984 /* Not sure exactly what kernel_trap means, but if it means
985 the kernel saves the registers without a prologue doing it,
986 we better not examine the prologue to see whether registers
987 have been saved yet. */
990 /* We need to figure out whether the registers that the proc_desc
991 claims are saved have been saved yet. */
995 /* Bitmasks; set if we have found a save for the register. */
996 unsigned long gen_save_found
= 0;
997 unsigned long float_save_found
= 0;
1000 /* If the address is odd, assume this is MIPS16 code. */
1001 addr
= PROC_LOW_ADDR (proc_desc
);
1002 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1004 /* Scan through this function's instructions preceding the current
1005 PC, and look for those that save registers. */
1006 while (addr
< fci
->pc
)
1008 inst
= mips_fetch_instruction (addr
);
1009 if (pc_is_mips16 (addr
))
1010 mips16_decode_reg_save (inst
, &gen_save_found
);
1012 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1015 gen_mask
= gen_save_found
;
1016 float_mask
= float_save_found
;
1019 /* Fill in the offsets for the registers which gen_mask says
1021 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1022 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1023 if (gen_mask
& 0x80000000)
1025 fci
->saved_regs
[ireg
] = reg_position
;
1026 reg_position
-= MIPS_SAVED_REGSIZE
;
1029 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1030 of that normally used by gcc. Therefore, we have to fetch the first
1031 instruction of the function, and if it's an entry instruction that
1032 saves $s0 or $s1, correct their saved addresses. */
1033 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1035 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1036 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1039 int sreg_count
= (inst
>> 6) & 3;
1041 /* Check if the ra register was pushed on the stack. */
1042 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1044 reg_position
-= MIPS_SAVED_REGSIZE
;
1046 /* Check if the s0 and s1 registers were pushed on the stack. */
1047 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1049 fci
->saved_regs
[reg
] = reg_position
;
1050 reg_position
-= MIPS_SAVED_REGSIZE
;
1055 /* Fill in the offsets for the registers which float_mask says
1057 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1059 /* The freg_offset points to where the first *double* register
1060 is saved. So skip to the high-order word. */
1061 if (!GDB_TARGET_IS_MIPS64
)
1062 reg_position
+= MIPS_SAVED_REGSIZE
;
1064 /* Fill in the offsets for the float registers which float_mask says
1066 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1067 if (float_mask
& 0x80000000)
1069 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1070 reg_position
-= MIPS_SAVED_REGSIZE
;
1073 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1077 read_next_frame_reg (fi
, regno
)
1078 struct frame_info
*fi
;
1081 for (; fi
; fi
= fi
->next
)
1083 /* We have to get the saved sp from the sigcontext
1084 if it is a signal handler frame. */
1085 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1089 if (fi
->saved_regs
== NULL
)
1090 mips_find_saved_regs (fi
);
1091 if (fi
->saved_regs
[regno
])
1092 return read_memory_integer (fi
->saved_regs
[regno
], MIPS_SAVED_REGSIZE
);
1095 return read_register (regno
);
1098 /* mips_addr_bits_remove - remove useless address bits */
1101 mips_addr_bits_remove (addr
)
1104 #if GDB_TARGET_IS_MIPS64
1105 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1107 /* This hack is a work-around for existing boards using PMON,
1108 the simulator, and any other 64-bit targets that doesn't have
1109 true 64-bit addressing. On these targets, the upper 32 bits
1110 of addresses are ignored by the hardware. Thus, the PC or SP
1111 are likely to have been sign extended to all 1s by instruction
1112 sequences that load 32-bit addresses. For example, a typical
1113 piece of code that loads an address is this:
1114 lui $r2, <upper 16 bits>
1115 ori $r2, <lower 16 bits>
1116 But the lui sign-extends the value such that the upper 32 bits
1117 may be all 1s. The workaround is simply to mask off these bits.
1118 In the future, gcc may be changed to support true 64-bit
1119 addressing, and this masking will have to be disabled. */
1120 addr
&= (CORE_ADDR
) 0xffffffff;
1123 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1124 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1125 So we still have to mask off useless bits from addresses. */
1126 addr
&= (CORE_ADDR
) 0xffffffff;
1133 mips_init_frame_pc_first (fromleaf
, prev
)
1135 struct frame_info
*prev
;
1139 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1140 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1141 tmp
= mips_skip_stub (pc
);
1142 prev
->pc
= tmp
? tmp
: pc
;
1147 mips_frame_saved_pc (frame
)
1148 struct frame_info
*frame
;
1151 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1152 /* We have to get the saved pc from the sigcontext
1153 if it is a signal handler frame. */
1154 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1155 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1157 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1158 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1160 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1162 return ADDR_BITS_REMOVE (saved_pc
);
1165 static struct mips_extra_func_info temp_proc_desc
;
1166 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1168 /* Set a register's saved stack address in temp_saved_regs. If an address
1169 has already been set for this register, do nothing; this way we will
1170 only recognize the first save of a given register in a function prologue.
1171 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1174 set_reg_offset (regno
, offset
)
1178 if (temp_saved_regs
[regno
] == 0)
1179 temp_saved_regs
[regno
] = offset
;
1183 /* Test whether the PC points to the return instruction at the
1184 end of a function. */
1187 mips_about_to_return (pc
)
1190 if (pc_is_mips16 (pc
))
1191 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1192 generates a "jr $ra"; other times it generates code to load
1193 the return address from the stack to an accessible register (such
1194 as $a3), then a "jr" using that register. This second case
1195 is almost impossible to distinguish from an indirect jump
1196 used for switch statements, so we don't even try. */
1197 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1199 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1203 /* This fencepost looks highly suspicious to me. Removing it also
1204 seems suspicious as it could affect remote debugging across serial
1208 heuristic_proc_start (pc
)
1216 pc
= ADDR_BITS_REMOVE (pc
);
1218 fence
= start_pc
- heuristic_fence_post
;
1222 if (heuristic_fence_post
== UINT_MAX
1223 || fence
< VM_MIN_ADDRESS
)
1224 fence
= VM_MIN_ADDRESS
;
1226 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1228 /* search back for previous return */
1229 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1230 if (start_pc
< fence
)
1232 /* It's not clear to me why we reach this point when
1233 stop_soon_quietly, but with this test, at least we
1234 don't print out warnings for every child forked (eg, on
1235 decstation). 22apr93 rich@cygnus.com. */
1236 if (!stop_soon_quietly
)
1238 static int blurb_printed
= 0;
1240 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1245 /* This actually happens frequently in embedded
1246 development, when you first connect to a board
1247 and your stack pointer and pc are nowhere in
1248 particular. This message needs to give people
1249 in that situation enough information to
1250 determine that it's no big deal. */
1251 printf_filtered ("\n\
1252 GDB is unable to find the start of the function at 0x%s\n\
1253 and thus can't determine the size of that function's stack frame.\n\
1254 This means that GDB may be unable to access that stack frame, or\n\
1255 the frames below it.\n\
1256 This problem is most likely caused by an invalid program counter or\n\
1258 However, if you think GDB should simply search farther back\n\
1259 from 0x%s for code which looks like the beginning of a\n\
1260 function, you can increase the range of the search using the `set\n\
1261 heuristic-fence-post' command.\n",
1262 paddr_nz (pc
), paddr_nz (pc
));
1269 else if (pc_is_mips16 (start_pc
))
1271 unsigned short inst
;
1273 /* On MIPS16, any one of the following is likely to be the
1274 start of a function:
1278 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1279 inst
= mips_fetch_instruction (start_pc
);
1280 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1281 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1282 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1283 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1285 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1286 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1291 else if (mips_about_to_return (start_pc
))
1293 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1298 /* skip nops (usually 1) 0 - is this */
1299 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1300 start_pc
+= MIPS_INSTLEN
;
1305 /* Fetch the immediate value from a MIPS16 instruction.
1306 If the previous instruction was an EXTEND, use it to extend
1307 the upper bits of the immediate value. This is a helper function
1308 for mips16_heuristic_proc_desc. */
1311 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1312 unsigned short prev_inst
; /* previous instruction */
1313 unsigned short inst
; /* current instruction */
1314 int nbits
; /* number of bits in imm field */
1315 int scale
; /* scale factor to be applied to imm */
1316 int is_signed
; /* is the imm field signed? */
1320 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1322 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1323 if (offset
& 0x8000) /* check for negative extend */
1324 offset
= 0 - (0x10000 - (offset
& 0xffff));
1325 return offset
| (inst
& 0x1f);
1329 int max_imm
= 1 << nbits
;
1330 int mask
= max_imm
- 1;
1331 int sign_bit
= max_imm
>> 1;
1333 offset
= inst
& mask
;
1334 if (is_signed
&& (offset
& sign_bit
))
1335 offset
= 0 - (max_imm
- offset
);
1336 return offset
* scale
;
1341 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1342 stream from start_pc to limit_pc. */
1345 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1346 CORE_ADDR start_pc
, limit_pc
;
1347 struct frame_info
*next_frame
;
1351 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1352 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1353 unsigned inst
= 0; /* current instruction */
1354 unsigned entry_inst
= 0; /* the entry instruction */
1357 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1358 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1360 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1362 /* Save the previous instruction. If it's an EXTEND, we'll extract
1363 the immediate offset extension from it in mips16_get_imm. */
1366 /* Fetch and decode the instruction. */
1367 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1368 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1369 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1371 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1372 if (offset
< 0) /* negative stack adjustment? */
1373 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1375 /* Exit loop if a positive stack adjustment is found, which
1376 usually means that the stack cleanup code in the function
1377 epilogue is reached. */
1380 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1382 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1383 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1384 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1385 set_reg_offset (reg
, sp
+ offset
);
1387 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1389 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1390 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1391 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1392 set_reg_offset (reg
, sp
+ offset
);
1394 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1396 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1397 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1398 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1400 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1402 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1403 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1404 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1406 else if (inst
== 0x673d) /* move $s1, $sp */
1409 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1411 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1413 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1414 frame_addr
= sp
+ offset
;
1415 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1416 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1418 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1420 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1421 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1422 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1423 set_reg_offset (reg
, frame_addr
+ offset
);
1425 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1427 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1428 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1429 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1430 set_reg_offset (reg
, frame_addr
+ offset
);
1432 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1433 entry_inst
= inst
; /* save for later processing */
1434 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1435 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1438 /* The entry instruction is typically the first instruction in a function,
1439 and it stores registers at offsets relative to the value of the old SP
1440 (before the prologue). But the value of the sp parameter to this
1441 function is the new SP (after the prologue has been executed). So we
1442 can't calculate those offsets until we've seen the entire prologue,
1443 and can calculate what the old SP must have been. */
1444 if (entry_inst
!= 0)
1446 int areg_count
= (entry_inst
>> 8) & 7;
1447 int sreg_count
= (entry_inst
>> 6) & 3;
1449 /* The entry instruction always subtracts 32 from the SP. */
1450 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1452 /* Now we can calculate what the SP must have been at the
1453 start of the function prologue. */
1454 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1456 /* Check if a0-a3 were saved in the caller's argument save area. */
1457 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1459 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1460 set_reg_offset (reg
, sp
+ offset
);
1461 offset
+= MIPS_SAVED_REGSIZE
;
1464 /* Check if the ra register was pushed on the stack. */
1466 if (entry_inst
& 0x20)
1468 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1469 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1470 offset
-= MIPS_SAVED_REGSIZE
;
1473 /* Check if the s0 and s1 registers were pushed on the stack. */
1474 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1476 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1477 set_reg_offset (reg
, sp
+ offset
);
1478 offset
-= MIPS_SAVED_REGSIZE
;
1484 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1485 CORE_ADDR start_pc
, limit_pc
;
1486 struct frame_info
*next_frame
;
1490 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1492 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1493 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1494 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1495 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1497 unsigned long inst
, high_word
, low_word
;
1500 /* Fetch the instruction. */
1501 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1503 /* Save some code by pre-extracting some useful fields. */
1504 high_word
= (inst
>> 16) & 0xffff;
1505 low_word
= inst
& 0xffff;
1506 reg
= high_word
& 0x1f;
1508 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1509 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1510 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1512 if (low_word
& 0x8000) /* negative stack adjustment? */
1513 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1515 /* Exit loop if a positive stack adjustment is found, which
1516 usually means that the stack cleanup code in the function
1517 epilogue is reached. */
1520 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1522 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1523 set_reg_offset (reg
, sp
+ low_word
);
1525 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1527 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1528 but the register size used is only 32 bits. Make the address
1529 for the saved register point to the lower 32 bits. */
1530 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1531 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1533 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1535 /* Old gcc frame, r30 is virtual frame pointer. */
1536 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1537 frame_addr
= sp
+ low_word
;
1538 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1540 unsigned alloca_adjust
;
1541 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1542 frame_addr
= read_next_frame_reg (next_frame
, 30);
1543 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1544 if (alloca_adjust
> 0)
1546 /* FP > SP + frame_size. This may be because
1547 * of an alloca or somethings similar.
1548 * Fix sp to "pre-alloca" value, and try again.
1550 sp
+= alloca_adjust
;
1555 /* move $30,$sp. With different versions of gas this will be either
1556 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1557 Accept any one of these. */
1558 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1560 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1561 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1563 unsigned alloca_adjust
;
1564 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1565 frame_addr
= read_next_frame_reg (next_frame
, 30);
1566 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1567 if (alloca_adjust
> 0)
1569 /* FP > SP + frame_size. This may be because
1570 * of an alloca or somethings similar.
1571 * Fix sp to "pre-alloca" value, and try again.
1573 sp
+= alloca_adjust
;
1578 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1580 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1581 set_reg_offset (reg
, frame_addr
+ low_word
);
1586 static mips_extra_func_info_t
1587 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1588 CORE_ADDR start_pc
, limit_pc
;
1589 struct frame_info
*next_frame
;
1591 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1595 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1596 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1597 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1598 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1599 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1601 if (start_pc
+ 200 < limit_pc
)
1602 limit_pc
= start_pc
+ 200;
1603 if (pc_is_mips16 (start_pc
))
1604 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1606 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1607 return &temp_proc_desc
;
1610 static mips_extra_func_info_t
1611 non_heuristic_proc_desc (pc
, addrptr
)
1615 CORE_ADDR startaddr
;
1616 mips_extra_func_info_t proc_desc
;
1617 struct block
*b
= block_for_pc (pc
);
1620 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1622 *addrptr
= startaddr
;
1623 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1627 if (startaddr
> BLOCK_START (b
))
1628 /* This is the "pathological" case referred to in a comment in
1629 print_frame_info. It might be better to move this check into
1633 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1636 /* If we never found a PDR for this function in symbol reading, then
1637 examine prologues to find the information. */
1640 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1641 if (PROC_FRAME_REG (proc_desc
) == -1)
1651 static mips_extra_func_info_t
1652 find_proc_desc (pc
, next_frame
)
1654 struct frame_info
*next_frame
;
1656 mips_extra_func_info_t proc_desc
;
1657 CORE_ADDR startaddr
;
1659 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1663 /* IF this is the topmost frame AND
1664 * (this proc does not have debugging information OR
1665 * the PC is in the procedure prologue)
1666 * THEN create a "heuristic" proc_desc (by analyzing
1667 * the actual code) to replace the "official" proc_desc.
1669 if (next_frame
== NULL
)
1671 struct symtab_and_line val
;
1672 struct symbol
*proc_symbol
=
1673 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1677 val
= find_pc_line (BLOCK_START
1678 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1680 val
.pc
= val
.end
? val
.end
: pc
;
1682 if (!proc_symbol
|| pc
< val
.pc
)
1684 mips_extra_func_info_t found_heuristic
=
1685 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1687 if (found_heuristic
)
1688 proc_desc
= found_heuristic
;
1694 /* Is linked_proc_desc_table really necessary? It only seems to be used
1695 by procedure call dummys. However, the procedures being called ought
1696 to have their own proc_descs, and even if they don't,
1697 heuristic_proc_desc knows how to create them! */
1699 register struct linked_proc_info
*link
;
1701 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1702 if (PROC_LOW_ADDR (&link
->info
) <= pc
1703 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1707 startaddr
= heuristic_proc_start (pc
);
1710 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1716 get_frame_pointer (frame
, proc_desc
)
1717 struct frame_info
*frame
;
1718 mips_extra_func_info_t proc_desc
;
1720 return ADDR_BITS_REMOVE (
1721 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1722 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1725 mips_extra_func_info_t cached_proc_desc
;
1728 mips_frame_chain (frame
)
1729 struct frame_info
*frame
;
1731 mips_extra_func_info_t proc_desc
;
1733 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1735 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1738 /* Check if the PC is inside a call stub. If it is, fetch the
1739 PC of the caller of that stub. */
1740 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1743 /* Look up the procedure descriptor for this PC. */
1744 proc_desc
= find_proc_desc (saved_pc
, frame
);
1748 cached_proc_desc
= proc_desc
;
1750 /* If no frame pointer and frame size is zero, we must be at end
1751 of stack (or otherwise hosed). If we don't check frame size,
1752 we loop forever if we see a zero size frame. */
1753 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1754 && PROC_FRAME_OFFSET (proc_desc
) == 0
1755 /* The previous frame from a sigtramp frame might be frameless
1756 and have frame size zero. */
1757 && !frame
->signal_handler_caller
)
1760 return get_frame_pointer (frame
, proc_desc
);
1764 mips_init_extra_frame_info (fromleaf
, fci
)
1766 struct frame_info
*fci
;
1770 /* Use proc_desc calculated in frame_chain */
1771 mips_extra_func_info_t proc_desc
=
1772 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1774 fci
->extra_info
= (struct frame_extra_info
*)
1775 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1777 fci
->saved_regs
= NULL
;
1778 fci
->extra_info
->proc_desc
=
1779 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1782 /* Fixup frame-pointer - only needed for top frame */
1783 /* This may not be quite right, if proc has a real frame register.
1784 Get the value of the frame relative sp, procedure might have been
1785 interrupted by a signal at it's very start. */
1786 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1787 && !PROC_DESC_IS_DUMMY (proc_desc
))
1788 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1790 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1792 if (proc_desc
== &temp_proc_desc
)
1796 /* Do not set the saved registers for a sigtramp frame,
1797 mips_find_saved_registers will do that for us.
1798 We can't use fci->signal_handler_caller, it is not yet set. */
1799 find_pc_partial_function (fci
->pc
, &name
,
1800 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1801 if (!IN_SIGTRAMP (fci
->pc
, name
))
1803 frame_saved_regs_zalloc (fci
);
1804 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1805 fci
->saved_regs
[PC_REGNUM
]
1806 = fci
->saved_regs
[RA_REGNUM
];
1810 /* hack: if argument regs are saved, guess these contain args */
1811 /* assume we can't tell how many args for now */
1812 fci
->extra_info
->num_args
= -1;
1813 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1815 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
1817 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1824 /* MIPS stack frames are almost impenetrable. When execution stops,
1825 we basically have to look at symbol information for the function
1826 that we stopped in, which tells us *which* register (if any) is
1827 the base of the frame pointer, and what offset from that register
1828 the frame itself is at.
1830 This presents a problem when trying to examine a stack in memory
1831 (that isn't executing at the moment), using the "frame" command. We
1832 don't have a PC, nor do we have any registers except SP.
1834 This routine takes two arguments, SP and PC, and tries to make the
1835 cached frames look as if these two arguments defined a frame on the
1836 cache. This allows the rest of info frame to extract the important
1837 arguments without difficulty. */
1840 setup_arbitrary_frame (argc
, argv
)
1845 error ("MIPS frame specifications require two arguments: sp and pc");
1847 return create_new_frame (argv
[0], argv
[1]);
1851 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1853 * For n32 ABI, eight.
1854 * For all others, he same as the size of a general register.
1856 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1857 #define MIPS_NABI32 1
1858 #define STACK_ARGSIZE 8
1860 #define MIPS_NABI32 0
1861 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1865 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1870 CORE_ADDR struct_addr
;
1876 int stack_offset
= 0;
1878 /* Macros to round N up or down to the next A boundary; A must be
1880 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1881 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1883 /* First ensure that the stack and structure return address (if any)
1884 are properly aligned. The stack has to be at least 64-bit aligned
1885 even on 32-bit machines, because doubles must be 64-bit aligned.
1886 On at least one MIPS variant, stack frames need to be 128-bit
1887 aligned, so we round to this widest known alignment. */
1888 sp
= ROUND_DOWN (sp
, 16);
1889 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
1891 /* Now make space on the stack for the args. We allocate more
1892 than necessary for EABI, because the first few arguments are
1893 passed in registers, but that's OK. */
1894 for (argnum
= 0; argnum
< nargs
; argnum
++)
1895 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
1896 sp
-= ROUND_UP (len
, 16);
1898 /* Initialize the integer and float register pointers. */
1900 float_argreg
= FPA0_REGNUM
;
1902 /* the struct_return pointer occupies the first parameter-passing reg */
1904 write_register (argreg
++, struct_addr
);
1906 /* Now load as many as possible of the first arguments into
1907 registers, and push the rest onto the stack. Loop thru args
1908 from first to last. */
1909 for (argnum
= 0; argnum
< nargs
; argnum
++)
1912 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1913 value_ptr arg
= args
[argnum
];
1914 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1915 int len
= TYPE_LENGTH (arg_type
);
1916 enum type_code typecode
= TYPE_CODE (arg_type
);
1918 /* The EABI passes structures that do not fit in a register by
1919 reference. In all other cases, pass the structure by value. */
1920 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
1921 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1923 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
1924 typecode
= TYPE_CODE_PTR
;
1925 len
= MIPS_SAVED_REGSIZE
;
1929 val
= (char *) VALUE_CONTENTS (arg
);
1931 /* 32-bit ABIs always start floating point arguments in an
1932 even-numbered floating point register. */
1933 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1934 && (float_argreg
& 1))
1937 /* Floating point arguments passed in registers have to be
1938 treated specially. On 32-bit architectures, doubles
1939 are passed in register pairs; the even register gets
1940 the low word, and the odd register gets the high word.
1941 On non-EABI processors, the first two floating point arguments are
1942 also copied to general registers, because MIPS16 functions
1943 don't use float registers for arguments. This duplication of
1944 arguments in general registers can't hurt non-MIPS16 functions
1945 because those registers are normally skipped. */
1946 if (typecode
== TYPE_CODE_FLT
1947 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1948 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
1950 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1952 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1953 unsigned long regval
;
1955 /* Write the low word of the double to the even register(s). */
1956 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
1957 write_register (float_argreg
++, regval
);
1959 write_register (argreg
+ 1, regval
);
1961 /* Write the high word of the double to the odd register(s). */
1962 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
1963 write_register (float_argreg
++, regval
);
1966 write_register (argreg
, regval
);
1973 /* This is a floating point value that fits entirely
1974 in a single register. */
1975 CORE_ADDR regval
= extract_address (val
, len
);
1976 write_register (float_argreg
++, regval
);
1979 write_register (argreg
, regval
);
1980 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1986 /* Copy the argument to general registers or the stack in
1987 register-sized pieces. Large arguments are split between
1988 registers and stack. */
1989 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1990 are treated specially: Irix cc passes them in registers
1991 where gcc sometimes puts them on the stack. For maximum
1992 compatibility, we will put them in both places. */
1994 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
1995 (len
% MIPS_SAVED_REGSIZE
!= 0));
1998 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2000 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2002 /* Write this portion of the argument to the stack. */
2003 /* Should shorter than int integer values be
2004 promoted to int before being stored? */
2006 int longword_offset
= 0;
2007 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2009 if (STACK_ARGSIZE
== 8 &&
2010 (typecode
== TYPE_CODE_INT
||
2011 typecode
== TYPE_CODE_PTR
||
2012 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2013 longword_offset
= STACK_ARGSIZE
- len
;
2014 else if ((typecode
== TYPE_CODE_STRUCT
||
2015 typecode
== TYPE_CODE_UNION
) &&
2016 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
2017 longword_offset
= STACK_ARGSIZE
- len
;
2020 write_memory (sp
+ stack_offset
+ longword_offset
,
2024 /* Note!!! This is NOT an else clause.
2025 Odd sized structs may go thru BOTH paths. */
2026 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2028 CORE_ADDR regval
= extract_address (val
, partial_len
);
2030 /* A non-floating-point argument being passed in a
2031 general register. If a struct or union, and if
2032 the remaining length is smaller than the register
2033 size, we have to adjust the register value on
2036 It does not seem to be necessary to do the
2037 same for integral types.
2039 Also don't do this adjustment on EABI and O64
2043 && MIPS_SAVED_REGSIZE
< 8
2044 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2045 && partial_len
< MIPS_SAVED_REGSIZE
2046 && (typecode
== TYPE_CODE_STRUCT
||
2047 typecode
== TYPE_CODE_UNION
))
2048 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2051 write_register (argreg
, regval
);
2054 /* If this is the old ABI, prevent subsequent floating
2055 point arguments from being passed in floating point
2058 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2064 /* The offset onto the stack at which we will start
2065 copying parameters (after the registers are used up)
2066 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2067 leaves room for the "home" area for register parameters.
2069 In the new EABI (and the NABI32), the 8 register parameters
2070 do not have "home" stack space reserved for them, so the
2071 stack offset does not get incremented until after
2072 we have used up the 8 parameter registers. */
2074 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2076 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2081 /* Return adjusted stack pointer. */
2086 mips_push_return_address (pc
, sp
)
2090 /* Set the return address register to point to the entry
2091 point of the program, where a breakpoint lies in wait. */
2092 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2097 mips_push_register (CORE_ADDR
* sp
, int regno
)
2099 char buffer
[MAX_REGISTER_RAW_SIZE
];
2102 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2104 regsize
= MIPS_SAVED_REGSIZE
;
2105 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2106 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2111 regsize
= REGISTER_RAW_SIZE (regno
);
2115 read_register_gen (regno
, buffer
);
2116 write_memory (*sp
, buffer
+ offset
, regsize
);
2119 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2120 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2123 mips_push_dummy_frame ()
2126 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2127 xmalloc (sizeof (struct linked_proc_info
));
2128 mips_extra_func_info_t proc_desc
= &link
->info
;
2129 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2130 CORE_ADDR old_sp
= sp
;
2131 link
->next
= linked_proc_desc_table
;
2132 linked_proc_desc_table
= link
;
2134 /* FIXME! are these correct ? */
2135 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2136 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2137 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2138 #define FLOAT_SINGLE_REG_SAVE_MASK \
2139 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2141 * The registers we must save are all those not preserved across
2142 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2143 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2144 * and FP Control/Status registers.
2147 * Dummy frame layout:
2150 * Saved MMHI, MMLO, FPC_CSR
2155 * Saved D18 (i.e. F19, F18)
2157 * Saved D0 (i.e. F1, F0)
2158 * Argument build area and stack arguments written via mips_push_arguments
2162 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2163 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2164 PROC_FRAME_OFFSET (proc_desc
) = 0;
2165 PROC_FRAME_ADJUST (proc_desc
) = 0;
2166 mips_push_register (&sp
, PC_REGNUM
);
2167 mips_push_register (&sp
, HI_REGNUM
);
2168 mips_push_register (&sp
, LO_REGNUM
);
2169 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2171 /* Save general CPU registers */
2172 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2173 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2174 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2175 for (ireg
= 32; --ireg
>= 0;)
2176 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2177 mips_push_register (&sp
, ireg
);
2179 /* Save floating point registers starting with high order word */
2180 PROC_FREG_MASK (proc_desc
) =
2181 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2182 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2183 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2185 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2186 for (ireg
= 32; --ireg
>= 0;)
2187 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2188 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2190 /* Update the frame pointer for the call dummy and the stack pointer.
2191 Set the procedure's starting and ending addresses to point to the
2192 call dummy address at the entry point. */
2193 write_register (PUSH_FP_REGNUM
, old_sp
);
2194 write_register (SP_REGNUM
, sp
);
2195 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2196 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2197 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2198 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2204 register int regnum
;
2205 struct frame_info
*frame
= get_current_frame ();
2206 CORE_ADDR new_sp
= FRAME_FP (frame
);
2208 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2210 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2211 if (frame
->saved_regs
== NULL
)
2212 mips_find_saved_regs (frame
);
2213 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2215 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2216 && frame
->saved_regs
[regnum
])
2217 write_register (regnum
,
2218 read_memory_integer (frame
->saved_regs
[regnum
],
2219 MIPS_SAVED_REGSIZE
));
2221 write_register (SP_REGNUM
, new_sp
);
2222 flush_cached_frames ();
2224 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2226 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2228 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2230 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2232 if (&pi_ptr
->info
== proc_desc
)
2237 error ("Can't locate dummy extra frame info\n");
2239 if (prev_ptr
!= NULL
)
2240 prev_ptr
->next
= pi_ptr
->next
;
2242 linked_proc_desc_table
= pi_ptr
->next
;
2246 write_register (HI_REGNUM
,
2247 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2248 MIPS_SAVED_REGSIZE
));
2249 write_register (LO_REGNUM
,
2250 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2251 MIPS_SAVED_REGSIZE
));
2252 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2253 write_register (FCRCS_REGNUM
,
2254 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2255 MIPS_SAVED_REGSIZE
));
2260 mips_print_register (regnum
, all
)
2263 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2265 /* Get the data in raw format. */
2266 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2268 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2272 /* If an even floating point register, also print as double. */
2273 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2274 && !((regnum
- FP0_REGNUM
) & 1))
2275 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2277 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2279 read_relative_register_raw_bytes (regnum
, dbuffer
);
2280 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2281 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2283 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2284 val_print (builtin_type_double
, dbuffer
, 0, 0,
2285 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2286 printf_filtered ("); ");
2288 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2290 /* The problem with printing numeric register names (r26, etc.) is that
2291 the user can't use them on input. Probably the best solution is to
2292 fix it so that either the numeric or the funky (a2, etc.) names
2293 are accepted on input. */
2294 if (regnum
< MIPS_NUMREGS
)
2295 printf_filtered ("(r%d): ", regnum
);
2297 printf_filtered (": ");
2299 /* If virtual format is floating, print it that way. */
2300 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2301 if (FP_REGISTER_DOUBLE
)
2302 { /* show 8-byte floats as float AND double: */
2303 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2305 printf_filtered (" (float) ");
2306 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2307 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2308 printf_filtered (", (double) ");
2309 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2310 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2313 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2314 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2315 /* Else print as integer in hex. */
2317 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2318 'x', 0, gdb_stdout
);
2321 /* Replacement for generic do_registers_info.
2322 Print regs in pretty columns. */
2325 do_fp_register_row (regnum
)
2327 { /* do values for FP (float) regs */
2328 char *raw_buffer
[2];
2330 /* use HI and LO to control the order of combining two flt regs */
2331 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2332 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2333 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2334 int inv1
, inv2
, inv3
;
2336 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2337 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2338 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2340 /* Get the data in raw format. */
2341 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2342 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2343 if (REGISTER_RAW_SIZE (regnum
) == 4)
2345 /* 4-byte registers: we can fit two registers per row. */
2346 /* Also print every pair of 4-byte regs as an 8-byte double. */
2347 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2348 error ("can't read register %d (%s)",
2349 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2351 /* copy the two floats into one double, and unpack both */
2352 memcpy (dbl_buffer
, raw_buffer
, sizeof (dbl_buffer
));
2353 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2354 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2355 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2357 printf_filtered (inv1
? " %-5s: <invalid float>" :
2358 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2359 printf_filtered (inv2
? " %-5s: <invalid float>" :
2360 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2361 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2362 " dbl: %-24.17g\n", doub
);
2363 /* may want to do hex display here (future enhancement) */
2367 { /* eight byte registers: print each one as float AND as double. */
2368 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2370 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof (dbl_buffer
));
2371 flt1
= unpack_double (builtin_type_float
,
2372 &raw_buffer
[HI
][offset
], &inv1
);
2373 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2375 printf_filtered (inv1
? " %-5s: <invalid float>" :
2376 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2377 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2378 " dbl: %-24.17g\n", doub
);
2379 /* may want to do hex display here (future enhancement) */
2385 /* Print a row's worth of GP (int) registers, with name labels above */
2388 do_gp_register_row (regnum
)
2391 /* do values for GP (int) regs */
2392 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2393 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2395 int start_regnum
= regnum
;
2396 int numregs
= NUM_REGS
;
2399 /* For GP registers, we print a separate row of names above the vals */
2400 printf_filtered (" ");
2401 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2403 if (*REGISTER_NAME (regnum
) == '\0')
2404 continue; /* unused register */
2405 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2406 break; /* end the row: reached FP register */
2407 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2408 REGISTER_NAME (regnum
));
2411 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2412 start_regnum
); /* print the R0 to R31 names */
2414 regnum
= start_regnum
; /* go back to start of row */
2415 /* now print the values in hex, 4 or 8 to the row */
2416 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2418 if (*REGISTER_NAME (regnum
) == '\0')
2419 continue; /* unused register */
2420 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2421 break; /* end row: reached FP register */
2422 /* OK: get the data in raw format. */
2423 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2424 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2425 /* pad small registers */
2426 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2427 printf_filtered (" ");
2428 /* Now print the register value in hex, endian order. */
2429 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2430 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2431 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2433 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2434 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2435 printf_filtered (" ");
2438 if (col
> 0) /* ie. if we actually printed anything... */
2439 printf_filtered ("\n");
2444 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2447 mips_do_registers_info (regnum
, fpregs
)
2451 if (regnum
!= -1) /* do one specified register */
2453 if (*(REGISTER_NAME (regnum
)) == '\0')
2454 error ("Not a valid register for the current processor type");
2456 mips_print_register (regnum
, 0);
2457 printf_filtered ("\n");
2460 /* do all (or most) registers */
2463 while (regnum
< NUM_REGS
)
2465 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2466 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2467 regnum
= do_fp_register_row (regnum
); /* FP regs */
2469 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2471 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2476 /* Return number of args passed to a frame. described by FIP.
2477 Can return -1, meaning no way to tell. */
2480 mips_frame_num_args (frame
)
2481 struct frame_info
*frame
;
2483 #if 0 /* FIXME Use or lose this! */
2484 struct chain_info_t
*p
;
2486 p
= mips_find_cached_frame (FRAME_FP (frame
));
2488 return p
->the_info
.numargs
;
2493 /* Is this a branch with a delay slot? */
2495 static int is_delayed
PARAMS ((unsigned long));
2502 for (i
= 0; i
< NUMOPCODES
; ++i
)
2503 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2504 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2506 return (i
< NUMOPCODES
2507 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2508 | INSN_COND_BRANCH_DELAY
2509 | INSN_COND_BRANCH_LIKELY
)));
2513 mips_step_skips_delay (pc
)
2516 char buf
[MIPS_INSTLEN
];
2518 /* There is no branch delay slot on MIPS16. */
2519 if (pc_is_mips16 (pc
))
2522 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2523 /* If error reading memory, guess that it is not a delayed branch. */
2525 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2529 /* Skip the PC past function prologue instructions (32-bit version).
2530 This is a helper function for mips_skip_prologue. */
2533 mips32_skip_prologue (pc
, lenient
)
2534 CORE_ADDR pc
; /* starting PC to search from */
2539 int seen_sp_adjust
= 0;
2540 int load_immediate_bytes
= 0;
2542 /* Skip the typical prologue instructions. These are the stack adjustment
2543 instruction and the instructions that save registers on the stack
2544 or in the gcc frame. */
2545 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2547 unsigned long high_word
;
2549 inst
= mips_fetch_instruction (pc
);
2550 high_word
= (inst
>> 16) & 0xffff;
2553 if (lenient
&& is_delayed (inst
))
2557 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2558 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2560 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2561 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2563 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2564 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2565 && (inst
& 0x001F0000)) /* reg != $zero */
2568 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2570 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2572 continue; /* reg != $zero */
2574 /* move $s8,$sp. With different versions of gas this will be either
2575 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2576 Accept any one of these. */
2577 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2580 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2582 else if (high_word
== 0x3c1c) /* lui $gp,n */
2584 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2586 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2587 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2589 /* The following instructions load $at or $t0 with an immediate
2590 value in preparation for a stack adjustment via
2591 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2592 a local variable, so we accept them only before a stack adjustment
2593 instruction was seen. */
2594 else if (!seen_sp_adjust
)
2596 if (high_word
== 0x3c01 || /* lui $at,n */
2597 high_word
== 0x3c08) /* lui $t0,n */
2599 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2602 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2603 high_word
== 0x3508 || /* ori $t0,$t0,n */
2604 high_word
== 0x3401 || /* ori $at,$zero,n */
2605 high_word
== 0x3408) /* ori $t0,$zero,n */
2607 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2617 /* In a frameless function, we might have incorrectly
2618 skipped some load immediate instructions. Undo the skipping
2619 if the load immediate was not followed by a stack adjustment. */
2620 if (load_immediate_bytes
&& !seen_sp_adjust
)
2621 pc
-= load_immediate_bytes
;
2625 /* Skip the PC past function prologue instructions (16-bit version).
2626 This is a helper function for mips_skip_prologue. */
2629 mips16_skip_prologue (pc
, lenient
)
2630 CORE_ADDR pc
; /* starting PC to search from */
2634 int extend_bytes
= 0;
2635 int prev_extend_bytes
;
2637 /* Table of instructions likely to be found in a function prologue. */
2640 unsigned short inst
;
2641 unsigned short mask
;
2648 , /* addiu $sp,offset */
2652 , /* daddiu $sp,offset */
2656 , /* sw reg,n($sp) */
2660 , /* sd reg,n($sp) */
2664 , /* sw $ra,n($sp) */
2668 , /* sd $ra,n($sp) */
2676 , /* sw $a0-$a3,n($s1) */
2680 , /* move reg,$a0-$a3 */
2684 , /* entry pseudo-op */
2688 , /* addiu $s1,$sp,n */
2691 } /* end of table marker */
2694 /* Skip the typical prologue instructions. These are the stack adjustment
2695 instruction and the instructions that save registers on the stack
2696 or in the gcc frame. */
2697 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2699 unsigned short inst
;
2702 inst
= mips_fetch_instruction (pc
);
2704 /* Normally we ignore an extend instruction. However, if it is
2705 not followed by a valid prologue instruction, we must adjust
2706 the pc back over the extend so that it won't be considered
2707 part of the prologue. */
2708 if ((inst
& 0xf800) == 0xf000) /* extend */
2710 extend_bytes
= MIPS16_INSTLEN
;
2713 prev_extend_bytes
= extend_bytes
;
2716 /* Check for other valid prologue instructions besides extend. */
2717 for (i
= 0; table
[i
].mask
!= 0; i
++)
2718 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2720 if (table
[i
].mask
!= 0) /* it was in table? */
2721 continue; /* ignore it */
2725 /* Return the current pc, adjusted backwards by 2 if
2726 the previous instruction was an extend. */
2727 return pc
- prev_extend_bytes
;
2733 /* To skip prologues, I use this predicate. Returns either PC itself
2734 if the code at PC does not look like a function prologue; otherwise
2735 returns an address that (if we're lucky) follows the prologue. If
2736 LENIENT, then we must skip everything which is involved in setting
2737 up the frame (it's OK to skip more, just so long as we don't skip
2738 anything which might clobber the registers which are being saved.
2739 We must skip more in the case where part of the prologue is in the
2740 delay slot of a non-prologue instruction). */
2743 mips_skip_prologue (pc
, lenient
)
2747 /* See if we can determine the end of the prologue via the symbol table.
2748 If so, then return either PC, or the PC after the prologue, whichever
2751 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2753 if (post_prologue_pc
!= 0)
2754 return max (pc
, post_prologue_pc
);
2756 /* Can't determine prologue from the symbol table, need to examine
2759 if (pc_is_mips16 (pc
))
2760 return mips16_skip_prologue (pc
, lenient
);
2762 return mips32_skip_prologue (pc
, lenient
);
2766 /* The lenient prologue stuff should be superseded by the code in
2767 init_extra_frame_info which looks to see whether the stores mentioned
2768 in the proc_desc have actually taken place. */
2770 /* Is address PC in the prologue (loosely defined) for function at
2774 mips_in_lenient_prologue (startaddr
, pc
)
2775 CORE_ADDR startaddr
;
2778 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2779 return pc
>= startaddr
&& pc
< end_prologue
;
2783 /* Determine how a return value is stored within the MIPS register
2784 file, given the return type `valtype'. */
2786 struct return_value_word
2794 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2797 return_value_location (valtype
, hi
, lo
)
2798 struct type
*valtype
;
2799 struct return_value_word
*hi
;
2800 struct return_value_word
*lo
;
2802 int len
= TYPE_LENGTH (valtype
);
2804 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2805 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2806 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2808 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2810 /* We need to break a 64bit float in two 32 bit halves and
2811 spread them across a floating-point register pair. */
2812 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2813 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2814 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2815 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2817 hi
->reg_offset
= lo
->reg_offset
;
2818 lo
->reg
= FP0_REGNUM
+ 0;
2819 hi
->reg
= FP0_REGNUM
+ 1;
2825 /* The floating point value fits in a single floating-point
2827 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2828 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2831 lo
->reg
= FP0_REGNUM
;
2842 /* Locate a result possibly spread across two registers. */
2844 lo
->reg
= regnum
+ 0;
2845 hi
->reg
= regnum
+ 1;
2846 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2847 && len
< MIPS_SAVED_REGSIZE
)
2849 /* "un-left-justify" the value in the low register */
2850 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2855 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2856 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2857 && len
< MIPS_SAVED_REGSIZE
* 2
2858 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2859 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2861 /* "un-left-justify" the value spread across two registers. */
2862 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2863 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2865 hi
->len
= len
- lo
->len
;
2869 /* Only perform a partial copy of the second register. */
2872 if (len
> MIPS_SAVED_REGSIZE
)
2874 lo
->len
= MIPS_SAVED_REGSIZE
;
2875 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
2883 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2884 && REGISTER_RAW_SIZE (regnum
) == 8
2885 && MIPS_SAVED_REGSIZE
== 4)
2887 /* Account for the fact that only the least-signficant part
2888 of the register is being used */
2889 lo
->reg_offset
+= 4;
2890 hi
->reg_offset
+= 4;
2893 hi
->buf_offset
= lo
->len
;
2897 /* Given a return value in `regbuf' with a type `valtype', extract and
2898 copy its value into `valbuf'. */
2901 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2902 struct type
*valtype
;
2903 char regbuf
[REGISTER_BYTES
];
2906 struct return_value_word lo
;
2907 struct return_value_word hi
;
2908 return_value_location (valtype
, &lo
, &hi
);
2910 memcpy (valbuf
+ lo
.buf_offset
,
2911 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
2915 memcpy (valbuf
+ hi
.buf_offset
,
2916 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
2922 int len
= TYPE_LENGTH (valtype
);
2925 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2926 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2927 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2928 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2929 regnum
= FP0_REGNUM
;
2931 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2932 { /* "un-left-justify" the value from the register */
2933 if (len
< REGISTER_RAW_SIZE (regnum
))
2934 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2935 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2936 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2937 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2938 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2939 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2941 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2942 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2946 /* Given a return value in `valbuf' with a type `valtype', write it's
2947 value into the appropriate register. */
2950 mips_store_return_value (valtype
, valbuf
)
2951 struct type
*valtype
;
2954 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2955 struct return_value_word lo
;
2956 struct return_value_word hi
;
2957 return_value_location (valtype
, &lo
, &hi
);
2959 memset (raw_buffer
, 0, sizeof (raw_buffer
));
2960 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
2961 write_register_bytes (REGISTER_BYTE (lo
.reg
),
2963 REGISTER_RAW_SIZE (lo
.reg
));
2967 memset (raw_buffer
, 0, sizeof (raw_buffer
));
2968 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
2969 write_register_bytes (REGISTER_BYTE (hi
.reg
),
2971 REGISTER_RAW_SIZE (hi
.reg
));
2977 int len
= TYPE_LENGTH (valtype
);
2978 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2981 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2982 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2983 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2984 && len
<= MIPS_REGSIZE
)))
2985 regnum
= FP0_REGNUM
;
2987 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2988 { /* "left-justify" the value in the register */
2989 if (len
< REGISTER_RAW_SIZE (regnum
))
2990 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2991 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2992 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2993 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2994 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2995 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2997 memcpy (raw_buffer
+ offset
, valbuf
, len
);
2998 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
2999 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3000 len
> REGISTER_RAW_SIZE (regnum
) ?
3001 len
: REGISTER_RAW_SIZE (regnum
));
3005 /* Exported procedure: Is PC in the signal trampoline code */
3008 in_sigtramp (pc
, ignore
)
3010 char *ignore
; /* function name */
3012 if (sigtramp_address
== 0)
3014 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3017 /* Commands to show/set the MIPS FPU type. */
3019 static void show_mipsfpu_command
PARAMS ((char *, int));
3021 show_mipsfpu_command (args
, from_tty
)
3027 switch (MIPS_FPU_TYPE
)
3029 case MIPS_FPU_SINGLE
:
3030 fpu
= "single-precision";
3032 case MIPS_FPU_DOUBLE
:
3033 fpu
= "double-precision";
3036 fpu
= "absent (none)";
3039 if (mips_fpu_type_auto
)
3040 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3043 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3048 static void set_mipsfpu_command
PARAMS ((char *, int));
3050 set_mipsfpu_command (args
, from_tty
)
3054 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3055 show_mipsfpu_command (args
, from_tty
);
3058 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3060 set_mipsfpu_single_command (args
, from_tty
)
3064 mips_fpu_type
= MIPS_FPU_SINGLE
;
3065 mips_fpu_type_auto
= 0;
3068 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3070 set_mipsfpu_double_command (args
, from_tty
)
3074 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3075 mips_fpu_type_auto
= 0;
3078 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3080 set_mipsfpu_none_command (args
, from_tty
)
3084 mips_fpu_type
= MIPS_FPU_NONE
;
3085 mips_fpu_type_auto
= 0;
3088 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3090 set_mipsfpu_auto_command (args
, from_tty
)
3094 mips_fpu_type_auto
= 1;
3097 /* Command to set the processor type. */
3100 mips_set_processor_type_command (args
, from_tty
)
3106 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3108 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3109 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3110 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3112 /* Restore the value. */
3113 tmp_mips_processor_type
= strsave (mips_processor_type
);
3118 if (!mips_set_processor_type (tmp_mips_processor_type
))
3120 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3121 /* Restore its value. */
3122 tmp_mips_processor_type
= strsave (mips_processor_type
);
3127 mips_show_processor_type_command (args
, from_tty
)
3133 /* Modify the actual processor type. */
3136 mips_set_processor_type (str
)
3144 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3146 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3148 mips_processor_type
= str
;
3149 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3151 /* FIXME tweak fpu flag too */
3158 /* Attempt to identify the particular processor model by reading the
3162 mips_read_processor_type ()
3166 prid
= read_register (PRID_REGNUM
);
3168 if ((prid
& ~0xf) == 0x700)
3169 return savestring ("r3041", strlen ("r3041"));
3174 /* Just like reinit_frame_cache, but with the right arguments to be
3175 callable as an sfunc. */
3178 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3181 struct cmd_list_element
*c
;
3183 reinit_frame_cache ();
3187 gdb_print_insn_mips (memaddr
, info
)
3189 disassemble_info
*info
;
3191 mips_extra_func_info_t proc_desc
;
3193 /* Search for the function containing this address. Set the low bit
3194 of the address when searching, in case we were given an even address
3195 that is the start of a 16-bit function. If we didn't do this,
3196 the search would fail because the symbol table says the function
3197 starts at an odd address, i.e. 1 byte past the given address. */
3198 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3199 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3201 /* Make an attempt to determine if this is a 16-bit function. If
3202 the procedure descriptor exists and the address therein is odd,
3203 it's definitely a 16-bit function. Otherwise, we have to just
3204 guess that if the address passed in is odd, it's 16-bits. */
3206 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3208 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3210 /* Round down the instruction address to the appropriate boundary. */
3211 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3213 /* Call the appropriate disassembler based on the target endian-ness. */
3214 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3215 return print_insn_big_mips (memaddr
, info
);
3217 return print_insn_little_mips (memaddr
, info
);
3220 /* Old-style breakpoint macros.
3221 The IDT board uses an unusual breakpoint value, and sometimes gets
3222 confused when it sees the usual MIPS breakpoint instruction. */
3224 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3225 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3226 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3227 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3228 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3229 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3230 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3231 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3233 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3234 counter value to determine whether a 16- or 32-bit breakpoint should be
3235 used. It returns a pointer to a string of bytes that encode a breakpoint
3236 instruction, stores the length of the string to *lenptr, and adjusts pc
3237 (if necessary) to point to the actual memory location where the
3238 breakpoint should be inserted. */
3241 mips_breakpoint_from_pc (pcptr
, lenptr
)
3245 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3247 if (pc_is_mips16 (*pcptr
))
3249 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3250 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3251 *lenptr
= sizeof (mips16_big_breakpoint
);
3252 return mips16_big_breakpoint
;
3256 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3257 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3258 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3260 *lenptr
= sizeof (big_breakpoint
);
3262 if (strcmp (target_shortname
, "mips") == 0)
3263 return idt_big_breakpoint
;
3264 else if (strcmp (target_shortname
, "ddb") == 0
3265 || strcmp (target_shortname
, "pmon") == 0
3266 || strcmp (target_shortname
, "lsi") == 0)
3267 return pmon_big_breakpoint
;
3269 return big_breakpoint
;
3274 if (pc_is_mips16 (*pcptr
))
3276 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3277 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3278 *lenptr
= sizeof (mips16_little_breakpoint
);
3279 return mips16_little_breakpoint
;
3283 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3284 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3285 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3287 *lenptr
= sizeof (little_breakpoint
);
3289 if (strcmp (target_shortname
, "mips") == 0)
3290 return idt_little_breakpoint
;
3291 else if (strcmp (target_shortname
, "ddb") == 0
3292 || strcmp (target_shortname
, "pmon") == 0
3293 || strcmp (target_shortname
, "lsi") == 0)
3294 return pmon_little_breakpoint
;
3296 return little_breakpoint
;
3301 /* If PC is in a mips16 call or return stub, return the address of the target
3302 PC, which is either the callee or the caller. There are several
3303 cases which must be handled:
3305 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3306 target PC is in $31 ($ra).
3307 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3308 and the target PC is in $2.
3309 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3310 before the jal instruction, this is effectively a call stub
3311 and the the target PC is in $2. Otherwise this is effectively
3312 a return stub and the target PC is in $18.
3314 See the source code for the stubs in gcc/config/mips/mips16.S for
3317 This function implements the SKIP_TRAMPOLINE_CODE macro.
3325 CORE_ADDR start_addr
;
3327 /* Find the starting address and name of the function containing the PC. */
3328 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3331 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3332 target PC is in $31 ($ra). */
3333 if (strcmp (name
, "__mips16_ret_sf") == 0
3334 || strcmp (name
, "__mips16_ret_df") == 0)
3335 return read_register (RA_REGNUM
);
3337 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3339 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3340 and the target PC is in $2. */
3341 if (name
[19] >= '0' && name
[19] <= '9')
3342 return read_register (2);
3344 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3345 before the jal instruction, this is effectively a call stub
3346 and the the target PC is in $2. Otherwise this is effectively
3347 a return stub and the target PC is in $18. */
3348 else if (name
[19] == 's' || name
[19] == 'd')
3350 if (pc
== start_addr
)
3352 /* Check if the target of the stub is a compiler-generated
3353 stub. Such a stub for a function bar might have a name
3354 like __fn_stub_bar, and might look like this:
3359 la $1,bar (becomes a lui/addiu pair)
3361 So scan down to the lui/addi and extract the target
3362 address from those two instructions. */
3364 CORE_ADDR target_pc
= read_register (2);
3368 /* See if the name of the target function is __fn_stub_*. */
3369 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3371 if (strncmp (name
, "__fn_stub_", 10) != 0
3372 && strcmp (name
, "etext") != 0
3373 && strcmp (name
, "_etext") != 0)
3376 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3377 The limit on the search is arbitrarily set to 20
3378 instructions. FIXME. */
3379 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3381 inst
= mips_fetch_instruction (target_pc
);
3382 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3383 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3384 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3385 return pc
| (inst
& 0xffff); /* low word */
3388 /* Couldn't find the lui/addui pair, so return stub address. */
3392 /* This is the 'return' part of a call stub. The return
3393 address is in $r18. */
3394 return read_register (18);
3397 return 0; /* not a stub */
3401 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3402 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3405 mips_in_call_stub (pc
, name
)
3409 CORE_ADDR start_addr
;
3411 /* Find the starting address of the function containing the PC. If the
3412 caller didn't give us a name, look it up at the same time. */
3413 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3416 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3418 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3419 if (name
[19] >= '0' && name
[19] <= '9')
3421 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3422 before the jal instruction, this is effectively a call stub. */
3423 else if (name
[19] == 's' || name
[19] == 'd')
3424 return pc
== start_addr
;
3427 return 0; /* not a stub */
3431 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3432 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3435 mips_in_return_stub (pc
, name
)
3439 CORE_ADDR start_addr
;
3441 /* Find the starting address of the function containing the PC. */
3442 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3445 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3446 if (strcmp (name
, "__mips16_ret_sf") == 0
3447 || strcmp (name
, "__mips16_ret_df") == 0)
3450 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3451 i.e. after the jal instruction, this is effectively a return stub. */
3452 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3453 && (name
[19] == 's' || name
[19] == 'd')
3454 && pc
!= start_addr
)
3457 return 0; /* not a stub */
3461 /* Return non-zero if the PC is in a library helper function that should
3462 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3465 mips_ignore_helper (pc
)
3470 /* Find the starting address and name of the function containing the PC. */
3471 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3474 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3475 that we want to ignore. */
3476 return (strcmp (name
, "__mips16_ret_sf") == 0
3477 || strcmp (name
, "__mips16_ret_df") == 0);
3481 /* Return a location where we can set a breakpoint that will be hit
3482 when an inferior function call returns. This is normally the
3483 program's entry point. Executables that don't have an entry
3484 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3485 whose address is the location where the breakpoint should be placed. */
3488 mips_call_dummy_address ()
3490 struct minimal_symbol
*sym
;
3492 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3494 return SYMBOL_VALUE_ADDRESS (sym
);
3496 return entry_point_address ();
3501 _initialize_mips_tdep ()
3503 static struct cmd_list_element
*mipsfpulist
= NULL
;
3504 struct cmd_list_element
*c
;
3506 if (!tm_print_insn
) /* Someone may have already set it */
3507 tm_print_insn
= gdb_print_insn_mips
;
3509 /* Let the user turn off floating point and set the fence post for
3510 heuristic_proc_start. */
3512 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3513 "Set use of MIPS floating-point coprocessor.",
3514 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3515 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3516 "Select single-precision MIPS floating-point coprocessor.",
3518 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3519 "Select double-precision MIPS floating-point coprocessor .",
3521 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3522 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3523 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3524 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3525 "Select no MIPS floating-point coprocessor.",
3527 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3528 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3529 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3530 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3531 "Select MIPS floating-point coprocessor automatically.",
3533 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3534 "Show current use of MIPS floating-point coprocessor target.",
3537 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3538 (char *) &tmp_mips_processor_type
,
3539 "Set the type of MIPS processor in use.\n\
3540 Set this to be able to access processor-type-specific registers.\n\
3543 c
->function
.cfunc
= mips_set_processor_type_command
;
3544 c
= add_show_from_set (c
, &showlist
);
3545 c
->function
.cfunc
= mips_show_processor_type_command
;
3547 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3548 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3550 /* We really would like to have both "0" and "unlimited" work, but
3551 command.c doesn't deal with that. So make it a var_zinteger
3552 because the user can always use "999999" or some such for unlimited. */
3553 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3554 (char *) &heuristic_fence_post
,
3556 Set the distance searched for the start of a function.\n\
3557 If you are debugging a stripped executable, GDB needs to search through the\n\
3558 program for the start of a function. This command sets the distance of the\n\
3559 search. The only need to set it is when debugging a stripped executable.",
3561 /* We need to throw away the frame cache when we set this, since it
3562 might change our ability to get backtraces. */
3563 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3564 add_show_from_set (c
, &showlist
);
3566 /* Allow the user to control whether the upper bits of 64-bit
3567 addresses should be zeroed. */
3569 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
3570 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3571 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3572 Without an argument, zeroing of upper address bits is enabled.", &setlist
),