1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2020 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->regnum
;
234 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
236 return mips_regnum (gdbarch
)->fp0
+ 12;
239 /* Return 1 if REGNUM refers to a floating-point general register, raw
240 or cooked. Otherwise return 0. */
243 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
245 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
247 return (rawnum
>= mips_regnum (gdbarch
)->fp0
248 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
251 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
253 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
255 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
256 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
258 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
259 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
261 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
263 /* Return the MIPS ABI associated with GDBARCH. */
265 mips_abi (struct gdbarch
*gdbarch
)
267 return gdbarch_tdep (gdbarch
)->mips_abi
;
271 mips_isa_regsize (struct gdbarch
*gdbarch
)
273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 /* If we know how big the registers are, use that size. */
276 if (tdep
->register_size_valid_p
)
277 return tdep
->register_size
;
279 /* Fall back to the previous behavior. */
280 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
281 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
284 /* Max saved register size. */
285 #define MAX_MIPS_ABI_REGSIZE 8
287 /* Return the currently configured (or set) saved register size. */
290 mips_abi_regsize (struct gdbarch
*gdbarch
)
292 switch (mips_abi (gdbarch
))
294 case MIPS_ABI_EABI32
:
300 case MIPS_ABI_EABI64
:
302 case MIPS_ABI_UNKNOWN
:
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
309 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
310 are some functions to handle addresses associated with compressed
311 code including but not limited to testing, setting, or clearing
312 bit 0 of such addresses. */
314 /* Return one iff compressed code is the MIPS16 instruction set. */
317 is_mips16_isa (struct gdbarch
*gdbarch
)
319 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
322 /* Return one iff compressed code is the microMIPS instruction set. */
325 is_micromips_isa (struct gdbarch
*gdbarch
)
327 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
330 /* Return one iff ADDR denotes compressed code. */
333 is_compact_addr (CORE_ADDR addr
)
338 /* Return one iff ADDR denotes standard ISA code. */
341 is_mips_addr (CORE_ADDR addr
)
343 return !is_compact_addr (addr
);
346 /* Return one iff ADDR denotes MIPS16 code. */
349 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
351 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
354 /* Return one iff ADDR denotes microMIPS code. */
357 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
359 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
362 /* Strip the ISA (compression) bit off from ADDR. */
365 unmake_compact_addr (CORE_ADDR addr
)
367 return ((addr
) & ~(CORE_ADDR
) 1);
370 /* Add the ISA (compression) bit to ADDR. */
373 make_compact_addr (CORE_ADDR addr
)
375 return ((addr
) | (CORE_ADDR
) 1);
378 /* Extern version of unmake_compact_addr; we use a separate function
379 so that unmake_compact_addr can be inlined throughout this file. */
382 mips_unmake_compact_addr (CORE_ADDR addr
)
384 return unmake_compact_addr (addr
);
387 /* Functions for setting and testing a bit in a minimal symbol that
388 marks it as MIPS16 or microMIPS function. The MSB of the minimal
389 symbol's "info" field is used for this purpose.
391 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
392 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
393 one of the "special" bits in a minimal symbol to mark it accordingly.
394 The test checks an ELF-private flag that is valid for true function
395 symbols only; for synthetic symbols such as for PLT stubs that have
396 no ELF-private part at all the MIPS BFD backend arranges for this
397 information to be carried in the asymbol's udata field instead.
399 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
400 in a minimal symbol. */
403 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
405 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
406 unsigned char st_other
;
408 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
409 st_other
= elfsym
->internal_elf_sym
.st_other
;
410 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
411 st_other
= sym
->udata
.i
;
415 if (ELF_ST_IS_MICROMIPS (st_other
))
417 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
418 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
420 else if (ELF_ST_IS_MIPS16 (st_other
))
422 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
423 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
427 /* Return one iff MSYM refers to standard ISA code. */
430 msymbol_is_mips (struct minimal_symbol
*msym
)
432 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
433 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
436 /* Return one iff MSYM refers to MIPS16 code. */
439 msymbol_is_mips16 (struct minimal_symbol
*msym
)
441 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 /* Return one iff MSYM refers to microMIPS code. */
447 msymbol_is_micromips (struct minimal_symbol
*msym
)
449 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
452 /* Set the ISA bit in the main symbol too, complementing the corresponding
453 minimal symbol setting and reflecting the run-time value of the symbol.
454 The need for comes from the ISA bit having been cleared as code in
455 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
456 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
457 of symbols referring to compressed code different in GDB to the values
458 used by actual code. That in turn makes them evaluate incorrectly in
459 expressions, producing results different to what the same expressions
460 yield when compiled into the program being debugged. */
463 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
465 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
467 /* We are in symbol reading so it is OK to cast away constness. */
468 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
469 CORE_ADDR compact_block_start
;
470 struct bound_minimal_symbol msym
;
472 compact_block_start
= BLOCK_START (block
) | 1;
473 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
474 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
476 BLOCK_START (block
) = compact_block_start
;
481 /* XFER a value from the big/little/left end of the register.
482 Depending on the size of the value it might occupy the entire
483 register or just part of it. Make an allowance for this, aligning
484 things accordingly. */
487 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
488 int reg_num
, int length
,
489 enum bfd_endian endian
, gdb_byte
*in
,
490 const gdb_byte
*out
, int buf_offset
)
494 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
495 /* Need to transfer the left or right part of the register, based on
496 the targets byte order. */
500 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
502 case BFD_ENDIAN_LITTLE
:
505 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
509 internal_error (__FILE__
, __LINE__
, _("bad switch"));
512 fprintf_unfiltered (gdb_stderr
,
513 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
514 reg_num
, reg_offset
, buf_offset
, length
);
515 if (mips_debug
&& out
!= NULL
)
518 fprintf_unfiltered (gdb_stdlog
, "out ");
519 for (i
= 0; i
< length
; i
++)
520 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
523 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
525 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
526 if (mips_debug
&& in
!= NULL
)
529 fprintf_unfiltered (gdb_stdlog
, "in ");
530 for (i
= 0; i
< length
; i
++)
531 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
534 fprintf_unfiltered (gdb_stdlog
, "\n");
537 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
538 compatiblity mode. A return value of 1 means that we have
539 physical 64-bit registers, but should treat them as 32-bit registers. */
542 mips2_fp_compat (struct frame_info
*frame
)
544 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
545 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
547 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
551 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
552 in all the places we deal with FP registers. PR gdb/413. */
553 /* Otherwise check the FR bit in the status register - it controls
554 the FP compatiblity mode. If it is clear we are in compatibility
556 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
563 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
565 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
567 /* The list of available "set mips " and "show mips " commands. */
569 static struct cmd_list_element
*setmipscmdlist
= NULL
;
570 static struct cmd_list_element
*showmipscmdlist
= NULL
;
572 /* Integer registers 0 thru 31 are handled explicitly by
573 mips_register_name(). Processor specific registers 32 and above
574 are listed in the following tables. */
577 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
581 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
582 "sr", "lo", "hi", "bad", "cause", "pc",
583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
590 /* Names of tx39 registers. */
592 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
593 "sr", "lo", "hi", "bad", "cause", "pc",
594 "", "", "", "", "", "", "", "",
595 "", "", "", "", "", "", "", "",
596 "", "", "", "", "", "", "", "",
597 "", "", "", "", "", "", "", "",
599 "", "", "", "", "", "", "", "",
600 "", "", "config", "cache", "debug", "depc", "epc",
603 /* Names of registers with Linux kernels. */
604 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
605 "sr", "lo", "hi", "bad", "cause", "pc",
606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
614 /* Return the name of the register corresponding to REGNO. */
616 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
618 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
619 /* GPR names for all ABIs other than n32/n64. */
620 static const char *mips_gpr_names
[] = {
621 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
622 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
623 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
624 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
627 /* GPR names for n32 and n64 ABIs. */
628 static const char *mips_n32_n64_gpr_names
[] = {
629 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
630 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
631 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
632 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
635 enum mips_abi abi
= mips_abi (gdbarch
);
637 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
638 but then don't make the raw register names visible. This (upper)
639 range of user visible register numbers are the pseudo-registers.
641 This approach was adopted accommodate the following scenario:
642 It is possible to debug a 64-bit device using a 32-bit
643 programming model. In such instances, the raw registers are
644 configured to be 64-bits wide, while the pseudo registers are
645 configured to be 32-bits wide. The registers that the user
646 sees - the pseudo registers - match the users expectations
647 given the programming model being used. */
648 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
649 if (regno
< gdbarch_num_regs (gdbarch
))
652 /* The MIPS integer registers are always mapped from 0 to 31. The
653 names of the registers (which reflects the conventions regarding
654 register use) vary depending on the ABI. */
655 if (0 <= rawnum
&& rawnum
< 32)
657 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
658 return mips_n32_n64_gpr_names
[rawnum
];
660 return mips_gpr_names
[rawnum
];
662 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
663 return tdesc_register_name (gdbarch
, rawnum
);
664 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
666 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
667 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
668 return tdep
->mips_processor_reg_names
[rawnum
- 32];
672 internal_error (__FILE__
, __LINE__
,
673 _("mips_register_name: bad register number %d"), rawnum
);
676 /* Return the groups that a MIPS register can be categorised into. */
679 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
680 struct reggroup
*reggroup
)
685 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
686 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
687 if (reggroup
== all_reggroup
)
689 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
690 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
691 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
692 (gdbarch), as not all architectures are multi-arch. */
693 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
694 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
695 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
697 if (reggroup
== float_reggroup
)
698 return float_p
&& pseudo
;
699 if (reggroup
== vector_reggroup
)
700 return vector_p
&& pseudo
;
701 if (reggroup
== general_reggroup
)
702 return (!vector_p
&& !float_p
) && pseudo
;
703 /* Save the pseudo registers. Need to make certain that any code
704 extracting register values from a saved register cache also uses
706 if (reggroup
== save_reggroup
)
707 return raw_p
&& pseudo
;
708 /* Restore the same pseudo register. */
709 if (reggroup
== restore_reggroup
)
710 return raw_p
&& pseudo
;
714 /* Return the groups that a MIPS register can be categorised into.
715 This version is only used if we have a target description which
716 describes real registers (and their groups). */
719 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
720 struct reggroup
*reggroup
)
722 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
723 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
726 /* Only save, restore, and display the pseudo registers. Need to
727 make certain that any code extracting register values from a
728 saved register cache also uses pseudo registers.
730 Note: saving and restoring the pseudo registers is slightly
731 strange; if we have 64 bits, we should save and restore all
732 64 bits. But this is hard and has little benefit. */
736 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
740 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
743 /* Map the symbol table registers which live in the range [1 *
744 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
745 registers. Take care of alignment and size problems. */
747 static enum register_status
748 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
749 int cookednum
, gdb_byte
*buf
)
751 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
752 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
753 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
754 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
755 return regcache
->raw_read (rawnum
, buf
);
756 else if (register_size (gdbarch
, rawnum
) >
757 register_size (gdbarch
, cookednum
))
759 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
760 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
763 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
765 enum register_status status
;
767 status
= regcache
->raw_read (rawnum
, ®val
);
768 if (status
== REG_VALID
)
769 store_signed_integer (buf
, 4, byte_order
, regval
);
774 internal_error (__FILE__
, __LINE__
, _("bad register size"));
778 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
779 struct regcache
*regcache
, int cookednum
,
782 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
783 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
784 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
785 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
786 regcache
->raw_write (rawnum
, buf
);
787 else if (register_size (gdbarch
, rawnum
) >
788 register_size (gdbarch
, cookednum
))
790 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
791 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
794 /* Sign extend the shortened version of the register prior
795 to placing it in the raw register. This is required for
796 some mips64 parts in order to avoid unpredictable behavior. */
797 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
798 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
799 regcache_raw_write_signed (regcache
, rawnum
, regval
);
803 internal_error (__FILE__
, __LINE__
, _("bad register size"));
807 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
808 struct agent_expr
*ax
, int reg
)
810 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
811 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
812 && reg
< 2 * gdbarch_num_regs (gdbarch
));
814 ax_reg_mask (ax
, rawnum
);
820 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
821 struct agent_expr
*ax
, int reg
)
823 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
824 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
825 && reg
< 2 * gdbarch_num_regs (gdbarch
));
826 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
830 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
832 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
833 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
836 ax_simple (ax
, aop_lsh
);
839 ax_simple (ax
, aop_rsh_signed
);
843 internal_error (__FILE__
, __LINE__
, _("bad register size"));
848 /* Table to translate 3-bit register field to actual register number. */
849 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
851 /* Heuristic_proc_start may hunt through the text section for a long
852 time across a 2400 baud serial line. Allows the user to limit this
855 static int heuristic_fence_post
= 0;
857 /* Number of bytes of storage in the actual machine representation for
858 register N. NOTE: This defines the pseudo register type so need to
859 rebuild the architecture vector. */
861 static bool mips64_transfers_32bit_regs_p
= false;
864 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
865 struct cmd_list_element
*c
)
867 struct gdbarch_info info
;
868 gdbarch_info_init (&info
);
869 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
870 instead of relying on globals. Doing that would let generic code
871 handle the search for this specific architecture. */
872 if (!gdbarch_update_p (info
))
874 mips64_transfers_32bit_regs_p
= 0;
875 error (_("32-bit compatibility mode not supported"));
879 /* Convert to/from a register and the corresponding memory value. */
881 /* This predicate tests for the case of an 8 byte floating point
882 value that is being transferred to or from a pair of floating point
883 registers each of which are (or are considered to be) only 4 bytes
886 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
889 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
890 && register_size (gdbarch
, regnum
) == 4
891 && mips_float_register_p (gdbarch
, regnum
)
892 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
895 /* This predicate tests for the case of a value of less than 8
896 bytes in width that is being transfered to or from an 8 byte
897 general purpose register. */
899 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
902 int num_regs
= gdbarch_num_regs (gdbarch
);
904 return (register_size (gdbarch
, regnum
) == 8
905 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
906 && TYPE_LENGTH (type
) < 8);
910 mips_convert_register_p (struct gdbarch
*gdbarch
,
911 int regnum
, struct type
*type
)
913 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
914 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
918 mips_register_to_value (struct frame_info
*frame
, int regnum
,
919 struct type
*type
, gdb_byte
*to
,
920 int *optimizedp
, int *unavailablep
)
922 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
924 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
926 get_frame_register (frame
, regnum
+ 0, to
+ 4);
927 get_frame_register (frame
, regnum
+ 1, to
+ 0);
929 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
930 optimizedp
, unavailablep
))
933 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
934 optimizedp
, unavailablep
))
936 *optimizedp
= *unavailablep
= 0;
939 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
941 int len
= TYPE_LENGTH (type
);
944 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
945 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
946 optimizedp
, unavailablep
))
949 *optimizedp
= *unavailablep
= 0;
954 internal_error (__FILE__
, __LINE__
,
955 _("mips_register_to_value: unrecognized case"));
960 mips_value_to_register (struct frame_info
*frame
, int regnum
,
961 struct type
*type
, const gdb_byte
*from
)
963 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
965 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
967 put_frame_register (frame
, regnum
+ 0, from
+ 4);
968 put_frame_register (frame
, regnum
+ 1, from
+ 0);
970 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
973 int len
= TYPE_LENGTH (type
);
975 /* Sign extend values, irrespective of type, that are stored to
976 a 64-bit general purpose register. (32-bit unsigned values
977 are stored as signed quantities within a 64-bit register.
978 When performing an operation, in compiled code, that combines
979 a 32-bit unsigned value with a signed 64-bit value, a type
980 conversion is first performed that zeroes out the high 32 bits.) */
981 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
984 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
986 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
987 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
988 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
992 if (from
[len
-1] & 0x80)
993 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
995 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
996 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
997 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
1002 internal_error (__FILE__
, __LINE__
,
1003 _("mips_value_to_register: unrecognized case"));
1007 /* Return the GDB type object for the "standard" data type of data in
1010 static struct type
*
1011 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1013 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1014 if (mips_float_register_p (gdbarch
, regnum
))
1016 /* The floating-point registers raw, or cooked, always match
1017 mips_isa_regsize(), and also map 1:1, byte for byte. */
1018 if (mips_isa_regsize (gdbarch
) == 4)
1019 return builtin_type (gdbarch
)->builtin_float
;
1021 return builtin_type (gdbarch
)->builtin_double
;
1023 else if (regnum
< gdbarch_num_regs (gdbarch
))
1025 /* The raw or ISA registers. These are all sized according to
1027 if (mips_isa_regsize (gdbarch
) == 4)
1028 return builtin_type (gdbarch
)->builtin_int32
;
1030 return builtin_type (gdbarch
)->builtin_int64
;
1034 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1036 /* The cooked or ABI registers. These are sized according to
1037 the ABI (with a few complications). */
1038 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1039 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1040 return builtin_type (gdbarch
)->builtin_int32
;
1041 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1042 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1043 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1044 /* The pseudo/cooked view of the embedded registers is always
1045 32-bit. The raw view is handled below. */
1046 return builtin_type (gdbarch
)->builtin_int32
;
1047 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1048 /* The target, while possibly using a 64-bit register buffer,
1049 is only transfering 32-bits of each integer register.
1050 Reflect this in the cooked/pseudo (ABI) register value. */
1051 return builtin_type (gdbarch
)->builtin_int32
;
1052 else if (mips_abi_regsize (gdbarch
) == 4)
1053 /* The ABI is restricted to 32-bit registers (the ISA could be
1055 return builtin_type (gdbarch
)->builtin_int32
;
1058 return builtin_type (gdbarch
)->builtin_int64
;
1062 /* Return the GDB type for the pseudo register REGNUM, which is the
1063 ABI-level view. This function is only called if there is a target
1064 description which includes registers, so we know precisely the
1065 types of hardware registers. */
1067 static struct type
*
1068 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1070 const int num_regs
= gdbarch_num_regs (gdbarch
);
1071 int rawnum
= regnum
% num_regs
;
1072 struct type
*rawtype
;
1074 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1076 /* Absent registers are still absent. */
1077 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1078 if (TYPE_LENGTH (rawtype
) == 0)
1081 /* Present the floating point registers however the hardware did;
1082 do not try to convert between FPU layouts. */
1083 if (mips_float_register_p (gdbarch
, rawnum
))
1086 /* Floating-point control registers are always 32-bit even though for
1087 backwards compatibility reasons 64-bit targets will transfer them
1088 as 64-bit quantities even if using XML descriptions. */
1089 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1090 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1091 return builtin_type (gdbarch
)->builtin_int32
;
1093 /* Use pointer types for registers if we can. For n32 we can not,
1094 since we do not have a 64-bit pointer type. */
1095 if (mips_abi_regsize (gdbarch
)
1096 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1098 if (rawnum
== MIPS_SP_REGNUM
1099 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1100 return builtin_type (gdbarch
)->builtin_data_ptr
;
1101 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1102 return builtin_type (gdbarch
)->builtin_func_ptr
;
1105 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1106 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1107 || rawnum
== mips_regnum (gdbarch
)->lo
1108 || rawnum
== mips_regnum (gdbarch
)->hi
1109 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1110 || rawnum
== mips_regnum (gdbarch
)->cause
1111 || rawnum
== mips_regnum (gdbarch
)->pc
1112 || (mips_regnum (gdbarch
)->dspacc
!= -1
1113 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1114 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1115 return builtin_type (gdbarch
)->builtin_int32
;
1117 /* The pseudo/cooked view of embedded registers is always
1118 32-bit, even if the target transfers 64-bit values for them.
1119 New targets relying on XML descriptions should only transfer
1120 the necessary 32 bits, but older versions of GDB expected 64,
1121 so allow the target to provide 64 bits without interfering
1122 with the displayed type. */
1123 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1124 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1125 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1126 return builtin_type (gdbarch
)->builtin_int32
;
1128 /* For all other registers, pass through the hardware type. */
1132 /* Should the upper word of 64-bit addresses be zeroed? */
1133 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1136 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1138 switch (mask_address_var
)
1140 case AUTO_BOOLEAN_TRUE
:
1142 case AUTO_BOOLEAN_FALSE
:
1145 case AUTO_BOOLEAN_AUTO
:
1146 return tdep
->default_mask_address_p
;
1148 internal_error (__FILE__
, __LINE__
,
1149 _("mips_mask_address_p: bad switch"));
1155 show_mask_address (struct ui_file
*file
, int from_tty
,
1156 struct cmd_list_element
*c
, const char *value
)
1158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1160 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1161 switch (mask_address_var
)
1163 case AUTO_BOOLEAN_TRUE
:
1164 printf_filtered ("The 32 bit mips address mask is enabled\n");
1166 case AUTO_BOOLEAN_FALSE
:
1167 printf_filtered ("The 32 bit mips address mask is disabled\n");
1169 case AUTO_BOOLEAN_AUTO
:
1171 ("The 32 bit address mask is set automatically. Currently %s\n",
1172 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1175 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1180 /* Tell if the program counter value in MEMADDR is in a standard ISA
1184 mips_pc_is_mips (CORE_ADDR memaddr
)
1186 struct bound_minimal_symbol sym
;
1188 /* Flags indicating that this is a MIPS16 or microMIPS function is
1189 stored by elfread.c in the high bit of the info field. Use this
1190 to decide if the function is standard MIPS. Otherwise if bit 0
1191 of the address is clear, then this is a standard MIPS function. */
1192 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1194 return msymbol_is_mips (sym
.minsym
);
1196 return is_mips_addr (memaddr
);
1199 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1202 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1204 struct bound_minimal_symbol sym
;
1206 /* A flag indicating that this is a MIPS16 function is stored by
1207 elfread.c in the high bit of the info field. Use this to decide
1208 if the function is MIPS16. Otherwise if bit 0 of the address is
1209 set, then ELF file flags will tell if this is a MIPS16 function. */
1210 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1212 return msymbol_is_mips16 (sym
.minsym
);
1214 return is_mips16_addr (gdbarch
, memaddr
);
1217 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1220 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1222 struct bound_minimal_symbol sym
;
1224 /* A flag indicating that this is a microMIPS function is stored by
1225 elfread.c in the high bit of the info field. Use this to decide
1226 if the function is microMIPS. Otherwise if bit 0 of the address
1227 is set, then ELF file flags will tell if this is a microMIPS
1229 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1231 return msymbol_is_micromips (sym
.minsym
);
1233 return is_micromips_addr (gdbarch
, memaddr
);
1236 /* Tell the ISA type of the function the program counter value in MEMADDR
1239 static enum mips_isa
1240 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1242 struct bound_minimal_symbol sym
;
1244 /* A flag indicating that this is a MIPS16 or a microMIPS function
1245 is stored by elfread.c in the high bit of the info field. Use
1246 this to decide if the function is MIPS16 or microMIPS or normal
1247 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1248 flags will tell if this is a MIPS16 or a microMIPS function. */
1249 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1252 if (msymbol_is_micromips (sym
.minsym
))
1253 return ISA_MICROMIPS
;
1254 else if (msymbol_is_mips16 (sym
.minsym
))
1261 if (is_mips_addr (memaddr
))
1263 else if (is_micromips_addr (gdbarch
, memaddr
))
1264 return ISA_MICROMIPS
;
1270 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1271 The need for comes from the ISA bit having been cleared, making
1272 addresses in FDE, range records, etc. referring to compressed code
1273 different to those in line information, the symbol table and finally
1274 the PC register. That in turn confuses many operations. */
1277 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1279 pc
= unmake_compact_addr (pc
);
1280 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1283 /* Recalculate the line record requested so that the resulting PC has
1284 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1285 this adjustment comes from some records associated with compressed
1286 code having the ISA bit cleared, most notably at function prologue
1287 ends. The ISA bit is in this context retrieved from the minimal
1288 symbol covering the address requested, which in turn has been
1289 constructed from the binary's symbol table rather than DWARF-2
1290 information. The correct setting of the ISA bit is required for
1291 breakpoint addresses to correctly match against the stop PC.
1293 As line entries can specify relative address adjustments we need to
1294 keep track of the absolute value of the last line address recorded
1295 in line information, so that we can calculate the actual address to
1296 apply the ISA bit adjustment to. We use PC for this tracking and
1297 keep the original address there.
1299 As such relative address adjustments can be odd within compressed
1300 code we need to keep track of the last line address with the ISA
1301 bit adjustment applied too, as the original address may or may not
1302 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1303 the adjusted address there.
1305 For relative address adjustments we then use these variables to
1306 calculate the address intended by line information, which will be
1307 PC-relative, and return an updated adjustment carrying ISA bit
1308 information, which will be ADJ_PC-relative. For absolute address
1309 adjustments we just return the same address that we store in ADJ_PC
1312 As the first line entry can be relative to an implied address value
1313 of 0 we need to have the initial address set up that we store in PC
1314 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1315 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1318 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1320 static CORE_ADDR adj_pc
;
1321 static CORE_ADDR pc
;
1324 pc
= rel
? pc
+ addr
: addr
;
1325 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1326 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1331 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1333 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1334 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1335 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1336 static const char mips_str_call_stub
[] = "__call_stub_";
1337 static const char mips_str_fn_stub
[] = "__fn_stub_";
1339 /* This is used as a PIC thunk prefix. */
1341 static const char mips_str_pic
[] = ".pic.";
1343 /* Return non-zero if the PC is inside a call thunk (aka stub or
1344 trampoline) that should be treated as a temporary frame. */
1347 mips_in_frame_stub (CORE_ADDR pc
)
1349 CORE_ADDR start_addr
;
1352 /* Find the starting address of the function containing the PC. */
1353 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1356 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1357 if (startswith (name
, mips_str_mips16_call_stub
))
1359 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1360 if (startswith (name
, mips_str_call_stub
))
1362 /* If the PC is in __fn_stub_*, this is a call stub. */
1363 if (startswith (name
, mips_str_fn_stub
))
1366 return 0; /* Not a stub. */
1369 /* MIPS believes that the PC has a sign extended value. Perhaps the
1370 all registers should be sign extended for simplicity? */
1373 mips_read_pc (readable_regcache
*regcache
)
1375 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1378 regcache
->cooked_read (regnum
, &pc
);
1383 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1387 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1388 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1389 intermediate frames. In this case we can get the caller's address
1390 from $ra, or if $ra contains an address within a thunk as well, then
1391 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1392 and thus the caller's address is in $s2. */
1393 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1395 pc
= frame_unwind_register_signed
1396 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1397 if (mips_in_frame_stub (pc
))
1398 pc
= frame_unwind_register_signed
1399 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1405 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1407 return frame_unwind_register_signed
1408 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1411 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1412 dummy frame. The frame ID's base needs to match the TOS value
1413 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1416 static struct frame_id
1417 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1419 return frame_id_build
1420 (get_frame_register_signed (this_frame
,
1421 gdbarch_num_regs (gdbarch
)
1423 get_frame_pc (this_frame
));
1426 /* Implement the "write_pc" gdbarch method. */
1429 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1431 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1433 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1436 /* Fetch and return instruction from the specified location. Handle
1437 MIPS16/microMIPS as appropriate. */
1440 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1441 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1443 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1444 gdb_byte buf
[MIPS_INSN32_SIZE
];
1452 instlen
= MIPS_INSN16_SIZE
;
1453 addr
= unmake_compact_addr (addr
);
1456 instlen
= MIPS_INSN32_SIZE
;
1459 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1462 err
= target_read_memory (addr
, buf
, instlen
);
1468 memory_error (TARGET_XFER_E_IO
, addr
);
1471 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1474 /* These are the fields of 32 bit mips instructions. */
1475 #define mips32_op(x) (x >> 26)
1476 #define itype_op(x) (x >> 26)
1477 #define itype_rs(x) ((x >> 21) & 0x1f)
1478 #define itype_rt(x) ((x >> 16) & 0x1f)
1479 #define itype_immediate(x) (x & 0xffff)
1481 #define jtype_op(x) (x >> 26)
1482 #define jtype_target(x) (x & 0x03ffffff)
1484 #define rtype_op(x) (x >> 26)
1485 #define rtype_rs(x) ((x >> 21) & 0x1f)
1486 #define rtype_rt(x) ((x >> 16) & 0x1f)
1487 #define rtype_rd(x) ((x >> 11) & 0x1f)
1488 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1489 #define rtype_funct(x) (x & 0x3f)
1491 /* MicroMIPS instruction fields. */
1492 #define micromips_op(x) ((x) >> 10)
1494 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1495 bit and the size respectively of the field extracted. */
1496 #define b0s4_imm(x) ((x) & 0xf)
1497 #define b0s5_imm(x) ((x) & 0x1f)
1498 #define b0s5_reg(x) ((x) & 0x1f)
1499 #define b0s7_imm(x) ((x) & 0x7f)
1500 #define b0s10_imm(x) ((x) & 0x3ff)
1501 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1502 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1503 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1504 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1505 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1506 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1507 #define b6s4_op(x) (((x) >> 6) & 0xf)
1508 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1510 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1511 respectively of the field extracted. */
1512 #define b0s6_op(x) ((x) & 0x3f)
1513 #define b0s11_op(x) ((x) & 0x7ff)
1514 #define b0s12_imm(x) ((x) & 0xfff)
1515 #define b0s16_imm(x) ((x) & 0xffff)
1516 #define b0s26_imm(x) ((x) & 0x3ffffff)
1517 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1518 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1519 #define b12s4_op(x) (((x) >> 12) & 0xf)
1521 /* Return the size in bytes of the instruction INSN encoded in the ISA
1525 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1530 if ((micromips_op (insn
) & 0x4) == 0x4
1531 || (micromips_op (insn
) & 0x7) == 0x0)
1532 return 2 * MIPS_INSN16_SIZE
;
1534 return MIPS_INSN16_SIZE
;
1536 if ((insn
& 0xf800) == 0xf000)
1537 return 2 * MIPS_INSN16_SIZE
;
1539 return MIPS_INSN16_SIZE
;
1541 return MIPS_INSN32_SIZE
;
1543 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1547 mips32_relative_offset (ULONGEST inst
)
1549 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1552 /* Determine the address of the next instruction executed after the INST
1553 floating condition branch instruction at PC. COUNT specifies the
1554 number of the floating condition bits tested by the branch. */
1557 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1558 ULONGEST inst
, CORE_ADDR pc
, int count
)
1560 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1561 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1562 int tf
= itype_rt (inst
) & 1;
1563 int mask
= (1 << count
) - 1;
1568 /* No way to handle; it'll most likely trap anyway. */
1571 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1572 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1574 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1575 pc
+= mips32_relative_offset (inst
);
1582 /* Return nonzero if the gdbarch is an Octeon series. */
1585 is_octeon (struct gdbarch
*gdbarch
)
1587 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1589 return (info
->mach
== bfd_mach_mips_octeon
1590 || info
->mach
== bfd_mach_mips_octeonp
1591 || info
->mach
== bfd_mach_mips_octeon2
);
1594 /* Return true if the OP represents the Octeon's BBIT instruction. */
1597 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1599 if (!is_octeon (gdbarch
))
1601 /* BBIT0 is encoded as LWC2: 110 010. */
1602 /* BBIT032 is encoded as LDC2: 110 110. */
1603 /* BBIT1 is encoded as SWC2: 111 010. */
1604 /* BBIT132 is encoded as SDC2: 111 110. */
1605 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1611 /* Determine where to set a single step breakpoint while considering
1612 branch prediction. */
1615 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1617 struct gdbarch
*gdbarch
= regcache
->arch ();
1620 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1621 op
= itype_op (inst
);
1622 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1626 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1637 goto greater_branch
;
1642 else if (op
== 17 && itype_rs (inst
) == 8)
1643 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1644 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1645 else if (op
== 17 && itype_rs (inst
) == 9
1646 && (itype_rt (inst
) & 2) == 0)
1647 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1648 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1649 else if (op
== 17 && itype_rs (inst
) == 10
1650 && (itype_rt (inst
) & 2) == 0)
1651 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1652 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1655 /* The new PC will be alternate mode. */
1659 reg
= jtype_target (inst
) << 2;
1660 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1661 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1663 else if (is_octeon_bbit_op (op
, gdbarch
))
1667 branch_if
= op
== 58 || op
== 62;
1668 bit
= itype_rt (inst
);
1670 /* Take into account the *32 instructions. */
1671 if (op
== 54 || op
== 62)
1674 if (((regcache_raw_get_signed (regcache
,
1675 itype_rs (inst
)) >> bit
) & 1)
1677 pc
+= mips32_relative_offset (inst
) + 4;
1679 pc
+= 8; /* After the delay slot. */
1683 pc
+= 4; /* Not a branch, next instruction is easy. */
1686 { /* This gets way messy. */
1688 /* Further subdivide into SPECIAL, REGIMM and other. */
1689 switch (op
& 0x07) /* Extract bits 28,27,26. */
1691 case 0: /* SPECIAL */
1692 op
= rtype_funct (inst
);
1697 /* Set PC to that address. */
1698 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1700 case 12: /* SYSCALL */
1702 struct gdbarch_tdep
*tdep
;
1704 tdep
= gdbarch_tdep (gdbarch
);
1705 if (tdep
->syscall_next_pc
!= NULL
)
1706 pc
= tdep
->syscall_next_pc (get_current_frame ());
1715 break; /* end SPECIAL */
1716 case 1: /* REGIMM */
1718 op
= itype_rt (inst
); /* branch condition */
1723 case 16: /* BLTZAL */
1724 case 18: /* BLTZALL */
1726 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1727 pc
+= mips32_relative_offset (inst
) + 4;
1729 pc
+= 8; /* after the delay slot */
1733 case 17: /* BGEZAL */
1734 case 19: /* BGEZALL */
1735 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1736 pc
+= mips32_relative_offset (inst
) + 4;
1738 pc
+= 8; /* after the delay slot */
1740 case 0x1c: /* BPOSGE32 */
1741 case 0x1e: /* BPOSGE64 */
1743 if (itype_rs (inst
) == 0)
1745 unsigned int pos
= (op
& 2) ? 64 : 32;
1746 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1749 /* No way to handle; it'll most likely trap anyway. */
1752 if ((regcache_raw_get_unsigned (regcache
,
1753 dspctl
) & 0x7f) >= pos
)
1754 pc
+= mips32_relative_offset (inst
);
1759 /* All of the other instructions in the REGIMM category */
1764 break; /* end REGIMM */
1769 reg
= jtype_target (inst
) << 2;
1770 /* Upper four bits get never changed... */
1771 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1774 case 4: /* BEQ, BEQL */
1776 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1777 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1778 pc
+= mips32_relative_offset (inst
) + 4;
1782 case 5: /* BNE, BNEL */
1784 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1785 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1786 pc
+= mips32_relative_offset (inst
) + 4;
1790 case 6: /* BLEZ, BLEZL */
1791 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1792 pc
+= mips32_relative_offset (inst
) + 4;
1798 greater_branch
: /* BGTZ, BGTZL */
1799 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1800 pc
+= mips32_relative_offset (inst
) + 4;
1807 } /* mips32_next_pc */
1809 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1813 micromips_relative_offset7 (ULONGEST insn
)
1815 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1818 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1822 micromips_relative_offset10 (ULONGEST insn
)
1824 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1827 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1831 micromips_relative_offset16 (ULONGEST insn
)
1833 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1836 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1839 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1843 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1844 return mips_insn_size (ISA_MICROMIPS
, insn
);
1847 /* Calculate the address of the next microMIPS instruction to execute
1848 after the INSN coprocessor 1 conditional branch instruction at the
1849 address PC. COUNT denotes the number of coprocessor condition bits
1850 examined by the branch. */
1853 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1854 ULONGEST insn
, CORE_ADDR pc
, int count
)
1856 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1857 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1858 int tf
= b5s5_op (insn
>> 16) & 1;
1859 int mask
= (1 << count
) - 1;
1864 /* No way to handle; it'll most likely trap anyway. */
1867 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1868 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1870 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1871 pc
+= micromips_relative_offset16 (insn
);
1873 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1878 /* Calculate the address of the next microMIPS instruction to execute
1879 after the instruction at the address PC. */
1882 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1884 struct gdbarch
*gdbarch
= regcache
->arch ();
1887 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1888 pc
+= MIPS_INSN16_SIZE
;
1889 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1891 /* 32-bit instructions. */
1892 case 2 * MIPS_INSN16_SIZE
:
1894 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1895 pc
+= MIPS_INSN16_SIZE
;
1896 switch (micromips_op (insn
>> 16))
1898 case 0x00: /* POOL32A: bits 000000 */
1899 switch (b0s6_op (insn
))
1901 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1902 switch (b6s10_ext (insn
))
1904 case 0x3c: /* JALR: 000000 0000111100 111100 */
1905 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1906 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1907 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1908 pc
= regcache_raw_get_signed (regcache
,
1909 b0s5_reg (insn
>> 16));
1911 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1913 struct gdbarch_tdep
*tdep
;
1915 tdep
= gdbarch_tdep (gdbarch
);
1916 if (tdep
->syscall_next_pc
!= NULL
)
1917 pc
= tdep
->syscall_next_pc (get_current_frame ());
1925 case 0x10: /* POOL32I: bits 010000 */
1926 switch (b5s5_op (insn
>> 16))
1928 case 0x00: /* BLTZ: bits 010000 00000 */
1929 case 0x01: /* BLTZAL: bits 010000 00001 */
1930 case 0x11: /* BLTZALS: bits 010000 10001 */
1931 if (regcache_raw_get_signed (regcache
,
1932 b0s5_reg (insn
>> 16)) < 0)
1933 pc
+= micromips_relative_offset16 (insn
);
1935 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1938 case 0x02: /* BGEZ: bits 010000 00010 */
1939 case 0x03: /* BGEZAL: bits 010000 00011 */
1940 case 0x13: /* BGEZALS: bits 010000 10011 */
1941 if (regcache_raw_get_signed (regcache
,
1942 b0s5_reg (insn
>> 16)) >= 0)
1943 pc
+= micromips_relative_offset16 (insn
);
1945 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1948 case 0x04: /* BLEZ: bits 010000 00100 */
1949 if (regcache_raw_get_signed (regcache
,
1950 b0s5_reg (insn
>> 16)) <= 0)
1951 pc
+= micromips_relative_offset16 (insn
);
1953 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1956 case 0x05: /* BNEZC: bits 010000 00101 */
1957 if (regcache_raw_get_signed (regcache
,
1958 b0s5_reg (insn
>> 16)) != 0)
1959 pc
+= micromips_relative_offset16 (insn
);
1962 case 0x06: /* BGTZ: bits 010000 00110 */
1963 if (regcache_raw_get_signed (regcache
,
1964 b0s5_reg (insn
>> 16)) > 0)
1965 pc
+= micromips_relative_offset16 (insn
);
1967 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1970 case 0x07: /* BEQZC: bits 010000 00111 */
1971 if (regcache_raw_get_signed (regcache
,
1972 b0s5_reg (insn
>> 16)) == 0)
1973 pc
+= micromips_relative_offset16 (insn
);
1976 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1977 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1978 if (((insn
>> 16) & 0x3) == 0x0)
1979 /* BC2F, BC2T: don't know how to handle these. */
1983 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1984 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1986 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1987 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1990 /* No way to handle; it'll most likely trap anyway. */
1993 if ((regcache_raw_get_unsigned (regcache
,
1994 dspctl
) & 0x7f) >= pos
)
1995 pc
+= micromips_relative_offset16 (insn
);
1997 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2001 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2002 /* BC1ANY2F: bits 010000 11100 xxx01 */
2003 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2004 /* BC1ANY2T: bits 010000 11101 xxx01 */
2005 if (((insn
>> 16) & 0x2) == 0x0)
2006 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2007 ((insn
>> 16) & 0x1) + 1);
2010 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2011 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2012 if (((insn
>> 16) & 0x3) == 0x1)
2013 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2018 case 0x1d: /* JALS: bits 011101 */
2019 case 0x35: /* J: bits 110101 */
2020 case 0x3d: /* JAL: bits 111101 */
2021 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2024 case 0x25: /* BEQ: bits 100101 */
2025 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2026 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2027 pc
+= micromips_relative_offset16 (insn
);
2029 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2032 case 0x2d: /* BNE: bits 101101 */
2033 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2034 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2035 pc
+= micromips_relative_offset16 (insn
);
2037 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2040 case 0x3c: /* JALX: bits 111100 */
2041 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2046 /* 16-bit instructions. */
2047 case MIPS_INSN16_SIZE
:
2048 switch (micromips_op (insn
))
2050 case 0x11: /* POOL16C: bits 010001 */
2051 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2052 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2053 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2054 else if (b5s5_op (insn
) == 0x18)
2055 /* JRADDIUSP: bits 010001 11000 */
2056 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2059 case 0x23: /* BEQZ16: bits 100011 */
2061 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2063 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2064 pc
+= micromips_relative_offset7 (insn
);
2066 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2070 case 0x2b: /* BNEZ16: bits 101011 */
2072 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2074 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2075 pc
+= micromips_relative_offset7 (insn
);
2077 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2081 case 0x33: /* B16: bits 110011 */
2082 pc
+= micromips_relative_offset10 (insn
);
2091 /* Decoding the next place to set a breakpoint is irregular for the
2092 mips 16 variant, but fortunately, there fewer instructions. We have
2093 to cope ith extensions for 16 bit instructions and a pair of actual
2094 32 bit instructions. We dont want to set a single step instruction
2095 on the extend instruction either. */
2097 /* Lots of mips16 instruction formats */
2098 /* Predicting jumps requires itype,ritype,i8type
2099 and their extensions extItype,extritype,extI8type. */
2100 enum mips16_inst_fmts
2102 itype
, /* 0 immediate 5,10 */
2103 ritype
, /* 1 5,3,8 */
2104 rrtype
, /* 2 5,3,3,5 */
2105 rritype
, /* 3 5,3,3,5 */
2106 rrrtype
, /* 4 5,3,3,3,2 */
2107 rriatype
, /* 5 5,3,3,1,4 */
2108 shifttype
, /* 6 5,3,3,3,2 */
2109 i8type
, /* 7 5,3,8 */
2110 i8movtype
, /* 8 5,3,3,5 */
2111 i8mov32rtype
, /* 9 5,3,5,3 */
2112 i64type
, /* 10 5,3,8 */
2113 ri64type
, /* 11 5,3,3,5 */
2114 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2115 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2116 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2117 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2118 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2119 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2120 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2121 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2122 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2123 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2125 /* I am heaping all the fields of the formats into one structure and
2126 then, only the fields which are involved in instruction extension. */
2130 unsigned int regx
; /* Function in i8 type. */
2135 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2136 for the bits which make up the immediate extension. */
2139 extended_offset (unsigned int extension
)
2143 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2145 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2147 value
|= extension
& 0x1f; /* Extract 4:0. */
2152 /* Only call this function if you know that this is an extendable
2153 instruction. It won't malfunction, but why make excess remote memory
2154 references? If the immediate operands get sign extended or something,
2155 do it after the extension is performed. */
2156 /* FIXME: Every one of these cases needs to worry about sign extension
2157 when the offset is to be used in relative addressing. */
2160 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2162 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2165 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2166 target_read_memory (pc
, buf
, 2);
2167 return extract_unsigned_integer (buf
, 2, byte_order
);
2171 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2172 unsigned int extension
,
2174 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2179 switch (insn_format
)
2186 value
= extended_offset ((extension
<< 16) | inst
);
2187 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2191 value
= inst
& 0x7ff;
2192 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2201 { /* A register identifier and an offset. */
2202 /* Most of the fields are the same as I type but the
2203 immediate value is of a different length. */
2207 value
= extended_offset ((extension
<< 16) | inst
);
2208 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2212 value
= inst
& 0xff; /* 8 bits */
2213 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2216 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2222 unsigned long value
;
2223 unsigned int nexthalf
;
2224 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2225 value
= value
<< 16;
2226 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2227 /* Low bit still set. */
2235 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2237 upk
->offset
= offset
;
2243 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2244 and having a signed 16-bit OFFSET. */
2247 add_offset_16 (CORE_ADDR pc
, int offset
)
2249 return pc
+ (offset
<< 1) + 2;
2253 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2254 unsigned int extension
, unsigned int insn
)
2256 struct gdbarch
*gdbarch
= regcache
->arch ();
2257 int op
= (insn
>> 11);
2260 case 2: /* Branch */
2262 struct upk_mips16 upk
;
2263 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2264 pc
= add_offset_16 (pc
, upk
.offset
);
2267 case 3: /* JAL , JALX - Watch out, these are 32 bit
2270 struct upk_mips16 upk
;
2271 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2272 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2273 if ((insn
>> 10) & 0x01) /* Exchange mode */
2274 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2281 struct upk_mips16 upk
;
2283 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2284 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2286 pc
= add_offset_16 (pc
, upk
.offset
);
2293 struct upk_mips16 upk
;
2295 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2296 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2298 pc
= add_offset_16 (pc
, upk
.offset
);
2303 case 12: /* I8 Formats btez btnez */
2305 struct upk_mips16 upk
;
2307 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2308 /* upk.regx contains the opcode */
2309 /* Test register is 24 */
2310 reg
= regcache_raw_get_signed (regcache
, 24);
2311 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2312 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2313 pc
= add_offset_16 (pc
, upk
.offset
);
2318 case 29: /* RR Formats JR, JALR, JALR-RA */
2320 struct upk_mips16 upk
;
2321 /* upk.fmt = rrtype; */
2326 upk
.regx
= (insn
>> 8) & 0x07;
2327 upk
.regy
= (insn
>> 5) & 0x07;
2328 if ((upk
.regy
& 1) == 0)
2329 reg
= mips_reg3_to_reg
[upk
.regx
];
2331 reg
= 31; /* Function return instruction. */
2332 pc
= regcache_raw_get_signed (regcache
, reg
);
2339 /* This is an instruction extension. Fetch the real instruction
2340 (which follows the extension) and decode things based on
2344 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2345 fetch_mips_16 (gdbarch
, pc
));
2358 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2360 struct gdbarch
*gdbarch
= regcache
->arch ();
2361 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2362 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2365 /* The mips_next_pc function supports single_step when the remote
2366 target monitor or stub is not developed enough to do a single_step.
2367 It works by decoding the current instruction and predicting where a
2368 branch will go. This isn't hard because all the data is available.
2369 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2371 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2373 struct gdbarch
*gdbarch
= regcache
->arch ();
2375 if (mips_pc_is_mips16 (gdbarch
, pc
))
2376 return mips16_next_pc (regcache
, pc
);
2377 else if (mips_pc_is_micromips (gdbarch
, pc
))
2378 return micromips_next_pc (regcache
, pc
);
2380 return mips32_next_pc (regcache
, pc
);
2383 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2387 mips16_instruction_is_compact_branch (unsigned short insn
)
2389 switch (insn
& 0xf800)
2392 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2394 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2395 case 0x2800: /* BNEZ */
2396 case 0x2000: /* BEQZ */
2397 case 0x1000: /* B */
2404 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2408 micromips_instruction_is_compact_branch (unsigned short insn
)
2410 switch (micromips_op (insn
))
2412 case 0x11: /* POOL16C: bits 010001 */
2413 return (b5s5_op (insn
) == 0x18
2414 /* JRADDIUSP: bits 010001 11000 */
2415 || b5s5_op (insn
) == 0xd);
2416 /* JRC: bits 010011 01101 */
2417 case 0x10: /* POOL32I: bits 010000 */
2418 return (b5s5_op (insn
) & 0x1d) == 0x5;
2419 /* BEQZC/BNEZC: bits 010000 001x1 */
2425 struct mips_frame_cache
2428 struct trad_frame_saved_reg
*saved_regs
;
2431 /* Set a register's saved stack address in temp_saved_regs. If an
2432 address has already been set for this register, do nothing; this
2433 way we will only recognize the first save of a given register in a
2436 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2437 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2438 Strictly speaking, only the second range is used as it is only second
2439 range (the ABI instead of ISA registers) that comes into play when finding
2440 saved registers in a frame. */
2443 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2444 int regnum
, CORE_ADDR offset
)
2446 if (this_cache
!= NULL
2447 && this_cache
->saved_regs
[regnum
].addr
== -1)
2449 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2451 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2457 /* Fetch the immediate value from a MIPS16 instruction.
2458 If the previous instruction was an EXTEND, use it to extend
2459 the upper bits of the immediate value. This is a helper function
2460 for mips16_scan_prologue. */
2463 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2464 unsigned short inst
, /* current instruction */
2465 int nbits
, /* number of bits in imm field */
2466 int scale
, /* scale factor to be applied to imm */
2467 int is_signed
) /* is the imm field signed? */
2471 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2473 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2474 if (offset
& 0x8000) /* check for negative extend */
2475 offset
= 0 - (0x10000 - (offset
& 0xffff));
2476 return offset
| (inst
& 0x1f);
2480 int max_imm
= 1 << nbits
;
2481 int mask
= max_imm
- 1;
2482 int sign_bit
= max_imm
>> 1;
2484 offset
= inst
& mask
;
2485 if (is_signed
&& (offset
& sign_bit
))
2486 offset
= 0 - (max_imm
- offset
);
2487 return offset
* scale
;
2492 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2493 the associated FRAME_CACHE if not null.
2494 Return the address of the first instruction past the prologue. */
2497 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2498 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2499 struct frame_info
*this_frame
,
2500 struct mips_frame_cache
*this_cache
)
2502 int prev_non_prologue_insn
= 0;
2503 int this_non_prologue_insn
;
2504 int non_prologue_insns
= 0;
2507 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2509 long frame_offset
= 0; /* Size of stack frame. */
2510 long frame_adjust
= 0; /* Offset of FP from SP. */
2511 int frame_reg
= MIPS_SP_REGNUM
;
2512 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2513 unsigned inst
= 0; /* current instruction */
2514 unsigned entry_inst
= 0; /* the entry instruction */
2515 unsigned save_inst
= 0; /* the save instruction */
2516 int prev_delay_slot
= 0;
2520 int extend_bytes
= 0;
2521 int prev_extend_bytes
= 0;
2522 CORE_ADDR end_prologue_addr
;
2524 /* Can be called when there's no process, and hence when there's no
2526 if (this_frame
!= NULL
)
2527 sp
= get_frame_register_signed (this_frame
,
2528 gdbarch_num_regs (gdbarch
)
2533 if (limit_pc
> start_pc
+ 200)
2534 limit_pc
= start_pc
+ 200;
2537 /* Permit at most one non-prologue non-control-transfer instruction
2538 in the middle which may have been reordered by the compiler for
2540 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2542 this_non_prologue_insn
= 0;
2545 /* Save the previous instruction. If it's an EXTEND, we'll extract
2546 the immediate offset extension from it in mips16_get_imm. */
2549 /* Fetch and decode the instruction. */
2550 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2553 /* Normally we ignore extend instructions. However, if it is
2554 not followed by a valid prologue instruction, then this
2555 instruction is not part of the prologue either. We must
2556 remember in this case to adjust the end_prologue_addr back
2558 if ((inst
& 0xf800) == 0xf000) /* extend */
2560 extend_bytes
= MIPS_INSN16_SIZE
;
2564 prev_extend_bytes
= extend_bytes
;
2567 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2568 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2570 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2571 if (offset
< 0) /* Negative stack adjustment? */
2572 frame_offset
-= offset
;
2574 /* Exit loop if a positive stack adjustment is found, which
2575 usually means that the stack cleanup code in the function
2576 epilogue is reached. */
2579 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2581 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2582 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2583 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2585 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2587 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2588 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2589 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2591 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2593 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2594 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2596 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2598 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2599 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2601 else if (inst
== 0x673d) /* move $s1, $sp */
2606 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2608 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2609 frame_addr
= sp
+ offset
;
2611 frame_adjust
= offset
;
2613 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2615 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2616 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2617 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2619 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2621 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2622 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2623 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2625 else if ((inst
& 0xf81f) == 0xe809
2626 && (inst
& 0x700) != 0x700) /* entry */
2627 entry_inst
= inst
; /* Save for later processing. */
2628 else if ((inst
& 0xff80) == 0x6480) /* save */
2630 save_inst
= inst
; /* Save for later processing. */
2631 if (prev_extend_bytes
) /* extend */
2632 save_inst
|= prev_inst
<< 16;
2634 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2636 /* This instruction is part of the prologue, but we don't
2637 need to do anything special to handle it. */
2639 else if (mips16_instruction_has_delay_slot (inst
, 0))
2640 /* JAL/JALR/JALX/JR */
2642 /* The instruction in the delay slot can be a part
2643 of the prologue, so move forward once more. */
2645 if (mips16_instruction_has_delay_slot (inst
, 1))
2648 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2649 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2654 this_non_prologue_insn
= 1;
2657 non_prologue_insns
+= this_non_prologue_insn
;
2659 /* A jump or branch, or enough non-prologue insns seen? If so,
2660 then we must have reached the end of the prologue by now. */
2661 if (prev_delay_slot
|| non_prologue_insns
> 1
2662 || mips16_instruction_is_compact_branch (inst
))
2665 prev_non_prologue_insn
= this_non_prologue_insn
;
2666 prev_delay_slot
= in_delay_slot
;
2667 prev_pc
= cur_pc
- prev_extend_bytes
;
2670 /* The entry instruction is typically the first instruction in a function,
2671 and it stores registers at offsets relative to the value of the old SP
2672 (before the prologue). But the value of the sp parameter to this
2673 function is the new SP (after the prologue has been executed). So we
2674 can't calculate those offsets until we've seen the entire prologue,
2675 and can calculate what the old SP must have been. */
2676 if (entry_inst
!= 0)
2678 int areg_count
= (entry_inst
>> 8) & 7;
2679 int sreg_count
= (entry_inst
>> 6) & 3;
2681 /* The entry instruction always subtracts 32 from the SP. */
2684 /* Now we can calculate what the SP must have been at the
2685 start of the function prologue. */
2688 /* Check if a0-a3 were saved in the caller's argument save area. */
2689 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2691 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2692 offset
+= mips_abi_regsize (gdbarch
);
2695 /* Check if the ra register was pushed on the stack. */
2697 if (entry_inst
& 0x20)
2699 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2700 offset
-= mips_abi_regsize (gdbarch
);
2703 /* Check if the s0 and s1 registers were pushed on the stack. */
2704 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2706 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2707 offset
-= mips_abi_regsize (gdbarch
);
2711 /* The SAVE instruction is similar to ENTRY, except that defined by the
2712 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2713 size of the frame is specified as an immediate field of instruction
2714 and an extended variation exists which lets additional registers and
2715 frame space to be specified. The instruction always treats registers
2716 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2717 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2719 static int args_table
[16] = {
2720 0, 0, 0, 0, 1, 1, 1, 1,
2721 2, 2, 2, 0, 3, 3, 4, -1,
2723 static int astatic_table
[16] = {
2724 0, 1, 2, 3, 0, 1, 2, 3,
2725 0, 1, 2, 4, 0, 1, 0, -1,
2727 int aregs
= (save_inst
>> 16) & 0xf;
2728 int xsregs
= (save_inst
>> 24) & 0x7;
2729 int args
= args_table
[aregs
];
2730 int astatic
= astatic_table
[aregs
];
2735 warning (_("Invalid number of argument registers encoded in SAVE."));
2740 warning (_("Invalid number of static registers encoded in SAVE."));
2744 /* For standard SAVE the frame size of 0 means 128. */
2745 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2746 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2749 frame_offset
+= frame_size
;
2751 /* Now we can calculate what the SP must have been at the
2752 start of the function prologue. */
2755 /* Check if A0-A3 were saved in the caller's argument save area. */
2756 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2758 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2759 offset
+= mips_abi_regsize (gdbarch
);
2764 /* Check if the RA register was pushed on the stack. */
2765 if (save_inst
& 0x40)
2767 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2768 offset
-= mips_abi_regsize (gdbarch
);
2771 /* Check if the S8 register was pushed on the stack. */
2774 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2775 offset
-= mips_abi_regsize (gdbarch
);
2778 /* Check if S2-S7 were pushed on the stack. */
2779 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2781 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2782 offset
-= mips_abi_regsize (gdbarch
);
2785 /* Check if the S1 register was pushed on the stack. */
2786 if (save_inst
& 0x10)
2788 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2789 offset
-= mips_abi_regsize (gdbarch
);
2791 /* Check if the S0 register was pushed on the stack. */
2792 if (save_inst
& 0x20)
2794 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2795 offset
-= mips_abi_regsize (gdbarch
);
2798 /* Check if A0-A3 were pushed on the stack. */
2799 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2801 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2802 offset
-= mips_abi_regsize (gdbarch
);
2806 if (this_cache
!= NULL
)
2809 (get_frame_register_signed (this_frame
,
2810 gdbarch_num_regs (gdbarch
) + frame_reg
)
2811 + frame_offset
- frame_adjust
);
2812 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2813 be able to get rid of the assignment below, evetually. But it's
2814 still needed for now. */
2815 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2816 + mips_regnum (gdbarch
)->pc
]
2817 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2820 /* Set end_prologue_addr to the address of the instruction immediately
2821 after the last one we scanned. Unless the last one looked like a
2822 non-prologue instruction (and we looked ahead), in which case use
2823 its address instead. */
2824 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2825 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2827 return end_prologue_addr
;
2830 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2831 Procedures that use the 32-bit instruction set are handled by the
2832 mips_insn32 unwinder. */
2834 static struct mips_frame_cache
*
2835 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2837 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2838 struct mips_frame_cache
*cache
;
2840 if ((*this_cache
) != NULL
)
2841 return (struct mips_frame_cache
*) (*this_cache
);
2842 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2843 (*this_cache
) = cache
;
2844 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2846 /* Analyze the function prologue. */
2848 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2849 CORE_ADDR start_addr
;
2851 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2852 if (start_addr
== 0)
2853 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2854 /* We can't analyze the prologue if we couldn't find the begining
2856 if (start_addr
== 0)
2859 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2860 (struct mips_frame_cache
*) *this_cache
);
2863 /* gdbarch_sp_regnum contains the value and not the address. */
2864 trad_frame_set_value (cache
->saved_regs
,
2865 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2868 return (struct mips_frame_cache
*) (*this_cache
);
2872 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2873 struct frame_id
*this_id
)
2875 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2877 /* This marks the outermost frame. */
2878 if (info
->base
== 0)
2880 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2883 static struct value
*
2884 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2885 void **this_cache
, int regnum
)
2887 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2889 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2893 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2894 struct frame_info
*this_frame
, void **this_cache
)
2896 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2897 CORE_ADDR pc
= get_frame_pc (this_frame
);
2898 if (mips_pc_is_mips16 (gdbarch
, pc
))
2903 static const struct frame_unwind mips_insn16_frame_unwind
=
2906 default_frame_unwind_stop_reason
,
2907 mips_insn16_frame_this_id
,
2908 mips_insn16_frame_prev_register
,
2910 mips_insn16_frame_sniffer
2914 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2917 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2922 static const struct frame_base mips_insn16_frame_base
=
2924 &mips_insn16_frame_unwind
,
2925 mips_insn16_frame_base_address
,
2926 mips_insn16_frame_base_address
,
2927 mips_insn16_frame_base_address
2930 static const struct frame_base
*
2931 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2933 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2934 CORE_ADDR pc
= get_frame_pc (this_frame
);
2935 if (mips_pc_is_mips16 (gdbarch
, pc
))
2936 return &mips_insn16_frame_base
;
2941 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2942 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2943 interpreted directly, and then multiplied by 4. */
2946 micromips_decode_imm9 (int imm
)
2948 imm
= (imm
^ 0x100) - 0x100;
2949 if (imm
> -3 && imm
< 2)
2954 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2955 the address of the first instruction past the prologue. */
2958 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2959 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2960 struct frame_info
*this_frame
,
2961 struct mips_frame_cache
*this_cache
)
2963 CORE_ADDR end_prologue_addr
;
2964 int prev_non_prologue_insn
= 0;
2965 int frame_reg
= MIPS_SP_REGNUM
;
2966 int this_non_prologue_insn
;
2967 int non_prologue_insns
= 0;
2968 long frame_offset
= 0; /* Size of stack frame. */
2969 long frame_adjust
= 0; /* Offset of FP from SP. */
2970 int prev_delay_slot
= 0;
2974 ULONGEST insn
; /* current instruction */
2978 long v1_off
= 0; /* The assumption is LUI will replace it. */
2989 /* Can be called when there's no process, and hence when there's no
2991 if (this_frame
!= NULL
)
2992 sp
= get_frame_register_signed (this_frame
,
2993 gdbarch_num_regs (gdbarch
)
2998 if (limit_pc
> start_pc
+ 200)
2999 limit_pc
= start_pc
+ 200;
3002 /* Permit at most one non-prologue non-control-transfer instruction
3003 in the middle which may have been reordered by the compiler for
3005 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3007 this_non_prologue_insn
= 0;
3011 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3012 loc
+= MIPS_INSN16_SIZE
;
3013 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3015 /* 32-bit instructions. */
3016 case 2 * MIPS_INSN16_SIZE
:
3018 insn
|= mips_fetch_instruction (gdbarch
,
3019 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3020 loc
+= MIPS_INSN16_SIZE
;
3021 switch (micromips_op (insn
>> 16))
3023 /* Record $sp/$fp adjustment. */
3024 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3025 case 0x0: /* POOL32A: bits 000000 */
3026 case 0x16: /* POOL32S: bits 010110 */
3027 op
= b0s11_op (insn
);
3028 sreg
= b0s5_reg (insn
>> 16);
3029 treg
= b5s5_reg (insn
>> 16);
3030 dreg
= b11s5_reg (insn
);
3032 /* SUBU: bits 000000 00111010000 */
3033 /* DSUBU: bits 010110 00111010000 */
3034 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3036 /* (D)SUBU $sp, $v1 */
3038 else if (op
!= 0x150
3039 /* ADDU: bits 000000 00101010000 */
3040 /* DADDU: bits 010110 00101010000 */
3041 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3042 this_non_prologue_insn
= 1;
3045 case 0x8: /* POOL32B: bits 001000 */
3046 op
= b12s4_op (insn
);
3047 breg
= b0s5_reg (insn
>> 16);
3048 reglist
= sreg
= b5s5_reg (insn
>> 16);
3049 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3050 if ((op
== 0x9 || op
== 0xc)
3051 /* SWP: bits 001000 1001 */
3052 /* SDP: bits 001000 1100 */
3053 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3054 /* S[DW]P reg,offset($sp) */
3056 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3057 set_reg_offset (gdbarch
, this_cache
,
3059 set_reg_offset (gdbarch
, this_cache
,
3060 sreg
+ 1, sp
+ offset
+ s
);
3062 else if ((op
== 0xd || op
== 0xf)
3063 /* SWM: bits 001000 1101 */
3064 /* SDM: bits 001000 1111 */
3065 && breg
== MIPS_SP_REGNUM
3066 /* SWM reglist,offset($sp) */
3067 && ((reglist
>= 1 && reglist
<= 9)
3068 || (reglist
>= 16 && reglist
<= 25)))
3070 int sreglist
= std::min(reglist
& 0xf, 8);
3072 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3073 for (i
= 0; i
< sreglist
; i
++)
3074 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3075 if ((reglist
& 0xf) > 8)
3076 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3077 if ((reglist
& 0x10) == 0x10)
3078 set_reg_offset (gdbarch
, this_cache
,
3079 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3082 this_non_prologue_insn
= 1;
3085 /* Record $sp/$fp adjustment. */
3086 /* Discard (D)ADDIU $gp used for PIC code. */
3087 case 0xc: /* ADDIU: bits 001100 */
3088 case 0x17: /* DADDIU: bits 010111 */
3089 sreg
= b0s5_reg (insn
>> 16);
3090 dreg
= b5s5_reg (insn
>> 16);
3091 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3092 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3093 /* (D)ADDIU $sp, imm */
3095 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3096 /* (D)ADDIU $fp, $sp, imm */
3098 frame_adjust
= offset
;
3101 else if (sreg
!= 28 || dreg
!= 28)
3102 /* (D)ADDIU $gp, imm */
3103 this_non_prologue_insn
= 1;
3106 /* LUI $v1 is used for larger $sp adjustments. */
3107 /* Discard LUI $gp used for PIC code. */
3108 case 0x10: /* POOL32I: bits 010000 */
3109 if (b5s5_op (insn
>> 16) == 0xd
3110 /* LUI: bits 010000 001101 */
3111 && b0s5_reg (insn
>> 16) == 3)
3113 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3114 else if (b5s5_op (insn
>> 16) != 0xd
3115 /* LUI: bits 010000 001101 */
3116 || b0s5_reg (insn
>> 16) != 28)
3118 this_non_prologue_insn
= 1;
3121 /* ORI $v1 is used for larger $sp adjustments. */
3122 case 0x14: /* ORI: bits 010100 */
3123 sreg
= b0s5_reg (insn
>> 16);
3124 dreg
= b5s5_reg (insn
>> 16);
3125 if (sreg
== 3 && dreg
== 3)
3127 v1_off
|= b0s16_imm (insn
);
3129 this_non_prologue_insn
= 1;
3132 case 0x26: /* SWC1: bits 100110 */
3133 case 0x2e: /* SDC1: bits 101110 */
3134 breg
= b0s5_reg (insn
>> 16);
3135 if (breg
!= MIPS_SP_REGNUM
)
3136 /* S[DW]C1 reg,offset($sp) */
3137 this_non_prologue_insn
= 1;
3140 case 0x36: /* SD: bits 110110 */
3141 case 0x3e: /* SW: bits 111110 */
3142 breg
= b0s5_reg (insn
>> 16);
3143 sreg
= b5s5_reg (insn
>> 16);
3144 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3145 if (breg
== MIPS_SP_REGNUM
)
3146 /* S[DW] reg,offset($sp) */
3147 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3149 this_non_prologue_insn
= 1;
3153 /* The instruction in the delay slot can be a part
3154 of the prologue, so move forward once more. */
3155 if (micromips_instruction_has_delay_slot (insn
, 0))
3158 this_non_prologue_insn
= 1;
3164 /* 16-bit instructions. */
3165 case MIPS_INSN16_SIZE
:
3166 switch (micromips_op (insn
))
3168 case 0x3: /* MOVE: bits 000011 */
3169 sreg
= b0s5_reg (insn
);
3170 dreg
= b5s5_reg (insn
);
3171 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3174 else if ((sreg
& 0x1c) != 0x4)
3175 /* MOVE reg, $a0-$a3 */
3176 this_non_prologue_insn
= 1;
3179 case 0x11: /* POOL16C: bits 010001 */
3180 if (b6s4_op (insn
) == 0x5)
3181 /* SWM: bits 010001 0101 */
3183 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3184 reglist
= b4s2_regl (insn
);
3185 for (i
= 0; i
<= reglist
; i
++)
3186 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3187 set_reg_offset (gdbarch
, this_cache
,
3188 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3191 this_non_prologue_insn
= 1;
3194 case 0x13: /* POOL16D: bits 010011 */
3195 if ((insn
& 0x1) == 0x1)
3196 /* ADDIUSP: bits 010011 1 */
3197 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3198 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3199 /* ADDIUS5: bits 010011 0 */
3200 /* ADDIUS5 $sp, imm */
3201 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3203 this_non_prologue_insn
= 1;
3206 case 0x32: /* SWSP: bits 110010 */
3207 offset
= b0s5_imm (insn
) << 2;
3208 sreg
= b5s5_reg (insn
);
3209 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3213 /* The instruction in the delay slot can be a part
3214 of the prologue, so move forward once more. */
3215 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3218 this_non_prologue_insn
= 1;
3224 frame_offset
-= sp_adj
;
3226 non_prologue_insns
+= this_non_prologue_insn
;
3228 /* A jump or branch, enough non-prologue insns seen or positive
3229 stack adjustment? If so, then we must have reached the end
3230 of the prologue by now. */
3231 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3232 || micromips_instruction_is_compact_branch (insn
))
3235 prev_non_prologue_insn
= this_non_prologue_insn
;
3236 prev_delay_slot
= in_delay_slot
;
3240 if (this_cache
!= NULL
)
3243 (get_frame_register_signed (this_frame
,
3244 gdbarch_num_regs (gdbarch
) + frame_reg
)
3245 + frame_offset
- frame_adjust
);
3246 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3247 be able to get rid of the assignment below, evetually. But it's
3248 still needed for now. */
3249 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3250 + mips_regnum (gdbarch
)->pc
]
3251 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3254 /* Set end_prologue_addr to the address of the instruction immediately
3255 after the last one we scanned. Unless the last one looked like a
3256 non-prologue instruction (and we looked ahead), in which case use
3257 its address instead. */
3259 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3261 return end_prologue_addr
;
3264 /* Heuristic unwinder for procedures using microMIPS instructions.
3265 Procedures that use the 32-bit instruction set are handled by the
3266 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3268 static struct mips_frame_cache
*
3269 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3271 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3272 struct mips_frame_cache
*cache
;
3274 if ((*this_cache
) != NULL
)
3275 return (struct mips_frame_cache
*) (*this_cache
);
3277 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3278 (*this_cache
) = cache
;
3279 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3281 /* Analyze the function prologue. */
3283 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3284 CORE_ADDR start_addr
;
3286 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3287 if (start_addr
== 0)
3288 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3289 /* We can't analyze the prologue if we couldn't find the begining
3291 if (start_addr
== 0)
3294 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3295 (struct mips_frame_cache
*) *this_cache
);
3298 /* gdbarch_sp_regnum contains the value and not the address. */
3299 trad_frame_set_value (cache
->saved_regs
,
3300 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3303 return (struct mips_frame_cache
*) (*this_cache
);
3307 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3308 struct frame_id
*this_id
)
3310 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3312 /* This marks the outermost frame. */
3313 if (info
->base
== 0)
3315 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3318 static struct value
*
3319 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3320 void **this_cache
, int regnum
)
3322 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3324 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3328 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3329 struct frame_info
*this_frame
, void **this_cache
)
3331 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3332 CORE_ADDR pc
= get_frame_pc (this_frame
);
3334 if (mips_pc_is_micromips (gdbarch
, pc
))
3339 static const struct frame_unwind mips_micro_frame_unwind
=
3342 default_frame_unwind_stop_reason
,
3343 mips_micro_frame_this_id
,
3344 mips_micro_frame_prev_register
,
3346 mips_micro_frame_sniffer
3350 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3353 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3358 static const struct frame_base mips_micro_frame_base
=
3360 &mips_micro_frame_unwind
,
3361 mips_micro_frame_base_address
,
3362 mips_micro_frame_base_address
,
3363 mips_micro_frame_base_address
3366 static const struct frame_base
*
3367 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3369 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3370 CORE_ADDR pc
= get_frame_pc (this_frame
);
3372 if (mips_pc_is_micromips (gdbarch
, pc
))
3373 return &mips_micro_frame_base
;
3378 /* Mark all the registers as unset in the saved_regs array
3379 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3382 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3384 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3388 const int num_regs
= gdbarch_num_regs (gdbarch
);
3391 for (i
= 0; i
< num_regs
; i
++)
3393 this_cache
->saved_regs
[i
].addr
= -1;
3398 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3399 the associated FRAME_CACHE if not null.
3400 Return the address of the first instruction past the prologue. */
3403 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3404 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3405 struct frame_info
*this_frame
,
3406 struct mips_frame_cache
*this_cache
)
3408 int prev_non_prologue_insn
;
3409 int this_non_prologue_insn
;
3410 int non_prologue_insns
;
3411 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3413 int prev_delay_slot
;
3418 int frame_reg
= MIPS_SP_REGNUM
;
3420 CORE_ADDR end_prologue_addr
;
3421 int seen_sp_adjust
= 0;
3422 int load_immediate_bytes
= 0;
3424 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3426 /* Can be called when there's no process, and hence when there's no
3428 if (this_frame
!= NULL
)
3429 sp
= get_frame_register_signed (this_frame
,
3430 gdbarch_num_regs (gdbarch
)
3435 if (limit_pc
> start_pc
+ 200)
3436 limit_pc
= start_pc
+ 200;
3439 prev_non_prologue_insn
= 0;
3440 non_prologue_insns
= 0;
3441 prev_delay_slot
= 0;
3444 /* Permit at most one non-prologue non-control-transfer instruction
3445 in the middle which may have been reordered by the compiler for
3448 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3450 unsigned long inst
, high_word
;
3454 this_non_prologue_insn
= 0;
3457 /* Fetch the instruction. */
3458 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3461 /* Save some code by pre-extracting some useful fields. */
3462 high_word
= (inst
>> 16) & 0xffff;
3463 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3464 reg
= high_word
& 0x1f;
3466 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3467 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3468 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3470 if (offset
< 0) /* Negative stack adjustment? */
3471 frame_offset
-= offset
;
3473 /* Exit loop if a positive stack adjustment is found, which
3474 usually means that the stack cleanup code in the function
3475 epilogue is reached. */
3479 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3480 && !regsize_is_64_bits
)
3482 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3484 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3485 && regsize_is_64_bits
)
3487 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3488 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3490 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3492 /* Old gcc frame, r30 is virtual frame pointer. */
3493 if (offset
!= frame_offset
)
3494 frame_addr
= sp
+ offset
;
3495 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3497 unsigned alloca_adjust
;
3500 frame_addr
= get_frame_register_signed
3501 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3504 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3505 if (alloca_adjust
> 0)
3507 /* FP > SP + frame_size. This may be because of
3508 an alloca or somethings similar. Fix sp to
3509 "pre-alloca" value, and try again. */
3510 sp
+= alloca_adjust
;
3511 /* Need to reset the status of all registers. Otherwise,
3512 we will hit a guard that prevents the new address
3513 for each register to be recomputed during the second
3515 reset_saved_regs (gdbarch
, this_cache
);
3520 /* move $30,$sp. With different versions of gas this will be either
3521 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3522 Accept any one of these. */
3523 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3525 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3526 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3528 unsigned alloca_adjust
;
3531 frame_addr
= get_frame_register_signed
3532 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3534 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3535 if (alloca_adjust
> 0)
3537 /* FP > SP + frame_size. This may be because of
3538 an alloca or somethings similar. Fix sp to
3539 "pre-alloca" value, and try again. */
3541 /* Need to reset the status of all registers. Otherwise,
3542 we will hit a guard that prevents the new address
3543 for each register to be recomputed during the second
3545 reset_saved_regs (gdbarch
, this_cache
);
3550 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3551 && !regsize_is_64_bits
)
3553 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3555 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3556 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3557 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3558 || high_word
== 0x3c1c /* lui $gp,n */
3559 || high_word
== 0x279c /* addiu $gp,$gp,n */
3560 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3561 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3564 /* These instructions are part of the prologue, but we don't
3565 need to do anything special to handle them. */
3567 /* The instructions below load $at or $t0 with an immediate
3568 value in preparation for a stack adjustment via
3569 subu $sp,$sp,[$at,$t0]. These instructions could also
3570 initialize a local variable, so we accept them only before
3571 a stack adjustment instruction was seen. */
3572 else if (!seen_sp_adjust
3574 && (high_word
== 0x3c01 /* lui $at,n */
3575 || high_word
== 0x3c08 /* lui $t0,n */
3576 || high_word
== 0x3421 /* ori $at,$at,n */
3577 || high_word
== 0x3508 /* ori $t0,$t0,n */
3578 || high_word
== 0x3401 /* ori $at,$zero,n */
3579 || high_word
== 0x3408 /* ori $t0,$zero,n */
3582 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3584 /* Check for branches and jumps. The instruction in the delay
3585 slot can be a part of the prologue, so move forward once more. */
3586 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3590 /* This instruction is not an instruction typically found
3591 in a prologue, so we must have reached the end of the
3595 this_non_prologue_insn
= 1;
3598 non_prologue_insns
+= this_non_prologue_insn
;
3600 /* A jump or branch, or enough non-prologue insns seen? If so,
3601 then we must have reached the end of the prologue by now. */
3602 if (prev_delay_slot
|| non_prologue_insns
> 1)
3605 prev_non_prologue_insn
= this_non_prologue_insn
;
3606 prev_delay_slot
= in_delay_slot
;
3610 if (this_cache
!= NULL
)
3613 (get_frame_register_signed (this_frame
,
3614 gdbarch_num_regs (gdbarch
) + frame_reg
)
3616 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3617 this assignment below, eventually. But it's still needed
3619 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3620 + mips_regnum (gdbarch
)->pc
]
3621 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3625 /* Set end_prologue_addr to the address of the instruction immediately
3626 after the last one we scanned. Unless the last one looked like a
3627 non-prologue instruction (and we looked ahead), in which case use
3628 its address instead. */
3630 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3632 /* In a frameless function, we might have incorrectly
3633 skipped some load immediate instructions. Undo the skipping
3634 if the load immediate was not followed by a stack adjustment. */
3635 if (load_immediate_bytes
&& !seen_sp_adjust
)
3636 end_prologue_addr
-= load_immediate_bytes
;
3638 return end_prologue_addr
;
3641 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3642 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3643 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3644 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3646 static struct mips_frame_cache
*
3647 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3649 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3650 struct mips_frame_cache
*cache
;
3652 if ((*this_cache
) != NULL
)
3653 return (struct mips_frame_cache
*) (*this_cache
);
3655 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3656 (*this_cache
) = cache
;
3657 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3659 /* Analyze the function prologue. */
3661 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3662 CORE_ADDR start_addr
;
3664 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3665 if (start_addr
== 0)
3666 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3667 /* We can't analyze the prologue if we couldn't find the begining
3669 if (start_addr
== 0)
3672 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3673 (struct mips_frame_cache
*) *this_cache
);
3676 /* gdbarch_sp_regnum contains the value and not the address. */
3677 trad_frame_set_value (cache
->saved_regs
,
3678 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3681 return (struct mips_frame_cache
*) (*this_cache
);
3685 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3686 struct frame_id
*this_id
)
3688 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3690 /* This marks the outermost frame. */
3691 if (info
->base
== 0)
3693 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3696 static struct value
*
3697 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3698 void **this_cache
, int regnum
)
3700 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3702 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3706 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3707 struct frame_info
*this_frame
, void **this_cache
)
3709 CORE_ADDR pc
= get_frame_pc (this_frame
);
3710 if (mips_pc_is_mips (pc
))
3715 static const struct frame_unwind mips_insn32_frame_unwind
=
3718 default_frame_unwind_stop_reason
,
3719 mips_insn32_frame_this_id
,
3720 mips_insn32_frame_prev_register
,
3722 mips_insn32_frame_sniffer
3726 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3729 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3734 static const struct frame_base mips_insn32_frame_base
=
3736 &mips_insn32_frame_unwind
,
3737 mips_insn32_frame_base_address
,
3738 mips_insn32_frame_base_address
,
3739 mips_insn32_frame_base_address
3742 static const struct frame_base
*
3743 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3745 CORE_ADDR pc
= get_frame_pc (this_frame
);
3746 if (mips_pc_is_mips (pc
))
3747 return &mips_insn32_frame_base
;
3752 static struct trad_frame_cache
*
3753 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3756 CORE_ADDR start_addr
;
3757 CORE_ADDR stack_addr
;
3758 struct trad_frame_cache
*this_trad_cache
;
3759 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3760 int num_regs
= gdbarch_num_regs (gdbarch
);
3762 if ((*this_cache
) != NULL
)
3763 return (struct trad_frame_cache
*) (*this_cache
);
3764 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3765 (*this_cache
) = this_trad_cache
;
3767 /* The return address is in the link register. */
3768 trad_frame_set_reg_realreg (this_trad_cache
,
3769 gdbarch_pc_regnum (gdbarch
),
3770 num_regs
+ MIPS_RA_REGNUM
);
3772 /* Frame ID, since it's a frameless / stackless function, no stack
3773 space is allocated and SP on entry is the current SP. */
3774 pc
= get_frame_pc (this_frame
);
3775 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3776 stack_addr
= get_frame_register_signed (this_frame
,
3777 num_regs
+ MIPS_SP_REGNUM
);
3778 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3780 /* Assume that the frame's base is the same as the
3782 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3784 return this_trad_cache
;
3788 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3789 struct frame_id
*this_id
)
3791 struct trad_frame_cache
*this_trad_cache
3792 = mips_stub_frame_cache (this_frame
, this_cache
);
3793 trad_frame_get_id (this_trad_cache
, this_id
);
3796 static struct value
*
3797 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3798 void **this_cache
, int regnum
)
3800 struct trad_frame_cache
*this_trad_cache
3801 = mips_stub_frame_cache (this_frame
, this_cache
);
3802 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3806 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3807 struct frame_info
*this_frame
, void **this_cache
)
3810 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3811 struct bound_minimal_symbol msym
;
3813 /* Use the stub unwinder for unreadable code. */
3814 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3817 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3820 /* Calling a PIC function from a non-PIC function passes through a
3821 stub. The stub for foo is named ".pic.foo". */
3822 msym
= lookup_minimal_symbol_by_pc (pc
);
3823 if (msym
.minsym
!= NULL
3824 && msym
.minsym
->linkage_name () != NULL
3825 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3831 static const struct frame_unwind mips_stub_frame_unwind
=
3834 default_frame_unwind_stop_reason
,
3835 mips_stub_frame_this_id
,
3836 mips_stub_frame_prev_register
,
3838 mips_stub_frame_sniffer
3842 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3845 struct trad_frame_cache
*this_trad_cache
3846 = mips_stub_frame_cache (this_frame
, this_cache
);
3847 return trad_frame_get_this_base (this_trad_cache
);
3850 static const struct frame_base mips_stub_frame_base
=
3852 &mips_stub_frame_unwind
,
3853 mips_stub_frame_base_address
,
3854 mips_stub_frame_base_address
,
3855 mips_stub_frame_base_address
3858 static const struct frame_base
*
3859 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3861 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3862 return &mips_stub_frame_base
;
3867 /* mips_addr_bits_remove - remove useless address bits */
3870 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3872 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3874 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3875 /* This hack is a work-around for existing boards using PMON, the
3876 simulator, and any other 64-bit targets that doesn't have true
3877 64-bit addressing. On these targets, the upper 32 bits of
3878 addresses are ignored by the hardware. Thus, the PC or SP are
3879 likely to have been sign extended to all 1s by instruction
3880 sequences that load 32-bit addresses. For example, a typical
3881 piece of code that loads an address is this:
3883 lui $r2, <upper 16 bits>
3884 ori $r2, <lower 16 bits>
3886 But the lui sign-extends the value such that the upper 32 bits
3887 may be all 1s. The workaround is simply to mask off these
3888 bits. In the future, gcc may be changed to support true 64-bit
3889 addressing, and this masking will have to be disabled. */
3890 return addr
&= 0xffffffffUL
;
3896 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3897 instruction and ending with a SC/SCD instruction. If such a sequence
3898 is found, attempt to step through it. A breakpoint is placed at the end of
3901 /* Instructions used during single-stepping of atomic sequences, standard
3903 #define LL_OPCODE 0x30
3904 #define LLD_OPCODE 0x34
3905 #define SC_OPCODE 0x38
3906 #define SCD_OPCODE 0x3c
3908 static std::vector
<CORE_ADDR
>
3909 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3911 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3913 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3917 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3918 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3920 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3921 /* Assume all atomic sequences start with a ll/lld instruction. */
3922 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3925 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3927 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3930 loc
+= MIPS_INSN32_SIZE
;
3931 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3933 /* Assume that there is at most one branch in the atomic
3934 sequence. If a branch is found, put a breakpoint in its
3935 destination address. */
3936 switch (itype_op (insn
))
3938 case 0: /* SPECIAL */
3939 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3940 return {}; /* fallback to the standard single-step code. */
3942 case 1: /* REGIMM */
3943 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3944 || ((itype_rt (insn
) & 0x1e) == 0
3945 && itype_rs (insn
) == 0)); /* BPOSGE* */
3949 return {}; /* fallback to the standard single-step code. */
3956 case 22: /* BLEZL */
3957 case 23: /* BGTTL */
3961 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3962 && (itype_rt (insn
) & 0x2) == 0);
3963 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3968 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3973 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3974 if (last_breakpoint
>= 1)
3975 return {}; /* More than one branch found, fallback to the
3976 standard single-step code. */
3977 breaks
[1] = branch_bp
;
3981 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3985 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3986 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3989 loc
+= MIPS_INSN32_SIZE
;
3991 /* Insert a breakpoint right after the end of the atomic sequence. */
3994 /* Check for duplicated breakpoints. Check also for a breakpoint
3995 placed (branch instruction's destination) in the atomic sequence. */
3996 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3997 last_breakpoint
= 0;
3999 std::vector
<CORE_ADDR
> next_pcs
;
4001 /* Effectively inserts the breakpoints. */
4002 for (index
= 0; index
<= last_breakpoint
; index
++)
4003 next_pcs
.push_back (breaks
[index
]);
4008 static std::vector
<CORE_ADDR
>
4009 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4012 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4013 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4014 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4015 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4023 /* Assume all atomic sequences start with a ll/lld instruction. */
4024 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4025 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4027 loc
+= MIPS_INSN16_SIZE
;
4029 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4030 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4032 loc
+= MIPS_INSN16_SIZE
;
4034 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4035 that no atomic sequence is longer than "atomic_sequence_length"
4037 for (insn_count
= 0;
4038 !sc_found
&& insn_count
< atomic_sequence_length
;
4043 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4044 loc
+= MIPS_INSN16_SIZE
;
4046 /* Assume that there is at most one conditional branch in the
4047 atomic sequence. If a branch is found, put a breakpoint in
4048 its destination address. */
4049 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4051 /* 32-bit instructions. */
4052 case 2 * MIPS_INSN16_SIZE
:
4053 switch (micromips_op (insn
))
4055 case 0x10: /* POOL32I: bits 010000 */
4056 if ((b5s5_op (insn
) & 0x18) != 0x0
4057 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4058 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4059 && (b5s5_op (insn
) & 0x1d) != 0x11
4060 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4061 && ((b5s5_op (insn
) & 0x1e) != 0x14
4062 || (insn
& 0x3) != 0x0)
4063 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4064 && (b5s5_op (insn
) & 0x1e) != 0x1a
4065 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4066 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4067 || (insn
& 0x3) != 0x0)
4068 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4069 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4070 || (insn
& 0x3) != 0x1))
4071 /* BC1ANY*: bits 010000 111xx xxx01 */
4075 case 0x25: /* BEQ: bits 100101 */
4076 case 0x2d: /* BNE: bits 101101 */
4078 insn
|= mips_fetch_instruction (gdbarch
,
4079 ISA_MICROMIPS
, loc
, NULL
);
4080 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4081 + micromips_relative_offset16 (insn
));
4085 case 0x00: /* POOL32A: bits 000000 */
4087 insn
|= mips_fetch_instruction (gdbarch
,
4088 ISA_MICROMIPS
, loc
, NULL
);
4089 if (b0s6_op (insn
) != 0x3c
4090 /* POOL32Axf: bits 000000 ... 111100 */
4091 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4092 /* JALR, JALR.HB: 000000 000x111100 111100 */
4093 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4097 case 0x1d: /* JALS: bits 011101 */
4098 case 0x35: /* J: bits 110101 */
4099 case 0x3d: /* JAL: bits 111101 */
4100 case 0x3c: /* JALX: bits 111100 */
4101 return {}; /* Fall back to the standard single-step code. */
4103 case 0x18: /* POOL32C: bits 011000 */
4104 if ((b12s4_op (insn
) & 0xb) == 0xb)
4105 /* SC, SCD: bits 011000 1x11 */
4109 loc
+= MIPS_INSN16_SIZE
;
4112 /* 16-bit instructions. */
4113 case MIPS_INSN16_SIZE
:
4114 switch (micromips_op (insn
))
4116 case 0x23: /* BEQZ16: bits 100011 */
4117 case 0x2b: /* BNEZ16: bits 101011 */
4118 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4122 case 0x11: /* POOL16C: bits 010001 */
4123 if ((b5s5_op (insn
) & 0x1c) != 0xc
4124 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4125 && b5s5_op (insn
) != 0x18)
4126 /* JRADDIUSP: bits 010001 11000 */
4128 return {}; /* Fall back to the standard single-step code. */
4130 case 0x33: /* B16: bits 110011 */
4131 return {}; /* Fall back to the standard single-step code. */
4137 if (last_breakpoint
>= 1)
4138 return {}; /* More than one branch found, fallback to the
4139 standard single-step code. */
4140 breaks
[1] = branch_bp
;
4147 /* Insert a breakpoint right after the end of the atomic sequence. */
4150 /* Check for duplicated breakpoints. Check also for a breakpoint
4151 placed (branch instruction's destination) in the atomic sequence */
4152 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4153 last_breakpoint
= 0;
4155 std::vector
<CORE_ADDR
> next_pcs
;
4157 /* Effectively inserts the breakpoints. */
4158 for (index
= 0; index
<= last_breakpoint
; index
++)
4159 next_pcs
.push_back (breaks
[index
]);
4164 static std::vector
<CORE_ADDR
>
4165 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4167 if (mips_pc_is_mips (pc
))
4168 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4169 else if (mips_pc_is_micromips (gdbarch
, pc
))
4170 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4175 /* mips_software_single_step() is called just before we want to resume
4176 the inferior, if we want to single-step it but there is no hardware
4177 or kernel single-step support (MIPS on GNU/Linux for example). We find
4178 the target of the coming instruction and breakpoint it. */
4180 std::vector
<CORE_ADDR
>
4181 mips_software_single_step (struct regcache
*regcache
)
4183 struct gdbarch
*gdbarch
= regcache
->arch ();
4184 CORE_ADDR pc
, next_pc
;
4186 pc
= regcache_read_pc (regcache
);
4187 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4189 if (!next_pcs
.empty ())
4192 next_pc
= mips_next_pc (regcache
, pc
);
4197 /* Test whether the PC points to the return instruction at the
4198 end of a function. */
4201 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4206 /* This used to check for MIPS16, but this piece of code is never
4207 called for MIPS16 functions. And likewise microMIPS ones. */
4208 gdb_assert (mips_pc_is_mips (pc
));
4210 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4212 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4216 /* This fencepost looks highly suspicious to me. Removing it also
4217 seems suspicious as it could affect remote debugging across serial
4221 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4227 struct inferior
*inf
;
4229 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4231 fence
= start_pc
- heuristic_fence_post
;
4235 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4236 fence
= VM_MIN_ADDRESS
;
4238 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4240 inf
= current_inferior ();
4242 /* Search back for previous return. */
4243 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4244 if (start_pc
< fence
)
4246 /* It's not clear to me why we reach this point when
4247 stop_soon, but with this test, at least we
4248 don't print out warnings for every child forked (eg, on
4249 decstation). 22apr93 rich@cygnus.com. */
4250 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4252 static int blurb_printed
= 0;
4254 warning (_("GDB can't find the start of the function at %s."),
4255 paddress (gdbarch
, pc
));
4259 /* This actually happens frequently in embedded
4260 development, when you first connect to a board
4261 and your stack pointer and pc are nowhere in
4262 particular. This message needs to give people
4263 in that situation enough information to
4264 determine that it's no big deal. */
4265 printf_filtered ("\n\
4266 GDB is unable to find the start of the function at %s\n\
4267 and thus can't determine the size of that function's stack frame.\n\
4268 This means that GDB may be unable to access that stack frame, or\n\
4269 the frames below it.\n\
4270 This problem is most likely caused by an invalid program counter or\n\
4272 However, if you think GDB should simply search farther back\n\
4273 from %s for code which looks like the beginning of a\n\
4274 function, you can increase the range of the search using the `set\n\
4275 heuristic-fence-post' command.\n",
4276 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4283 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4285 unsigned short inst
;
4287 /* On MIPS16, any one of the following is likely to be the
4288 start of a function:
4294 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4295 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4296 if ((inst
& 0xff80) == 0x6480) /* save */
4298 if (start_pc
- instlen
>= fence
)
4300 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4301 start_pc
- instlen
, NULL
);
4302 if ((inst
& 0xf800) == 0xf000) /* extend */
4303 start_pc
-= instlen
;
4307 else if (((inst
& 0xf81f) == 0xe809
4308 && (inst
& 0x700) != 0x700) /* entry */
4309 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4310 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4311 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4313 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4314 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4319 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4327 /* On microMIPS, any one of the following is likely to be the
4328 start of a function:
4332 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4333 switch (micromips_op (insn
))
4335 case 0xc: /* ADDIU: bits 001100 */
4336 case 0x17: /* DADDIU: bits 010111 */
4337 sreg
= b0s5_reg (insn
);
4338 dreg
= b5s5_reg (insn
);
4340 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4341 pc
+ MIPS_INSN16_SIZE
, NULL
);
4342 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4343 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4344 /* (D)ADDIU $sp, imm */
4349 case 0x10: /* POOL32I: bits 010000 */
4350 if (b5s5_op (insn
) == 0xd
4351 /* LUI: bits 010000 001101 */
4352 && b0s5_reg (insn
>> 16) == 28)
4357 case 0x13: /* POOL16D: bits 010011 */
4358 if ((insn
& 0x1) == 0x1)
4359 /* ADDIUSP: bits 010011 1 */
4361 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4367 /* ADDIUS5: bits 010011 0 */
4369 dreg
= b5s5_reg (insn
);
4370 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4371 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4372 /* ADDIUS5 $sp, -imm */
4380 else if (mips_about_to_return (gdbarch
, start_pc
))
4382 /* Skip return and its delay slot. */
4383 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4390 struct mips_objfile_private
4396 /* According to the current ABI, should the type be passed in a
4397 floating-point register (assuming that there is space)? When there
4398 is no FPU, FP are not even considered as possible candidates for
4399 FP registers and, consequently this returns false - forces FP
4400 arguments into integer registers. */
4403 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4404 struct type
*arg_type
)
4406 return ((typecode
== TYPE_CODE_FLT
4407 || (MIPS_EABI (gdbarch
)
4408 && (typecode
== TYPE_CODE_STRUCT
4409 || typecode
== TYPE_CODE_UNION
)
4410 && arg_type
->num_fields () == 1
4411 && check_typedef (arg_type
->field (0).type ())->code ()
4413 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4416 /* On o32, argument passing in GPRs depends on the alignment of the type being
4417 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4420 mips_type_needs_double_align (struct type
*type
)
4422 enum type_code typecode
= type
->code ();
4424 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4426 else if (typecode
== TYPE_CODE_STRUCT
)
4428 if (type
->num_fields () < 1)
4430 return mips_type_needs_double_align (type
->field (0).type ());
4432 else if (typecode
== TYPE_CODE_UNION
)
4436 n
= type
->num_fields ();
4437 for (i
= 0; i
< n
; i
++)
4438 if (mips_type_needs_double_align (type
->field (i
).type ()))
4445 /* Adjust the address downward (direction of stack growth) so that it
4446 is correctly aligned for a new stack frame. */
4448 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4450 return align_down (addr
, 16);
4453 /* Implement the "push_dummy_code" gdbarch method. */
4456 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4457 CORE_ADDR funaddr
, struct value
**args
,
4458 int nargs
, struct type
*value_type
,
4459 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4460 struct regcache
*regcache
)
4462 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4466 /* Reserve enough room on the stack for our breakpoint instruction. */
4467 bp_slot
= sp
- sizeof (nop_insn
);
4469 /* Return to microMIPS mode if calling microMIPS code to avoid
4470 triggering an address error exception on processors that only
4471 support microMIPS execution. */
4472 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4473 ? make_compact_addr (bp_slot
) : bp_slot
);
4475 /* The breakpoint layer automatically adjusts the address of
4476 breakpoints inserted in a branch delay slot. With enough
4477 bad luck, the 4 bytes located just before our breakpoint
4478 instruction could look like a branch instruction, and thus
4479 trigger the adjustement, and break the function call entirely.
4480 So, we reserve those 4 bytes and write a nop instruction
4481 to prevent that from happening. */
4482 nop_addr
= bp_slot
- sizeof (nop_insn
);
4483 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4484 sp
= mips_frame_align (gdbarch
, nop_addr
);
4486 /* Inferior resumes at the function entry point. */
4493 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4494 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4495 int nargs
, struct value
**args
, CORE_ADDR sp
,
4496 function_call_return_method return_method
,
4497 CORE_ADDR struct_addr
)
4503 int stack_offset
= 0;
4504 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4505 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4506 int abi_regsize
= mips_abi_regsize (gdbarch
);
4508 /* For shared libraries, "t9" needs to point at the function
4510 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4512 /* Set the return address register to point to the entry point of
4513 the program, where a breakpoint lies in wait. */
4514 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4516 /* First ensure that the stack and structure return address (if any)
4517 are properly aligned. The stack has to be at least 64-bit
4518 aligned even on 32-bit machines, because doubles must be 64-bit
4519 aligned. For n32 and n64, stack frames need to be 128-bit
4520 aligned, so we round to this widest known alignment. */
4522 sp
= align_down (sp
, 16);
4523 struct_addr
= align_down (struct_addr
, 16);
4525 /* Now make space on the stack for the args. We allocate more
4526 than necessary for EABI, because the first few arguments are
4527 passed in registers, but that's OK. */
4528 for (argnum
= 0; argnum
< nargs
; argnum
++)
4529 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4530 sp
-= align_up (arg_space
, 16);
4533 fprintf_unfiltered (gdb_stdlog
,
4534 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4535 paddress (gdbarch
, sp
),
4536 (long) align_up (arg_space
, 16));
4538 /* Initialize the integer and float register pointers. */
4539 argreg
= MIPS_A0_REGNUM
;
4540 float_argreg
= mips_fpa0_regnum (gdbarch
);
4542 /* The struct_return pointer occupies the first parameter-passing reg. */
4543 if (return_method
== return_method_struct
)
4546 fprintf_unfiltered (gdb_stdlog
,
4547 "mips_eabi_push_dummy_call: "
4548 "struct_return reg=%d %s\n",
4549 argreg
, paddress (gdbarch
, struct_addr
));
4550 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4553 /* Now load as many as possible of the first arguments into
4554 registers, and push the rest onto the stack. Loop thru args
4555 from first to last. */
4556 for (argnum
= 0; argnum
< nargs
; argnum
++)
4558 const gdb_byte
*val
;
4559 /* This holds the address of structures that are passed by
4561 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4562 struct value
*arg
= args
[argnum
];
4563 struct type
*arg_type
= check_typedef (value_type (arg
));
4564 int len
= TYPE_LENGTH (arg_type
);
4565 enum type_code typecode
= arg_type
->code ();
4568 fprintf_unfiltered (gdb_stdlog
,
4569 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4570 argnum
+ 1, len
, (int) typecode
);
4572 /* The EABI passes structures that do not fit in a register by
4574 if (len
> abi_regsize
4575 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4577 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4578 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4579 value_address (arg
));
4580 typecode
= TYPE_CODE_PTR
;
4584 fprintf_unfiltered (gdb_stdlog
, " push");
4587 val
= value_contents (arg
);
4589 /* 32-bit ABIs always start floating point arguments in an
4590 even-numbered floating point register. Round the FP register
4591 up before the check to see if there are any FP registers
4592 left. Non MIPS_EABI targets also pass the FP in the integer
4593 registers so also round up normal registers. */
4594 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4596 if ((float_argreg
& 1))
4600 /* Floating point arguments passed in registers have to be
4601 treated specially. On 32-bit architectures, doubles
4602 are passed in register pairs; the even register gets
4603 the low word, and the odd register gets the high word.
4604 On non-EABI processors, the first two floating point arguments are
4605 also copied to general registers, because MIPS16 functions
4606 don't use float registers for arguments. This duplication of
4607 arguments in general registers can't hurt non-MIPS16 functions
4608 because those registers are normally skipped. */
4609 /* MIPS_EABI squeezes a struct that contains a single floating
4610 point value into an FP register instead of pushing it onto the
4612 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4613 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4615 /* EABI32 will pass doubles in consecutive registers, even on
4616 64-bit cores. At one time, we used to check the size of
4617 `float_argreg' to determine whether or not to pass doubles
4618 in consecutive registers, but this is not sufficient for
4619 making the ABI determination. */
4620 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4622 int low_offset
= gdbarch_byte_order (gdbarch
)
4623 == BFD_ENDIAN_BIG
? 4 : 0;
4626 /* Write the low word of the double to the even register(s). */
4627 regval
= extract_signed_integer (val
+ low_offset
,
4630 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4631 float_argreg
, phex (regval
, 4));
4632 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4634 /* Write the high word of the double to the odd register(s). */
4635 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4638 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4639 float_argreg
, phex (regval
, 4));
4640 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4644 /* This is a floating point value that fits entirely
4645 in a single register. */
4646 /* On 32 bit ABI's the float_argreg is further adjusted
4647 above to ensure that it is even register aligned. */
4648 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4650 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4651 float_argreg
, phex (regval
, len
));
4652 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4657 /* Copy the argument to general registers or the stack in
4658 register-sized pieces. Large arguments are split between
4659 registers and stack. */
4660 /* Note: structs whose size is not a multiple of abi_regsize
4661 are treated specially: Irix cc passes
4662 them in registers where gcc sometimes puts them on the
4663 stack. For maximum compatibility, we will put them in
4665 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4667 /* Note: Floating-point values that didn't fit into an FP
4668 register are only written to memory. */
4671 /* Remember if the argument was written to the stack. */
4672 int stack_used_p
= 0;
4673 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4676 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4679 /* Write this portion of the argument to the stack. */
4680 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4682 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4684 /* Should shorter than int integer values be
4685 promoted to int before being stored? */
4686 int longword_offset
= 0;
4689 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4691 if (abi_regsize
== 8
4692 && (typecode
== TYPE_CODE_INT
4693 || typecode
== TYPE_CODE_PTR
4694 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4695 longword_offset
= abi_regsize
- len
;
4696 else if ((typecode
== TYPE_CODE_STRUCT
4697 || typecode
== TYPE_CODE_UNION
)
4698 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4699 longword_offset
= abi_regsize
- len
;
4704 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4705 paddress (gdbarch
, stack_offset
));
4706 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4707 paddress (gdbarch
, longword_offset
));
4710 addr
= sp
+ stack_offset
+ longword_offset
;
4715 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4716 paddress (gdbarch
, addr
));
4717 for (i
= 0; i
< partial_len
; i
++)
4719 fprintf_unfiltered (gdb_stdlog
, "%02x",
4723 write_memory (addr
, val
, partial_len
);
4726 /* Note!!! This is NOT an else clause. Odd sized
4727 structs may go thru BOTH paths. Floating point
4728 arguments will not. */
4729 /* Write this portion of the argument to a general
4730 purpose register. */
4731 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4732 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4735 extract_signed_integer (val
, partial_len
, byte_order
);
4738 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4740 phex (regval
, abi_regsize
));
4741 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4748 /* Compute the offset into the stack at which we will
4749 copy the next parameter.
4751 In the new EABI (and the NABI32), the stack_offset
4752 only needs to be adjusted when it has been used. */
4755 stack_offset
+= align_up (partial_len
, abi_regsize
);
4759 fprintf_unfiltered (gdb_stdlog
, "\n");
4762 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4764 /* Return adjusted stack pointer. */
4768 /* Determine the return value convention being used. */
4770 static enum return_value_convention
4771 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4772 struct type
*type
, struct regcache
*regcache
,
4773 struct value
*value
,
4774 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4776 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4777 int fp_return_type
= 0;
4778 int offset
, regnum
, xfer
;
4780 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4781 return RETURN_VALUE_STRUCT_CONVENTION
;
4783 /* Floating point type? */
4784 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4786 if (type
->code () == TYPE_CODE_FLT
)
4788 /* Structs with a single field of float type
4789 are returned in a floating point register. */
4790 if ((type
->code () == TYPE_CODE_STRUCT
4791 || type
->code () == TYPE_CODE_UNION
)
4792 && type
->num_fields () == 1)
4794 struct type
*fieldtype
= type
->field (0).type ();
4796 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4803 /* A floating-point value belongs in the least significant part
4806 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4807 regnum
= mips_regnum (gdbarch
)->fp0
;
4811 /* An integer value goes in V0/V1. */
4813 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4814 regnum
= MIPS_V0_REGNUM
;
4817 offset
< TYPE_LENGTH (type
);
4818 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4820 xfer
= mips_abi_regsize (gdbarch
);
4821 if (offset
+ xfer
> TYPE_LENGTH (type
))
4822 xfer
= TYPE_LENGTH (type
) - offset
;
4823 mips_xfer_register (gdbarch
, regcache
,
4824 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4825 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4829 return RETURN_VALUE_REGISTER_CONVENTION
;
4833 /* N32/N64 ABI stuff. */
4835 /* Search for a naturally aligned double at OFFSET inside a struct
4836 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4840 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4845 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4848 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4851 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4854 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4857 struct type
*field_type
;
4859 /* We're only looking at normal fields. */
4860 if (field_is_static (&arg_type
->field (i
))
4861 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4864 /* If we have gone past the offset, there is no double to pass. */
4865 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4869 field_type
= check_typedef (arg_type
->field (i
).type ());
4871 /* If this field is entirely before the requested offset, go
4872 on to the next one. */
4873 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4876 /* If this is our special aligned double, we can stop. */
4877 if (field_type
->code () == TYPE_CODE_FLT
4878 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4881 /* This field starts at or before the requested offset, and
4882 overlaps it. If it is a structure, recurse inwards. */
4883 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4890 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4891 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4892 int nargs
, struct value
**args
, CORE_ADDR sp
,
4893 function_call_return_method return_method
,
4894 CORE_ADDR struct_addr
)
4900 int stack_offset
= 0;
4901 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4902 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4904 /* For shared libraries, "t9" needs to point at the function
4906 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4908 /* Set the return address register to point to the entry point of
4909 the program, where a breakpoint lies in wait. */
4910 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4912 /* First ensure that the stack and structure return address (if any)
4913 are properly aligned. The stack has to be at least 64-bit
4914 aligned even on 32-bit machines, because doubles must be 64-bit
4915 aligned. For n32 and n64, stack frames need to be 128-bit
4916 aligned, so we round to this widest known alignment. */
4918 sp
= align_down (sp
, 16);
4919 struct_addr
= align_down (struct_addr
, 16);
4921 /* Now make space on the stack for the args. */
4922 for (argnum
= 0; argnum
< nargs
; argnum
++)
4923 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4924 sp
-= align_up (arg_space
, 16);
4927 fprintf_unfiltered (gdb_stdlog
,
4928 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4929 paddress (gdbarch
, sp
),
4930 (long) align_up (arg_space
, 16));
4932 /* Initialize the integer and float register pointers. */
4933 argreg
= MIPS_A0_REGNUM
;
4934 float_argreg
= mips_fpa0_regnum (gdbarch
);
4936 /* The struct_return pointer occupies the first parameter-passing reg. */
4937 if (return_method
== return_method_struct
)
4940 fprintf_unfiltered (gdb_stdlog
,
4941 "mips_n32n64_push_dummy_call: "
4942 "struct_return reg=%d %s\n",
4943 argreg
, paddress (gdbarch
, struct_addr
));
4944 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4947 /* Now load as many as possible of the first arguments into
4948 registers, and push the rest onto the stack. Loop thru args
4949 from first to last. */
4950 for (argnum
= 0; argnum
< nargs
; argnum
++)
4952 const gdb_byte
*val
;
4953 struct value
*arg
= args
[argnum
];
4954 struct type
*arg_type
= check_typedef (value_type (arg
));
4955 int len
= TYPE_LENGTH (arg_type
);
4956 enum type_code typecode
= arg_type
->code ();
4959 fprintf_unfiltered (gdb_stdlog
,
4960 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4961 argnum
+ 1, len
, (int) typecode
);
4963 val
= value_contents (arg
);
4965 /* A 128-bit long double value requires an even-odd pair of
4966 floating-point registers. */
4968 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4969 && (float_argreg
& 1))
4975 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4976 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4978 /* This is a floating point value that fits entirely
4979 in a single register or a pair of registers. */
4980 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4981 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4983 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4984 float_argreg
, phex (regval
, reglen
));
4985 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4988 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4989 argreg
, phex (regval
, reglen
));
4990 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4995 regval
= extract_unsigned_integer (val
+ reglen
,
4996 reglen
, byte_order
);
4998 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4999 float_argreg
, phex (regval
, reglen
));
5000 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5003 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5004 argreg
, phex (regval
, reglen
));
5005 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5012 /* Copy the argument to general registers or the stack in
5013 register-sized pieces. Large arguments are split between
5014 registers and stack. */
5015 /* For N32/N64, structs, unions, or other composite types are
5016 treated as a sequence of doublewords, and are passed in integer
5017 or floating point registers as though they were simple scalar
5018 parameters to the extent that they fit, with any excess on the
5019 stack packed according to the normal memory layout of the
5021 The caller does not reserve space for the register arguments;
5022 the callee is responsible for reserving it if required. */
5023 /* Note: Floating-point values that didn't fit into an FP
5024 register are only written to memory. */
5027 /* Remember if the argument was written to the stack. */
5028 int stack_used_p
= 0;
5029 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5032 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5035 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5036 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5038 /* Write this portion of the argument to the stack. */
5039 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5041 /* Should shorter than int integer values be
5042 promoted to int before being stored? */
5043 int longword_offset
= 0;
5046 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5048 if ((typecode
== TYPE_CODE_INT
5049 || typecode
== TYPE_CODE_PTR
)
5051 longword_offset
= MIPS64_REGSIZE
- len
;
5056 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5057 paddress (gdbarch
, stack_offset
));
5058 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5059 paddress (gdbarch
, longword_offset
));
5062 addr
= sp
+ stack_offset
+ longword_offset
;
5067 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5068 paddress (gdbarch
, addr
));
5069 for (i
= 0; i
< partial_len
; i
++)
5071 fprintf_unfiltered (gdb_stdlog
, "%02x",
5075 write_memory (addr
, val
, partial_len
);
5078 /* Note!!! This is NOT an else clause. Odd sized
5079 structs may go thru BOTH paths. */
5080 /* Write this portion of the argument to a general
5081 purpose register. */
5082 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5086 /* Sign extend pointers, 32-bit integers and signed
5087 16-bit and 8-bit integers; everything else is taken
5090 if ((partial_len
== 4
5091 && (typecode
== TYPE_CODE_PTR
5092 || typecode
== TYPE_CODE_INT
))
5094 && typecode
== TYPE_CODE_INT
5095 && !arg_type
->is_unsigned ()))
5096 regval
= extract_signed_integer (val
, partial_len
,
5099 regval
= extract_unsigned_integer (val
, partial_len
,
5102 /* A non-floating-point argument being passed in a
5103 general register. If a struct or union, and if
5104 the remaining length is smaller than the register
5105 size, we have to adjust the register value on
5108 It does not seem to be necessary to do the
5109 same for integral types. */
5111 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5112 && partial_len
< MIPS64_REGSIZE
5113 && (typecode
== TYPE_CODE_STRUCT
5114 || typecode
== TYPE_CODE_UNION
))
5115 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5119 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5121 phex (regval
, MIPS64_REGSIZE
));
5122 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5124 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5125 TYPE_LENGTH (arg_type
) - len
))
5128 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5130 phex (regval
, MIPS64_REGSIZE
));
5131 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5142 /* Compute the offset into the stack at which we will
5143 copy the next parameter.
5145 In N32 (N64?), the stack_offset only needs to be
5146 adjusted when it has been used. */
5149 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5153 fprintf_unfiltered (gdb_stdlog
, "\n");
5156 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5158 /* Return adjusted stack pointer. */
5162 static enum return_value_convention
5163 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5164 struct type
*type
, struct regcache
*regcache
,
5165 struct value
*value
,
5166 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5170 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5172 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5173 if needed), as appropriate for the type. Composite results (struct,
5174 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5177 * A struct with only one or two floating point fields is returned in $f0
5178 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5181 * Any other composite results of at most 128 bits are returned in
5182 $2 (first 64 bits) and $3 (remainder, if necessary).
5184 * Larger composite results are handled by converting the function to a
5185 procedure with an implicit first parameter, which is a pointer to an area
5186 reserved by the caller to receive the result. [The o32-bit ABI requires
5187 that all composite results be handled by conversion to implicit first
5188 parameters. The MIPS/SGI Fortran implementation has always made a
5189 specific exception to return COMPLEX results in the floating point
5192 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5193 return RETURN_VALUE_STRUCT_CONVENTION
;
5194 else if (type
->code () == TYPE_CODE_FLT
5195 && TYPE_LENGTH (type
) == 16
5196 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5198 /* A 128-bit floating-point value fills both $f0 and $f2. The
5199 two registers are used in the same as memory order, so the
5200 eight bytes with the lower memory address are in $f0. */
5202 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5203 mips_xfer_register (gdbarch
, regcache
,
5204 (gdbarch_num_regs (gdbarch
)
5205 + mips_regnum (gdbarch
)->fp0
),
5206 8, gdbarch_byte_order (gdbarch
),
5207 readbuf
, writebuf
, 0);
5208 mips_xfer_register (gdbarch
, regcache
,
5209 (gdbarch_num_regs (gdbarch
)
5210 + mips_regnum (gdbarch
)->fp0
+ 2),
5211 8, gdbarch_byte_order (gdbarch
),
5212 readbuf
? readbuf
+ 8 : readbuf
,
5213 writebuf
? writebuf
+ 8 : writebuf
, 0);
5214 return RETURN_VALUE_REGISTER_CONVENTION
;
5216 else if (type
->code () == TYPE_CODE_FLT
5217 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5219 /* A single or double floating-point value that fits in FP0. */
5221 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5222 mips_xfer_register (gdbarch
, regcache
,
5223 (gdbarch_num_regs (gdbarch
)
5224 + mips_regnum (gdbarch
)->fp0
),
5226 gdbarch_byte_order (gdbarch
),
5227 readbuf
, writebuf
, 0);
5228 return RETURN_VALUE_REGISTER_CONVENTION
;
5230 else if (type
->code () == TYPE_CODE_STRUCT
5231 && type
->num_fields () <= 2
5232 && type
->num_fields () >= 1
5233 && ((type
->num_fields () == 1
5234 && (check_typedef (type
->field (0).type ())->code ()
5236 || (type
->num_fields () == 2
5237 && (check_typedef (type
->field (0).type ())->code ()
5239 && (check_typedef (type
->field (1).type ())->code ()
5240 == TYPE_CODE_FLT
))))
5242 /* A struct that contains one or two floats. Each value is part
5243 in the least significant part of their floating point
5244 register (or GPR, for soft float). */
5247 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5248 ? mips_regnum (gdbarch
)->fp0
5250 field
< type
->num_fields (); field
++, regnum
+= 2)
5252 int offset
= (FIELD_BITPOS (type
->field (field
))
5255 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5257 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5259 /* A 16-byte long double field goes in two consecutive
5261 mips_xfer_register (gdbarch
, regcache
,
5262 gdbarch_num_regs (gdbarch
) + regnum
,
5264 gdbarch_byte_order (gdbarch
),
5265 readbuf
, writebuf
, offset
);
5266 mips_xfer_register (gdbarch
, regcache
,
5267 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5269 gdbarch_byte_order (gdbarch
),
5270 readbuf
, writebuf
, offset
+ 8);
5273 mips_xfer_register (gdbarch
, regcache
,
5274 gdbarch_num_regs (gdbarch
) + regnum
,
5275 TYPE_LENGTH (type
->field (field
).type ()),
5276 gdbarch_byte_order (gdbarch
),
5277 readbuf
, writebuf
, offset
);
5279 return RETURN_VALUE_REGISTER_CONVENTION
;
5281 else if (type
->code () == TYPE_CODE_STRUCT
5282 || type
->code () == TYPE_CODE_UNION
5283 || type
->code () == TYPE_CODE_ARRAY
)
5285 /* A composite type. Extract the left justified value,
5286 regardless of the byte order. I.e. DO NOT USE
5290 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5291 offset
< TYPE_LENGTH (type
);
5292 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5294 int xfer
= register_size (gdbarch
, regnum
);
5295 if (offset
+ xfer
> TYPE_LENGTH (type
))
5296 xfer
= TYPE_LENGTH (type
) - offset
;
5298 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5299 offset
, xfer
, regnum
);
5300 mips_xfer_register (gdbarch
, regcache
,
5301 gdbarch_num_regs (gdbarch
) + regnum
,
5302 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5305 return RETURN_VALUE_REGISTER_CONVENTION
;
5309 /* A scalar extract each part but least-significant-byte
5313 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5314 offset
< TYPE_LENGTH (type
);
5315 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5317 int xfer
= register_size (gdbarch
, regnum
);
5318 if (offset
+ xfer
> TYPE_LENGTH (type
))
5319 xfer
= TYPE_LENGTH (type
) - offset
;
5321 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5322 offset
, xfer
, regnum
);
5323 mips_xfer_register (gdbarch
, regcache
,
5324 gdbarch_num_regs (gdbarch
) + regnum
,
5325 xfer
, gdbarch_byte_order (gdbarch
),
5326 readbuf
, writebuf
, offset
);
5328 return RETURN_VALUE_REGISTER_CONVENTION
;
5332 /* Which registers to use for passing floating-point values between
5333 function calls, one of floating-point, general and both kinds of
5334 registers. O32 and O64 use different register kinds for standard
5335 MIPS and MIPS16 code; to make the handling of cases where we may
5336 not know what kind of code is being used (e.g. no debug information)
5337 easier we sometimes use both kinds. */
5346 /* O32 ABI stuff. */
5349 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5350 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5351 int nargs
, struct value
**args
, CORE_ADDR sp
,
5352 function_call_return_method return_method
,
5353 CORE_ADDR struct_addr
)
5359 int stack_offset
= 0;
5360 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5361 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5363 /* For shared libraries, "t9" needs to point at the function
5365 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5367 /* Set the return address register to point to the entry point of
5368 the program, where a breakpoint lies in wait. */
5369 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5371 /* First ensure that the stack and structure return address (if any)
5372 are properly aligned. The stack has to be at least 64-bit
5373 aligned even on 32-bit machines, because doubles must be 64-bit
5374 aligned. For n32 and n64, stack frames need to be 128-bit
5375 aligned, so we round to this widest known alignment. */
5377 sp
= align_down (sp
, 16);
5378 struct_addr
= align_down (struct_addr
, 16);
5380 /* Now make space on the stack for the args. */
5381 for (argnum
= 0; argnum
< nargs
; argnum
++)
5383 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5385 /* Align to double-word if necessary. */
5386 if (mips_type_needs_double_align (arg_type
))
5387 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5388 /* Allocate space on the stack. */
5389 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5391 sp
-= align_up (arg_space
, 16);
5394 fprintf_unfiltered (gdb_stdlog
,
5395 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5396 paddress (gdbarch
, sp
),
5397 (long) align_up (arg_space
, 16));
5399 /* Initialize the integer and float register pointers. */
5400 argreg
= MIPS_A0_REGNUM
;
5401 float_argreg
= mips_fpa0_regnum (gdbarch
);
5403 /* The struct_return pointer occupies the first parameter-passing reg. */
5404 if (return_method
== return_method_struct
)
5407 fprintf_unfiltered (gdb_stdlog
,
5408 "mips_o32_push_dummy_call: "
5409 "struct_return reg=%d %s\n",
5410 argreg
, paddress (gdbarch
, struct_addr
));
5411 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5412 stack_offset
+= MIPS32_REGSIZE
;
5415 /* Now load as many as possible of the first arguments into
5416 registers, and push the rest onto the stack. Loop thru args
5417 from first to last. */
5418 for (argnum
= 0; argnum
< nargs
; argnum
++)
5420 const gdb_byte
*val
;
5421 struct value
*arg
= args
[argnum
];
5422 struct type
*arg_type
= check_typedef (value_type (arg
));
5423 int len
= TYPE_LENGTH (arg_type
);
5424 enum type_code typecode
= arg_type
->code ();
5427 fprintf_unfiltered (gdb_stdlog
,
5428 "mips_o32_push_dummy_call: %d len=%d type=%d",
5429 argnum
+ 1, len
, (int) typecode
);
5431 val
= value_contents (arg
);
5433 /* 32-bit ABIs always start floating point arguments in an
5434 even-numbered floating point register. Round the FP register
5435 up before the check to see if there are any FP registers
5436 left. O32 targets also pass the FP in the integer registers
5437 so also round up normal registers. */
5438 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5440 if ((float_argreg
& 1))
5444 /* Floating point arguments passed in registers have to be
5445 treated specially. On 32-bit architectures, doubles are
5446 passed in register pairs; the even FP register gets the
5447 low word, and the odd FP register gets the high word.
5448 On O32, the first two floating point arguments are also
5449 copied to general registers, following their memory order,
5450 because MIPS16 functions don't use float registers for
5451 arguments. This duplication of arguments in general
5452 registers can't hurt non-MIPS16 functions, because those
5453 registers are normally skipped. */
5455 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5456 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5458 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5460 int freg_offset
= gdbarch_byte_order (gdbarch
)
5461 == BFD_ENDIAN_BIG
? 1 : 0;
5462 unsigned long regval
;
5465 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5467 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5468 float_argreg
+ freg_offset
,
5470 regcache_cooked_write_unsigned (regcache
,
5471 float_argreg
++ + freg_offset
,
5474 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5475 argreg
, phex (regval
, 4));
5476 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5479 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5481 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5482 float_argreg
- freg_offset
,
5484 regcache_cooked_write_unsigned (regcache
,
5485 float_argreg
++ - freg_offset
,
5488 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5489 argreg
, phex (regval
, 4));
5490 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5494 /* This is a floating point value that fits entirely
5495 in a single register. */
5496 /* On 32 bit ABI's the float_argreg is further adjusted
5497 above to ensure that it is even register aligned. */
5498 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5500 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5501 float_argreg
, phex (regval
, len
));
5502 regcache_cooked_write_unsigned (regcache
,
5503 float_argreg
++, regval
);
5504 /* Although two FP registers are reserved for each
5505 argument, only one corresponding integer register is
5508 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5509 argreg
, phex (regval
, len
));
5510 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5512 /* Reserve space for the FP register. */
5513 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5517 /* Copy the argument to general registers or the stack in
5518 register-sized pieces. Large arguments are split between
5519 registers and stack. */
5520 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5521 are treated specially: Irix cc passes
5522 them in registers where gcc sometimes puts them on the
5523 stack. For maximum compatibility, we will put them in
5525 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5526 && len
% MIPS32_REGSIZE
!= 0);
5527 /* Structures should be aligned to eight bytes (even arg registers)
5528 on MIPS_ABI_O32, if their first member has double precision. */
5529 if (mips_type_needs_double_align (arg_type
))
5534 stack_offset
+= MIPS32_REGSIZE
;
5539 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5542 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5545 /* Write this portion of the argument to the stack. */
5546 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5547 || odd_sized_struct
)
5549 /* Should shorter than int integer values be
5550 promoted to int before being stored? */
5551 int longword_offset
= 0;
5556 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5557 paddress (gdbarch
, stack_offset
));
5558 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5559 paddress (gdbarch
, longword_offset
));
5562 addr
= sp
+ stack_offset
+ longword_offset
;
5567 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5568 paddress (gdbarch
, addr
));
5569 for (i
= 0; i
< partial_len
; i
++)
5571 fprintf_unfiltered (gdb_stdlog
, "%02x",
5575 write_memory (addr
, val
, partial_len
);
5578 /* Note!!! This is NOT an else clause. Odd sized
5579 structs may go thru BOTH paths. */
5580 /* Write this portion of the argument to a general
5581 purpose register. */
5582 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5584 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5586 /* Value may need to be sign extended, because
5587 mips_isa_regsize() != mips_abi_regsize(). */
5589 /* A non-floating-point argument being passed in a
5590 general register. If a struct or union, and if
5591 the remaining length is smaller than the register
5592 size, we have to adjust the register value on
5595 It does not seem to be necessary to do the
5596 same for integral types.
5598 Also don't do this adjustment on O64 binaries.
5600 cagney/2001-07-23: gdb/179: Also, GCC, when
5601 outputting LE O32 with sizeof (struct) <
5602 mips_abi_regsize(), generates a left shift
5603 as part of storing the argument in a register
5604 (the left shift isn't generated when
5605 sizeof (struct) >= mips_abi_regsize()). Since
5606 it is quite possible that this is GCC
5607 contradicting the LE/O32 ABI, GDB has not been
5608 adjusted to accommodate this. Either someone
5609 needs to demonstrate that the LE/O32 ABI
5610 specifies such a left shift OR this new ABI gets
5611 identified as such and GDB gets tweaked
5614 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5615 && partial_len
< MIPS32_REGSIZE
5616 && (typecode
== TYPE_CODE_STRUCT
5617 || typecode
== TYPE_CODE_UNION
))
5618 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5622 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5624 phex (regval
, MIPS32_REGSIZE
));
5625 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5628 /* Prevent subsequent floating point arguments from
5629 being passed in floating point registers. */
5630 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5636 /* Compute the offset into the stack at which we will
5637 copy the next parameter.
5639 In older ABIs, the caller reserved space for
5640 registers that contained arguments. This was loosely
5641 refered to as their "home". Consequently, space is
5642 always allocated. */
5644 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5648 fprintf_unfiltered (gdb_stdlog
, "\n");
5651 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5653 /* Return adjusted stack pointer. */
5657 static enum return_value_convention
5658 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5659 struct type
*type
, struct regcache
*regcache
,
5660 struct value
*value
,
5661 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5663 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5664 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5665 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5666 enum mips_fval_reg fval_reg
;
5668 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5669 if (type
->code () == TYPE_CODE_STRUCT
5670 || type
->code () == TYPE_CODE_UNION
5671 || type
->code () == TYPE_CODE_ARRAY
)
5672 return RETURN_VALUE_STRUCT_CONVENTION
;
5673 else if (type
->code () == TYPE_CODE_FLT
5674 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5676 /* A single-precision floating-point value. If reading in or copying,
5677 then we get it from/put it to FP0 for standard MIPS code or GPR2
5678 for MIPS16 code. If writing out only, then we put it to both FP0
5679 and GPR2. We do not support reading in with no function known, if
5680 this safety check ever triggers, then we'll have to try harder. */
5681 gdb_assert (function
|| !readbuf
);
5686 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5689 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5691 case mips_fval_both
:
5692 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5695 if (fval_reg
!= mips_fval_gpr
)
5696 mips_xfer_register (gdbarch
, regcache
,
5697 (gdbarch_num_regs (gdbarch
)
5698 + mips_regnum (gdbarch
)->fp0
),
5700 gdbarch_byte_order (gdbarch
),
5701 readbuf
, writebuf
, 0);
5702 if (fval_reg
!= mips_fval_fpr
)
5703 mips_xfer_register (gdbarch
, regcache
,
5704 gdbarch_num_regs (gdbarch
) + 2,
5706 gdbarch_byte_order (gdbarch
),
5707 readbuf
, writebuf
, 0);
5708 return RETURN_VALUE_REGISTER_CONVENTION
;
5710 else if (type
->code () == TYPE_CODE_FLT
5711 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5713 /* A double-precision floating-point value. If reading in or copying,
5714 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5715 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5716 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5717 no function known, if this safety check ever triggers, then we'll
5718 have to try harder. */
5719 gdb_assert (function
|| !readbuf
);
5724 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5727 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5729 case mips_fval_both
:
5730 fprintf_unfiltered (gdb_stderr
,
5731 "Return float in $fp1/$fp0 and $2/$3\n");
5734 if (fval_reg
!= mips_fval_gpr
)
5736 /* The most significant part goes in FP1, and the least significant
5738 switch (gdbarch_byte_order (gdbarch
))
5740 case BFD_ENDIAN_LITTLE
:
5741 mips_xfer_register (gdbarch
, regcache
,
5742 (gdbarch_num_regs (gdbarch
)
5743 + mips_regnum (gdbarch
)->fp0
+ 0),
5744 4, gdbarch_byte_order (gdbarch
),
5745 readbuf
, writebuf
, 0);
5746 mips_xfer_register (gdbarch
, regcache
,
5747 (gdbarch_num_regs (gdbarch
)
5748 + mips_regnum (gdbarch
)->fp0
+ 1),
5749 4, gdbarch_byte_order (gdbarch
),
5750 readbuf
, writebuf
, 4);
5752 case BFD_ENDIAN_BIG
:
5753 mips_xfer_register (gdbarch
, regcache
,
5754 (gdbarch_num_regs (gdbarch
)
5755 + mips_regnum (gdbarch
)->fp0
+ 1),
5756 4, gdbarch_byte_order (gdbarch
),
5757 readbuf
, writebuf
, 0);
5758 mips_xfer_register (gdbarch
, regcache
,
5759 (gdbarch_num_regs (gdbarch
)
5760 + mips_regnum (gdbarch
)->fp0
+ 0),
5761 4, gdbarch_byte_order (gdbarch
),
5762 readbuf
, writebuf
, 4);
5765 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5768 if (fval_reg
!= mips_fval_fpr
)
5770 /* The two 32-bit parts are always placed in GPR2 and GPR3
5771 following these registers' memory order. */
5772 mips_xfer_register (gdbarch
, regcache
,
5773 gdbarch_num_regs (gdbarch
) + 2,
5774 4, gdbarch_byte_order (gdbarch
),
5775 readbuf
, writebuf
, 0);
5776 mips_xfer_register (gdbarch
, regcache
,
5777 gdbarch_num_regs (gdbarch
) + 3,
5778 4, gdbarch_byte_order (gdbarch
),
5779 readbuf
, writebuf
, 4);
5781 return RETURN_VALUE_REGISTER_CONVENTION
;
5784 else if (type
->code () == TYPE_CODE_STRUCT
5785 && type
->num_fields () <= 2
5786 && type
->num_fields () >= 1
5787 && ((type
->num_fields () == 1
5788 && (TYPE_CODE (type
->field (0).type ())
5790 || (type
->num_fields () == 2
5791 && (TYPE_CODE (type
->field (0).type ())
5793 && (TYPE_CODE (type
->field (1).type ())
5795 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5797 /* A struct that contains one or two floats. Each value is part
5798 in the least significant part of their floating point
5802 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5803 field
< type
->num_fields (); field
++, regnum
+= 2)
5805 int offset
= (FIELD_BITPOS (type
->fields ()[field
])
5808 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5810 mips_xfer_register (gdbarch
, regcache
,
5811 gdbarch_num_regs (gdbarch
) + regnum
,
5812 TYPE_LENGTH (type
->field (field
).type ()),
5813 gdbarch_byte_order (gdbarch
),
5814 readbuf
, writebuf
, offset
);
5816 return RETURN_VALUE_REGISTER_CONVENTION
;
5820 else if (type
->code () == TYPE_CODE_STRUCT
5821 || type
->code () == TYPE_CODE_UNION
)
5823 /* A structure or union. Extract the left justified value,
5824 regardless of the byte order. I.e. DO NOT USE
5828 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5829 offset
< TYPE_LENGTH (type
);
5830 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5832 int xfer
= register_size (gdbarch
, regnum
);
5833 if (offset
+ xfer
> TYPE_LENGTH (type
))
5834 xfer
= TYPE_LENGTH (type
) - offset
;
5836 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5837 offset
, xfer
, regnum
);
5838 mips_xfer_register (gdbarch
, regcache
,
5839 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5840 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5842 return RETURN_VALUE_REGISTER_CONVENTION
;
5847 /* A scalar extract each part but least-significant-byte
5848 justified. o32 thinks registers are 4 byte, regardless of
5852 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5853 offset
< TYPE_LENGTH (type
);
5854 offset
+= MIPS32_REGSIZE
, regnum
++)
5856 int xfer
= MIPS32_REGSIZE
;
5857 if (offset
+ xfer
> TYPE_LENGTH (type
))
5858 xfer
= TYPE_LENGTH (type
) - offset
;
5860 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5861 offset
, xfer
, regnum
);
5862 mips_xfer_register (gdbarch
, regcache
,
5863 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5864 gdbarch_byte_order (gdbarch
),
5865 readbuf
, writebuf
, offset
);
5867 return RETURN_VALUE_REGISTER_CONVENTION
;
5871 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5875 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5876 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5878 struct value
**args
, CORE_ADDR sp
,
5879 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5885 int stack_offset
= 0;
5886 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5887 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5889 /* For shared libraries, "t9" needs to point at the function
5891 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5893 /* Set the return address register to point to the entry point of
5894 the program, where a breakpoint lies in wait. */
5895 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5897 /* First ensure that the stack and structure return address (if any)
5898 are properly aligned. The stack has to be at least 64-bit
5899 aligned even on 32-bit machines, because doubles must be 64-bit
5900 aligned. For n32 and n64, stack frames need to be 128-bit
5901 aligned, so we round to this widest known alignment. */
5903 sp
= align_down (sp
, 16);
5904 struct_addr
= align_down (struct_addr
, 16);
5906 /* Now make space on the stack for the args. */
5907 for (argnum
= 0; argnum
< nargs
; argnum
++)
5909 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5911 /* Allocate space on the stack. */
5912 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5914 sp
-= align_up (arg_space
, 16);
5917 fprintf_unfiltered (gdb_stdlog
,
5918 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5919 paddress (gdbarch
, sp
),
5920 (long) align_up (arg_space
, 16));
5922 /* Initialize the integer and float register pointers. */
5923 argreg
= MIPS_A0_REGNUM
;
5924 float_argreg
= mips_fpa0_regnum (gdbarch
);
5926 /* The struct_return pointer occupies the first parameter-passing reg. */
5927 if (return_method
== return_method_struct
)
5930 fprintf_unfiltered (gdb_stdlog
,
5931 "mips_o64_push_dummy_call: "
5932 "struct_return reg=%d %s\n",
5933 argreg
, paddress (gdbarch
, struct_addr
));
5934 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5935 stack_offset
+= MIPS64_REGSIZE
;
5938 /* Now load as many as possible of the first arguments into
5939 registers, and push the rest onto the stack. Loop thru args
5940 from first to last. */
5941 for (argnum
= 0; argnum
< nargs
; argnum
++)
5943 const gdb_byte
*val
;
5944 struct value
*arg
= args
[argnum
];
5945 struct type
*arg_type
= check_typedef (value_type (arg
));
5946 int len
= TYPE_LENGTH (arg_type
);
5947 enum type_code typecode
= arg_type
->code ();
5950 fprintf_unfiltered (gdb_stdlog
,
5951 "mips_o64_push_dummy_call: %d len=%d type=%d",
5952 argnum
+ 1, len
, (int) typecode
);
5954 val
= value_contents (arg
);
5956 /* Floating point arguments passed in registers have to be
5957 treated specially. On 32-bit architectures, doubles are
5958 passed in register pairs; the even FP register gets the
5959 low word, and the odd FP register gets the high word.
5960 On O64, the first two floating point arguments are also
5961 copied to general registers, because MIPS16 functions
5962 don't use float registers for arguments. This duplication
5963 of arguments in general registers can't hurt non-MIPS16
5964 functions because those registers are normally skipped. */
5966 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5967 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5969 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5971 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5972 float_argreg
, phex (regval
, len
));
5973 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5975 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5976 argreg
, phex (regval
, len
));
5977 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5979 /* Reserve space for the FP register. */
5980 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5984 /* Copy the argument to general registers or the stack in
5985 register-sized pieces. Large arguments are split between
5986 registers and stack. */
5987 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5988 are treated specially: Irix cc passes them in registers
5989 where gcc sometimes puts them on the stack. For maximum
5990 compatibility, we will put them in both places. */
5991 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5992 && len
% MIPS64_REGSIZE
!= 0);
5995 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5998 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
6001 /* Write this portion of the argument to the stack. */
6002 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
6003 || odd_sized_struct
)
6005 /* Should shorter than int integer values be
6006 promoted to int before being stored? */
6007 int longword_offset
= 0;
6009 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6011 if ((typecode
== TYPE_CODE_INT
6012 || typecode
== TYPE_CODE_PTR
6013 || typecode
== TYPE_CODE_FLT
)
6015 longword_offset
= MIPS64_REGSIZE
- len
;
6020 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6021 paddress (gdbarch
, stack_offset
));
6022 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6023 paddress (gdbarch
, longword_offset
));
6026 addr
= sp
+ stack_offset
+ longword_offset
;
6031 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6032 paddress (gdbarch
, addr
));
6033 for (i
= 0; i
< partial_len
; i
++)
6035 fprintf_unfiltered (gdb_stdlog
, "%02x",
6039 write_memory (addr
, val
, partial_len
);
6042 /* Note!!! This is NOT an else clause. Odd sized
6043 structs may go thru BOTH paths. */
6044 /* Write this portion of the argument to a general
6045 purpose register. */
6046 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6048 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6050 /* Value may need to be sign extended, because
6051 mips_isa_regsize() != mips_abi_regsize(). */
6053 /* A non-floating-point argument being passed in a
6054 general register. If a struct or union, and if
6055 the remaining length is smaller than the register
6056 size, we have to adjust the register value on
6059 It does not seem to be necessary to do the
6060 same for integral types. */
6062 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6063 && partial_len
< MIPS64_REGSIZE
6064 && (typecode
== TYPE_CODE_STRUCT
6065 || typecode
== TYPE_CODE_UNION
))
6066 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6070 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6072 phex (regval
, MIPS64_REGSIZE
));
6073 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6076 /* Prevent subsequent floating point arguments from
6077 being passed in floating point registers. */
6078 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6084 /* Compute the offset into the stack at which we will
6085 copy the next parameter.
6087 In older ABIs, the caller reserved space for
6088 registers that contained arguments. This was loosely
6089 refered to as their "home". Consequently, space is
6090 always allocated. */
6092 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6096 fprintf_unfiltered (gdb_stdlog
, "\n");
6099 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6101 /* Return adjusted stack pointer. */
6105 static enum return_value_convention
6106 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6107 struct type
*type
, struct regcache
*regcache
,
6108 struct value
*value
,
6109 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6111 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6112 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6113 enum mips_fval_reg fval_reg
;
6115 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6116 if (type
->code () == TYPE_CODE_STRUCT
6117 || type
->code () == TYPE_CODE_UNION
6118 || type
->code () == TYPE_CODE_ARRAY
)
6119 return RETURN_VALUE_STRUCT_CONVENTION
;
6120 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6122 /* A floating-point value. If reading in or copying, then we get it
6123 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6124 If writing out only, then we put it to both FP0 and GPR2. We do
6125 not support reading in with no function known, if this safety
6126 check ever triggers, then we'll have to try harder. */
6127 gdb_assert (function
|| !readbuf
);
6132 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6135 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6137 case mips_fval_both
:
6138 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6141 if (fval_reg
!= mips_fval_gpr
)
6142 mips_xfer_register (gdbarch
, regcache
,
6143 (gdbarch_num_regs (gdbarch
)
6144 + mips_regnum (gdbarch
)->fp0
),
6146 gdbarch_byte_order (gdbarch
),
6147 readbuf
, writebuf
, 0);
6148 if (fval_reg
!= mips_fval_fpr
)
6149 mips_xfer_register (gdbarch
, regcache
,
6150 gdbarch_num_regs (gdbarch
) + 2,
6152 gdbarch_byte_order (gdbarch
),
6153 readbuf
, writebuf
, 0);
6154 return RETURN_VALUE_REGISTER_CONVENTION
;
6158 /* A scalar extract each part but least-significant-byte
6162 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6163 offset
< TYPE_LENGTH (type
);
6164 offset
+= MIPS64_REGSIZE
, regnum
++)
6166 int xfer
= MIPS64_REGSIZE
;
6167 if (offset
+ xfer
> TYPE_LENGTH (type
))
6168 xfer
= TYPE_LENGTH (type
) - offset
;
6170 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6171 offset
, xfer
, regnum
);
6172 mips_xfer_register (gdbarch
, regcache
,
6173 gdbarch_num_regs (gdbarch
) + regnum
,
6174 xfer
, gdbarch_byte_order (gdbarch
),
6175 readbuf
, writebuf
, offset
);
6177 return RETURN_VALUE_REGISTER_CONVENTION
;
6181 /* Floating point register management.
6183 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6184 64bit operations, these early MIPS cpus treat fp register pairs
6185 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6186 registers and offer a compatibility mode that emulates the MIPS2 fp
6187 model. When operating in MIPS2 fp compat mode, later cpu's split
6188 double precision floats into two 32-bit chunks and store them in
6189 consecutive fp regs. To display 64-bit floats stored in this
6190 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6191 Throw in user-configurable endianness and you have a real mess.
6193 The way this works is:
6194 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6195 double-precision value will be split across two logical registers.
6196 The lower-numbered logical register will hold the low-order bits,
6197 regardless of the processor's endianness.
6198 - If we are on a 64-bit processor, and we are looking for a
6199 single-precision value, it will be in the low ordered bits
6200 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6201 save slot in memory.
6202 - If we are in 64-bit mode, everything is straightforward.
6204 Note that this code only deals with "live" registers at the top of the
6205 stack. We will attempt to deal with saved registers later, when
6206 the raw/cooked register interface is in place. (We need a general
6207 interface that can deal with dynamic saved register sizes -- fp
6208 regs could be 32 bits wide in one frame and 64 on the frame above
6211 /* Copy a 32-bit single-precision value from the current frame
6212 into rare_buffer. */
6215 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6216 gdb_byte
*rare_buffer
)
6218 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6219 int raw_size
= register_size (gdbarch
, regno
);
6220 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6222 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6223 error (_("can't read register %d (%s)"),
6224 regno
, gdbarch_register_name (gdbarch
, regno
));
6227 /* We have a 64-bit value for this register. Find the low-order
6231 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6236 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6240 memcpy (rare_buffer
, raw_buffer
, 4);
6244 /* Copy a 64-bit double-precision value from the current frame into
6245 rare_buffer. This may include getting half of it from the next
6249 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6250 gdb_byte
*rare_buffer
)
6252 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6253 int raw_size
= register_size (gdbarch
, regno
);
6255 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6257 /* We have a 64-bit value for this register, and we should use
6259 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6260 error (_("can't read register %d (%s)"),
6261 regno
, gdbarch_register_name (gdbarch
, regno
));
6265 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6267 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6268 internal_error (__FILE__
, __LINE__
,
6269 _("mips_read_fp_register_double: bad access to "
6270 "odd-numbered FP register"));
6272 /* mips_read_fp_register_single will find the correct 32 bits from
6274 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6276 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6277 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6281 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6282 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6288 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6290 { /* Do values for FP (float) regs. */
6291 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6292 gdb_byte
*raw_buffer
;
6293 std::string flt_str
, dbl_str
;
6295 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6296 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6300 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6302 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6303 fprintf_filtered (file
, "%*s",
6304 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6307 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6309 struct value_print_options opts
;
6311 /* 4-byte registers: Print hex and floating. Also print even
6312 numbered registers as doubles. */
6313 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6314 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6316 get_formatted_print_options (&opts
, 'x');
6317 print_scalar_formatted (raw_buffer
,
6318 builtin_type (gdbarch
)->builtin_uint32
,
6321 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6323 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6325 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6326 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6328 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6333 struct value_print_options opts
;
6335 /* Eight byte registers: print each one as hex, float and double. */
6336 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6337 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6339 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6340 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6342 get_formatted_print_options (&opts
, 'x');
6343 print_scalar_formatted (raw_buffer
,
6344 builtin_type (gdbarch
)->builtin_uint64
,
6347 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6348 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6353 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6356 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6357 struct value_print_options opts
;
6360 if (mips_float_register_p (gdbarch
, regnum
))
6362 mips_print_fp_register (file
, frame
, regnum
);
6366 val
= get_frame_register_value (frame
, regnum
);
6368 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6370 /* The problem with printing numeric register names (r26, etc.) is that
6371 the user can't use them on input. Probably the best solution is to
6372 fix it so that either the numeric or the funky (a2, etc.) names
6373 are accepted on input. */
6374 if (regnum
< MIPS_NUMREGS
)
6375 fprintf_filtered (file
, "(r%d): ", regnum
);
6377 fprintf_filtered (file
, ": ");
6379 get_formatted_print_options (&opts
, 'x');
6380 value_print_scalar_formatted (val
, &opts
, 0, file
);
6383 /* Print IEEE exception condition bits in FLAGS. */
6386 print_fpu_flags (struct ui_file
*file
, int flags
)
6388 if (flags
& (1 << 0))
6389 fputs_filtered (" inexact", file
);
6390 if (flags
& (1 << 1))
6391 fputs_filtered (" uflow", file
);
6392 if (flags
& (1 << 2))
6393 fputs_filtered (" oflow", file
);
6394 if (flags
& (1 << 3))
6395 fputs_filtered (" div0", file
);
6396 if (flags
& (1 << 4))
6397 fputs_filtered (" inval", file
);
6398 if (flags
& (1 << 5))
6399 fputs_filtered (" unimp", file
);
6400 fputc_filtered ('\n', file
);
6403 /* Print interesting information about the floating point processor
6404 (if present) or emulator. */
6407 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6408 struct frame_info
*frame
, const char *args
)
6410 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6411 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6415 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6416 type
= MIPS_FPU_NONE
;
6418 fprintf_filtered (file
, "fpu type: %s\n",
6419 type
== MIPS_FPU_DOUBLE
? "double-precision"
6420 : type
== MIPS_FPU_SINGLE
? "single-precision"
6423 if (type
== MIPS_FPU_NONE
)
6426 fprintf_filtered (file
, "reg size: %d bits\n",
6427 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6429 fputs_filtered ("cond :", file
);
6430 if (fcs
& (1 << 23))
6431 fputs_filtered (" 0", file
);
6432 for (i
= 1; i
<= 7; i
++)
6433 if (fcs
& (1 << (24 + i
)))
6434 fprintf_filtered (file
, " %d", i
);
6435 fputc_filtered ('\n', file
);
6437 fputs_filtered ("cause :", file
);
6438 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6439 fputs ("mask :", stdout
);
6440 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6441 fputs ("flags :", stdout
);
6442 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6444 fputs_filtered ("rounding: ", file
);
6447 case 0: fputs_filtered ("nearest\n", file
); break;
6448 case 1: fputs_filtered ("zero\n", file
); break;
6449 case 2: fputs_filtered ("+inf\n", file
); break;
6450 case 3: fputs_filtered ("-inf\n", file
); break;
6453 fputs_filtered ("flush :", file
);
6454 if (fcs
& (1 << 21))
6455 fputs_filtered (" nearest", file
);
6456 if (fcs
& (1 << 22))
6457 fputs_filtered (" override", file
);
6458 if (fcs
& (1 << 24))
6459 fputs_filtered (" zero", file
);
6460 if ((fcs
& (0xb << 21)) == 0)
6461 fputs_filtered (" no", file
);
6462 fputc_filtered ('\n', file
);
6464 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6465 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6466 fputc_filtered ('\n', file
);
6468 default_print_float_info (gdbarch
, file
, frame
, args
);
6471 /* Replacement for generic do_registers_info.
6472 Print regs in pretty columns. */
6475 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6478 fprintf_filtered (file
, " ");
6479 mips_print_fp_register (file
, frame
, regnum
);
6480 fprintf_filtered (file
, "\n");
6485 /* Print a row's worth of GP (int) registers, with name labels above. */
6488 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6491 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6492 /* Do values for GP (int) regs. */
6493 const gdb_byte
*raw_buffer
;
6494 struct value
*value
;
6495 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6500 /* For GP registers, we print a separate row of names above the vals. */
6501 for (col
= 0, regnum
= start_regnum
;
6502 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6505 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6506 continue; /* unused register */
6507 if (mips_float_register_p (gdbarch
, regnum
))
6508 break; /* End the row: reached FP register. */
6509 /* Large registers are handled separately. */
6510 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6513 break; /* End the row before this register. */
6515 /* Print this register on a row by itself. */
6516 mips_print_register (file
, frame
, regnum
);
6517 fprintf_filtered (file
, "\n");
6521 fprintf_filtered (file
, " ");
6522 fprintf_filtered (file
,
6523 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6524 gdbarch_register_name (gdbarch
, regnum
));
6531 /* Print the R0 to R31 names. */
6532 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6533 fprintf_filtered (file
, "\n R%-4d",
6534 start_regnum
% gdbarch_num_regs (gdbarch
));
6536 fprintf_filtered (file
, "\n ");
6538 /* Now print the values in hex, 4 or 8 to the row. */
6539 for (col
= 0, regnum
= start_regnum
;
6540 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6543 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6544 continue; /* unused register */
6545 if (mips_float_register_p (gdbarch
, regnum
))
6546 break; /* End row: reached FP register. */
6547 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6548 break; /* End row: large register. */
6550 /* OK: get the data in raw format. */
6551 value
= get_frame_register_value (frame
, regnum
);
6552 if (value_optimized_out (value
)
6553 || !value_entirely_available (value
))
6555 fprintf_filtered (file
, "%*s ",
6556 (int) mips_abi_regsize (gdbarch
) * 2,
6557 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6558 : "<unavailable>"));
6562 raw_buffer
= value_contents_all (value
);
6563 /* pad small registers */
6565 byte
< (mips_abi_regsize (gdbarch
)
6566 - register_size (gdbarch
, regnum
)); byte
++)
6567 fprintf_filtered (file
, " ");
6568 /* Now print the register value in hex, endian order. */
6569 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6571 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6572 byte
< register_size (gdbarch
, regnum
); byte
++)
6573 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6575 for (byte
= register_size (gdbarch
, regnum
) - 1;
6577 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6578 fprintf_filtered (file
, " ");
6581 if (col
> 0) /* ie. if we actually printed anything... */
6582 fprintf_filtered (file
, "\n");
6587 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6590 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6591 struct frame_info
*frame
, int regnum
, int all
)
6593 if (regnum
!= -1) /* Do one specified register. */
6595 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6596 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6597 error (_("Not a valid register for the current processor type"));
6599 mips_print_register (file
, frame
, regnum
);
6600 fprintf_filtered (file
, "\n");
6603 /* Do all (or most) registers. */
6605 regnum
= gdbarch_num_regs (gdbarch
);
6606 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6608 if (mips_float_register_p (gdbarch
, regnum
))
6610 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6611 regnum
= print_fp_register_row (file
, frame
, regnum
);
6613 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6616 regnum
= print_gp_register_row (file
, frame
, regnum
);
6622 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6623 struct frame_info
*frame
)
6625 CORE_ADDR pc
= get_frame_pc (frame
);
6630 if ((mips_pc_is_mips (pc
)
6631 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6632 || (mips_pc_is_micromips (gdbarch
, pc
)
6633 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6634 || (mips_pc_is_mips16 (gdbarch
, pc
)
6635 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6638 isa
= mips_pc_isa (gdbarch
, pc
);
6639 /* _has_delay_slot above will have validated the read. */
6640 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6641 size
= mips_insn_size (isa
, insn
);
6643 const address_space
*aspace
= get_frame_address_space (frame
);
6645 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6648 /* To skip prologues, I use this predicate. Returns either PC itself
6649 if the code at PC does not look like a function prologue; otherwise
6650 returns an address that (if we're lucky) follows the prologue. If
6651 LENIENT, then we must skip everything which is involved in setting
6652 up the frame (it's OK to skip more, just so long as we don't skip
6653 anything which might clobber the registers which are being saved.
6654 We must skip more in the case where part of the prologue is in the
6655 delay slot of a non-prologue instruction). */
6658 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6661 CORE_ADDR func_addr
;
6663 /* See if we can determine the end of the prologue via the symbol table.
6664 If so, then return either PC, or the PC after the prologue, whichever
6666 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6668 CORE_ADDR post_prologue_pc
6669 = skip_prologue_using_sal (gdbarch
, func_addr
);
6670 if (post_prologue_pc
!= 0)
6671 return std::max (pc
, post_prologue_pc
);
6674 /* Can't determine prologue from the symbol table, need to examine
6677 /* Find an upper limit on the function prologue using the debug
6678 information. If the debug information could not be used to provide
6679 that bound, then use an arbitrary large number as the upper bound. */
6680 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6682 limit_pc
= pc
+ 100; /* Magic. */
6684 if (mips_pc_is_mips16 (gdbarch
, pc
))
6685 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6686 else if (mips_pc_is_micromips (gdbarch
, pc
))
6687 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6689 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6692 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6693 This is a helper function for mips_stack_frame_destroyed_p. */
6696 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6698 CORE_ADDR func_addr
= 0, func_end
= 0;
6700 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6702 /* The MIPS epilogue is max. 12 bytes long. */
6703 CORE_ADDR addr
= func_end
- 12;
6705 if (addr
< func_addr
+ 4)
6706 addr
= func_addr
+ 4;
6710 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6712 unsigned long high_word
;
6715 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6716 high_word
= (inst
>> 16) & 0xffff;
6718 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6719 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6720 && inst
!= 0x03e00008 /* jr $ra */
6721 && inst
!= 0x00000000) /* nop */
6731 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6732 This is a helper function for mips_stack_frame_destroyed_p. */
6735 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6737 CORE_ADDR func_addr
= 0;
6738 CORE_ADDR func_end
= 0;
6746 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6749 /* The microMIPS epilogue is max. 12 bytes long. */
6750 addr
= func_end
- 12;
6752 if (addr
< func_addr
+ 2)
6753 addr
= func_addr
+ 2;
6757 for (; pc
< func_end
; pc
+= loc
)
6760 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6761 loc
+= MIPS_INSN16_SIZE
;
6762 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6764 /* 32-bit instructions. */
6765 case 2 * MIPS_INSN16_SIZE
:
6767 insn
|= mips_fetch_instruction (gdbarch
,
6768 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6769 loc
+= MIPS_INSN16_SIZE
;
6770 switch (micromips_op (insn
>> 16))
6772 case 0xc: /* ADDIU: bits 001100 */
6773 case 0x17: /* DADDIU: bits 010111 */
6774 sreg
= b0s5_reg (insn
>> 16);
6775 dreg
= b5s5_reg (insn
>> 16);
6776 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6777 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6778 /* (D)ADDIU $sp, imm */
6788 /* 16-bit instructions. */
6789 case MIPS_INSN16_SIZE
:
6790 switch (micromips_op (insn
))
6792 case 0x3: /* MOVE: bits 000011 */
6793 sreg
= b0s5_reg (insn
);
6794 dreg
= b5s5_reg (insn
);
6795 if (sreg
== 0 && dreg
== 0)
6796 /* MOVE $zero, $zero aka NOP */
6800 case 0x11: /* POOL16C: bits 010001 */
6801 if (b5s5_op (insn
) == 0x18
6802 /* JRADDIUSP: bits 010011 11000 */
6803 || (b5s5_op (insn
) == 0xd
6804 /* JRC: bits 010011 01101 */
6805 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6810 case 0x13: /* POOL16D: bits 010011 */
6811 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6812 if ((insn
& 0x1) == 0x1
6813 /* ADDIUSP: bits 010011 1 */
6827 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6828 This is a helper function for mips_stack_frame_destroyed_p. */
6831 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6833 CORE_ADDR func_addr
= 0, func_end
= 0;
6835 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6837 /* The MIPS epilogue is max. 12 bytes long. */
6838 CORE_ADDR addr
= func_end
- 12;
6840 if (addr
< func_addr
+ 4)
6841 addr
= func_addr
+ 4;
6845 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6847 unsigned short inst
;
6849 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6851 if ((inst
& 0xf800) == 0xf000) /* extend */
6854 if (inst
!= 0x6300 /* addiu $sp,offset */
6855 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6856 && inst
!= 0xe820 /* jr $ra */
6857 && inst
!= 0xe8a0 /* jrc $ra */
6858 && inst
!= 0x6500) /* nop */
6868 /* Implement the stack_frame_destroyed_p gdbarch method.
6870 The epilogue is defined here as the area at the end of a function,
6871 after an instruction which destroys the function's stack frame. */
6874 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6876 if (mips_pc_is_mips16 (gdbarch
, pc
))
6877 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6878 else if (mips_pc_is_micromips (gdbarch
, pc
))
6879 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6881 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6884 /* Commands to show/set the MIPS FPU type. */
6887 show_mipsfpu_command (const char *args
, int from_tty
)
6891 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6894 ("The MIPS floating-point coprocessor is unknown "
6895 "because the current architecture is not MIPS.\n");
6899 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6901 case MIPS_FPU_SINGLE
:
6902 fpu
= "single-precision";
6904 case MIPS_FPU_DOUBLE
:
6905 fpu
= "double-precision";
6908 fpu
= "absent (none)";
6911 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6913 if (mips_fpu_type_auto
)
6914 printf_unfiltered ("The MIPS floating-point coprocessor "
6915 "is set automatically (currently %s)\n",
6919 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6924 set_mipsfpu_single_command (const char *args
, int from_tty
)
6926 struct gdbarch_info info
;
6927 gdbarch_info_init (&info
);
6928 mips_fpu_type
= MIPS_FPU_SINGLE
;
6929 mips_fpu_type_auto
= 0;
6930 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6931 instead of relying on globals. Doing that would let generic code
6932 handle the search for this specific architecture. */
6933 if (!gdbarch_update_p (info
))
6934 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6938 set_mipsfpu_double_command (const char *args
, int from_tty
)
6940 struct gdbarch_info info
;
6941 gdbarch_info_init (&info
);
6942 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6943 mips_fpu_type_auto
= 0;
6944 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6945 instead of relying on globals. Doing that would let generic code
6946 handle the search for this specific architecture. */
6947 if (!gdbarch_update_p (info
))
6948 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6952 set_mipsfpu_none_command (const char *args
, int from_tty
)
6954 struct gdbarch_info info
;
6955 gdbarch_info_init (&info
);
6956 mips_fpu_type
= MIPS_FPU_NONE
;
6957 mips_fpu_type_auto
= 0;
6958 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6959 instead of relying on globals. Doing that would let generic code
6960 handle the search for this specific architecture. */
6961 if (!gdbarch_update_p (info
))
6962 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6966 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6968 mips_fpu_type_auto
= 1;
6971 /* Just like reinit_frame_cache, but with the right arguments to be
6972 callable as an sfunc. */
6975 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6976 struct cmd_list_element
*c
)
6978 reinit_frame_cache ();
6982 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6984 gdb_disassembler
*di
6985 = static_cast<gdb_disassembler
*>(info
->application_data
);
6986 struct gdbarch
*gdbarch
= di
->arch ();
6988 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6989 disassembler needs to be able to locally determine the ISA, and
6990 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6992 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6993 info
->mach
= bfd_mach_mips16
;
6994 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6995 info
->mach
= bfd_mach_mips_micromips
;
6997 /* Round down the instruction address to the appropriate boundary. */
6998 memaddr
&= (info
->mach
== bfd_mach_mips16
6999 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7001 return default_print_insn (memaddr
, info
);
7004 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7007 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7009 CORE_ADDR pc
= *pcptr
;
7011 if (mips_pc_is_mips16 (gdbarch
, pc
))
7013 *pcptr
= unmake_compact_addr (pc
);
7014 return MIPS_BP_KIND_MIPS16
;
7016 else if (mips_pc_is_micromips (gdbarch
, pc
))
7021 *pcptr
= unmake_compact_addr (pc
);
7022 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7023 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7024 return MIPS_BP_KIND_MICROMIPS16
;
7026 return MIPS_BP_KIND_MICROMIPS32
;
7029 return MIPS_BP_KIND_MIPS32
;
7032 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7034 static const gdb_byte
*
7035 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7037 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7041 case MIPS_BP_KIND_MIPS16
:
7043 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7044 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7047 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7048 return mips16_big_breakpoint
;
7050 return mips16_little_breakpoint
;
7052 case MIPS_BP_KIND_MICROMIPS16
:
7054 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7055 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7059 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7060 return micromips16_big_breakpoint
;
7062 return micromips16_little_breakpoint
;
7064 case MIPS_BP_KIND_MICROMIPS32
:
7066 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7067 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7070 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7071 return micromips32_big_breakpoint
;
7073 return micromips32_little_breakpoint
;
7075 case MIPS_BP_KIND_MIPS32
:
7077 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7078 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7081 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7082 return big_breakpoint
;
7084 return little_breakpoint
;
7087 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7091 /* Return non-zero if the standard MIPS instruction INST has a branch
7092 delay slot (i.e. it is a jump or branch instruction). This function
7093 is based on mips32_next_pc. */
7096 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7102 op
= itype_op (inst
);
7103 if ((inst
& 0xe0000000) != 0)
7105 rs
= itype_rs (inst
);
7106 rt
= itype_rt (inst
);
7107 return (is_octeon_bbit_op (op
, gdbarch
)
7108 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7109 || op
== 29 /* JALX: bits 011101 */
7112 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7113 || (rs
== 9 && (rt
& 0x2) == 0)
7114 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7115 || (rs
== 10 && (rt
& 0x2) == 0))));
7116 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7119 switch (op
& 0x07) /* extract bits 28,27,26 */
7121 case 0: /* SPECIAL */
7122 op
= rtype_funct (inst
);
7123 return (op
== 8 /* JR */
7124 || op
== 9); /* JALR */
7125 break; /* end SPECIAL */
7126 case 1: /* REGIMM */
7127 rs
= itype_rs (inst
);
7128 rt
= itype_rt (inst
); /* branch condition */
7129 return ((rt
& 0xc) == 0
7130 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7131 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7132 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7133 /* BPOSGE32, BPOSGE64: bits 1110x */
7134 break; /* end REGIMM */
7135 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7141 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7142 delay slot (i.e. it is a jump or branch instruction). */
7145 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7150 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7154 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7157 /* Return non-zero if the microMIPS instruction INSN, comprising the
7158 16-bit major opcode word in the high 16 bits and any second word
7159 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7160 jump or branch instruction). The instruction must be 32-bit if
7161 MUSTBE32 is set or can be any instruction otherwise. */
7164 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7166 ULONGEST major
= insn
>> 16;
7168 switch (micromips_op (major
))
7170 /* 16-bit instructions. */
7171 case 0x33: /* B16: bits 110011 */
7172 case 0x2b: /* BNEZ16: bits 101011 */
7173 case 0x23: /* BEQZ16: bits 100011 */
7175 case 0x11: /* POOL16C: bits 010001 */
7177 && ((b5s5_op (major
) == 0xc
7178 /* JR16: bits 010001 01100 */
7179 || (b5s5_op (major
) & 0x1e) == 0xe)));
7180 /* JALR16, JALRS16: bits 010001 0111x */
7181 /* 32-bit instructions. */
7182 case 0x3d: /* JAL: bits 111101 */
7183 case 0x3c: /* JALX: bits 111100 */
7184 case 0x35: /* J: bits 110101 */
7185 case 0x2d: /* BNE: bits 101101 */
7186 case 0x25: /* BEQ: bits 100101 */
7187 case 0x1d: /* JALS: bits 011101 */
7189 case 0x10: /* POOL32I: bits 010000 */
7190 return ((b5s5_op (major
) & 0x1c) == 0x0
7191 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7192 || (b5s5_op (major
) & 0x1d) == 0x4
7193 /* BLEZ, BGTZ: bits 010000 001x0 */
7194 || (b5s5_op (major
) & 0x1d) == 0x11
7195 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7196 || ((b5s5_op (major
) & 0x1e) == 0x14
7197 && (major
& 0x3) == 0x0)
7198 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7199 || (b5s5_op (major
) & 0x1e) == 0x1a
7200 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7201 || ((b5s5_op (major
) & 0x1e) == 0x1c
7202 && (major
& 0x3) == 0x0)
7203 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7204 || ((b5s5_op (major
) & 0x1c) == 0x1c
7205 && (major
& 0x3) == 0x1));
7206 /* BC1ANY*: bits 010000 111xx xxx01 */
7207 case 0x0: /* POOL32A: bits 000000 */
7208 return (b0s6_op (insn
) == 0x3c
7209 /* POOL32Axf: bits 000000 ... 111100 */
7210 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7211 /* JALR, JALR.HB: 000000 000x111100 111100 */
7212 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7218 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7219 slot (i.e. it is a non-compact jump instruction). The instruction
7220 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7223 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7224 CORE_ADDR addr
, int mustbe32
)
7230 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7233 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7235 if (size
== 2 * MIPS_INSN16_SIZE
)
7237 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7242 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7245 /* Return non-zero if the MIPS16 instruction INST, which must be
7246 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7247 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7248 instruction). This function is based on mips16_next_pc. */
7251 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7253 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7255 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7258 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7259 slot (i.e. it is a non-compact jump instruction). The instruction
7260 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7263 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7264 CORE_ADDR addr
, int mustbe32
)
7266 unsigned short insn
;
7269 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7273 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7276 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7277 This assumes KSSEG exists. */
7280 mips_segment_boundary (CORE_ADDR bpaddr
)
7282 CORE_ADDR mask
= CORE_ADDR_MAX
;
7285 if (sizeof (CORE_ADDR
) == 8)
7286 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7287 a compiler warning produced where CORE_ADDR is a 32-bit type even
7288 though in that case this is dead code). */
7289 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7292 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7293 segsize
= 29; /* 32-bit compatibility segment */
7295 segsize
= 62; /* xkseg */
7297 case 2: /* xkphys */
7300 default: /* xksseg (1), xkuseg/kuseg (0) */
7304 else if (bpaddr
& 0x80000000) /* kernel segment */
7307 segsize
= 31; /* user segment */
7309 return bpaddr
& mask
;
7312 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7313 it backwards if necessary. Return the address of the new location. */
7316 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7318 CORE_ADDR prev_addr
;
7320 CORE_ADDR func_addr
;
7322 /* If a breakpoint is set on the instruction in a branch delay slot,
7323 GDB gets confused. When the breakpoint is hit, the PC isn't on
7324 the instruction in the branch delay slot, the PC will point to
7325 the branch instruction. Since the PC doesn't match any known
7326 breakpoints, GDB reports a trap exception.
7328 There are two possible fixes for this problem.
7330 1) When the breakpoint gets hit, see if the BD bit is set in the
7331 Cause register (which indicates the last exception occurred in a
7332 branch delay slot). If the BD bit is set, fix the PC to point to
7333 the instruction in the branch delay slot.
7335 2) When the user sets the breakpoint, don't allow him to set the
7336 breakpoint on the instruction in the branch delay slot. Instead
7337 move the breakpoint to the branch instruction (which will have
7340 The problem with the first solution is that if the user then
7341 single-steps the processor, the branch instruction will get
7342 skipped (since GDB thinks the PC is on the instruction in the
7345 So, we'll use the second solution. To do this we need to know if
7346 the instruction we're trying to set the breakpoint on is in the
7347 branch delay slot. */
7349 boundary
= mips_segment_boundary (bpaddr
);
7351 /* Make sure we don't scan back before the beginning of the current
7352 function, since we may fetch constant data or insns that look like
7353 a jump. Of course we might do that anyway if the compiler has
7354 moved constants inline. :-( */
7355 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7356 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7357 boundary
= func_addr
;
7359 if (mips_pc_is_mips (bpaddr
))
7361 if (bpaddr
== boundary
)
7364 /* If the previous instruction has a branch delay slot, we have
7365 to move the breakpoint to the branch instruction. */
7366 prev_addr
= bpaddr
- 4;
7367 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7372 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7373 CORE_ADDR addr
, jmpaddr
;
7376 boundary
= unmake_compact_addr (boundary
);
7378 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7379 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7380 so try for that first, then try the 2 byte JALR/JR.
7381 The microMIPS ASE has a whole range of jumps and branches
7382 with delay slots, some of which take 4 bytes and some take
7383 2 bytes, so the idea is the same.
7384 FIXME: We have to assume that bpaddr is not the second half
7385 of an extended instruction. */
7386 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7387 ? micromips_insn_at_pc_has_delay_slot
7388 : mips16_insn_at_pc_has_delay_slot
);
7392 for (i
= 1; i
< 4; i
++)
7394 if (unmake_compact_addr (addr
) == boundary
)
7396 addr
-= MIPS_INSN16_SIZE
;
7397 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7398 /* Looks like a JR/JALR at [target-1], but it could be
7399 the second word of a previous JAL/JALX, so record it
7400 and check back one more. */
7402 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7405 /* Looks like a JAL/JALX at [target-2], but it could also
7406 be the second word of a previous JAL/JALX, record it,
7407 and check back one more. */
7410 /* Looks like a JAL/JALX at [target-3], so any previously
7411 recorded JAL/JALX or JR/JALR must be wrong, because:
7414 -2: JAL-ext (can't be JAL/JALX)
7415 -1: bdslot (can't be JR/JALR)
7418 Of course it could be another JAL-ext which looks
7419 like a JAL, but in that case we'd have broken out
7420 of this loop at [target-2]:
7424 -2: bdslot (can't be jmp)
7431 /* Not a jump instruction: if we're at [target-1] this
7432 could be the second word of a JAL/JALX, so continue;
7433 otherwise we're done. */
7446 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7447 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7450 mips_is_stub_suffix (const char *suffix
, int zero
)
7455 return zero
&& suffix
[1] == '\0';
7457 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7462 return suffix
[1] == '\0';
7468 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7469 call stubs, one of sf, df, sc, or dc. */
7472 mips_is_stub_mode (const char *mode
)
7474 return ((mode
[0] == 's' || mode
[0] == 'd')
7475 && (mode
[1] == 'f' || mode
[1] == 'c'));
7478 /* Code at PC is a compiler-generated stub. Such a stub for a function
7479 bar might have a name like __fn_stub_bar, and might look like this:
7486 followed by (or interspersed with):
7493 addiu $25, $25, %lo(bar)
7496 ($1 may be used in old code; for robustness we accept any register)
7499 lui $28, %hi(_gp_disp)
7500 addiu $28, $28, %lo(_gp_disp)
7503 addiu $25, $25, %lo(bar)
7506 In the case of a __call_stub_bar stub, the sequence to set up
7507 arguments might look like this:
7514 followed by (or interspersed with) one of the jump sequences above.
7516 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7517 of J or JR, respectively, followed by:
7523 We are at the beginning of the stub here, and scan down and extract
7524 the target address from the jump immediate instruction or, if a jump
7525 register instruction is used, from the register referred. Return
7526 the value of PC calculated or 0 if inconclusive.
7528 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7531 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7533 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7534 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7535 int addrreg
= MIPS_ZERO_REGNUM
;
7536 CORE_ADDR start_pc
= pc
;
7537 CORE_ADDR target_pc
= 0;
7544 status
== 0 && target_pc
== 0 && i
< 20;
7545 i
++, pc
+= MIPS_INSN32_SIZE
)
7547 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7553 switch (itype_op (inst
))
7555 case 0: /* SPECIAL */
7556 switch (rtype_funct (inst
))
7560 rs
= rtype_rs (inst
);
7561 if (rs
== MIPS_GP_REGNUM
)
7562 target_pc
= gp
; /* Hmm... */
7563 else if (rs
== addrreg
)
7567 case 0x21: /* ADDU */
7568 rt
= rtype_rt (inst
);
7569 rs
= rtype_rs (inst
);
7570 rd
= rtype_rd (inst
);
7571 if (rd
== MIPS_GP_REGNUM
7572 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7573 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7581 target_pc
= jtype_target (inst
) << 2;
7582 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7586 rt
= itype_rt (inst
);
7587 rs
= itype_rs (inst
);
7590 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7591 if (rt
== MIPS_GP_REGNUM
)
7593 else if (rt
== addrreg
)
7599 rt
= itype_rt (inst
);
7600 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7601 if (rt
== MIPS_GP_REGNUM
)
7603 else if (rt
!= MIPS_ZERO_REGNUM
)
7611 rt
= itype_rt (inst
);
7612 rs
= itype_rs (inst
);
7613 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7614 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7618 memset (buf
, 0, sizeof (buf
));
7619 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7621 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7630 /* If PC is in a MIPS16 call or return stub, return the address of the
7631 target PC, which is either the callee or the caller. There are several
7632 cases which must be handled:
7634 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7635 and the target PC is in $31 ($ra).
7636 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7637 and the target PC is in $2.
7638 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7639 i.e. before the JALR instruction, this is effectively a call stub
7640 and the target PC is in $2. Otherwise this is effectively
7641 a return stub and the target PC is in $18.
7642 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7643 JAL or JALR instruction, this is effectively a call stub and the
7644 target PC is buried in the instruction stream. Otherwise this
7645 is effectively a return stub and the target PC is in $18.
7646 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7647 stub and the target PC is buried in the instruction stream.
7649 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7650 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7654 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7656 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7657 CORE_ADDR start_addr
;
7661 /* Find the starting address and name of the function containing the PC. */
7662 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7665 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7666 and the target PC is in $31 ($ra). */
7667 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7668 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7669 && mips_is_stub_mode (name
+ prefixlen
)
7670 && name
[prefixlen
+ 2] == '\0')
7671 return get_frame_register_signed
7672 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7674 /* If the PC is in __mips16_call_stub_*, this is one of the call
7675 call/return stubs. */
7676 prefixlen
= strlen (mips_str_mips16_call_stub
);
7677 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7679 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7680 and the target PC is in $2. */
7681 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7682 return get_frame_register_signed
7683 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7685 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7686 i.e. before the JALR instruction, this is effectively a call stub
7687 and the target PC is in $2. Otherwise this is effectively
7688 a return stub and the target PC is in $18. */
7689 else if (mips_is_stub_mode (name
+ prefixlen
)
7690 && name
[prefixlen
+ 2] == '_'
7691 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7693 if (pc
== start_addr
)
7694 /* This is the 'call' part of a call stub. The return
7695 address is in $2. */
7696 return get_frame_register_signed
7697 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7699 /* This is the 'return' part of a call stub. The return
7700 address is in $18. */
7701 return get_frame_register_signed
7702 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7705 return 0; /* Not a stub. */
7708 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7709 compiler-generated call or call/return stubs. */
7710 if (startswith (name
, mips_str_fn_stub
)
7711 || startswith (name
, mips_str_call_stub
))
7713 if (pc
== start_addr
)
7714 /* This is the 'call' part of a call stub. Call this helper
7715 to scan through this code for interesting instructions
7716 and determine the final PC. */
7717 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7719 /* This is the 'return' part of a call stub. The return address
7721 return get_frame_register_signed
7722 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7725 return 0; /* Not a stub. */
7728 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7729 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7732 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7734 CORE_ADDR start_addr
;
7737 /* Find the starting address of the function containing the PC. */
7738 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7741 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7742 the start, i.e. after the JALR instruction, this is effectively
7744 prefixlen
= strlen (mips_str_mips16_call_stub
);
7745 if (pc
!= start_addr
7746 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7747 && mips_is_stub_mode (name
+ prefixlen
)
7748 && name
[prefixlen
+ 2] == '_'
7749 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7752 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7753 the JAL or JALR instruction, this is effectively a return stub. */
7754 prefixlen
= strlen (mips_str_call_fp_stub
);
7755 if (pc
!= start_addr
7756 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7759 /* Consume the .pic. prefix of any PIC stub, this function must return
7760 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7761 or the call stub path will trigger in handle_inferior_event causing
7763 prefixlen
= strlen (mips_str_pic
);
7764 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7767 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7768 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7769 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7770 && mips_is_stub_mode (name
+ prefixlen
)
7771 && name
[prefixlen
+ 2] == '\0')
7774 return 0; /* Not a stub. */
7777 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7778 PC of the stub target. The stub just loads $t9 and jumps to it,
7779 so that $t9 has the correct value at function entry. */
7782 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7784 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7785 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7786 struct bound_minimal_symbol msym
;
7788 gdb_byte stub_code
[16];
7789 int32_t stub_words
[4];
7791 /* The stub for foo is named ".pic.foo", and is either two
7792 instructions inserted before foo or a three instruction sequence
7793 which jumps to foo. */
7794 msym
= lookup_minimal_symbol_by_pc (pc
);
7795 if (msym
.minsym
== NULL
7796 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7797 || msym
.minsym
->linkage_name () == NULL
7798 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7801 /* A two-instruction header. */
7802 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7805 /* A three-instruction (plus delay slot) trampoline. */
7806 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7808 if (target_read_memory (pc
, stub_code
, 16) != 0)
7810 for (i
= 0; i
< 4; i
++)
7811 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7814 /* A stub contains these instructions:
7817 addiu t9, t9, %lo(target)
7820 This works even for N64, since stubs are only generated with
7822 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7823 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7824 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7825 && stub_words
[3] == 0x00000000)
7826 return ((((stub_words
[0] & 0x0000ffff) << 16)
7827 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7830 /* Not a recognized stub. */
7835 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7837 CORE_ADDR requested_pc
= pc
;
7838 CORE_ADDR target_pc
;
7845 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7849 new_pc
= find_solib_trampoline_target (frame
, pc
);
7853 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7857 while (pc
!= target_pc
);
7859 return pc
!= requested_pc
? pc
: 0;
7862 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7863 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7866 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7869 if (num
>= 0 && num
< 32)
7871 else if (num
>= 38 && num
< 70)
7872 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7874 regnum
= mips_regnum (gdbarch
)->hi
;
7876 regnum
= mips_regnum (gdbarch
)->lo
;
7877 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7878 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7881 return gdbarch_num_regs (gdbarch
) + regnum
;
7885 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7886 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7889 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7892 if (num
>= 0 && num
< 32)
7894 else if (num
>= 32 && num
< 64)
7895 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7897 regnum
= mips_regnum (gdbarch
)->hi
;
7899 regnum
= mips_regnum (gdbarch
)->lo
;
7900 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7901 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7904 return gdbarch_num_regs (gdbarch
) + regnum
;
7908 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7910 /* Only makes sense to supply raw registers. */
7911 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7912 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7913 decide if it is valid. Should instead define a standard sim/gdb
7914 register numbering scheme. */
7915 if (gdbarch_register_name (gdbarch
,
7916 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7917 && gdbarch_register_name (gdbarch
,
7918 gdbarch_num_regs (gdbarch
)
7919 + regnum
)[0] != '\0')
7922 return LEGACY_SIM_REGNO_IGNORE
;
7926 /* Convert an integer into an address. Extracting the value signed
7927 guarantees a correctly sign extended address. */
7930 mips_integer_to_address (struct gdbarch
*gdbarch
,
7931 struct type
*type
, const gdb_byte
*buf
)
7933 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7934 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7937 /* Dummy virtual frame pointer method. This is no more or less accurate
7938 than most other architectures; we just need to be explicit about it,
7939 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7940 an assertion failure. */
7943 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7944 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7946 *reg
= MIPS_SP_REGNUM
;
7951 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7953 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7954 const char *name
= bfd_section_name (sect
);
7956 if (*abip
!= MIPS_ABI_UNKNOWN
)
7959 if (!startswith (name
, ".mdebug."))
7962 if (strcmp (name
, ".mdebug.abi32") == 0)
7963 *abip
= MIPS_ABI_O32
;
7964 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7965 *abip
= MIPS_ABI_N32
;
7966 else if (strcmp (name
, ".mdebug.abi64") == 0)
7967 *abip
= MIPS_ABI_N64
;
7968 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7969 *abip
= MIPS_ABI_O64
;
7970 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7971 *abip
= MIPS_ABI_EABI32
;
7972 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7973 *abip
= MIPS_ABI_EABI64
;
7975 warning (_("unsupported ABI %s."), name
+ 8);
7979 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7981 int *lbp
= (int *) obj
;
7982 const char *name
= bfd_section_name (sect
);
7984 if (startswith (name
, ".gcc_compiled_long32"))
7986 else if (startswith (name
, ".gcc_compiled_long64"))
7988 else if (startswith (name
, ".gcc_compiled_long"))
7989 warning (_("unrecognized .gcc_compiled_longXX"));
7992 static enum mips_abi
7993 global_mips_abi (void)
7997 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7998 if (mips_abi_strings
[i
] == mips_abi_string
)
7999 return (enum mips_abi
) i
;
8001 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8004 /* Return the default compressed instruction set, either of MIPS16
8005 or microMIPS, selected when none could have been determined from
8006 the ELF header of the binary being executed (or no binary has been
8009 static enum mips_isa
8010 global_mips_compression (void)
8014 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8015 if (mips_compression_strings
[i
] == mips_compression_string
)
8016 return (enum mips_isa
) i
;
8018 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8022 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8024 /* If the size matches the set of 32-bit or 64-bit integer registers,
8025 assume that's what we've got. */
8026 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8027 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8029 /* If the size matches the full set of registers GDB traditionally
8030 knows about, including floating point, for either 32-bit or
8031 64-bit, assume that's what we've got. */
8032 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8033 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8035 /* Otherwise we don't have a useful guess. */
8038 static struct value
*
8039 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8041 const int *reg_p
= (const int *) baton
;
8042 return value_of_register (*reg_p
, frame
);
8045 static struct gdbarch
*
8046 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8048 struct gdbarch
*gdbarch
;
8049 struct gdbarch_tdep
*tdep
;
8051 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8053 enum mips_fpu_type fpu_type
;
8054 tdesc_arch_data_up tdesc_data
;
8055 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8056 const char * const *reg_names
;
8057 struct mips_regnum mips_regnum
, *regnum
;
8058 enum mips_isa mips_isa
;
8062 /* First of all, extract the elf_flags, if available. */
8063 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8064 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8065 else if (arches
!= NULL
)
8066 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8070 fprintf_unfiltered (gdb_stdlog
,
8071 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8073 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8074 switch ((elf_flags
& EF_MIPS_ABI
))
8076 case E_MIPS_ABI_O32
:
8077 found_abi
= MIPS_ABI_O32
;
8079 case E_MIPS_ABI_O64
:
8080 found_abi
= MIPS_ABI_O64
;
8082 case E_MIPS_ABI_EABI32
:
8083 found_abi
= MIPS_ABI_EABI32
;
8085 case E_MIPS_ABI_EABI64
:
8086 found_abi
= MIPS_ABI_EABI64
;
8089 if ((elf_flags
& EF_MIPS_ABI2
))
8090 found_abi
= MIPS_ABI_N32
;
8092 found_abi
= MIPS_ABI_UNKNOWN
;
8096 /* GCC creates a pseudo-section whose name describes the ABI. */
8097 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8098 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8100 /* If we have no useful BFD information, use the ABI from the last
8101 MIPS architecture (if there is one). */
8102 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8103 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8105 /* Try the architecture for any hint of the correct ABI. */
8106 if (found_abi
== MIPS_ABI_UNKNOWN
8107 && info
.bfd_arch_info
!= NULL
8108 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8110 switch (info
.bfd_arch_info
->mach
)
8112 case bfd_mach_mips3900
:
8113 found_abi
= MIPS_ABI_EABI32
;
8115 case bfd_mach_mips4100
:
8116 case bfd_mach_mips5000
:
8117 found_abi
= MIPS_ABI_EABI64
;
8119 case bfd_mach_mips8000
:
8120 case bfd_mach_mips10000
:
8121 /* On Irix, ELF64 executables use the N64 ABI. The
8122 pseudo-sections which describe the ABI aren't present
8123 on IRIX. (Even for executables created by gcc.) */
8124 if (info
.abfd
!= NULL
8125 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8126 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8127 found_abi
= MIPS_ABI_N64
;
8129 found_abi
= MIPS_ABI_N32
;
8134 /* Default 64-bit objects to N64 instead of O32. */
8135 if (found_abi
== MIPS_ABI_UNKNOWN
8136 && info
.abfd
!= NULL
8137 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8138 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8139 found_abi
= MIPS_ABI_N64
;
8142 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8145 /* What has the user specified from the command line? */
8146 wanted_abi
= global_mips_abi ();
8148 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8151 /* Now that we have found what the ABI for this binary would be,
8152 check whether the user is overriding it. */
8153 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8154 mips_abi
= wanted_abi
;
8155 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8156 mips_abi
= found_abi
;
8158 mips_abi
= MIPS_ABI_O32
;
8160 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8163 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8164 if (mips_abi
!= MIPS_ABI_EABI32
8165 && mips_abi
!= MIPS_ABI_O32
8166 && info
.bfd_arch_info
!= NULL
8167 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8168 && info
.bfd_arch_info
->bits_per_word
< 64)
8169 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8171 /* Determine the default compressed ISA. */
8172 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8173 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8174 mips_isa
= ISA_MICROMIPS
;
8175 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8176 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8177 mips_isa
= ISA_MIPS16
;
8179 mips_isa
= global_mips_compression ();
8180 mips_compression_string
= mips_compression_strings
[mips_isa
];
8182 /* Also used when doing an architecture lookup. */
8184 fprintf_unfiltered (gdb_stdlog
,
8185 "mips_gdbarch_init: "
8186 "mips64_transfers_32bit_regs_p = %d\n",
8187 mips64_transfers_32bit_regs_p
);
8189 /* Determine the MIPS FPU type. */
8192 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8193 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8194 Tag_GNU_MIPS_ABI_FP
);
8195 #endif /* HAVE_ELF */
8197 if (!mips_fpu_type_auto
)
8198 fpu_type
= mips_fpu_type
;
8199 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8201 switch (elf_fpu_type
)
8203 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8204 fpu_type
= MIPS_FPU_DOUBLE
;
8206 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8207 fpu_type
= MIPS_FPU_SINGLE
;
8209 case Val_GNU_MIPS_ABI_FP_SOFT
:
8211 /* Soft float or unknown. */
8212 fpu_type
= MIPS_FPU_NONE
;
8216 else if (info
.bfd_arch_info
!= NULL
8217 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8218 switch (info
.bfd_arch_info
->mach
)
8220 case bfd_mach_mips3900
:
8221 case bfd_mach_mips4100
:
8222 case bfd_mach_mips4111
:
8223 case bfd_mach_mips4120
:
8224 fpu_type
= MIPS_FPU_NONE
;
8226 case bfd_mach_mips4650
:
8227 fpu_type
= MIPS_FPU_SINGLE
;
8230 fpu_type
= MIPS_FPU_DOUBLE
;
8233 else if (arches
!= NULL
)
8234 fpu_type
= MIPS_FPU_TYPE (arches
->gdbarch
);
8236 fpu_type
= MIPS_FPU_DOUBLE
;
8238 fprintf_unfiltered (gdb_stdlog
,
8239 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8241 /* Check for blatant incompatibilities. */
8243 /* If we have only 32-bit registers, then we can't debug a 64-bit
8245 if (info
.target_desc
8246 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8247 && mips_abi
!= MIPS_ABI_EABI32
8248 && mips_abi
!= MIPS_ABI_O32
)
8251 /* Fill in the OS dependent register numbers and names. */
8252 if (info
.osabi
== GDB_OSABI_LINUX
)
8254 mips_regnum
.fp0
= 38;
8255 mips_regnum
.pc
= 37;
8256 mips_regnum
.cause
= 36;
8257 mips_regnum
.badvaddr
= 35;
8258 mips_regnum
.hi
= 34;
8259 mips_regnum
.lo
= 33;
8260 mips_regnum
.fp_control_status
= 70;
8261 mips_regnum
.fp_implementation_revision
= 71;
8262 mips_regnum
.dspacc
= -1;
8263 mips_regnum
.dspctl
= -1;
8267 reg_names
= mips_linux_reg_names
;
8271 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8272 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8273 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8274 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8275 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8276 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8277 mips_regnum
.fp_control_status
= 70;
8278 mips_regnum
.fp_implementation_revision
= 71;
8279 mips_regnum
.dspacc
= dspacc
= -1;
8280 mips_regnum
.dspctl
= dspctl
= -1;
8281 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8282 if (info
.bfd_arch_info
!= NULL
8283 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8284 reg_names
= mips_tx39_reg_names
;
8286 reg_names
= mips_generic_reg_names
;
8289 /* Check any target description for validity. */
8290 if (tdesc_has_registers (info
.target_desc
))
8292 static const char *const mips_gprs
[] = {
8293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8295 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8296 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8298 static const char *const mips_fprs
[] = {
8299 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8300 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8301 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8302 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8305 const struct tdesc_feature
*feature
;
8308 feature
= tdesc_find_feature (info
.target_desc
,
8309 "org.gnu.gdb.mips.cpu");
8310 if (feature
== NULL
)
8313 tdesc_data
= tdesc_data_alloc ();
8316 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8317 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8321 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8322 mips_regnum
.lo
, "lo");
8323 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8324 mips_regnum
.hi
, "hi");
8325 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8326 mips_regnum
.pc
, "pc");
8331 feature
= tdesc_find_feature (info
.target_desc
,
8332 "org.gnu.gdb.mips.cp0");
8333 if (feature
== NULL
)
8337 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8338 mips_regnum
.badvaddr
, "badvaddr");
8339 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8340 MIPS_PS_REGNUM
, "status");
8341 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8342 mips_regnum
.cause
, "cause");
8347 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8348 backend is not prepared for that, though. */
8349 feature
= tdesc_find_feature (info
.target_desc
,
8350 "org.gnu.gdb.mips.fpu");
8351 if (feature
== NULL
)
8355 for (i
= 0; i
< 32; i
++)
8356 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8357 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8359 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8360 mips_regnum
.fp_control_status
,
8363 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8364 mips_regnum
.fp_implementation_revision
,
8370 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8374 feature
= tdesc_find_feature (info
.target_desc
,
8375 "org.gnu.gdb.mips.dsp");
8376 /* The DSP registers are optional; it's OK if they are absent. */
8377 if (feature
!= NULL
)
8381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8382 dspacc
+ i
++, "hi1");
8383 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8384 dspacc
+ i
++, "lo1");
8385 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8386 dspacc
+ i
++, "hi2");
8387 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8388 dspacc
+ i
++, "lo2");
8389 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8390 dspacc
+ i
++, "hi3");
8391 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8392 dspacc
+ i
++, "lo3");
8394 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8400 mips_regnum
.dspacc
= dspacc
;
8401 mips_regnum
.dspctl
= dspctl
;
8403 num_regs
= mips_regnum
.dspctl
+ 1;
8407 /* It would be nice to detect an attempt to use a 64-bit ABI
8408 when only 32-bit registers are provided. */
8412 /* Try to find a pre-existing architecture. */
8413 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8415 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8417 /* MIPS needs to be pedantic about which ABI and the compressed
8418 ISA variation the object is using. */
8419 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8421 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8423 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8425 /* Need to be pedantic about which register virtual size is
8427 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8428 != mips64_transfers_32bit_regs_p
)
8430 /* Be pedantic about which FPU is selected. */
8431 if (MIPS_FPU_TYPE (arches
->gdbarch
) != fpu_type
)
8434 return arches
->gdbarch
;
8437 /* Need a new architecture. Fill in a target specific vector. */
8438 tdep
= XCNEW (struct gdbarch_tdep
);
8439 gdbarch
= gdbarch_alloc (&info
, tdep
);
8440 tdep
->elf_flags
= elf_flags
;
8441 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8442 tdep
->found_abi
= found_abi
;
8443 tdep
->mips_abi
= mips_abi
;
8444 tdep
->mips_isa
= mips_isa
;
8445 tdep
->mips_fpu_type
= fpu_type
;
8446 tdep
->register_size_valid_p
= 0;
8447 tdep
->register_size
= 0;
8449 if (info
.target_desc
)
8451 /* Some useful properties can be inferred from the target. */
8452 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8454 tdep
->register_size_valid_p
= 1;
8455 tdep
->register_size
= 4;
8457 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8459 tdep
->register_size_valid_p
= 1;
8460 tdep
->register_size
= 8;
8464 /* Initially set everything according to the default ABI/ISA. */
8465 set_gdbarch_short_bit (gdbarch
, 16);
8466 set_gdbarch_int_bit (gdbarch
, 32);
8467 set_gdbarch_float_bit (gdbarch
, 32);
8468 set_gdbarch_double_bit (gdbarch
, 64);
8469 set_gdbarch_long_double_bit (gdbarch
, 64);
8470 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8471 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8472 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8474 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8475 mips_ax_pseudo_register_collect
);
8476 set_gdbarch_ax_pseudo_register_push_stack
8477 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8479 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8480 mips_elf_make_msymbol_special
);
8481 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8482 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8483 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8485 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8486 *regnum
= mips_regnum
;
8487 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8488 set_gdbarch_num_regs (gdbarch
, num_regs
);
8489 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8490 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8491 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8492 tdep
->mips_processor_reg_names
= reg_names
;
8493 tdep
->regnum
= regnum
;
8498 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8499 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8500 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8501 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8502 tdep
->default_mask_address_p
= 0;
8503 set_gdbarch_long_bit (gdbarch
, 32);
8504 set_gdbarch_ptr_bit (gdbarch
, 32);
8505 set_gdbarch_long_long_bit (gdbarch
, 64);
8508 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8509 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8510 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8511 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8512 tdep
->default_mask_address_p
= 0;
8513 set_gdbarch_long_bit (gdbarch
, 32);
8514 set_gdbarch_ptr_bit (gdbarch
, 32);
8515 set_gdbarch_long_long_bit (gdbarch
, 64);
8517 case MIPS_ABI_EABI32
:
8518 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8519 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8520 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8521 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8522 tdep
->default_mask_address_p
= 0;
8523 set_gdbarch_long_bit (gdbarch
, 32);
8524 set_gdbarch_ptr_bit (gdbarch
, 32);
8525 set_gdbarch_long_long_bit (gdbarch
, 64);
8527 case MIPS_ABI_EABI64
:
8528 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8529 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8530 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8531 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8532 tdep
->default_mask_address_p
= 0;
8533 set_gdbarch_long_bit (gdbarch
, 64);
8534 set_gdbarch_ptr_bit (gdbarch
, 64);
8535 set_gdbarch_long_long_bit (gdbarch
, 64);
8538 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8539 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8540 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8541 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8542 tdep
->default_mask_address_p
= 0;
8543 set_gdbarch_long_bit (gdbarch
, 32);
8544 set_gdbarch_ptr_bit (gdbarch
, 32);
8545 set_gdbarch_long_long_bit (gdbarch
, 64);
8546 set_gdbarch_long_double_bit (gdbarch
, 128);
8547 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8550 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8551 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8552 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8553 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8554 tdep
->default_mask_address_p
= 0;
8555 set_gdbarch_long_bit (gdbarch
, 64);
8556 set_gdbarch_ptr_bit (gdbarch
, 64);
8557 set_gdbarch_long_long_bit (gdbarch
, 64);
8558 set_gdbarch_long_double_bit (gdbarch
, 128);
8559 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8562 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8565 /* GCC creates a pseudo-section whose name specifies the size of
8566 longs, since -mlong32 or -mlong64 may be used independent of
8567 other options. How those options affect pointer sizes is ABI and
8568 architecture dependent, so use them to override the default sizes
8569 set by the ABI. This table shows the relationship between ABI,
8570 -mlongXX, and size of pointers:
8572 ABI -mlongXX ptr bits
8573 --- -------- --------
8587 Note that for o32 and eabi32, pointers are always 32 bits
8588 regardless of any -mlongXX option. For all others, pointers and
8589 longs are the same, as set by -mlongXX or set by defaults. */
8591 if (info
.abfd
!= NULL
)
8595 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8598 set_gdbarch_long_bit (gdbarch
, long_bit
);
8602 case MIPS_ABI_EABI32
:
8607 case MIPS_ABI_EABI64
:
8608 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8611 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8616 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8617 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8620 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8621 flag in object files because to do so would make it impossible to
8622 link with libraries compiled without "-gp32". This is
8623 unnecessarily restrictive.
8625 We could solve this problem by adding "-gp32" multilibs to gcc,
8626 but to set this flag before gcc is built with such multilibs will
8627 break too many systems.''
8629 But even more unhelpfully, the default linker output target for
8630 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8631 for 64-bit programs - you need to change the ABI to change this,
8632 and not all gcc targets support that currently. Therefore using
8633 this flag to detect 32-bit mode would do the wrong thing given
8634 the current gcc - it would make GDB treat these 64-bit programs
8635 as 32-bit programs by default. */
8637 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8638 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8640 /* Add/remove bits from an address. The MIPS needs be careful to
8641 ensure that all 32 bit addresses are sign extended to 64 bits. */
8642 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8644 /* Unwind the frame. */
8645 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8646 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8647 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8649 /* Map debug register numbers onto internal register numbers. */
8650 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8651 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8652 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8653 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8654 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8655 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8657 /* MIPS version of CALL_DUMMY. */
8659 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8660 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8661 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8663 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8665 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8666 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8667 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8669 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8670 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8671 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8672 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8673 mips_adjust_breakpoint_address
);
8675 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8677 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8679 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8680 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8681 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8683 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8685 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8687 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8688 if (mips_abi
== MIPS_ABI_N64
)
8689 set_gdbarch_disassembler_options_implicit
8690 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8691 else if (mips_abi
== MIPS_ABI_N32
)
8692 set_gdbarch_disassembler_options_implicit
8693 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8695 set_gdbarch_disassembler_options_implicit
8696 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8697 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8698 set_gdbarch_valid_disassembler_options (gdbarch
,
8699 disassembler_options_mips ());
8701 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8702 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8703 need to all be folded into the target vector. Since they are
8704 being used as guards for target_stopped_by_watchpoint, why not have
8705 target_stopped_by_watchpoint return the type of watchpoint that the code
8707 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8709 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8711 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8712 to support MIPS16. This is a bad thing. Make sure not to do it
8713 if we have an OS ABI that actually supports shared libraries, since
8714 shared library support is more important. If we have an OS someday
8715 that supports both shared libraries and MIPS16, we'll have to find
8716 a better place for these.
8717 macro/2012-04-25: But that applies to return trampolines only and
8718 currently no MIPS OS ABI uses shared libraries that have them. */
8719 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8721 set_gdbarch_single_step_through_delay (gdbarch
,
8722 mips_single_step_through_delay
);
8724 /* Virtual tables. */
8725 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8727 mips_register_g_packet_guesses (gdbarch
);
8729 /* Hook in OS ABI-specific overrides, if they have been registered. */
8730 info
.tdesc_data
= tdesc_data
.get ();
8731 gdbarch_init_osabi (info
, gdbarch
);
8733 /* The hook may have adjusted num_regs, fetch the final value and
8734 set pc_regnum and sp_regnum now that it has been fixed. */
8735 num_regs
= gdbarch_num_regs (gdbarch
);
8736 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8737 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8739 /* Unwind the frame. */
8740 dwarf2_append_unwinders (gdbarch
);
8741 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8742 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8743 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8744 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8745 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8746 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8747 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8748 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8749 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8751 if (tdesc_data
!= nullptr)
8753 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8754 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8756 /* Override the normal target description methods to handle our
8757 dual real and pseudo registers. */
8758 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8759 set_gdbarch_register_reggroup_p (gdbarch
,
8760 mips_tdesc_register_reggroup_p
);
8762 num_regs
= gdbarch_num_regs (gdbarch
);
8763 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8764 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8765 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8768 /* Add ABI-specific aliases for the registers. */
8769 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8770 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8771 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8772 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8774 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8775 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8776 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8778 /* Add some other standard aliases. */
8779 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8780 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8781 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8783 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8784 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8785 value_of_mips_user_reg
,
8786 &mips_numeric_register_aliases
[i
].regnum
);
8792 mips_abi_update (const char *ignore_args
,
8793 int from_tty
, struct cmd_list_element
*c
)
8795 struct gdbarch_info info
;
8797 /* Force the architecture to update, and (if it's a MIPS architecture)
8798 mips_gdbarch_init will take care of the rest. */
8799 gdbarch_info_init (&info
);
8800 gdbarch_update_p (info
);
8803 /* Print out which MIPS ABI is in use. */
8806 show_mips_abi (struct ui_file
*file
,
8808 struct cmd_list_element
*ignored_cmd
,
8809 const char *ignored_value
)
8811 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8814 "The MIPS ABI is unknown because the current architecture "
8818 enum mips_abi global_abi
= global_mips_abi ();
8819 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8820 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8822 if (global_abi
== MIPS_ABI_UNKNOWN
)
8825 "The MIPS ABI is set automatically (currently \"%s\").\n",
8827 else if (global_abi
== actual_abi
)
8830 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8834 /* Probably shouldn't happen... */
8835 fprintf_filtered (file
,
8836 "The (auto detected) MIPS ABI \"%s\" is in use "
8837 "even though the user setting was \"%s\".\n",
8838 actual_abi_str
, mips_abi_strings
[global_abi
]);
8843 /* Print out which MIPS compressed ISA encoding is used. */
8846 show_mips_compression (struct ui_file
*file
, int from_tty
,
8847 struct cmd_list_element
*c
, const char *value
)
8849 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8853 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8856 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8862 case MIPS_FPU_SINGLE
:
8864 case MIPS_FPU_DOUBLE
:
8872 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8874 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8878 int ef_mips_32bitmode
;
8879 /* Determine the ISA. */
8880 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8898 /* Determine the size of a pointer. */
8899 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8900 fprintf_unfiltered (file
,
8901 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8903 fprintf_unfiltered (file
,
8904 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8906 fprintf_unfiltered (file
,
8907 "mips_dump_tdep: ef_mips_arch = %d\n",
8909 fprintf_unfiltered (file
,
8910 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8911 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8912 fprintf_unfiltered (file
,
8914 "mips_mask_address_p() %d (default %d)\n",
8915 mips_mask_address_p (tdep
),
8916 tdep
->default_mask_address_p
);
8918 fprintf_unfiltered (file
,
8919 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8920 MIPS_DEFAULT_FPU_TYPE
,
8921 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8922 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8923 MIPS_EABI (gdbarch
));
8924 fprintf_unfiltered (file
,
8925 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8926 MIPS_FPU_TYPE (gdbarch
),
8927 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch
)));
8930 void _initialize_mips_tdep ();
8932 _initialize_mips_tdep ()
8934 static struct cmd_list_element
*mipsfpulist
= NULL
;
8936 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8937 if (MIPS_ABI_LAST
+ 1
8938 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8939 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8941 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8943 /* Create feature sets with the appropriate properties. The values
8944 are not important. */
8945 mips_tdesc_gp32
= allocate_target_description ().release ();
8946 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8948 mips_tdesc_gp64
= allocate_target_description ().release ();
8949 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8951 /* Add root prefix command for all "set mips"/"show mips" commands. */
8952 add_basic_prefix_cmd ("mips", no_class
,
8953 _("Various MIPS specific commands."),
8954 &setmipscmdlist
, "set mips ", 0, &setlist
);
8956 add_show_prefix_cmd ("mips", no_class
,
8957 _("Various MIPS specific commands."),
8958 &showmipscmdlist
, "show mips ", 0, &showlist
);
8960 /* Allow the user to override the ABI. */
8961 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8962 &mips_abi_string
, _("\
8963 Set the MIPS ABI used by this program."), _("\
8964 Show the MIPS ABI used by this program."), _("\
8965 This option can be set to one of:\n\
8966 auto - the default ABI associated with the current binary\n\
8975 &setmipscmdlist
, &showmipscmdlist
);
8977 /* Allow the user to set the ISA to assume for compressed code if ELF
8978 file flags don't tell or there is no program file selected. This
8979 setting is updated whenever unambiguous ELF file flags are interpreted,
8980 and carried over to subsequent sessions. */
8981 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8982 &mips_compression_string
, _("\
8983 Set the compressed ISA encoding used by MIPS code."), _("\
8984 Show the compressed ISA encoding used by MIPS code."), _("\
8985 Select the compressed ISA encoding used in functions that have no symbol\n\
8986 information available. The encoding can be set to either of:\n\
8989 and is updated automatically from ELF file flags if available."),
8991 show_mips_compression
,
8992 &setmipscmdlist
, &showmipscmdlist
);
8994 /* Let the user turn off floating point and set the fence post for
8995 heuristic_proc_start. */
8997 add_basic_prefix_cmd ("mipsfpu", class_support
,
8998 _("Set use of MIPS floating-point coprocessor."),
8999 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9000 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9001 _("Select single-precision MIPS floating-point coprocessor."),
9003 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9004 _("Select double-precision MIPS floating-point coprocessor."),
9006 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9007 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9008 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9009 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9010 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9011 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9012 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9013 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9014 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9015 _("Select MIPS floating-point coprocessor automatically."),
9017 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9018 _("Show current use of MIPS floating-point coprocessor target."),
9021 /* We really would like to have both "0" and "unlimited" work, but
9022 command.c doesn't deal with that. So make it a var_zinteger
9023 because the user can always use "999999" or some such for unlimited. */
9024 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9025 &heuristic_fence_post
, _("\
9026 Set the distance searched for the start of a function."), _("\
9027 Show the distance searched for the start of a function."), _("\
9028 If you are debugging a stripped executable, GDB needs to search through the\n\
9029 program for the start of a function. This command sets the distance of the\n\
9030 search. The only need to set it is when debugging a stripped executable."),
9031 reinit_frame_cache_sfunc
,
9032 NULL
, /* FIXME: i18n: The distance searched for
9033 the start of a function is %s. */
9034 &setlist
, &showlist
);
9036 /* Allow the user to control whether the upper bits of 64-bit
9037 addresses should be zeroed. */
9038 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9039 &mask_address_var
, _("\
9040 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9041 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9042 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9043 allow GDB to determine the correct value."),
9044 NULL
, show_mask_address
,
9045 &setmipscmdlist
, &showmipscmdlist
);
9047 /* Allow the user to control the size of 32 bit registers within the
9048 raw remote packet. */
9049 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9050 &mips64_transfers_32bit_regs_p
, _("\
9051 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9053 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9055 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9056 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9057 64 bits for others. Use \"off\" to disable compatibility mode"),
9058 set_mips64_transfers_32bit_regs
,
9059 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9060 MIPS target that transfers 32-bit
9061 quantities is %s. */
9062 &setlist
, &showlist
);
9064 /* Debug this files internals. */
9065 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9067 Set mips debugging."), _("\
9068 Show mips debugging."), _("\
9069 When non-zero, mips specific debugging is enabled."),
9071 NULL
, /* FIXME: i18n: Mips debugging is
9073 &setdebuglist
, &showdebuglist
);