1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_default_stack_argsize
;
142 int gdb_target_is_mips64
;
143 int default_mask_address_p
;
145 enum gdb_osabi osabi
;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* XFER a value from the big/little/left end of the register.
177 Depending on the size of the value it might occupy the entire
178 register or just part of it. Make an allowance for this, aligning
179 things accordingly. */
182 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
183 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
186 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
188 /* Need to transfer the left or right part of the register, based on
189 the targets byte order. */
193 reg_offset
= REGISTER_RAW_SIZE (reg_num
) - length
;
195 case BFD_ENDIAN_LITTLE
:
198 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
202 internal_error (__FILE__
, __LINE__
, "bad switch");
205 fprintf_unfiltered (gdb_stderr
,
206 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
207 reg_num
, reg_offset
, buf_offset
, length
);
208 if (mips_debug
&& out
!= NULL
)
211 fprintf_unfiltered (gdb_stdlog
, "out ");
212 for (i
= 0; i
< length
; i
++)
213 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
216 regcache_raw_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
218 regcache_raw_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
219 if (mips_debug
&& in
!= NULL
)
222 fprintf_unfiltered (gdb_stdlog
, "in ");
223 for (i
= 0; i
< length
; i
++)
224 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
227 fprintf_unfiltered (gdb_stdlog
, "\n");
230 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
231 compatiblity mode. A return value of 1 means that we have
232 physical 64-bit registers, but should treat them as 32-bit registers. */
235 mips2_fp_compat (void)
237 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
239 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
243 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
244 in all the places we deal with FP registers. PR gdb/413. */
245 /* Otherwise check the FR bit in the status register - it controls
246 the FP compatiblity mode. If it is clear we are in compatibility
248 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
255 /* Indicate that the ABI makes use of double-precision registers
256 provided by the FPU (rather than combining pairs of registers to
257 form double-precision values). Do not use "TARGET_IS_MIPS64" to
258 determine if the ABI is using double-precision registers. See also
260 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
262 /* The amount of space reserved on the stack for registers. This is
263 different to MIPS_SAVED_REGSIZE as it determines the alignment of
264 data allocated after the registers have run out. */
266 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
268 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
270 static const char *mips_stack_argsize_string
= size_auto
;
273 mips_stack_argsize (void)
275 if (mips_stack_argsize_string
== size_auto
)
276 return MIPS_DEFAULT_STACK_ARGSIZE
;
277 else if (mips_stack_argsize_string
== size_64
)
279 else /* if (mips_stack_argsize_string == size_32) */
283 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
285 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
287 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
289 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
291 static void mips_print_register (int, int);
293 static mips_extra_func_info_t
294 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
296 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
298 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
300 int mips_set_processor_type (char *);
302 static void mips_show_processor_type_command (char *, int);
304 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
306 static mips_extra_func_info_t
307 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
309 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
310 mips_extra_func_info_t proc_desc
);
312 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
313 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
315 static struct type
*mips_float_register_type (void);
316 static struct type
*mips_double_register_type (void);
318 /* This value is the model of MIPS in use. It is derived from the value
319 of the PrID register. */
321 char *mips_processor_type
;
323 char *tmp_mips_processor_type
;
325 /* The list of available "set mips " and "show mips " commands */
327 static struct cmd_list_element
*setmipscmdlist
= NULL
;
328 static struct cmd_list_element
*showmipscmdlist
= NULL
;
330 /* A set of original names, to be used when restoring back to generic
331 registers from a specific set. */
333 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
334 char **mips_processor_reg_names
= mips_generic_reg_names
;
337 mips_register_name (int i
)
339 return mips_processor_reg_names
[i
];
342 /* Names of IDT R3041 registers. */
344 char *mips_r3041_reg_names
[] = {
345 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
346 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
347 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
348 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
349 "sr", "lo", "hi", "bad", "cause","pc",
350 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
351 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
352 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
353 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
354 "fsr", "fir", "fp", "",
355 "", "", "bus", "ccfg", "", "", "", "",
356 "", "", "port", "cmp", "", "", "epc", "prid",
359 /* Names of IDT R3051 registers. */
361 char *mips_r3051_reg_names
[] = {
362 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
363 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
364 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
365 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
366 "sr", "lo", "hi", "bad", "cause","pc",
367 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
368 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
369 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
370 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
371 "fsr", "fir", "fp", "",
372 "inx", "rand", "elo", "", "ctxt", "", "", "",
373 "", "", "ehi", "", "", "", "epc", "prid",
376 /* Names of IDT R3081 registers. */
378 char *mips_r3081_reg_names
[] = {
379 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
380 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
381 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
382 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
383 "sr", "lo", "hi", "bad", "cause","pc",
384 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
385 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
386 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
387 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
388 "fsr", "fir", "fp", "",
389 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
390 "", "", "ehi", "", "", "", "epc", "prid",
393 /* Names of LSI 33k registers. */
395 char *mips_lsi33k_reg_names
[] = {
396 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
397 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
398 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
399 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
400 "epc", "hi", "lo", "sr", "cause","badvaddr",
401 "dcic", "bpc", "bda", "", "", "", "", "",
402 "", "", "", "", "", "", "", "",
403 "", "", "", "", "", "", "", "",
404 "", "", "", "", "", "", "", "",
406 "", "", "", "", "", "", "", "",
407 "", "", "", "", "", "", "", "",
413 } mips_processor_type_table
[] = {
414 { "generic", mips_generic_reg_names
},
415 { "r3041", mips_r3041_reg_names
},
416 { "r3051", mips_r3051_reg_names
},
417 { "r3071", mips_r3081_reg_names
},
418 { "r3081", mips_r3081_reg_names
},
419 { "lsi33k", mips_lsi33k_reg_names
},
427 /* Table to translate MIPS16 register field to actual register number. */
428 static int mips16_to_32_reg
[8] =
429 {16, 17, 2, 3, 4, 5, 6, 7};
431 /* Heuristic_proc_start may hunt through the text section for a long
432 time across a 2400 baud serial line. Allows the user to limit this
435 static unsigned int heuristic_fence_post
= 0;
437 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
438 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
439 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
440 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
441 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
442 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
443 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
444 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
445 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
446 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
447 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
448 this will corrupt pdr.iline. Fortunately we don't use it. */
449 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
450 #define _PROC_MAGIC_ 0x0F0F0F0F
451 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
452 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
454 struct linked_proc_info
456 struct mips_extra_func_info info
;
457 struct linked_proc_info
*next
;
459 *linked_proc_desc_table
= NULL
;
462 mips_print_extra_frame_info (struct frame_info
*fi
)
466 && fi
->extra_info
->proc_desc
467 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
468 printf_filtered (" frame pointer is at %s+%s\n",
469 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
470 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
473 /* Number of bytes of storage in the actual machine representation for
474 register N. NOTE: This indirectly defines the register size
475 transfered by the GDB protocol. */
477 static int mips64_transfers_32bit_regs_p
= 0;
480 mips_register_raw_size (int reg_nr
)
482 if (mips64_transfers_32bit_regs_p
)
483 return REGISTER_VIRTUAL_SIZE (reg_nr
);
484 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
485 && FP_REGISTER_DOUBLE
)
486 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
493 /* Convert between RAW and VIRTUAL registers. The RAW register size
494 defines the remote-gdb packet. */
497 mips_register_convertible (int reg_nr
)
499 if (mips64_transfers_32bit_regs_p
)
502 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
506 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
507 char *raw_buf
, char *virt_buf
)
509 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
511 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
512 TYPE_LENGTH (virtual_type
));
516 TYPE_LENGTH (virtual_type
));
520 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
521 char *virt_buf
, char *raw_buf
)
523 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
524 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
525 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
527 TYPE_LENGTH (virtual_type
));
531 TYPE_LENGTH (virtual_type
));
535 mips_register_convert_to_type (int regnum
, struct type
*type
, char *buffer
)
537 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
538 && REGISTER_RAW_SIZE (regnum
) == 4
539 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
540 && TYPE_CODE(type
) == TYPE_CODE_FLT
541 && TYPE_LENGTH(type
) == 8)
544 memcpy (temp
, ((char *)(buffer
))+4, 4);
545 memcpy (((char *)(buffer
))+4, (buffer
), 4);
546 memcpy (((char *)(buffer
)), temp
, 4);
551 mips_register_convert_from_type (int regnum
, struct type
*type
, char *buffer
)
553 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
554 && REGISTER_RAW_SIZE (regnum
) == 4
555 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
556 && TYPE_CODE(type
) == TYPE_CODE_FLT
557 && TYPE_LENGTH(type
) == 8)
560 memcpy (temp
, ((char *)(buffer
))+4, 4);
561 memcpy (((char *)(buffer
))+4, (buffer
), 4);
562 memcpy (((char *)(buffer
)), temp
, 4);
566 /* Return the GDB type object for the "standard" data type
567 of data in register REG.
569 Note: kevinb/2002-08-01: The definition below should faithfully
570 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
571 definitions found in config/mips/tm-*.h. I'm concerned about
572 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
573 though. In some cases FP_REGNUM is in this range, and I doubt
574 that this code is correct for the 64-bit case. */
577 mips_register_virtual_type (int reg
)
579 if (FP0_REGNUM
<= reg
&& reg
< FP0_REGNUM
+ 32)
581 /* Floating point registers... */
582 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
583 return builtin_type_ieee_double_big
;
585 return builtin_type_ieee_double_little
;
587 else if (reg
== PS_REGNUM
/* CR */)
588 return builtin_type_uint32
;
589 else if (FCRCS_REGNUM
<= reg
&& reg
<= LAST_EMBED_REGNUM
)
590 return builtin_type_uint32
;
593 /* Everything else...
594 Return type appropriate for width of register. */
595 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_uint64
))
596 return builtin_type_uint64
;
598 return builtin_type_uint32
;
602 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
607 return ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
610 /* Should the upper word of 64-bit addresses be zeroed? */
611 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
614 mips_mask_address_p (void)
616 switch (mask_address_var
)
618 case AUTO_BOOLEAN_TRUE
:
620 case AUTO_BOOLEAN_FALSE
:
623 case AUTO_BOOLEAN_AUTO
:
624 return MIPS_DEFAULT_MASK_ADDRESS_P
;
626 internal_error (__FILE__
, __LINE__
,
627 "mips_mask_address_p: bad switch");
633 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
635 switch (mask_address_var
)
637 case AUTO_BOOLEAN_TRUE
:
638 printf_filtered ("The 32 bit mips address mask is enabled\n");
640 case AUTO_BOOLEAN_FALSE
:
641 printf_filtered ("The 32 bit mips address mask is disabled\n");
643 case AUTO_BOOLEAN_AUTO
:
644 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
645 mips_mask_address_p () ? "enabled" : "disabled");
648 internal_error (__FILE__
, __LINE__
,
649 "show_mask_address: bad switch");
654 /* Should call_function allocate stack space for a struct return? */
657 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
659 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
663 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
665 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
669 mips_o32_use_struct_convention (int gcc_p
, struct type
*type
)
671 return 1; /* Structures are returned by ref in extra arg0. */
674 /* Should call_function pass struct by reference?
675 For each architecture, structs are passed either by
676 value or by reference, depending on their size. */
679 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
681 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
682 int len
= TYPE_LENGTH (check_typedef (type
));
684 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
685 return (len
> MIPS_SAVED_REGSIZE
);
691 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
693 return 0; /* Assumption: N32/N64 never passes struct by ref. */
697 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
699 return 0; /* Assumption: O32/O64 never passes struct by ref. */
702 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
705 pc_is_mips16 (bfd_vma memaddr
)
707 struct minimal_symbol
*sym
;
709 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
710 if (IS_MIPS16_ADDR (memaddr
))
713 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
714 the high bit of the info field. Use this to decide if the function is
715 MIPS16 or normal MIPS. */
716 sym
= lookup_minimal_symbol_by_pc (memaddr
);
718 return MSYMBOL_IS_SPECIAL (sym
);
723 /* MIPS believes that the PC has a sign extended value. Perhaphs the
724 all registers should be sign extended for simplicity? */
727 mips_read_pc (ptid_t ptid
)
729 return read_signed_register_pid (PC_REGNUM
, ptid
);
732 /* This returns the PC of the first inst after the prologue. If we can't
733 find the prologue, then return 0. */
736 after_prologue (CORE_ADDR pc
,
737 mips_extra_func_info_t proc_desc
)
739 struct symtab_and_line sal
;
740 CORE_ADDR func_addr
, func_end
;
742 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
743 to read the stack pointer from the current machine state, because
744 the current machine state has nothing to do with the information
745 we need from the proc_desc; and the process may or may not exist
748 proc_desc
= find_proc_desc (pc
, NULL
, 0);
752 /* If function is frameless, then we need to do it the hard way. I
753 strongly suspect that frameless always means prologueless... */
754 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
755 && PROC_FRAME_OFFSET (proc_desc
) == 0)
759 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
760 return 0; /* Unknown */
762 sal
= find_pc_line (func_addr
, 0);
764 if (sal
.end
< func_end
)
767 /* The line after the prologue is after the end of the function. In this
768 case, tell the caller to find the prologue the hard way. */
773 /* Decode a MIPS32 instruction that saves a register in the stack, and
774 set the appropriate bit in the general register mask or float register mask
775 to indicate which register is saved. This is a helper function
776 for mips_find_saved_regs. */
779 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
780 unsigned long *float_mask
)
784 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
785 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
786 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
788 /* It might be possible to use the instruction to
789 find the offset, rather than the code below which
790 is based on things being in a certain order in the
791 frame, but figuring out what the instruction's offset
792 is relative to might be a little tricky. */
793 reg
= (inst
& 0x001f0000) >> 16;
794 *gen_mask
|= (1 << reg
);
796 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
797 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
798 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
801 reg
= ((inst
& 0x001f0000) >> 16);
802 *float_mask
|= (1 << reg
);
806 /* Decode a MIPS16 instruction that saves a register in the stack, and
807 set the appropriate bit in the general register or float register mask
808 to indicate which register is saved. This is a helper function
809 for mips_find_saved_regs. */
812 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
814 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
816 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
817 *gen_mask
|= (1 << reg
);
819 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
821 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
822 *gen_mask
|= (1 << reg
);
824 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
825 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
826 *gen_mask
|= (1 << RA_REGNUM
);
830 /* Fetch and return instruction from the specified location. If the PC
831 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
834 mips_fetch_instruction (CORE_ADDR addr
)
836 char buf
[MIPS_INSTLEN
];
840 if (pc_is_mips16 (addr
))
842 instlen
= MIPS16_INSTLEN
;
843 addr
= UNMAKE_MIPS16_ADDR (addr
);
846 instlen
= MIPS_INSTLEN
;
847 status
= read_memory_nobpt (addr
, buf
, instlen
);
849 memory_error (status
, addr
);
850 return extract_unsigned_integer (buf
, instlen
);
854 /* These the fields of 32 bit mips instructions */
855 #define mips32_op(x) (x >> 26)
856 #define itype_op(x) (x >> 26)
857 #define itype_rs(x) ((x >> 21) & 0x1f)
858 #define itype_rt(x) ((x >> 16) & 0x1f)
859 #define itype_immediate(x) (x & 0xffff)
861 #define jtype_op(x) (x >> 26)
862 #define jtype_target(x) (x & 0x03ffffff)
864 #define rtype_op(x) (x >> 26)
865 #define rtype_rs(x) ((x >> 21) & 0x1f)
866 #define rtype_rt(x) ((x >> 16) & 0x1f)
867 #define rtype_rd(x) ((x >> 11) & 0x1f)
868 #define rtype_shamt(x) ((x >> 6) & 0x1f)
869 #define rtype_funct(x) (x & 0x3f)
872 mips32_relative_offset (unsigned long inst
)
875 x
= itype_immediate (inst
);
876 if (x
& 0x8000) /* sign bit set */
878 x
|= 0xffff0000; /* sign extension */
884 /* Determine whate to set a single step breakpoint while considering
887 mips32_next_pc (CORE_ADDR pc
)
891 inst
= mips_fetch_instruction (pc
);
892 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
894 if (itype_op (inst
) >> 2 == 5)
895 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
897 op
= (itype_op (inst
) & 0x03);
912 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
913 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
915 int tf
= itype_rt (inst
) & 0x01;
916 int cnum
= itype_rt (inst
) >> 2;
917 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
918 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
920 if (((cond
>> cnum
) & 0x01) == tf
)
921 pc
+= mips32_relative_offset (inst
) + 4;
926 pc
+= 4; /* Not a branch, next instruction is easy */
929 { /* This gets way messy */
931 /* Further subdivide into SPECIAL, REGIMM and other */
932 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
934 case 0: /* SPECIAL */
935 op
= rtype_funct (inst
);
940 /* Set PC to that address */
941 pc
= read_signed_register (rtype_rs (inst
));
947 break; /* end SPECIAL */
950 op
= itype_rt (inst
); /* branch condition */
955 case 16: /* BLTZAL */
956 case 18: /* BLTZALL */
958 if (read_signed_register (itype_rs (inst
)) < 0)
959 pc
+= mips32_relative_offset (inst
) + 4;
961 pc
+= 8; /* after the delay slot */
965 case 17: /* BGEZAL */
966 case 19: /* BGEZALL */
967 greater_equal_branch
:
968 if (read_signed_register (itype_rs (inst
)) >= 0)
969 pc
+= mips32_relative_offset (inst
) + 4;
971 pc
+= 8; /* after the delay slot */
973 /* All of the other instructions in the REGIMM category */
978 break; /* end REGIMM */
983 reg
= jtype_target (inst
) << 2;
984 /* Upper four bits get never changed... */
985 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
988 /* FIXME case JALX : */
991 reg
= jtype_target (inst
) << 2;
992 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
993 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
995 break; /* The new PC will be alternate mode */
996 case 4: /* BEQ, BEQL */
998 if (read_signed_register (itype_rs (inst
)) ==
999 read_signed_register (itype_rt (inst
)))
1000 pc
+= mips32_relative_offset (inst
) + 4;
1004 case 5: /* BNE, BNEL */
1006 if (read_signed_register (itype_rs (inst
)) !=
1007 read_signed_register (itype_rt (inst
)))
1008 pc
+= mips32_relative_offset (inst
) + 4;
1012 case 6: /* BLEZ, BLEZL */
1014 if (read_signed_register (itype_rs (inst
) <= 0))
1015 pc
+= mips32_relative_offset (inst
) + 4;
1021 greater_branch
: /* BGTZ, BGTZL */
1022 if (read_signed_register (itype_rs (inst
) > 0))
1023 pc
+= mips32_relative_offset (inst
) + 4;
1030 } /* mips32_next_pc */
1032 /* Decoding the next place to set a breakpoint is irregular for the
1033 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1034 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1035 We dont want to set a single step instruction on the extend instruction
1039 /* Lots of mips16 instruction formats */
1040 /* Predicting jumps requires itype,ritype,i8type
1041 and their extensions extItype,extritype,extI8type
1043 enum mips16_inst_fmts
1045 itype
, /* 0 immediate 5,10 */
1046 ritype
, /* 1 5,3,8 */
1047 rrtype
, /* 2 5,3,3,5 */
1048 rritype
, /* 3 5,3,3,5 */
1049 rrrtype
, /* 4 5,3,3,3,2 */
1050 rriatype
, /* 5 5,3,3,1,4 */
1051 shifttype
, /* 6 5,3,3,3,2 */
1052 i8type
, /* 7 5,3,8 */
1053 i8movtype
, /* 8 5,3,3,5 */
1054 i8mov32rtype
, /* 9 5,3,5,3 */
1055 i64type
, /* 10 5,3,8 */
1056 ri64type
, /* 11 5,3,3,5 */
1057 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1058 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1059 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1060 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1061 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1062 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1063 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1064 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1065 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1066 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1068 /* I am heaping all the fields of the formats into one structure and
1069 then, only the fields which are involved in instruction extension */
1073 unsigned int regx
; /* Function in i8 type */
1078 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1079 for the bits which make up the immediatate extension. */
1082 extended_offset (unsigned int extension
)
1085 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1087 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1089 value
|= extension
& 0x01f; /* extract 4:0 */
1093 /* Only call this function if you know that this is an extendable
1094 instruction, It wont malfunction, but why make excess remote memory references?
1095 If the immediate operands get sign extended or somthing, do it after
1096 the extension is performed.
1098 /* FIXME: Every one of these cases needs to worry about sign extension
1099 when the offset is to be used in relative addressing */
1103 fetch_mips_16 (CORE_ADDR pc
)
1106 pc
&= 0xfffffffe; /* clear the low order bit */
1107 target_read_memory (pc
, buf
, 2);
1108 return extract_unsigned_integer (buf
, 2);
1112 unpack_mips16 (CORE_ADDR pc
,
1113 unsigned int extension
,
1115 enum mips16_inst_fmts insn_format
,
1116 struct upk_mips16
*upk
)
1121 switch (insn_format
)
1128 value
= extended_offset (extension
);
1129 value
= value
<< 11; /* rom for the original value */
1130 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1134 value
= inst
& 0x7ff;
1135 /* FIXME : Consider sign extension */
1144 { /* A register identifier and an offset */
1145 /* Most of the fields are the same as I type but the
1146 immediate value is of a different length */
1150 value
= extended_offset (extension
);
1151 value
= value
<< 8; /* from the original instruction */
1152 value
|= inst
& 0xff; /* eleven bits from instruction */
1153 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1154 if (value
& 0x4000) /* test the sign bit , bit 26 */
1156 value
&= ~0x3fff; /* remove the sign bit */
1162 value
= inst
& 0xff; /* 8 bits */
1163 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1164 /* FIXME: Do sign extension , this format needs it */
1165 if (value
& 0x80) /* THIS CONFUSES ME */
1167 value
&= 0xef; /* remove the sign bit */
1177 unsigned long value
;
1178 unsigned int nexthalf
;
1179 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1180 value
= value
<< 16;
1181 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1189 internal_error (__FILE__
, __LINE__
,
1192 upk
->offset
= offset
;
1199 add_offset_16 (CORE_ADDR pc
, int offset
)
1201 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1205 extended_mips16_next_pc (CORE_ADDR pc
,
1206 unsigned int extension
,
1209 int op
= (insn
>> 11);
1212 case 2: /* Branch */
1215 struct upk_mips16 upk
;
1216 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1217 offset
= upk
.offset
;
1223 pc
+= (offset
<< 1) + 2;
1226 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1228 struct upk_mips16 upk
;
1229 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1230 pc
= add_offset_16 (pc
, upk
.offset
);
1231 if ((insn
>> 10) & 0x01) /* Exchange mode */
1232 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1239 struct upk_mips16 upk
;
1241 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1242 reg
= read_signed_register (upk
.regx
);
1244 pc
+= (upk
.offset
<< 1) + 2;
1251 struct upk_mips16 upk
;
1253 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1254 reg
= read_signed_register (upk
.regx
);
1256 pc
+= (upk
.offset
<< 1) + 2;
1261 case 12: /* I8 Formats btez btnez */
1263 struct upk_mips16 upk
;
1265 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1266 /* upk.regx contains the opcode */
1267 reg
= read_signed_register (24); /* Test register is 24 */
1268 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1269 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1270 /* pc = add_offset_16(pc,upk.offset) ; */
1271 pc
+= (upk
.offset
<< 1) + 2;
1276 case 29: /* RR Formats JR, JALR, JALR-RA */
1278 struct upk_mips16 upk
;
1279 /* upk.fmt = rrtype; */
1284 upk
.regx
= (insn
>> 8) & 0x07;
1285 upk
.regy
= (insn
>> 5) & 0x07;
1293 break; /* Function return instruction */
1299 break; /* BOGUS Guess */
1301 pc
= read_signed_register (reg
);
1308 /* This is an instruction extension. Fetch the real instruction
1309 (which follows the extension) and decode things based on
1313 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1326 mips16_next_pc (CORE_ADDR pc
)
1328 unsigned int insn
= fetch_mips_16 (pc
);
1329 return extended_mips16_next_pc (pc
, 0, insn
);
1332 /* The mips_next_pc function supports single_step when the remote
1333 target monitor or stub is not developed enough to do a single_step.
1334 It works by decoding the current instruction and predicting where a
1335 branch will go. This isnt hard because all the data is available.
1336 The MIPS32 and MIPS16 variants are quite different */
1338 mips_next_pc (CORE_ADDR pc
)
1341 return mips16_next_pc (pc
);
1343 return mips32_next_pc (pc
);
1346 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1349 Note: kevinb/2002-08-09: The only caller of this function is (and
1350 should remain) mips_frame_init_saved_regs(). In fact,
1351 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1352 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1353 functions should really be combined and now that there is only one
1354 caller, it should be straightforward. (Watch out for multiple returns
1358 mips_find_saved_regs (struct frame_info
*fci
)
1361 CORE_ADDR reg_position
;
1362 /* r0 bit means kernel trap */
1364 /* What registers have been saved? Bitmasks. */
1365 unsigned long gen_mask
, float_mask
;
1366 mips_extra_func_info_t proc_desc
;
1369 frame_saved_regs_zalloc (fci
);
1371 /* If it is the frame for sigtramp, the saved registers are located
1372 in a sigcontext structure somewhere on the stack.
1373 If the stack layout for sigtramp changes we might have to change these
1374 constants and the companion fixup_sigtramp in mdebugread.c */
1375 #ifndef SIGFRAME_BASE
1376 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1377 above the sigtramp frame. */
1378 #define SIGFRAME_BASE MIPS_REGSIZE
1379 /* FIXME! Are these correct?? */
1380 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1381 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1382 #define SIGFRAME_FPREGSAVE_OFF \
1383 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1385 #ifndef SIGFRAME_REG_SIZE
1386 /* FIXME! Is this correct?? */
1387 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1389 if (fci
->signal_handler_caller
)
1391 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1393 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1394 + ireg
* SIGFRAME_REG_SIZE
;
1395 fci
->saved_regs
[ireg
] = reg_position
;
1397 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1399 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1400 + ireg
* SIGFRAME_REG_SIZE
;
1401 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1403 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1407 proc_desc
= fci
->extra_info
->proc_desc
;
1408 if (proc_desc
== NULL
)
1409 /* I'm not sure how/whether this can happen. Normally when we can't
1410 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1411 and set the saved_regs right away. */
1414 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1415 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1416 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1418 if ( /* In any frame other than the innermost or a frame interrupted by
1419 a signal, we assume that all registers have been saved.
1420 This assumes that all register saves in a function happen before
1421 the first function call. */
1422 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1424 /* In a dummy frame we know exactly where things are saved. */
1425 && !PROC_DESC_IS_DUMMY (proc_desc
)
1427 /* Don't bother unless we are inside a function prologue. Outside the
1428 prologue, we know where everything is. */
1430 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1432 /* Not sure exactly what kernel_trap means, but if it means
1433 the kernel saves the registers without a prologue doing it,
1434 we better not examine the prologue to see whether registers
1435 have been saved yet. */
1438 /* We need to figure out whether the registers that the proc_desc
1439 claims are saved have been saved yet. */
1443 /* Bitmasks; set if we have found a save for the register. */
1444 unsigned long gen_save_found
= 0;
1445 unsigned long float_save_found
= 0;
1448 /* If the address is odd, assume this is MIPS16 code. */
1449 addr
= PROC_LOW_ADDR (proc_desc
);
1450 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1452 /* Scan through this function's instructions preceding the current
1453 PC, and look for those that save registers. */
1454 while (addr
< fci
->pc
)
1456 inst
= mips_fetch_instruction (addr
);
1457 if (pc_is_mips16 (addr
))
1458 mips16_decode_reg_save (inst
, &gen_save_found
);
1460 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1463 gen_mask
= gen_save_found
;
1464 float_mask
= float_save_found
;
1467 /* Fill in the offsets for the registers which gen_mask says
1469 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1470 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1471 if (gen_mask
& 0x80000000)
1473 fci
->saved_regs
[ireg
] = reg_position
;
1474 reg_position
-= MIPS_SAVED_REGSIZE
;
1477 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1478 of that normally used by gcc. Therefore, we have to fetch the first
1479 instruction of the function, and if it's an entry instruction that
1480 saves $s0 or $s1, correct their saved addresses. */
1481 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1483 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1484 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1487 int sreg_count
= (inst
>> 6) & 3;
1489 /* Check if the ra register was pushed on the stack. */
1490 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1492 reg_position
-= MIPS_SAVED_REGSIZE
;
1494 /* Check if the s0 and s1 registers were pushed on the stack. */
1495 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1497 fci
->saved_regs
[reg
] = reg_position
;
1498 reg_position
-= MIPS_SAVED_REGSIZE
;
1503 /* Fill in the offsets for the registers which float_mask says
1505 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1507 /* Apparently, the freg_offset gives the offset to the first 64 bit
1510 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1511 designates the first saved 64 bit register.
1513 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1514 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1515 FREG_OFFSET, designates the address of the lower register of the
1516 register pair. Adjust the offset so that it designates the upper
1517 register of the pair -- i.e., the address of the first saved 32
1520 if (MIPS_SAVED_REGSIZE
== 4)
1521 reg_position
+= MIPS_SAVED_REGSIZE
;
1523 /* Fill in the offsets for the float registers which float_mask says
1525 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1526 if (float_mask
& 0x80000000)
1528 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1529 reg_position
-= MIPS_SAVED_REGSIZE
;
1532 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1535 /* Set up the 'saved_regs' array. This is a data structure containing
1536 the addresses on the stack where each register has been saved, for
1537 each stack frame. Registers that have not been saved will have
1538 zero here. The stack pointer register is special: rather than the
1539 address where the stack register has been saved, saved_regs[SP_REGNUM]
1540 will have the actual value of the previous frame's stack register. */
1543 mips_frame_init_saved_regs (struct frame_info
*frame
)
1545 if (frame
->saved_regs
== NULL
)
1547 mips_find_saved_regs (frame
);
1549 frame
->saved_regs
[SP_REGNUM
] = frame
->frame
;
1553 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1555 for (; fi
; fi
= fi
->next
)
1557 /* We have to get the saved sp from the sigcontext
1558 if it is a signal handler frame. */
1559 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1563 if (fi
->saved_regs
== NULL
)
1564 FRAME_INIT_SAVED_REGS (fi
);
1565 if (fi
->saved_regs
[regno
])
1566 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1569 return read_signed_register (regno
);
1572 /* mips_addr_bits_remove - remove useless address bits */
1575 mips_addr_bits_remove (CORE_ADDR addr
)
1577 if (GDB_TARGET_IS_MIPS64
)
1579 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1581 /* This hack is a work-around for existing boards using
1582 PMON, the simulator, and any other 64-bit targets that
1583 doesn't have true 64-bit addressing. On these targets,
1584 the upper 32 bits of addresses are ignored by the
1585 hardware. Thus, the PC or SP are likely to have been
1586 sign extended to all 1s by instruction sequences that
1587 load 32-bit addresses. For example, a typical piece of
1588 code that loads an address is this:
1589 lui $r2, <upper 16 bits>
1590 ori $r2, <lower 16 bits>
1591 But the lui sign-extends the value such that the upper 32
1592 bits may be all 1s. The workaround is simply to mask off
1593 these bits. In the future, gcc may be changed to support
1594 true 64-bit addressing, and this masking will have to be
1596 addr
&= (CORE_ADDR
) 0xffffffff;
1599 else if (mips_mask_address_p ())
1601 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1602 masking off bits, instead, the actual target should be asking
1603 for the address to be converted to a valid pointer. */
1604 /* Even when GDB is configured for some 32-bit targets
1605 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1606 so CORE_ADDR is 64 bits. So we still have to mask off
1607 useless bits from addresses. */
1608 addr
&= (CORE_ADDR
) 0xffffffff;
1613 /* mips_software_single_step() is called just before we want to resume
1614 the inferior, if we want to single-step it but there is no hardware
1615 or kernel single-step support (MIPS on GNU/Linux for example). We find
1616 the target of the coming instruction and breakpoint it.
1618 single_step is also called just after the inferior stops. If we had
1619 set up a simulated single-step, we undo our damage. */
1622 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1624 static CORE_ADDR next_pc
;
1625 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1626 static binsn_quantum break_mem
;
1629 if (insert_breakpoints_p
)
1631 pc
= read_register (PC_REGNUM
);
1632 next_pc
= mips_next_pc (pc
);
1634 target_insert_breakpoint (next_pc
, break_mem
);
1637 target_remove_breakpoint (next_pc
, break_mem
);
1641 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1645 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1646 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1647 tmp
= mips_skip_stub (pc
);
1648 prev
->pc
= tmp
? tmp
: pc
;
1653 mips_frame_saved_pc (struct frame_info
*frame
)
1656 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1657 /* We have to get the saved pc from the sigcontext
1658 if it is a signal handler frame. */
1659 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1660 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1662 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1663 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1665 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1667 return ADDR_BITS_REMOVE (saved_pc
);
1670 static struct mips_extra_func_info temp_proc_desc
;
1671 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1673 /* Set a register's saved stack address in temp_saved_regs. If an address
1674 has already been set for this register, do nothing; this way we will
1675 only recognize the first save of a given register in a function prologue.
1676 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1679 set_reg_offset (int regno
, CORE_ADDR offset
)
1681 if (temp_saved_regs
[regno
] == 0)
1682 temp_saved_regs
[regno
] = offset
;
1686 /* Test whether the PC points to the return instruction at the
1687 end of a function. */
1690 mips_about_to_return (CORE_ADDR pc
)
1692 if (pc_is_mips16 (pc
))
1693 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1694 generates a "jr $ra"; other times it generates code to load
1695 the return address from the stack to an accessible register (such
1696 as $a3), then a "jr" using that register. This second case
1697 is almost impossible to distinguish from an indirect jump
1698 used for switch statements, so we don't even try. */
1699 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1701 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1705 /* This fencepost looks highly suspicious to me. Removing it also
1706 seems suspicious as it could affect remote debugging across serial
1710 heuristic_proc_start (CORE_ADDR pc
)
1717 pc
= ADDR_BITS_REMOVE (pc
);
1719 fence
= start_pc
- heuristic_fence_post
;
1723 if (heuristic_fence_post
== UINT_MAX
1724 || fence
< VM_MIN_ADDRESS
)
1725 fence
= VM_MIN_ADDRESS
;
1727 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1729 /* search back for previous return */
1730 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1731 if (start_pc
< fence
)
1733 /* It's not clear to me why we reach this point when
1734 stop_soon_quietly, but with this test, at least we
1735 don't print out warnings for every child forked (eg, on
1736 decstation). 22apr93 rich@cygnus.com. */
1737 if (!stop_soon_quietly
)
1739 static int blurb_printed
= 0;
1741 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1746 /* This actually happens frequently in embedded
1747 development, when you first connect to a board
1748 and your stack pointer and pc are nowhere in
1749 particular. This message needs to give people
1750 in that situation enough information to
1751 determine that it's no big deal. */
1752 printf_filtered ("\n\
1753 GDB is unable to find the start of the function at 0x%s\n\
1754 and thus can't determine the size of that function's stack frame.\n\
1755 This means that GDB may be unable to access that stack frame, or\n\
1756 the frames below it.\n\
1757 This problem is most likely caused by an invalid program counter or\n\
1759 However, if you think GDB should simply search farther back\n\
1760 from 0x%s for code which looks like the beginning of a\n\
1761 function, you can increase the range of the search using the `set\n\
1762 heuristic-fence-post' command.\n",
1763 paddr_nz (pc
), paddr_nz (pc
));
1770 else if (pc_is_mips16 (start_pc
))
1772 unsigned short inst
;
1774 /* On MIPS16, any one of the following is likely to be the
1775 start of a function:
1779 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1780 inst
= mips_fetch_instruction (start_pc
);
1781 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1782 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1783 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1784 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1786 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1787 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1792 else if (mips_about_to_return (start_pc
))
1794 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1801 /* Fetch the immediate value from a MIPS16 instruction.
1802 If the previous instruction was an EXTEND, use it to extend
1803 the upper bits of the immediate value. This is a helper function
1804 for mips16_heuristic_proc_desc. */
1807 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1808 unsigned short inst
, /* current instruction */
1809 int nbits
, /* number of bits in imm field */
1810 int scale
, /* scale factor to be applied to imm */
1811 int is_signed
) /* is the imm field signed? */
1815 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1817 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1818 if (offset
& 0x8000) /* check for negative extend */
1819 offset
= 0 - (0x10000 - (offset
& 0xffff));
1820 return offset
| (inst
& 0x1f);
1824 int max_imm
= 1 << nbits
;
1825 int mask
= max_imm
- 1;
1826 int sign_bit
= max_imm
>> 1;
1828 offset
= inst
& mask
;
1829 if (is_signed
&& (offset
& sign_bit
))
1830 offset
= 0 - (max_imm
- offset
);
1831 return offset
* scale
;
1836 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1837 stream from start_pc to limit_pc. */
1840 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1841 struct frame_info
*next_frame
, CORE_ADDR sp
)
1844 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1845 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1846 unsigned inst
= 0; /* current instruction */
1847 unsigned entry_inst
= 0; /* the entry instruction */
1850 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1851 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1853 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1855 /* Save the previous instruction. If it's an EXTEND, we'll extract
1856 the immediate offset extension from it in mips16_get_imm. */
1859 /* Fetch and decode the instruction. */
1860 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1861 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1862 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1864 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1865 if (offset
< 0) /* negative stack adjustment? */
1866 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1868 /* Exit loop if a positive stack adjustment is found, which
1869 usually means that the stack cleanup code in the function
1870 epilogue is reached. */
1873 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1875 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1876 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1877 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1878 set_reg_offset (reg
, sp
+ offset
);
1880 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1882 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1883 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1884 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1885 set_reg_offset (reg
, sp
+ offset
);
1887 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1889 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1890 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1891 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1893 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1895 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1896 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1897 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1899 else if (inst
== 0x673d) /* move $s1, $sp */
1902 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1904 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1906 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1907 frame_addr
= sp
+ offset
;
1908 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1909 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1911 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1913 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1914 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1915 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1916 set_reg_offset (reg
, frame_addr
+ offset
);
1918 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1920 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1921 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1922 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1923 set_reg_offset (reg
, frame_addr
+ offset
);
1925 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1926 entry_inst
= inst
; /* save for later processing */
1927 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1928 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1931 /* The entry instruction is typically the first instruction in a function,
1932 and it stores registers at offsets relative to the value of the old SP
1933 (before the prologue). But the value of the sp parameter to this
1934 function is the new SP (after the prologue has been executed). So we
1935 can't calculate those offsets until we've seen the entire prologue,
1936 and can calculate what the old SP must have been. */
1937 if (entry_inst
!= 0)
1939 int areg_count
= (entry_inst
>> 8) & 7;
1940 int sreg_count
= (entry_inst
>> 6) & 3;
1942 /* The entry instruction always subtracts 32 from the SP. */
1943 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1945 /* Now we can calculate what the SP must have been at the
1946 start of the function prologue. */
1947 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1949 /* Check if a0-a3 were saved in the caller's argument save area. */
1950 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1952 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1953 set_reg_offset (reg
, sp
+ offset
);
1954 offset
+= MIPS_SAVED_REGSIZE
;
1957 /* Check if the ra register was pushed on the stack. */
1959 if (entry_inst
& 0x20)
1961 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1962 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1963 offset
-= MIPS_SAVED_REGSIZE
;
1966 /* Check if the s0 and s1 registers were pushed on the stack. */
1967 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1969 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1970 set_reg_offset (reg
, sp
+ offset
);
1971 offset
-= MIPS_SAVED_REGSIZE
;
1977 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1978 struct frame_info
*next_frame
, CORE_ADDR sp
)
1981 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1983 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1984 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1985 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1986 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1988 unsigned long inst
, high_word
, low_word
;
1991 /* Fetch the instruction. */
1992 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1994 /* Save some code by pre-extracting some useful fields. */
1995 high_word
= (inst
>> 16) & 0xffff;
1996 low_word
= inst
& 0xffff;
1997 reg
= high_word
& 0x1f;
1999 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2000 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2001 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2003 if (low_word
& 0x8000) /* negative stack adjustment? */
2004 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2006 /* Exit loop if a positive stack adjustment is found, which
2007 usually means that the stack cleanup code in the function
2008 epilogue is reached. */
2011 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2013 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2014 set_reg_offset (reg
, sp
+ low_word
);
2016 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2018 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2019 but the register size used is only 32 bits. Make the address
2020 for the saved register point to the lower 32 bits. */
2021 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2022 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
2024 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2026 /* Old gcc frame, r30 is virtual frame pointer. */
2027 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2028 frame_addr
= sp
+ low_word
;
2029 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2031 unsigned alloca_adjust
;
2032 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2033 frame_addr
= read_next_frame_reg (next_frame
, 30);
2034 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2035 if (alloca_adjust
> 0)
2037 /* FP > SP + frame_size. This may be because
2038 * of an alloca or somethings similar.
2039 * Fix sp to "pre-alloca" value, and try again.
2041 sp
+= alloca_adjust
;
2046 /* move $30,$sp. With different versions of gas this will be either
2047 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2048 Accept any one of these. */
2049 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2051 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2052 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2054 unsigned alloca_adjust
;
2055 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2056 frame_addr
= read_next_frame_reg (next_frame
, 30);
2057 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2058 if (alloca_adjust
> 0)
2060 /* FP > SP + frame_size. This may be because
2061 * of an alloca or somethings similar.
2062 * Fix sp to "pre-alloca" value, and try again.
2064 sp
+= alloca_adjust
;
2069 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2071 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2072 set_reg_offset (reg
, frame_addr
+ low_word
);
2077 static mips_extra_func_info_t
2078 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2079 struct frame_info
*next_frame
, int cur_frame
)
2084 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
2090 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2091 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2092 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2093 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2094 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2096 if (start_pc
+ 200 < limit_pc
)
2097 limit_pc
= start_pc
+ 200;
2098 if (pc_is_mips16 (start_pc
))
2099 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2101 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2102 return &temp_proc_desc
;
2105 struct mips_objfile_private
2111 /* Global used to communicate between non_heuristic_proc_desc and
2112 compare_pdr_entries within qsort (). */
2113 static bfd
*the_bfd
;
2116 compare_pdr_entries (const void *a
, const void *b
)
2118 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2119 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2123 else if (lhs
== rhs
)
2129 static mips_extra_func_info_t
2130 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2132 CORE_ADDR startaddr
;
2133 mips_extra_func_info_t proc_desc
;
2134 struct block
*b
= block_for_pc (pc
);
2136 struct obj_section
*sec
;
2137 struct mips_objfile_private
*priv
;
2139 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
2142 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2144 *addrptr
= startaddr
;
2148 sec
= find_pc_section (pc
);
2151 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2153 /* Search the ".pdr" section generated by GAS. This includes most of
2154 the information normally found in ECOFF PDRs. */
2156 the_bfd
= sec
->objfile
->obfd
;
2158 && (the_bfd
->format
== bfd_object
2159 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2160 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2162 /* Right now GAS only outputs the address as a four-byte sequence.
2163 This means that we should not bother with this method on 64-bit
2164 targets (until that is fixed). */
2166 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2167 sizeof (struct mips_objfile_private
));
2169 sec
->objfile
->obj_private
= priv
;
2171 else if (priv
== NULL
)
2175 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2176 sizeof (struct mips_objfile_private
));
2178 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2181 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2182 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2184 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2185 priv
->contents
, 0, priv
->size
);
2187 /* In general, the .pdr section is sorted. However, in the
2188 presence of multiple code sections (and other corner cases)
2189 it can become unsorted. Sort it so that we can use a faster
2191 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2196 sec
->objfile
->obj_private
= priv
;
2200 if (priv
->size
!= 0)
2206 high
= priv
->size
/ 32;
2212 mid
= (low
+ high
) / 2;
2214 ptr
= priv
->contents
+ mid
* 32;
2215 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2216 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2217 SECT_OFF_TEXT (sec
->objfile
));
2218 if (pdr_pc
== startaddr
)
2220 if (pdr_pc
> startaddr
)
2225 while (low
!= high
);
2229 struct symbol
*sym
= find_pc_function (pc
);
2231 /* Fill in what we need of the proc_desc. */
2232 proc_desc
= (mips_extra_func_info_t
)
2233 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2234 sizeof (struct mips_extra_func_info
));
2235 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2237 /* Only used for dummy frames. */
2238 PROC_HIGH_ADDR (proc_desc
) = 0;
2240 PROC_FRAME_OFFSET (proc_desc
)
2241 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2242 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2244 PROC_FRAME_ADJUST (proc_desc
) = 0;
2245 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2247 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2249 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2251 PROC_FREG_OFFSET (proc_desc
)
2252 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2253 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2255 proc_desc
->pdr
.isym
= (long) sym
;
2265 if (startaddr
> BLOCK_START (b
))
2267 /* This is the "pathological" case referred to in a comment in
2268 print_frame_info. It might be better to move this check into
2273 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2275 /* If we never found a PDR for this function in symbol reading, then
2276 examine prologues to find the information. */
2279 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2280 if (PROC_FRAME_REG (proc_desc
) == -1)
2290 static mips_extra_func_info_t
2291 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2293 mips_extra_func_info_t proc_desc
;
2294 CORE_ADDR startaddr
;
2296 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2300 /* IF this is the topmost frame AND
2301 * (this proc does not have debugging information OR
2302 * the PC is in the procedure prologue)
2303 * THEN create a "heuristic" proc_desc (by analyzing
2304 * the actual code) to replace the "official" proc_desc.
2306 if (next_frame
== NULL
)
2308 struct symtab_and_line val
;
2309 struct symbol
*proc_symbol
=
2310 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2314 val
= find_pc_line (BLOCK_START
2315 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2317 val
.pc
= val
.end
? val
.end
: pc
;
2319 if (!proc_symbol
|| pc
< val
.pc
)
2321 mips_extra_func_info_t found_heuristic
=
2322 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2323 pc
, next_frame
, cur_frame
);
2324 if (found_heuristic
)
2325 proc_desc
= found_heuristic
;
2331 /* Is linked_proc_desc_table really necessary? It only seems to be used
2332 by procedure call dummys. However, the procedures being called ought
2333 to have their own proc_descs, and even if they don't,
2334 heuristic_proc_desc knows how to create them! */
2336 register struct linked_proc_info
*link
;
2338 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2339 if (PROC_LOW_ADDR (&link
->info
) <= pc
2340 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2344 startaddr
= heuristic_proc_start (pc
);
2347 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2353 get_frame_pointer (struct frame_info
*frame
,
2354 mips_extra_func_info_t proc_desc
)
2356 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
2357 PROC_FRAME_REG (proc_desc
)) +
2358 PROC_FRAME_OFFSET (proc_desc
) -
2359 PROC_FRAME_ADJUST (proc_desc
));
2362 mips_extra_func_info_t cached_proc_desc
;
2365 mips_frame_chain (struct frame_info
*frame
)
2367 mips_extra_func_info_t proc_desc
;
2369 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2371 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2374 /* Check if the PC is inside a call stub. If it is, fetch the
2375 PC of the caller of that stub. */
2376 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2379 /* Look up the procedure descriptor for this PC. */
2380 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2384 cached_proc_desc
= proc_desc
;
2386 /* If no frame pointer and frame size is zero, we must be at end
2387 of stack (or otherwise hosed). If we don't check frame size,
2388 we loop forever if we see a zero size frame. */
2389 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2390 && PROC_FRAME_OFFSET (proc_desc
) == 0
2391 /* The previous frame from a sigtramp frame might be frameless
2392 and have frame size zero. */
2393 && !frame
->signal_handler_caller
2394 /* Check if this is a call dummy frame. */
2395 && frame
->pc
!= mips_call_dummy_address ())
2398 return get_frame_pointer (frame
, proc_desc
);
2402 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2406 /* Use proc_desc calculated in frame_chain */
2407 mips_extra_func_info_t proc_desc
=
2408 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2410 fci
->extra_info
= (struct frame_extra_info
*)
2411 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2413 fci
->saved_regs
= NULL
;
2414 fci
->extra_info
->proc_desc
=
2415 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2418 /* Fixup frame-pointer - only needed for top frame */
2419 /* This may not be quite right, if proc has a real frame register.
2420 Get the value of the frame relative sp, procedure might have been
2421 interrupted by a signal at it's very start. */
2422 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2423 && !PROC_DESC_IS_DUMMY (proc_desc
))
2424 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2426 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2428 if (proc_desc
== &temp_proc_desc
)
2432 /* Do not set the saved registers for a sigtramp frame,
2433 mips_find_saved_registers will do that for us.
2434 We can't use fci->signal_handler_caller, it is not yet set. */
2435 find_pc_partial_function (fci
->pc
, &name
,
2436 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2437 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2439 frame_saved_regs_zalloc (fci
);
2440 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2441 fci
->saved_regs
[PC_REGNUM
]
2442 = fci
->saved_regs
[RA_REGNUM
];
2443 /* Set value of previous frame's stack pointer. Remember that
2444 saved_regs[SP_REGNUM] is special in that it contains the
2445 value of the stack pointer register. The other saved_regs
2446 values are addresses (in the inferior) at which a given
2447 register's value may be found. */
2448 fci
->saved_regs
[SP_REGNUM
] = fci
->frame
;
2452 /* hack: if argument regs are saved, guess these contain args */
2453 /* assume we can't tell how many args for now */
2454 fci
->extra_info
->num_args
= -1;
2455 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2457 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2459 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2466 /* MIPS stack frames are almost impenetrable. When execution stops,
2467 we basically have to look at symbol information for the function
2468 that we stopped in, which tells us *which* register (if any) is
2469 the base of the frame pointer, and what offset from that register
2470 the frame itself is at.
2472 This presents a problem when trying to examine a stack in memory
2473 (that isn't executing at the moment), using the "frame" command. We
2474 don't have a PC, nor do we have any registers except SP.
2476 This routine takes two arguments, SP and PC, and tries to make the
2477 cached frames look as if these two arguments defined a frame on the
2478 cache. This allows the rest of info frame to extract the important
2479 arguments without difficulty. */
2482 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2485 error ("MIPS frame specifications require two arguments: sp and pc");
2487 return create_new_frame (argv
[0], argv
[1]);
2490 /* According to the current ABI, should the type be passed in a
2491 floating-point register (assuming that there is space)? When there
2492 is no FPU, FP are not even considered as possibile candidates for
2493 FP registers and, consequently this returns false - forces FP
2494 arguments into integer registers. */
2497 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2499 return ((typecode
== TYPE_CODE_FLT
2501 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2502 && TYPE_NFIELDS (arg_type
) == 1
2503 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2504 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2507 /* On o32, argument passing in GPRs depends on the alignment of the type being
2508 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2511 mips_type_needs_double_align (struct type
*type
)
2513 enum type_code typecode
= TYPE_CODE (type
);
2515 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2517 else if (typecode
== TYPE_CODE_STRUCT
)
2519 if (TYPE_NFIELDS (type
) < 1)
2521 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2523 else if (typecode
== TYPE_CODE_UNION
)
2527 n
= TYPE_NFIELDS (type
);
2528 for (i
= 0; i
< n
; i
++)
2529 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2536 /* Macros to round N up or down to the next A boundary;
2537 A must be a power of two. */
2539 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2540 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2543 mips_eabi_push_arguments (int nargs
,
2544 struct value
**args
,
2547 CORE_ADDR struct_addr
)
2553 int stack_offset
= 0;
2555 /* First ensure that the stack and structure return address (if any)
2556 are properly aligned. The stack has to be at least 64-bit
2557 aligned even on 32-bit machines, because doubles must be 64-bit
2558 aligned. For n32 and n64, stack frames need to be 128-bit
2559 aligned, so we round to this widest known alignment. */
2561 sp
= ROUND_DOWN (sp
, 16);
2562 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2564 /* Now make space on the stack for the args. We allocate more
2565 than necessary for EABI, because the first few arguments are
2566 passed in registers, but that's OK. */
2567 for (argnum
= 0; argnum
< nargs
; argnum
++)
2568 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2569 MIPS_STACK_ARGSIZE
);
2570 sp
-= ROUND_UP (len
, 16);
2573 fprintf_unfiltered (gdb_stdlog
,
2574 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2575 paddr_nz (sp
), ROUND_UP (len
, 16));
2577 /* Initialize the integer and float register pointers. */
2579 float_argreg
= FPA0_REGNUM
;
2581 /* The struct_return pointer occupies the first parameter-passing reg. */
2585 fprintf_unfiltered (gdb_stdlog
,
2586 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2587 argreg
, paddr_nz (struct_addr
));
2588 write_register (argreg
++, struct_addr
);
2591 /* Now load as many as possible of the first arguments into
2592 registers, and push the rest onto the stack. Loop thru args
2593 from first to last. */
2594 for (argnum
= 0; argnum
< nargs
; argnum
++)
2597 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2598 struct value
*arg
= args
[argnum
];
2599 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2600 int len
= TYPE_LENGTH (arg_type
);
2601 enum type_code typecode
= TYPE_CODE (arg_type
);
2604 fprintf_unfiltered (gdb_stdlog
,
2605 "mips_eabi_push_arguments: %d len=%d type=%d",
2606 argnum
+ 1, len
, (int) typecode
);
2608 /* The EABI passes structures that do not fit in a register by
2610 if (len
> MIPS_SAVED_REGSIZE
2611 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2613 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2614 typecode
= TYPE_CODE_PTR
;
2615 len
= MIPS_SAVED_REGSIZE
;
2618 fprintf_unfiltered (gdb_stdlog
, " push");
2621 val
= (char *) VALUE_CONTENTS (arg
);
2623 /* 32-bit ABIs always start floating point arguments in an
2624 even-numbered floating point register. Round the FP register
2625 up before the check to see if there are any FP registers
2626 left. Non MIPS_EABI targets also pass the FP in the integer
2627 registers so also round up normal registers. */
2628 if (!FP_REGISTER_DOUBLE
2629 && fp_register_arg_p (typecode
, arg_type
))
2631 if ((float_argreg
& 1))
2635 /* Floating point arguments passed in registers have to be
2636 treated specially. On 32-bit architectures, doubles
2637 are passed in register pairs; the even register gets
2638 the low word, and the odd register gets the high word.
2639 On non-EABI processors, the first two floating point arguments are
2640 also copied to general registers, because MIPS16 functions
2641 don't use float registers for arguments. This duplication of
2642 arguments in general registers can't hurt non-MIPS16 functions
2643 because those registers are normally skipped. */
2644 /* MIPS_EABI squeezes a struct that contains a single floating
2645 point value into an FP register instead of pushing it onto the
2647 if (fp_register_arg_p (typecode
, arg_type
)
2648 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2650 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2652 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2653 unsigned long regval
;
2655 /* Write the low word of the double to the even register(s). */
2656 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2658 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2659 float_argreg
, phex (regval
, 4));
2660 write_register (float_argreg
++, regval
);
2662 /* Write the high word of the double to the odd register(s). */
2663 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2665 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2666 float_argreg
, phex (regval
, 4));
2667 write_register (float_argreg
++, regval
);
2671 /* This is a floating point value that fits entirely
2672 in a single register. */
2673 /* On 32 bit ABI's the float_argreg is further adjusted
2674 above to ensure that it is even register aligned. */
2675 LONGEST regval
= extract_unsigned_integer (val
, len
);
2677 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2678 float_argreg
, phex (regval
, len
));
2679 write_register (float_argreg
++, regval
);
2684 /* Copy the argument to general registers or the stack in
2685 register-sized pieces. Large arguments are split between
2686 registers and stack. */
2687 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2688 are treated specially: Irix cc passes them in registers
2689 where gcc sometimes puts them on the stack. For maximum
2690 compatibility, we will put them in both places. */
2691 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2692 (len
% MIPS_SAVED_REGSIZE
!= 0));
2694 /* Note: Floating-point values that didn't fit into an FP
2695 register are only written to memory. */
2698 /* Remember if the argument was written to the stack. */
2699 int stack_used_p
= 0;
2701 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2704 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2707 /* Write this portion of the argument to the stack. */
2708 if (argreg
> MIPS_LAST_ARG_REGNUM
2710 || fp_register_arg_p (typecode
, arg_type
))
2712 /* Should shorter than int integer values be
2713 promoted to int before being stored? */
2714 int longword_offset
= 0;
2717 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2719 if (MIPS_STACK_ARGSIZE
== 8 &&
2720 (typecode
== TYPE_CODE_INT
||
2721 typecode
== TYPE_CODE_PTR
||
2722 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2723 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2724 else if ((typecode
== TYPE_CODE_STRUCT
||
2725 typecode
== TYPE_CODE_UNION
) &&
2726 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2727 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2732 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2733 paddr_nz (stack_offset
));
2734 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2735 paddr_nz (longword_offset
));
2738 addr
= sp
+ stack_offset
+ longword_offset
;
2743 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2745 for (i
= 0; i
< partial_len
; i
++)
2747 fprintf_unfiltered (gdb_stdlog
, "%02x",
2751 write_memory (addr
, val
, partial_len
);
2754 /* Note!!! This is NOT an else clause. Odd sized
2755 structs may go thru BOTH paths. Floating point
2756 arguments will not. */
2757 /* Write this portion of the argument to a general
2758 purpose register. */
2759 if (argreg
<= MIPS_LAST_ARG_REGNUM
2760 && !fp_register_arg_p (typecode
, arg_type
))
2762 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2765 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2767 phex (regval
, MIPS_SAVED_REGSIZE
));
2768 write_register (argreg
, regval
);
2775 /* Compute the the offset into the stack at which we
2776 will copy the next parameter.
2778 In the new EABI (and the NABI32), the stack_offset
2779 only needs to be adjusted when it has been used. */
2782 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2786 fprintf_unfiltered (gdb_stdlog
, "\n");
2789 /* Return adjusted stack pointer. */
2793 /* N32/N64 version of push_arguments. */
2796 mips_n32n64_push_arguments (int nargs
,
2797 struct value
**args
,
2800 CORE_ADDR struct_addr
)
2806 int stack_offset
= 0;
2808 /* First ensure that the stack and structure return address (if any)
2809 are properly aligned. The stack has to be at least 64-bit
2810 aligned even on 32-bit machines, because doubles must be 64-bit
2811 aligned. For n32 and n64, stack frames need to be 128-bit
2812 aligned, so we round to this widest known alignment. */
2814 sp
= ROUND_DOWN (sp
, 16);
2815 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2817 /* Now make space on the stack for the args. */
2818 for (argnum
= 0; argnum
< nargs
; argnum
++)
2819 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2820 MIPS_STACK_ARGSIZE
);
2821 sp
-= ROUND_UP (len
, 16);
2824 fprintf_unfiltered (gdb_stdlog
,
2825 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2826 paddr_nz (sp
), ROUND_UP (len
, 16));
2828 /* Initialize the integer and float register pointers. */
2830 float_argreg
= FPA0_REGNUM
;
2832 /* The struct_return pointer occupies the first parameter-passing reg. */
2836 fprintf_unfiltered (gdb_stdlog
,
2837 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2838 argreg
, paddr_nz (struct_addr
));
2839 write_register (argreg
++, struct_addr
);
2842 /* Now load as many as possible of the first arguments into
2843 registers, and push the rest onto the stack. Loop thru args
2844 from first to last. */
2845 for (argnum
= 0; argnum
< nargs
; argnum
++)
2848 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2849 struct value
*arg
= args
[argnum
];
2850 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2851 int len
= TYPE_LENGTH (arg_type
);
2852 enum type_code typecode
= TYPE_CODE (arg_type
);
2855 fprintf_unfiltered (gdb_stdlog
,
2856 "mips_n32n64_push_arguments: %d len=%d type=%d",
2857 argnum
+ 1, len
, (int) typecode
);
2859 val
= (char *) VALUE_CONTENTS (arg
);
2861 if (fp_register_arg_p (typecode
, arg_type
)
2862 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2864 /* This is a floating point value that fits entirely
2865 in a single register. */
2866 /* On 32 bit ABI's the float_argreg is further adjusted
2867 above to ensure that it is even register aligned. */
2868 LONGEST regval
= extract_unsigned_integer (val
, len
);
2870 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2871 float_argreg
, phex (regval
, len
));
2872 write_register (float_argreg
++, regval
);
2875 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2876 argreg
, phex (regval
, len
));
2877 write_register (argreg
, regval
);
2882 /* Copy the argument to general registers or the stack in
2883 register-sized pieces. Large arguments are split between
2884 registers and stack. */
2885 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2886 are treated specially: Irix cc passes them in registers
2887 where gcc sometimes puts them on the stack. For maximum
2888 compatibility, we will put them in both places. */
2889 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2890 (len
% MIPS_SAVED_REGSIZE
!= 0));
2891 /* Note: Floating-point values that didn't fit into an FP
2892 register are only written to memory. */
2895 /* Rememer if the argument was written to the stack. */
2896 int stack_used_p
= 0;
2897 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
2898 len
: MIPS_SAVED_REGSIZE
;
2901 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2904 /* Write this portion of the argument to the stack. */
2905 if (argreg
> MIPS_LAST_ARG_REGNUM
2907 || fp_register_arg_p (typecode
, arg_type
))
2909 /* Should shorter than int integer values be
2910 promoted to int before being stored? */
2911 int longword_offset
= 0;
2914 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2916 if (MIPS_STACK_ARGSIZE
== 8 &&
2917 (typecode
== TYPE_CODE_INT
||
2918 typecode
== TYPE_CODE_PTR
||
2919 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2920 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2921 else if ((typecode
== TYPE_CODE_STRUCT
||
2922 typecode
== TYPE_CODE_UNION
) &&
2923 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2924 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2929 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2930 paddr_nz (stack_offset
));
2931 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2932 paddr_nz (longword_offset
));
2935 addr
= sp
+ stack_offset
+ longword_offset
;
2940 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2942 for (i
= 0; i
< partial_len
; i
++)
2944 fprintf_unfiltered (gdb_stdlog
, "%02x",
2948 write_memory (addr
, val
, partial_len
);
2951 /* Note!!! This is NOT an else clause. Odd sized
2952 structs may go thru BOTH paths. Floating point
2953 arguments will not. */
2954 /* Write this portion of the argument to a general
2955 purpose register. */
2956 if (argreg
<= MIPS_LAST_ARG_REGNUM
2957 && !fp_register_arg_p (typecode
, arg_type
))
2959 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2961 /* A non-floating-point argument being passed in a
2962 general register. If a struct or union, and if
2963 the remaining length is smaller than the register
2964 size, we have to adjust the register value on
2967 It does not seem to be necessary to do the
2968 same for integral types.
2970 cagney/2001-07-23: gdb/179: Also, GCC, when
2971 outputting LE O32 with sizeof (struct) <
2972 MIPS_SAVED_REGSIZE, generates a left shift as
2973 part of storing the argument in a register a
2974 register (the left shift isn't generated when
2975 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2976 is quite possible that this is GCC contradicting
2977 the LE/O32 ABI, GDB has not been adjusted to
2978 accommodate this. Either someone needs to
2979 demonstrate that the LE/O32 ABI specifies such a
2980 left shift OR this new ABI gets identified as
2981 such and GDB gets tweaked accordingly. */
2983 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2984 && partial_len
< MIPS_SAVED_REGSIZE
2985 && (typecode
== TYPE_CODE_STRUCT
||
2986 typecode
== TYPE_CODE_UNION
))
2987 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2991 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2993 phex (regval
, MIPS_SAVED_REGSIZE
));
2994 write_register (argreg
, regval
);
3001 /* Compute the the offset into the stack at which we
3002 will copy the next parameter.
3004 In N32 (N64?), the stack_offset only needs to be
3005 adjusted when it has been used. */
3008 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3012 fprintf_unfiltered (gdb_stdlog
, "\n");
3015 /* Return adjusted stack pointer. */
3019 /* O32 version of push_arguments. */
3022 mips_o32_push_arguments (int nargs
,
3023 struct value
**args
,
3026 CORE_ADDR struct_addr
)
3032 int stack_offset
= 0;
3034 /* First ensure that the stack and structure return address (if any)
3035 are properly aligned. The stack has to be at least 64-bit
3036 aligned even on 32-bit machines, because doubles must be 64-bit
3037 aligned. For n32 and n64, stack frames need to be 128-bit
3038 aligned, so we round to this widest known alignment. */
3040 sp
= ROUND_DOWN (sp
, 16);
3041 struct_addr
= ROUND_DOWN (struct_addr
, 16);
3043 /* Now make space on the stack for the args. */
3044 for (argnum
= 0; argnum
< nargs
; argnum
++)
3045 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3046 MIPS_STACK_ARGSIZE
);
3047 sp
-= ROUND_UP (len
, 16);
3050 fprintf_unfiltered (gdb_stdlog
,
3051 "mips_o32_push_arguments: sp=0x%s allocated %d\n",
3052 paddr_nz (sp
), ROUND_UP (len
, 16));
3054 /* Initialize the integer and float register pointers. */
3056 float_argreg
= FPA0_REGNUM
;
3058 /* The struct_return pointer occupies the first parameter-passing reg. */
3062 fprintf_unfiltered (gdb_stdlog
,
3063 "mips_o32_push_arguments: struct_return reg=%d 0x%s\n",
3064 argreg
, paddr_nz (struct_addr
));
3065 write_register (argreg
++, struct_addr
);
3066 stack_offset
+= MIPS_STACK_ARGSIZE
;
3069 /* Now load as many as possible of the first arguments into
3070 registers, and push the rest onto the stack. Loop thru args
3071 from first to last. */
3072 for (argnum
= 0; argnum
< nargs
; argnum
++)
3075 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3076 struct value
*arg
= args
[argnum
];
3077 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3078 int len
= TYPE_LENGTH (arg_type
);
3079 enum type_code typecode
= TYPE_CODE (arg_type
);
3082 fprintf_unfiltered (gdb_stdlog
,
3083 "mips_o32_push_arguments: %d len=%d type=%d",
3084 argnum
+ 1, len
, (int) typecode
);
3086 val
= (char *) VALUE_CONTENTS (arg
);
3088 /* 32-bit ABIs always start floating point arguments in an
3089 even-numbered floating point register. Round the FP register
3090 up before the check to see if there are any FP registers
3091 left. O32/O64 targets also pass the FP in the integer
3092 registers so also round up normal registers. */
3093 if (!FP_REGISTER_DOUBLE
3094 && fp_register_arg_p (typecode
, arg_type
))
3096 if ((float_argreg
& 1))
3100 /* Floating point arguments passed in registers have to be
3101 treated specially. On 32-bit architectures, doubles
3102 are passed in register pairs; the even register gets
3103 the low word, and the odd register gets the high word.
3104 On O32/O64, the first two floating point arguments are
3105 also copied to general registers, because MIPS16 functions
3106 don't use float registers for arguments. This duplication of
3107 arguments in general registers can't hurt non-MIPS16 functions
3108 because those registers are normally skipped. */
3110 if (fp_register_arg_p (typecode
, arg_type
)
3111 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3113 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3115 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3116 unsigned long regval
;
3118 /* Write the low word of the double to the even register(s). */
3119 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3121 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3122 float_argreg
, phex (regval
, 4));
3123 write_register (float_argreg
++, regval
);
3125 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3126 argreg
, phex (regval
, 4));
3127 write_register (argreg
++, regval
);
3129 /* Write the high word of the double to the odd register(s). */
3130 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3132 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3133 float_argreg
, phex (regval
, 4));
3134 write_register (float_argreg
++, regval
);
3137 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3138 argreg
, phex (regval
, 4));
3139 write_register (argreg
++, regval
);
3143 /* This is a floating point value that fits entirely
3144 in a single register. */
3145 /* On 32 bit ABI's the float_argreg is further adjusted
3146 above to ensure that it is even register aligned. */
3147 LONGEST regval
= extract_unsigned_integer (val
, len
);
3149 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3150 float_argreg
, phex (regval
, len
));
3151 write_register (float_argreg
++, regval
);
3152 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3153 registers for each argument. The below is (my
3154 guess) to ensure that the corresponding integer
3155 register has reserved the same space. */
3157 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3158 argreg
, phex (regval
, len
));
3159 write_register (argreg
, regval
);
3160 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3162 /* Reserve space for the FP register. */
3163 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3167 /* Copy the argument to general registers or the stack in
3168 register-sized pieces. Large arguments are split between
3169 registers and stack. */
3170 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3171 are treated specially: Irix cc passes them in registers
3172 where gcc sometimes puts them on the stack. For maximum
3173 compatibility, we will put them in both places. */
3174 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3175 (len
% MIPS_SAVED_REGSIZE
!= 0));
3176 /* Structures should be aligned to eight bytes (even arg registers)
3177 on MIPS_ABI_O32, if their first member has double precision. */
3178 if (MIPS_SAVED_REGSIZE
< 8
3179 && mips_type_needs_double_align (arg_type
))
3184 /* Note: Floating-point values that didn't fit into an FP
3185 register are only written to memory. */
3188 /* Remember if the argument was written to the stack. */
3189 int stack_used_p
= 0;
3191 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3194 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3197 /* Write this portion of the argument to the stack. */
3198 if (argreg
> MIPS_LAST_ARG_REGNUM
3200 || fp_register_arg_p (typecode
, arg_type
))
3202 /* Should shorter than int integer values be
3203 promoted to int before being stored? */
3204 int longword_offset
= 0;
3207 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3209 if (MIPS_STACK_ARGSIZE
== 8 &&
3210 (typecode
== TYPE_CODE_INT
||
3211 typecode
== TYPE_CODE_PTR
||
3212 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3213 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3218 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3219 paddr_nz (stack_offset
));
3220 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3221 paddr_nz (longword_offset
));
3224 addr
= sp
+ stack_offset
+ longword_offset
;
3229 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3231 for (i
= 0; i
< partial_len
; i
++)
3233 fprintf_unfiltered (gdb_stdlog
, "%02x",
3237 write_memory (addr
, val
, partial_len
);
3240 /* Note!!! This is NOT an else clause. Odd sized
3241 structs may go thru BOTH paths. Floating point
3242 arguments will not. */
3243 /* Write this portion of the argument to a general
3244 purpose register. */
3245 if (argreg
<= MIPS_LAST_ARG_REGNUM
3246 && !fp_register_arg_p (typecode
, arg_type
))
3248 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3249 /* Value may need to be sign extended, because
3250 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3252 /* A non-floating-point argument being passed in a
3253 general register. If a struct or union, and if
3254 the remaining length is smaller than the register
3255 size, we have to adjust the register value on
3258 It does not seem to be necessary to do the
3259 same for integral types.
3261 Also don't do this adjustment on O64 binaries.
3263 cagney/2001-07-23: gdb/179: Also, GCC, when
3264 outputting LE O32 with sizeof (struct) <
3265 MIPS_SAVED_REGSIZE, generates a left shift as
3266 part of storing the argument in a register a
3267 register (the left shift isn't generated when
3268 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3269 is quite possible that this is GCC contradicting
3270 the LE/O32 ABI, GDB has not been adjusted to
3271 accommodate this. Either someone needs to
3272 demonstrate that the LE/O32 ABI specifies such a
3273 left shift OR this new ABI gets identified as
3274 such and GDB gets tweaked accordingly. */
3276 if (MIPS_SAVED_REGSIZE
< 8
3277 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3278 && partial_len
< MIPS_SAVED_REGSIZE
3279 && (typecode
== TYPE_CODE_STRUCT
||
3280 typecode
== TYPE_CODE_UNION
))
3281 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3285 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3287 phex (regval
, MIPS_SAVED_REGSIZE
));
3288 write_register (argreg
, regval
);
3291 /* Prevent subsequent floating point arguments from
3292 being passed in floating point registers. */
3293 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3299 /* Compute the the offset into the stack at which we
3300 will copy the next parameter.
3302 In older ABIs, the caller reserved space for
3303 registers that contained arguments. This was loosely
3304 refered to as their "home". Consequently, space is
3305 always allocated. */
3307 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3311 fprintf_unfiltered (gdb_stdlog
, "\n");
3314 /* Return adjusted stack pointer. */
3318 /* O64 version of push_arguments. */
3321 mips_o64_push_arguments (int nargs
,
3322 struct value
**args
,
3325 CORE_ADDR struct_addr
)
3331 int stack_offset
= 0;
3333 /* First ensure that the stack and structure return address (if any)
3334 are properly aligned. The stack has to be at least 64-bit
3335 aligned even on 32-bit machines, because doubles must be 64-bit
3336 aligned. For n32 and n64, stack frames need to be 128-bit
3337 aligned, so we round to this widest known alignment. */
3339 sp
= ROUND_DOWN (sp
, 16);
3340 struct_addr
= ROUND_DOWN (struct_addr
, 16);
3342 /* Now make space on the stack for the args. */
3343 for (argnum
= 0; argnum
< nargs
; argnum
++)
3344 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3345 MIPS_STACK_ARGSIZE
);
3346 sp
-= ROUND_UP (len
, 16);
3349 fprintf_unfiltered (gdb_stdlog
,
3350 "mips_o64_push_arguments: sp=0x%s allocated %d\n",
3351 paddr_nz (sp
), ROUND_UP (len
, 16));
3353 /* Initialize the integer and float register pointers. */
3355 float_argreg
= FPA0_REGNUM
;
3357 /* The struct_return pointer occupies the first parameter-passing reg. */
3361 fprintf_unfiltered (gdb_stdlog
,
3362 "mips_o64_push_arguments: struct_return reg=%d 0x%s\n",
3363 argreg
, paddr_nz (struct_addr
));
3364 write_register (argreg
++, struct_addr
);
3365 stack_offset
+= MIPS_STACK_ARGSIZE
;
3368 /* Now load as many as possible of the first arguments into
3369 registers, and push the rest onto the stack. Loop thru args
3370 from first to last. */
3371 for (argnum
= 0; argnum
< nargs
; argnum
++)
3374 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3375 struct value
*arg
= args
[argnum
];
3376 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3377 int len
= TYPE_LENGTH (arg_type
);
3378 enum type_code typecode
= TYPE_CODE (arg_type
);
3381 fprintf_unfiltered (gdb_stdlog
,
3382 "mips_o64_push_arguments: %d len=%d type=%d",
3383 argnum
+ 1, len
, (int) typecode
);
3385 val
= (char *) VALUE_CONTENTS (arg
);
3387 /* 32-bit ABIs always start floating point arguments in an
3388 even-numbered floating point register. Round the FP register
3389 up before the check to see if there are any FP registers
3390 left. O32/O64 targets also pass the FP in the integer
3391 registers so also round up normal registers. */
3392 if (!FP_REGISTER_DOUBLE
3393 && fp_register_arg_p (typecode
, arg_type
))
3395 if ((float_argreg
& 1))
3399 /* Floating point arguments passed in registers have to be
3400 treated specially. On 32-bit architectures, doubles
3401 are passed in register pairs; the even register gets
3402 the low word, and the odd register gets the high word.
3403 On O32/O64, the first two floating point arguments are
3404 also copied to general registers, because MIPS16 functions
3405 don't use float registers for arguments. This duplication of
3406 arguments in general registers can't hurt non-MIPS16 functions
3407 because those registers are normally skipped. */
3409 if (fp_register_arg_p (typecode
, arg_type
)
3410 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3412 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3414 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3415 unsigned long regval
;
3417 /* Write the low word of the double to the even register(s). */
3418 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3420 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3421 float_argreg
, phex (regval
, 4));
3422 write_register (float_argreg
++, regval
);
3424 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3425 argreg
, phex (regval
, 4));
3426 write_register (argreg
++, regval
);
3428 /* Write the high word of the double to the odd register(s). */
3429 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3431 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3432 float_argreg
, phex (regval
, 4));
3433 write_register (float_argreg
++, regval
);
3436 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3437 argreg
, phex (regval
, 4));
3438 write_register (argreg
++, regval
);
3442 /* This is a floating point value that fits entirely
3443 in a single register. */
3444 /* On 32 bit ABI's the float_argreg is further adjusted
3445 above to ensure that it is even register aligned. */
3446 LONGEST regval
= extract_unsigned_integer (val
, len
);
3448 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3449 float_argreg
, phex (regval
, len
));
3450 write_register (float_argreg
++, regval
);
3451 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3452 registers for each argument. The below is (my
3453 guess) to ensure that the corresponding integer
3454 register has reserved the same space. */
3456 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3457 argreg
, phex (regval
, len
));
3458 write_register (argreg
, regval
);
3459 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3461 /* Reserve space for the FP register. */
3462 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3466 /* Copy the argument to general registers or the stack in
3467 register-sized pieces. Large arguments are split between
3468 registers and stack. */
3469 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3470 are treated specially: Irix cc passes them in registers
3471 where gcc sometimes puts them on the stack. For maximum
3472 compatibility, we will put them in both places. */
3473 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3474 (len
% MIPS_SAVED_REGSIZE
!= 0));
3475 /* Structures should be aligned to eight bytes (even arg registers)
3476 on MIPS_ABI_O32, if their first member has double precision. */
3477 if (MIPS_SAVED_REGSIZE
< 8
3478 && mips_type_needs_double_align (arg_type
))
3483 /* Note: Floating-point values that didn't fit into an FP
3484 register are only written to memory. */
3487 /* Remember if the argument was written to the stack. */
3488 int stack_used_p
= 0;
3490 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3493 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3496 /* Write this portion of the argument to the stack. */
3497 if (argreg
> MIPS_LAST_ARG_REGNUM
3499 || fp_register_arg_p (typecode
, arg_type
))
3501 /* Should shorter than int integer values be
3502 promoted to int before being stored? */
3503 int longword_offset
= 0;
3506 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3508 if (MIPS_STACK_ARGSIZE
== 8 &&
3509 (typecode
== TYPE_CODE_INT
||
3510 typecode
== TYPE_CODE_PTR
||
3511 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3512 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3517 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3518 paddr_nz (stack_offset
));
3519 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3520 paddr_nz (longword_offset
));
3523 addr
= sp
+ stack_offset
+ longword_offset
;
3528 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3530 for (i
= 0; i
< partial_len
; i
++)
3532 fprintf_unfiltered (gdb_stdlog
, "%02x",
3536 write_memory (addr
, val
, partial_len
);
3539 /* Note!!! This is NOT an else clause. Odd sized
3540 structs may go thru BOTH paths. Floating point
3541 arguments will not. */
3542 /* Write this portion of the argument to a general
3543 purpose register. */
3544 if (argreg
<= MIPS_LAST_ARG_REGNUM
3545 && !fp_register_arg_p (typecode
, arg_type
))
3547 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3548 /* Value may need to be sign extended, because
3549 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3551 /* A non-floating-point argument being passed in a
3552 general register. If a struct or union, and if
3553 the remaining length is smaller than the register
3554 size, we have to adjust the register value on
3557 It does not seem to be necessary to do the
3558 same for integral types.
3560 Also don't do this adjustment on O64 binaries.
3562 cagney/2001-07-23: gdb/179: Also, GCC, when
3563 outputting LE O32 with sizeof (struct) <
3564 MIPS_SAVED_REGSIZE, generates a left shift as
3565 part of storing the argument in a register a
3566 register (the left shift isn't generated when
3567 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3568 is quite possible that this is GCC contradicting
3569 the LE/O32 ABI, GDB has not been adjusted to
3570 accommodate this. Either someone needs to
3571 demonstrate that the LE/O32 ABI specifies such a
3572 left shift OR this new ABI gets identified as
3573 such and GDB gets tweaked accordingly. */
3575 if (MIPS_SAVED_REGSIZE
< 8
3576 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3577 && partial_len
< MIPS_SAVED_REGSIZE
3578 && (typecode
== TYPE_CODE_STRUCT
||
3579 typecode
== TYPE_CODE_UNION
))
3580 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3584 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3586 phex (regval
, MIPS_SAVED_REGSIZE
));
3587 write_register (argreg
, regval
);
3590 /* Prevent subsequent floating point arguments from
3591 being passed in floating point registers. */
3592 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3598 /* Compute the the offset into the stack at which we
3599 will copy the next parameter.
3601 In older ABIs, the caller reserved space for
3602 registers that contained arguments. This was loosely
3603 refered to as their "home". Consequently, space is
3604 always allocated. */
3606 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3610 fprintf_unfiltered (gdb_stdlog
, "\n");
3613 /* Return adjusted stack pointer. */
3618 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
3620 /* Set the return address register to point to the entry
3621 point of the program, where a breakpoint lies in wait. */
3622 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
3627 mips_push_register (CORE_ADDR
* sp
, int regno
)
3629 char *buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3632 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
3634 regsize
= MIPS_SAVED_REGSIZE
;
3635 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3636 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
3641 regsize
= REGISTER_RAW_SIZE (regno
);
3645 read_register_gen (regno
, buffer
);
3646 write_memory (*sp
, buffer
+ offset
, regsize
);
3649 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3650 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3653 mips_push_dummy_frame (void)
3656 struct linked_proc_info
*link
= (struct linked_proc_info
*)
3657 xmalloc (sizeof (struct linked_proc_info
));
3658 mips_extra_func_info_t proc_desc
= &link
->info
;
3659 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
3660 CORE_ADDR old_sp
= sp
;
3661 link
->next
= linked_proc_desc_table
;
3662 linked_proc_desc_table
= link
;
3664 /* FIXME! are these correct ? */
3665 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3666 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3667 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3668 #define FLOAT_SINGLE_REG_SAVE_MASK \
3669 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3671 * The registers we must save are all those not preserved across
3672 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3673 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3674 * and FP Control/Status registers.
3677 * Dummy frame layout:
3680 * Saved MMHI, MMLO, FPC_CSR
3685 * Saved D18 (i.e. F19, F18)
3687 * Saved D0 (i.e. F1, F0)
3688 * Argument build area and stack arguments written via mips_push_arguments
3692 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3693 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
3694 PROC_FRAME_OFFSET (proc_desc
) = 0;
3695 PROC_FRAME_ADJUST (proc_desc
) = 0;
3696 mips_push_register (&sp
, PC_REGNUM
);
3697 mips_push_register (&sp
, HI_REGNUM
);
3698 mips_push_register (&sp
, LO_REGNUM
);
3699 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
3701 /* Save general CPU registers */
3702 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
3703 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3704 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
3705 for (ireg
= 32; --ireg
>= 0;)
3706 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
3707 mips_push_register (&sp
, ireg
);
3709 /* Save floating point registers starting with high order word */
3710 PROC_FREG_MASK (proc_desc
) =
3711 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
3712 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
3713 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3715 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
3716 for (ireg
= 32; --ireg
>= 0;)
3717 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
3718 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
3720 /* Update the frame pointer for the call dummy and the stack pointer.
3721 Set the procedure's starting and ending addresses to point to the
3722 call dummy address at the entry point. */
3723 write_register (PUSH_FP_REGNUM
, old_sp
);
3724 write_register (SP_REGNUM
, sp
);
3725 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
3726 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
3727 SET_PROC_DESC_IS_DUMMY (proc_desc
);
3728 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
3732 mips_pop_frame (void)
3734 register int regnum
;
3735 struct frame_info
*frame
= get_current_frame ();
3736 CORE_ADDR new_sp
= FRAME_FP (frame
);
3738 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
3740 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
3741 if (frame
->saved_regs
== NULL
)
3742 FRAME_INIT_SAVED_REGS (frame
);
3743 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3745 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3746 && frame
->saved_regs
[regnum
])
3747 write_register (regnum
,
3748 read_memory_integer (frame
->saved_regs
[regnum
],
3749 MIPS_SAVED_REGSIZE
));
3751 write_register (SP_REGNUM
, new_sp
);
3752 flush_cached_frames ();
3754 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3756 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3758 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3760 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3762 if (&pi_ptr
->info
== proc_desc
)
3767 error ("Can't locate dummy extra frame info\n");
3769 if (prev_ptr
!= NULL
)
3770 prev_ptr
->next
= pi_ptr
->next
;
3772 linked_proc_desc_table
= pi_ptr
->next
;
3776 write_register (HI_REGNUM
,
3777 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3778 MIPS_SAVED_REGSIZE
));
3779 write_register (LO_REGNUM
,
3780 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3781 MIPS_SAVED_REGSIZE
));
3782 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3783 write_register (FCRCS_REGNUM
,
3784 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3785 MIPS_SAVED_REGSIZE
));
3789 /* Floating point register management.
3791 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3792 64bit operations, these early MIPS cpus treat fp register pairs
3793 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3794 registers and offer a compatibility mode that emulates the MIPS2 fp
3795 model. When operating in MIPS2 fp compat mode, later cpu's split
3796 double precision floats into two 32-bit chunks and store them in
3797 consecutive fp regs. To display 64-bit floats stored in this
3798 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3799 Throw in user-configurable endianness and you have a real mess.
3801 The way this works is:
3802 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3803 double-precision value will be split across two logical registers.
3804 The lower-numbered logical register will hold the low-order bits,
3805 regardless of the processor's endianness.
3806 - If we are on a 64-bit processor, and we are looking for a
3807 single-precision value, it will be in the low ordered bits
3808 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3809 save slot in memory.
3810 - If we are in 64-bit mode, everything is straightforward.
3812 Note that this code only deals with "live" registers at the top of the
3813 stack. We will attempt to deal with saved registers later, when
3814 the raw/cooked register interface is in place. (We need a general
3815 interface that can deal with dynamic saved register sizes -- fp
3816 regs could be 32 bits wide in one frame and 64 on the frame above
3819 static struct type
*
3820 mips_float_register_type (void)
3822 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3823 return builtin_type_ieee_single_big
;
3825 return builtin_type_ieee_single_little
;
3828 static struct type
*
3829 mips_double_register_type (void)
3831 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3832 return builtin_type_ieee_double_big
;
3834 return builtin_type_ieee_double_little
;
3837 /* Copy a 32-bit single-precision value from the current frame
3838 into rare_buffer. */
3841 mips_read_fp_register_single (int regno
, char *rare_buffer
)
3843 int raw_size
= REGISTER_RAW_SIZE (regno
);
3844 char *raw_buffer
= alloca (raw_size
);
3846 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
3847 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3850 /* We have a 64-bit value for this register. Find the low-order
3854 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3859 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3863 memcpy (rare_buffer
, raw_buffer
, 4);
3867 /* Copy a 64-bit double-precision value from the current frame into
3868 rare_buffer. This may include getting half of it from the next
3872 mips_read_fp_register_double (int regno
, char *rare_buffer
)
3874 int raw_size
= REGISTER_RAW_SIZE (regno
);
3876 if (raw_size
== 8 && !mips2_fp_compat ())
3878 /* We have a 64-bit value for this register, and we should use
3880 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
3881 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3885 if ((regno
- FP0_REGNUM
) & 1)
3886 internal_error (__FILE__
, __LINE__
,
3887 "mips_read_fp_register_double: bad access to "
3888 "odd-numbered FP register");
3890 /* mips_read_fp_register_single will find the correct 32 bits from
3892 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3894 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
3895 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
3899 mips_read_fp_register_single (regno
, rare_buffer
);
3900 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
3906 mips_print_register (int regnum
, int all
)
3908 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3910 /* Get the data in raw format. */
3911 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3913 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
3917 /* If we have a actual 32-bit floating point register (or we are in
3918 32-bit compatibility mode), and the register is even-numbered,
3919 also print it as a double (spanning two registers). */
3920 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
3921 && (REGISTER_RAW_SIZE (regnum
) == 4
3922 || mips2_fp_compat ())
3923 && !((regnum
- FP0_REGNUM
) & 1))
3925 char *dbuffer
= alloca (2 * MAX_REGISTER_RAW_SIZE
);
3927 mips_read_fp_register_double (regnum
, dbuffer
);
3929 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
3930 val_print (mips_double_register_type (), dbuffer
, 0, 0,
3931 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3932 printf_filtered ("); ");
3934 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3936 /* The problem with printing numeric register names (r26, etc.) is that
3937 the user can't use them on input. Probably the best solution is to
3938 fix it so that either the numeric or the funky (a2, etc.) names
3939 are accepted on input. */
3940 if (regnum
< MIPS_NUMREGS
)
3941 printf_filtered ("(r%d): ", regnum
);
3943 printf_filtered (": ");
3945 /* If virtual format is floating, print it that way. */
3946 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3947 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
3949 /* We have a meaningful 64-bit value in this register. Show
3950 it as a 32-bit float and a 64-bit double. */
3951 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3953 printf_filtered (" (float) ");
3954 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3955 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3956 printf_filtered (", (double) ");
3957 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3958 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3961 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3962 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3963 /* Else print as integer in hex. */
3968 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3969 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3973 print_scalar_formatted (raw_buffer
+ offset
,
3974 REGISTER_VIRTUAL_TYPE (regnum
),
3975 'x', 0, gdb_stdout
);
3979 /* Replacement for generic do_registers_info.
3980 Print regs in pretty columns. */
3983 do_fp_register_row (int regnum
)
3984 { /* do values for FP (float) regs */
3986 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3987 int inv1
, inv2
, inv3
;
3989 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3991 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3993 /* 4-byte registers: we can fit two registers per row. */
3994 /* Also print every pair of 4-byte regs as an 8-byte double. */
3995 mips_read_fp_register_single (regnum
, raw_buffer
);
3996 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3998 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3999 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
4001 mips_read_fp_register_double (regnum
, raw_buffer
);
4002 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
4004 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
4006 printf_filtered (": <invalid float>");
4008 printf_filtered ("%-17.9g", flt1
);
4010 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
4012 printf_filtered (": <invalid float>");
4014 printf_filtered ("%-17.9g", flt2
);
4016 printf_filtered (" dbl: ");
4018 printf_filtered ("<invalid double>");
4020 printf_filtered ("%-24.17g", doub
);
4021 printf_filtered ("\n");
4023 /* may want to do hex display here (future enhancement) */
4028 /* Eight byte registers: print each one as float AND as double. */
4029 mips_read_fp_register_single (regnum
, raw_buffer
);
4030 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
4032 mips_read_fp_register_double (regnum
, raw_buffer
);
4033 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
4035 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
4037 printf_filtered ("<invalid float>");
4039 printf_filtered ("flt: %-17.9g", flt1
);
4041 printf_filtered (" dbl: ");
4043 printf_filtered ("<invalid double>");
4045 printf_filtered ("%-24.17g", doub
);
4047 printf_filtered ("\n");
4048 /* may want to do hex display here (future enhancement) */
4054 /* Print a row's worth of GP (int) registers, with name labels above */
4057 do_gp_register_row (int regnum
)
4059 /* do values for GP (int) regs */
4060 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4061 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
4063 int start_regnum
= regnum
;
4064 int numregs
= NUM_REGS
;
4067 /* For GP registers, we print a separate row of names above the vals */
4068 printf_filtered (" ");
4069 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
4071 if (*REGISTER_NAME (regnum
) == '\0')
4072 continue; /* unused register */
4073 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4074 break; /* end the row: reached FP register */
4075 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
4076 REGISTER_NAME (regnum
));
4079 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
4080 start_regnum
); /* print the R0 to R31 names */
4082 regnum
= start_regnum
; /* go back to start of row */
4083 /* now print the values in hex, 4 or 8 to the row */
4084 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
4086 if (*REGISTER_NAME (regnum
) == '\0')
4087 continue; /* unused register */
4088 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4089 break; /* end row: reached FP register */
4090 /* OK: get the data in raw format. */
4091 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4092 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4093 /* pad small registers */
4094 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
4095 printf_filtered (" ");
4096 /* Now print the register value in hex, endian order. */
4097 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4098 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
4099 byte
< REGISTER_RAW_SIZE (regnum
);
4101 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
4103 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
4106 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
4107 printf_filtered (" ");
4110 if (col
> 0) /* ie. if we actually printed anything... */
4111 printf_filtered ("\n");
4116 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4119 mips_do_registers_info (int regnum
, int fpregs
)
4121 if (regnum
!= -1) /* do one specified register */
4123 if (*(REGISTER_NAME (regnum
)) == '\0')
4124 error ("Not a valid register for the current processor type");
4126 mips_print_register (regnum
, 0);
4127 printf_filtered ("\n");
4130 /* do all (or most) registers */
4133 while (regnum
< NUM_REGS
)
4135 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4136 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
4137 regnum
= do_fp_register_row (regnum
); /* FP regs */
4139 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4141 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
4146 /* Is this a branch with a delay slot? */
4148 static int is_delayed (unsigned long);
4151 is_delayed (unsigned long insn
)
4154 for (i
= 0; i
< NUMOPCODES
; ++i
)
4155 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4156 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4158 return (i
< NUMOPCODES
4159 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4160 | INSN_COND_BRANCH_DELAY
4161 | INSN_COND_BRANCH_LIKELY
)));
4165 mips_step_skips_delay (CORE_ADDR pc
)
4167 char buf
[MIPS_INSTLEN
];
4169 /* There is no branch delay slot on MIPS16. */
4170 if (pc_is_mips16 (pc
))
4173 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4174 /* If error reading memory, guess that it is not a delayed branch. */
4176 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4180 /* Skip the PC past function prologue instructions (32-bit version).
4181 This is a helper function for mips_skip_prologue. */
4184 mips32_skip_prologue (CORE_ADDR pc
)
4188 int seen_sp_adjust
= 0;
4189 int load_immediate_bytes
= 0;
4191 /* Skip the typical prologue instructions. These are the stack adjustment
4192 instruction and the instructions that save registers on the stack
4193 or in the gcc frame. */
4194 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4196 unsigned long high_word
;
4198 inst
= mips_fetch_instruction (pc
);
4199 high_word
= (inst
>> 16) & 0xffff;
4201 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4202 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4204 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4205 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4207 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4208 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4209 && (inst
& 0x001F0000)) /* reg != $zero */
4212 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4214 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4216 continue; /* reg != $zero */
4218 /* move $s8,$sp. With different versions of gas this will be either
4219 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4220 Accept any one of these. */
4221 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4224 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4226 else if (high_word
== 0x3c1c) /* lui $gp,n */
4228 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4230 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4231 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4233 /* The following instructions load $at or $t0 with an immediate
4234 value in preparation for a stack adjustment via
4235 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4236 a local variable, so we accept them only before a stack adjustment
4237 instruction was seen. */
4238 else if (!seen_sp_adjust
)
4240 if (high_word
== 0x3c01 || /* lui $at,n */
4241 high_word
== 0x3c08) /* lui $t0,n */
4243 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4246 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4247 high_word
== 0x3508 || /* ori $t0,$t0,n */
4248 high_word
== 0x3401 || /* ori $at,$zero,n */
4249 high_word
== 0x3408) /* ori $t0,$zero,n */
4251 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4261 /* In a frameless function, we might have incorrectly
4262 skipped some load immediate instructions. Undo the skipping
4263 if the load immediate was not followed by a stack adjustment. */
4264 if (load_immediate_bytes
&& !seen_sp_adjust
)
4265 pc
-= load_immediate_bytes
;
4269 /* Skip the PC past function prologue instructions (16-bit version).
4270 This is a helper function for mips_skip_prologue. */
4273 mips16_skip_prologue (CORE_ADDR pc
)
4276 int extend_bytes
= 0;
4277 int prev_extend_bytes
;
4279 /* Table of instructions likely to be found in a function prologue. */
4282 unsigned short inst
;
4283 unsigned short mask
;
4290 , /* addiu $sp,offset */
4294 , /* daddiu $sp,offset */
4298 , /* sw reg,n($sp) */
4302 , /* sd reg,n($sp) */
4306 , /* sw $ra,n($sp) */
4310 , /* sd $ra,n($sp) */
4318 , /* sw $a0-$a3,n($s1) */
4322 , /* move reg,$a0-$a3 */
4326 , /* entry pseudo-op */
4330 , /* addiu $s1,$sp,n */
4333 } /* end of table marker */
4336 /* Skip the typical prologue instructions. These are the stack adjustment
4337 instruction and the instructions that save registers on the stack
4338 or in the gcc frame. */
4339 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4341 unsigned short inst
;
4344 inst
= mips_fetch_instruction (pc
);
4346 /* Normally we ignore an extend instruction. However, if it is
4347 not followed by a valid prologue instruction, we must adjust
4348 the pc back over the extend so that it won't be considered
4349 part of the prologue. */
4350 if ((inst
& 0xf800) == 0xf000) /* extend */
4352 extend_bytes
= MIPS16_INSTLEN
;
4355 prev_extend_bytes
= extend_bytes
;
4358 /* Check for other valid prologue instructions besides extend. */
4359 for (i
= 0; table
[i
].mask
!= 0; i
++)
4360 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4362 if (table
[i
].mask
!= 0) /* it was in table? */
4363 continue; /* ignore it */
4367 /* Return the current pc, adjusted backwards by 2 if
4368 the previous instruction was an extend. */
4369 return pc
- prev_extend_bytes
;
4375 /* To skip prologues, I use this predicate. Returns either PC itself
4376 if the code at PC does not look like a function prologue; otherwise
4377 returns an address that (if we're lucky) follows the prologue. If
4378 LENIENT, then we must skip everything which is involved in setting
4379 up the frame (it's OK to skip more, just so long as we don't skip
4380 anything which might clobber the registers which are being saved.
4381 We must skip more in the case where part of the prologue is in the
4382 delay slot of a non-prologue instruction). */
4385 mips_skip_prologue (CORE_ADDR pc
)
4387 /* See if we can determine the end of the prologue via the symbol table.
4388 If so, then return either PC, or the PC after the prologue, whichever
4391 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4393 if (post_prologue_pc
!= 0)
4394 return max (pc
, post_prologue_pc
);
4396 /* Can't determine prologue from the symbol table, need to examine
4399 if (pc_is_mips16 (pc
))
4400 return mips16_skip_prologue (pc
);
4402 return mips32_skip_prologue (pc
);
4405 /* Determine how a return value is stored within the MIPS register
4406 file, given the return type `valtype'. */
4408 struct return_value_word
4417 return_value_location (struct type
*valtype
,
4418 struct return_value_word
*hi
,
4419 struct return_value_word
*lo
)
4421 int len
= TYPE_LENGTH (valtype
);
4423 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4424 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4425 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4427 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4429 /* We need to break a 64bit float in two 32 bit halves and
4430 spread them across a floating-point register pair. */
4431 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4432 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4433 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4434 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4436 hi
->reg_offset
= lo
->reg_offset
;
4437 lo
->reg
= FP0_REGNUM
+ 0;
4438 hi
->reg
= FP0_REGNUM
+ 1;
4444 /* The floating point value fits in a single floating-point
4446 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4447 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4450 lo
->reg
= FP0_REGNUM
;
4461 /* Locate a result possibly spread across two registers. */
4463 lo
->reg
= regnum
+ 0;
4464 hi
->reg
= regnum
+ 1;
4465 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4466 && len
< MIPS_SAVED_REGSIZE
)
4468 /* "un-left-justify" the value in the low register */
4469 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4474 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4475 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4476 && len
< MIPS_SAVED_REGSIZE
* 2
4477 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4478 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4480 /* "un-left-justify" the value spread across two registers. */
4481 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4482 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4484 hi
->len
= len
- lo
->len
;
4488 /* Only perform a partial copy of the second register. */
4491 if (len
> MIPS_SAVED_REGSIZE
)
4493 lo
->len
= MIPS_SAVED_REGSIZE
;
4494 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4502 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4503 && REGISTER_RAW_SIZE (regnum
) == 8
4504 && MIPS_SAVED_REGSIZE
== 4)
4506 /* Account for the fact that only the least-signficant part
4507 of the register is being used */
4508 lo
->reg_offset
+= 4;
4509 hi
->reg_offset
+= 4;
4512 hi
->buf_offset
= lo
->len
;
4516 /* Given a return value in `regbuf' with a type `valtype', extract and
4517 copy its value into `valbuf'. */
4520 mips_eabi_extract_return_value (struct type
*valtype
,
4521 char regbuf
[REGISTER_BYTES
],
4524 struct return_value_word lo
;
4525 struct return_value_word hi
;
4526 return_value_location (valtype
, &hi
, &lo
);
4528 memcpy (valbuf
+ lo
.buf_offset
,
4529 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4533 memcpy (valbuf
+ hi
.buf_offset
,
4534 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4539 mips_o64_extract_return_value (struct type
*valtype
,
4540 char regbuf
[REGISTER_BYTES
],
4543 struct return_value_word lo
;
4544 struct return_value_word hi
;
4545 return_value_location (valtype
, &hi
, &lo
);
4547 memcpy (valbuf
+ lo
.buf_offset
,
4548 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4552 memcpy (valbuf
+ hi
.buf_offset
,
4553 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4557 /* Given a return value in `valbuf' with a type `valtype', write it's
4558 value into the appropriate register. */
4561 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4563 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4564 struct return_value_word lo
;
4565 struct return_value_word hi
;
4566 return_value_location (valtype
, &hi
, &lo
);
4568 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4569 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4570 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4572 REGISTER_RAW_SIZE (lo
.reg
));
4576 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4577 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4578 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4580 REGISTER_RAW_SIZE (hi
.reg
));
4585 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4587 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4588 struct return_value_word lo
;
4589 struct return_value_word hi
;
4590 return_value_location (valtype
, &hi
, &lo
);
4592 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4593 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4594 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4596 REGISTER_RAW_SIZE (lo
.reg
));
4600 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4601 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4602 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4604 REGISTER_RAW_SIZE (hi
.reg
));
4608 /* O32 ABI stuff. */
4611 mips_o32_xfer_return_value (struct type
*type
,
4612 struct regcache
*regcache
,
4613 bfd_byte
*in
, const bfd_byte
*out
)
4615 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4616 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4617 && TYPE_LENGTH (type
) == 4
4618 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4620 /* A single-precision floating-point value. It fits in the
4621 least significant part of FP0. */
4623 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4624 mips_xfer_register (regcache
, FP0_REGNUM
, TYPE_LENGTH (type
),
4625 TARGET_BYTE_ORDER
, in
, out
, 0);
4627 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4628 && TYPE_LENGTH (type
) == 8
4629 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4631 /* A double-precision floating-point value. It fits in the
4632 least significant part of FP0/FP1 but with byte ordering
4633 based on the target (???). */
4635 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0/$fp1\n");
4636 switch (TARGET_BYTE_ORDER
)
4638 case BFD_ENDIAN_LITTLE
:
4639 mips_xfer_register (regcache
, FP0_REGNUM
+ 0, 4,
4640 TARGET_BYTE_ORDER
, in
, out
, 0);
4641 mips_xfer_register (regcache
, FP0_REGNUM
+ 1, 4,
4642 TARGET_BYTE_ORDER
, in
, out
, 4);
4644 case BFD_ENDIAN_BIG
:
4645 mips_xfer_register (regcache
, FP0_REGNUM
+ 1, 4,
4646 TARGET_BYTE_ORDER
, in
, out
, 0);
4647 mips_xfer_register (regcache
, FP0_REGNUM
+ 0, 4,
4648 TARGET_BYTE_ORDER
, in
, out
, 4);
4651 internal_error (__FILE__
, __LINE__
, "bad switch");
4655 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4656 && TYPE_NFIELDS (type
) <= 2
4657 && TYPE_NFIELDS (type
) >= 1
4658 && ((TYPE_NFIELDS (type
) == 1
4659 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4661 || (TYPE_NFIELDS (type
) == 2
4662 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4664 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4666 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4668 /* A struct that contains one or two floats. Each value is part
4669 in the least significant part of their floating point
4671 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
4674 for (field
= 0, regnum
= FP0_REGNUM
;
4675 field
< TYPE_NFIELDS (type
);
4676 field
++, regnum
+= 2)
4678 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4681 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4682 mips_xfer_register (regcache
, regnum
, TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4683 TARGET_BYTE_ORDER
, in
, out
, offset
);
4688 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4689 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4691 /* A structure or union. Extract the left justified value,
4692 regardless of the byte order. I.e. DO NOT USE
4696 for (offset
= 0, regnum
= V0_REGNUM
;
4697 offset
< TYPE_LENGTH (type
);
4698 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4700 int xfer
= REGISTER_RAW_SIZE (regnum
);
4701 if (offset
+ xfer
> TYPE_LENGTH (type
))
4702 xfer
= TYPE_LENGTH (type
) - offset
;
4704 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4705 offset
, xfer
, regnum
);
4706 mips_xfer_register (regcache
, regnum
, xfer
, BFD_ENDIAN_UNKNOWN
,
4713 /* A scalar extract each part but least-significant-byte
4714 justified. o32 thinks registers are 4 byte, regardless of
4715 the ISA. mips_stack_argsize controls this. */
4718 for (offset
= 0, regnum
= V0_REGNUM
;
4719 offset
< TYPE_LENGTH (type
);
4720 offset
+= mips_stack_argsize (), regnum
++)
4722 int xfer
= mips_stack_argsize ();
4724 if (offset
+ xfer
> TYPE_LENGTH (type
))
4725 xfer
= TYPE_LENGTH (type
) - offset
;
4727 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4728 offset
, xfer
, regnum
);
4729 mips_xfer_register (regcache
, regnum
, xfer
, TARGET_BYTE_ORDER
,
4736 mips_o32_extract_return_value (struct type
*type
,
4737 struct regcache
*regcache
,
4740 mips_o32_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4744 mips_o32_store_return_value (struct type
*type
, char *valbuf
)
4746 mips_o32_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4749 /* N32/N44 ABI stuff. */
4752 mips_n32n64_xfer_return_value (struct type
*type
,
4753 struct regcache
*regcache
,
4754 bfd_byte
*in
, const bfd_byte
*out
)
4756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4757 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4758 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4760 /* A floating-point value belongs in the least significant part
4763 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4764 mips_xfer_register (regcache
, FP0_REGNUM
, TYPE_LENGTH (type
),
4765 TARGET_BYTE_ORDER
, in
, out
, 0);
4767 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4768 && TYPE_NFIELDS (type
) <= 2
4769 && TYPE_NFIELDS (type
) >= 1
4770 && ((TYPE_NFIELDS (type
) == 1
4771 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4773 || (TYPE_NFIELDS (type
) == 2
4774 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4776 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4778 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4780 /* A struct that contains one or two floats. Each value is part
4781 in the least significant part of their floating point
4783 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
4786 for (field
= 0, regnum
= FP0_REGNUM
;
4787 field
< TYPE_NFIELDS (type
);
4788 field
++, regnum
+= 2)
4790 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4793 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4794 mips_xfer_register (regcache
, regnum
, TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4795 TARGET_BYTE_ORDER
, in
, out
, offset
);
4798 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4799 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4801 /* A structure or union. Extract the left justified value,
4802 regardless of the byte order. I.e. DO NOT USE
4806 for (offset
= 0, regnum
= V0_REGNUM
;
4807 offset
< TYPE_LENGTH (type
);
4808 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4810 int xfer
= REGISTER_RAW_SIZE (regnum
);
4811 if (offset
+ xfer
> TYPE_LENGTH (type
))
4812 xfer
= TYPE_LENGTH (type
) - offset
;
4814 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4815 offset
, xfer
, regnum
);
4816 mips_xfer_register (regcache
, regnum
, xfer
, BFD_ENDIAN_UNKNOWN
,
4822 /* A scalar extract each part but least-significant-byte
4826 for (offset
= 0, regnum
= V0_REGNUM
;
4827 offset
< TYPE_LENGTH (type
);
4828 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4830 int xfer
= REGISTER_RAW_SIZE (regnum
);
4832 if (offset
+ xfer
> TYPE_LENGTH (type
))
4833 xfer
= TYPE_LENGTH (type
) - offset
;
4835 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4836 offset
, xfer
, regnum
);
4837 mips_xfer_register (regcache
, regnum
, xfer
, TARGET_BYTE_ORDER
,
4844 mips_n32n64_extract_return_value (struct type
*type
,
4845 struct regcache
*regcache
,
4848 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4852 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
4854 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4858 mips_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
4860 /* Nothing to do -- push_arguments does all the work. */
4864 mips_extract_struct_value_address (struct regcache
*ignore
)
4866 /* FIXME: This will only work at random. The caller passes the
4867 struct_return address in V0, but it is not preserved. It may
4868 still be there, or this may be a random value. */
4869 return read_register (V0_REGNUM
);
4872 /* Exported procedure: Is PC in the signal trampoline code */
4875 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4877 if (sigtramp_address
== 0)
4879 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4882 /* Root of all "set mips "/"show mips " commands. This will eventually be
4883 used for all MIPS-specific commands. */
4886 show_mips_command (char *args
, int from_tty
)
4888 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4892 set_mips_command (char *args
, int from_tty
)
4894 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4895 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4898 /* Commands to show/set the MIPS FPU type. */
4901 show_mipsfpu_command (char *args
, int from_tty
)
4904 switch (MIPS_FPU_TYPE
)
4906 case MIPS_FPU_SINGLE
:
4907 fpu
= "single-precision";
4909 case MIPS_FPU_DOUBLE
:
4910 fpu
= "double-precision";
4913 fpu
= "absent (none)";
4916 internal_error (__FILE__
, __LINE__
, "bad switch");
4918 if (mips_fpu_type_auto
)
4919 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4922 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4928 set_mipsfpu_command (char *args
, int from_tty
)
4930 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4931 show_mipsfpu_command (args
, from_tty
);
4935 set_mipsfpu_single_command (char *args
, int from_tty
)
4937 mips_fpu_type
= MIPS_FPU_SINGLE
;
4938 mips_fpu_type_auto
= 0;
4939 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
4943 set_mipsfpu_double_command (char *args
, int from_tty
)
4945 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4946 mips_fpu_type_auto
= 0;
4947 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4951 set_mipsfpu_none_command (char *args
, int from_tty
)
4953 mips_fpu_type
= MIPS_FPU_NONE
;
4954 mips_fpu_type_auto
= 0;
4955 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
4959 set_mipsfpu_auto_command (char *args
, int from_tty
)
4961 mips_fpu_type_auto
= 1;
4964 /* Command to set the processor type. */
4967 mips_set_processor_type_command (char *args
, int from_tty
)
4971 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
4973 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
4974 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
4975 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
4977 /* Restore the value. */
4978 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
4983 if (!mips_set_processor_type (tmp_mips_processor_type
))
4985 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
4986 /* Restore its value. */
4987 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
4992 mips_show_processor_type_command (char *args
, int from_tty
)
4996 /* Modify the actual processor type. */
4999 mips_set_processor_type (char *str
)
5006 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5008 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
5010 mips_processor_type
= str
;
5011 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
5013 /* FIXME tweak fpu flag too */
5020 /* Attempt to identify the particular processor model by reading the
5024 mips_read_processor_type (void)
5028 prid
= read_register (PRID_REGNUM
);
5030 if ((prid
& ~0xf) == 0x700)
5031 return savestring ("r3041", strlen ("r3041"));
5036 /* Just like reinit_frame_cache, but with the right arguments to be
5037 callable as an sfunc. */
5040 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5041 struct cmd_list_element
*c
)
5043 reinit_frame_cache ();
5047 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
5049 mips_extra_func_info_t proc_desc
;
5051 /* Search for the function containing this address. Set the low bit
5052 of the address when searching, in case we were given an even address
5053 that is the start of a 16-bit function. If we didn't do this,
5054 the search would fail because the symbol table says the function
5055 starts at an odd address, i.e. 1 byte past the given address. */
5056 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5057 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
5059 /* Make an attempt to determine if this is a 16-bit function. If
5060 the procedure descriptor exists and the address therein is odd,
5061 it's definitely a 16-bit function. Otherwise, we have to just
5062 guess that if the address passed in is odd, it's 16-bits. */
5064 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
5065 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
5067 info
->mach
= pc_is_mips16 (memaddr
) ?
5068 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
5070 /* Round down the instruction address to the appropriate boundary. */
5071 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5073 /* Call the appropriate disassembler based on the target endian-ness. */
5074 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5075 return print_insn_big_mips (memaddr
, info
);
5077 return print_insn_little_mips (memaddr
, info
);
5080 /* Old-style breakpoint macros.
5081 The IDT board uses an unusual breakpoint value, and sometimes gets
5082 confused when it sees the usual MIPS breakpoint instruction. */
5084 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
5085 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
5086 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
5087 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
5088 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
5089 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
5090 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
5091 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
5093 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5094 counter value to determine whether a 16- or 32-bit breakpoint should be
5095 used. It returns a pointer to a string of bytes that encode a breakpoint
5096 instruction, stores the length of the string to *lenptr, and adjusts pc
5097 (if necessary) to point to the actual memory location where the
5098 breakpoint should be inserted. */
5100 const unsigned char *
5101 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5103 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5105 if (pc_is_mips16 (*pcptr
))
5107 static unsigned char mips16_big_breakpoint
[] =
5108 MIPS16_BIG_BREAKPOINT
;
5109 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
5110 *lenptr
= sizeof (mips16_big_breakpoint
);
5111 return mips16_big_breakpoint
;
5115 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
5116 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
5117 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
5119 *lenptr
= sizeof (big_breakpoint
);
5121 if (strcmp (target_shortname
, "mips") == 0)
5122 return idt_big_breakpoint
;
5123 else if (strcmp (target_shortname
, "ddb") == 0
5124 || strcmp (target_shortname
, "pmon") == 0
5125 || strcmp (target_shortname
, "lsi") == 0)
5126 return pmon_big_breakpoint
;
5128 return big_breakpoint
;
5133 if (pc_is_mips16 (*pcptr
))
5135 static unsigned char mips16_little_breakpoint
[] =
5136 MIPS16_LITTLE_BREAKPOINT
;
5137 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
5138 *lenptr
= sizeof (mips16_little_breakpoint
);
5139 return mips16_little_breakpoint
;
5143 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
5144 static unsigned char pmon_little_breakpoint
[] =
5145 PMON_LITTLE_BREAKPOINT
;
5146 static unsigned char idt_little_breakpoint
[] =
5147 IDT_LITTLE_BREAKPOINT
;
5149 *lenptr
= sizeof (little_breakpoint
);
5151 if (strcmp (target_shortname
, "mips") == 0)
5152 return idt_little_breakpoint
;
5153 else if (strcmp (target_shortname
, "ddb") == 0
5154 || strcmp (target_shortname
, "pmon") == 0
5155 || strcmp (target_shortname
, "lsi") == 0)
5156 return pmon_little_breakpoint
;
5158 return little_breakpoint
;
5163 /* If PC is in a mips16 call or return stub, return the address of the target
5164 PC, which is either the callee or the caller. There are several
5165 cases which must be handled:
5167 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5168 target PC is in $31 ($ra).
5169 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5170 and the target PC is in $2.
5171 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5172 before the jal instruction, this is effectively a call stub
5173 and the the target PC is in $2. Otherwise this is effectively
5174 a return stub and the target PC is in $18.
5176 See the source code for the stubs in gcc/config/mips/mips16.S for
5179 This function implements the SKIP_TRAMPOLINE_CODE macro.
5183 mips_skip_stub (CORE_ADDR pc
)
5186 CORE_ADDR start_addr
;
5188 /* Find the starting address and name of the function containing the PC. */
5189 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5192 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5193 target PC is in $31 ($ra). */
5194 if (strcmp (name
, "__mips16_ret_sf") == 0
5195 || strcmp (name
, "__mips16_ret_df") == 0)
5196 return read_signed_register (RA_REGNUM
);
5198 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5200 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5201 and the target PC is in $2. */
5202 if (name
[19] >= '0' && name
[19] <= '9')
5203 return read_signed_register (2);
5205 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5206 before the jal instruction, this is effectively a call stub
5207 and the the target PC is in $2. Otherwise this is effectively
5208 a return stub and the target PC is in $18. */
5209 else if (name
[19] == 's' || name
[19] == 'd')
5211 if (pc
== start_addr
)
5213 /* Check if the target of the stub is a compiler-generated
5214 stub. Such a stub for a function bar might have a name
5215 like __fn_stub_bar, and might look like this:
5220 la $1,bar (becomes a lui/addiu pair)
5222 So scan down to the lui/addi and extract the target
5223 address from those two instructions. */
5225 CORE_ADDR target_pc
= read_signed_register (2);
5229 /* See if the name of the target function is __fn_stub_*. */
5230 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5232 if (strncmp (name
, "__fn_stub_", 10) != 0
5233 && strcmp (name
, "etext") != 0
5234 && strcmp (name
, "_etext") != 0)
5237 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5238 The limit on the search is arbitrarily set to 20
5239 instructions. FIXME. */
5240 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5242 inst
= mips_fetch_instruction (target_pc
);
5243 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5244 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5245 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5246 return pc
| (inst
& 0xffff); /* low word */
5249 /* Couldn't find the lui/addui pair, so return stub address. */
5253 /* This is the 'return' part of a call stub. The return
5254 address is in $r18. */
5255 return read_signed_register (18);
5258 return 0; /* not a stub */
5262 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5263 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5266 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5268 CORE_ADDR start_addr
;
5270 /* Find the starting address of the function containing the PC. If the
5271 caller didn't give us a name, look it up at the same time. */
5272 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5275 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5277 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5278 if (name
[19] >= '0' && name
[19] <= '9')
5280 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5281 before the jal instruction, this is effectively a call stub. */
5282 else if (name
[19] == 's' || name
[19] == 'd')
5283 return pc
== start_addr
;
5286 return 0; /* not a stub */
5290 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5291 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5294 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5296 CORE_ADDR start_addr
;
5298 /* Find the starting address of the function containing the PC. */
5299 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5302 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5303 if (strcmp (name
, "__mips16_ret_sf") == 0
5304 || strcmp (name
, "__mips16_ret_df") == 0)
5307 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5308 i.e. after the jal instruction, this is effectively a return stub. */
5309 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5310 && (name
[19] == 's' || name
[19] == 'd')
5311 && pc
!= start_addr
)
5314 return 0; /* not a stub */
5318 /* Return non-zero if the PC is in a library helper function that should
5319 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5322 mips_ignore_helper (CORE_ADDR pc
)
5326 /* Find the starting address and name of the function containing the PC. */
5327 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5330 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5331 that we want to ignore. */
5332 return (strcmp (name
, "__mips16_ret_sf") == 0
5333 || strcmp (name
, "__mips16_ret_df") == 0);
5337 /* Return a location where we can set a breakpoint that will be hit
5338 when an inferior function call returns. This is normally the
5339 program's entry point. Executables that don't have an entry
5340 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5341 whose address is the location where the breakpoint should be placed. */
5344 mips_call_dummy_address (void)
5346 struct minimal_symbol
*sym
;
5348 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
5350 return SYMBOL_VALUE_ADDRESS (sym
);
5352 return entry_point_address ();
5356 /* If the current gcc for this target does not produce correct debugging
5357 information for float parameters, both prototyped and unprototyped, then
5358 define this macro. This forces gdb to always assume that floats are
5359 passed as doubles and then converted in the callee.
5361 For the mips chip, it appears that the debug info marks the parameters as
5362 floats regardless of whether the function is prototyped, but the actual
5363 values are passed as doubles for the non-prototyped case and floats for
5364 the prototyped case. Thus we choose to make the non-prototyped case work
5365 for C and break the prototyped case, since the non-prototyped case is
5366 probably much more common. (FIXME). */
5369 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
5371 return current_language
->la_language
== language_c
;
5374 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5375 the register stored on the stack (32) is different to its real raw
5376 size (64). The below ensures that registers are fetched from the
5377 stack using their ABI size and then stored into the RAW_BUFFER
5378 using their raw size.
5380 The alternative to adding this function would be to add an ABI
5381 macro - REGISTER_STACK_SIZE(). */
5384 mips_get_saved_register (char *raw_buffer
,
5387 struct frame_info
*frame
,
5389 enum lval_type
*lval
)
5393 if (!target_has_registers
)
5394 error ("No registers.");
5396 /* Normal systems don't optimize out things with register numbers. */
5397 if (optimized
!= NULL
)
5399 addr
= find_saved_register (frame
, regnum
);
5403 *lval
= lval_memory
;
5404 if (regnum
== SP_REGNUM
)
5406 if (raw_buffer
!= NULL
)
5408 /* Put it back in target format. */
5409 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
5416 if (raw_buffer
!= NULL
)
5420 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5422 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
5424 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
5425 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
5431 *lval
= lval_register
;
5432 addr
= REGISTER_BYTE (regnum
);
5433 if (raw_buffer
!= NULL
)
5434 read_register_gen (regnum
, raw_buffer
);
5440 /* Immediately after a function call, return the saved pc.
5441 Can't always go through the frames for this because on some machines
5442 the new frame is not set up until the new function executes
5443 some instructions. */
5446 mips_saved_pc_after_call (struct frame_info
*frame
)
5448 return read_signed_register (RA_REGNUM
);
5452 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5456 mips_stab_reg_to_regnum (int num
)
5461 return num
+ FP0_REGNUM
- 38;
5464 /* Convert a ecoff register number to a gdb REGNUM */
5467 mips_ecoff_reg_to_regnum (int num
)
5472 return num
+ FP0_REGNUM
- 32;
5475 /* Convert an integer into an address. By first converting the value
5476 into a pointer and then extracting it signed, the address is
5477 guarenteed to be correctly sign extended. */
5480 mips_integer_to_address (struct type
*type
, void *buf
)
5482 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5483 LONGEST val
= unpack_long (type
, buf
);
5484 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5485 return extract_signed_integer (tmp
,
5486 TYPE_LENGTH (builtin_type_void_data_ptr
));
5490 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5492 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5493 const char *name
= bfd_get_section_name (abfd
, sect
);
5495 if (*abip
!= MIPS_ABI_UNKNOWN
)
5498 if (strncmp (name
, ".mdebug.", 8) != 0)
5501 if (strcmp (name
, ".mdebug.abi32") == 0)
5502 *abip
= MIPS_ABI_O32
;
5503 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5504 *abip
= MIPS_ABI_N32
;
5505 else if (strcmp (name
, ".mdebug.abiN64") == 0)
5506 *abip
= MIPS_ABI_N64
;
5507 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5508 *abip
= MIPS_ABI_O64
;
5509 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5510 *abip
= MIPS_ABI_EABI32
;
5511 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5512 *abip
= MIPS_ABI_EABI64
;
5514 warning ("unsupported ABI %s.", name
+ 8);
5517 static enum mips_abi
5518 global_mips_abi (void)
5522 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5523 if (mips_abi_strings
[i
] == mips_abi_string
)
5524 return (enum mips_abi
) i
;
5526 internal_error (__FILE__
, __LINE__
,
5527 "unknown ABI string");
5530 static struct gdbarch
*
5531 mips_gdbarch_init (struct gdbarch_info info
,
5532 struct gdbarch_list
*arches
)
5534 static LONGEST mips_call_dummy_words
[] =
5536 struct gdbarch
*gdbarch
;
5537 struct gdbarch_tdep
*tdep
;
5539 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5540 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
5542 /* Reset the disassembly info, in case it was set to something
5544 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
5545 tm_print_insn_info
.arch
= bfd_arch_unknown
;
5546 tm_print_insn_info
.mach
= 0;
5552 /* First of all, extract the elf_flags, if available. */
5553 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5554 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5556 /* Try to determine the OS ABI of the object we are loading. If
5557 we end up with `unknown', just leave it that way. */
5558 osabi
= gdbarch_lookup_osabi (info
.abfd
);
5561 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5562 switch ((elf_flags
& EF_MIPS_ABI
))
5564 case E_MIPS_ABI_O32
:
5565 mips_abi
= MIPS_ABI_O32
;
5567 case E_MIPS_ABI_O64
:
5568 mips_abi
= MIPS_ABI_O64
;
5570 case E_MIPS_ABI_EABI32
:
5571 mips_abi
= MIPS_ABI_EABI32
;
5573 case E_MIPS_ABI_EABI64
:
5574 mips_abi
= MIPS_ABI_EABI64
;
5577 if ((elf_flags
& EF_MIPS_ABI2
))
5578 mips_abi
= MIPS_ABI_N32
;
5580 mips_abi
= MIPS_ABI_UNKNOWN
;
5584 /* GCC creates a pseudo-section whose name describes the ABI. */
5585 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5586 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5588 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5589 Use the ABI from the last architecture if there is one. */
5590 if (info
.abfd
== NULL
&& arches
!= NULL
)
5591 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5593 /* Try the architecture for any hint of the correct ABI. */
5594 if (mips_abi
== MIPS_ABI_UNKNOWN
5595 && info
.bfd_arch_info
!= NULL
5596 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5598 switch (info
.bfd_arch_info
->mach
)
5600 case bfd_mach_mips3900
:
5601 mips_abi
= MIPS_ABI_EABI32
;
5603 case bfd_mach_mips4100
:
5604 case bfd_mach_mips5000
:
5605 mips_abi
= MIPS_ABI_EABI64
;
5607 case bfd_mach_mips8000
:
5608 case bfd_mach_mips10000
:
5609 /* On Irix, ELF64 executables use the N64 ABI. The
5610 pseudo-sections which describe the ABI aren't present
5611 on IRIX. (Even for executables created by gcc.) */
5612 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5613 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5614 mips_abi
= MIPS_ABI_N64
;
5616 mips_abi
= MIPS_ABI_N32
;
5621 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5622 mips_abi
= MIPS_ABI_O32
;
5624 /* Now that we have found what the ABI for this binary would be,
5625 check whether the user is overriding it. */
5626 found_abi
= mips_abi
;
5627 wanted_abi
= global_mips_abi ();
5628 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5629 mips_abi
= wanted_abi
;
5633 fprintf_unfiltered (gdb_stdlog
,
5634 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5636 fprintf_unfiltered (gdb_stdlog
,
5637 "mips_gdbarch_init: mips_abi = %d\n",
5639 fprintf_unfiltered (gdb_stdlog
,
5640 "mips_gdbarch_init: found_mips_abi = %d\n",
5644 /* try to find a pre-existing architecture */
5645 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5647 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5649 /* MIPS needs to be pedantic about which ABI the object is
5651 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5653 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5655 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
5656 return arches
->gdbarch
;
5659 /* Need a new architecture. Fill in a target specific vector. */
5660 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5661 gdbarch
= gdbarch_alloc (&info
, tdep
);
5662 tdep
->elf_flags
= elf_flags
;
5663 tdep
->osabi
= osabi
;
5665 /* Initially set everything according to the default ABI/ISA. */
5666 set_gdbarch_short_bit (gdbarch
, 16);
5667 set_gdbarch_int_bit (gdbarch
, 32);
5668 set_gdbarch_float_bit (gdbarch
, 32);
5669 set_gdbarch_double_bit (gdbarch
, 64);
5670 set_gdbarch_long_double_bit (gdbarch
, 64);
5671 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
5672 set_gdbarch_max_register_raw_size (gdbarch
, 8);
5673 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
5674 tdep
->found_abi
= found_abi
;
5675 tdep
->mips_abi
= mips_abi
;
5680 set_gdbarch_push_arguments (gdbarch
, mips_o32_push_arguments
);
5681 set_gdbarch_store_return_value (gdbarch
, mips_o32_store_return_value
);
5682 set_gdbarch_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5683 tdep
->mips_default_saved_regsize
= 4;
5684 tdep
->mips_default_stack_argsize
= 4;
5685 tdep
->mips_fp_register_double
= 0;
5686 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5687 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5688 tdep
->gdb_target_is_mips64
= 0;
5689 tdep
->default_mask_address_p
= 0;
5690 set_gdbarch_long_bit (gdbarch
, 32);
5691 set_gdbarch_ptr_bit (gdbarch
, 32);
5692 set_gdbarch_long_long_bit (gdbarch
, 64);
5693 set_gdbarch_reg_struct_has_addr (gdbarch
,
5694 mips_o32_reg_struct_has_addr
);
5695 set_gdbarch_use_struct_convention (gdbarch
,
5696 mips_o32_use_struct_convention
);
5699 set_gdbarch_push_arguments (gdbarch
, mips_o64_push_arguments
);
5700 set_gdbarch_store_return_value (gdbarch
, mips_o64_store_return_value
);
5701 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5702 tdep
->mips_default_saved_regsize
= 8;
5703 tdep
->mips_default_stack_argsize
= 8;
5704 tdep
->mips_fp_register_double
= 1;
5705 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5706 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5707 tdep
->gdb_target_is_mips64
= 1;
5708 tdep
->default_mask_address_p
= 0;
5709 set_gdbarch_long_bit (gdbarch
, 32);
5710 set_gdbarch_ptr_bit (gdbarch
, 32);
5711 set_gdbarch_long_long_bit (gdbarch
, 64);
5712 set_gdbarch_reg_struct_has_addr (gdbarch
,
5713 mips_o32_reg_struct_has_addr
);
5714 set_gdbarch_use_struct_convention (gdbarch
,
5715 mips_o32_use_struct_convention
);
5717 case MIPS_ABI_EABI32
:
5718 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5719 set_gdbarch_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5720 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5721 tdep
->mips_default_saved_regsize
= 4;
5722 tdep
->mips_default_stack_argsize
= 4;
5723 tdep
->mips_fp_register_double
= 0;
5724 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5725 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5726 tdep
->gdb_target_is_mips64
= 0;
5727 tdep
->default_mask_address_p
= 0;
5728 set_gdbarch_long_bit (gdbarch
, 32);
5729 set_gdbarch_ptr_bit (gdbarch
, 32);
5730 set_gdbarch_long_long_bit (gdbarch
, 64);
5731 set_gdbarch_reg_struct_has_addr (gdbarch
,
5732 mips_eabi_reg_struct_has_addr
);
5733 set_gdbarch_use_struct_convention (gdbarch
,
5734 mips_eabi_use_struct_convention
);
5736 case MIPS_ABI_EABI64
:
5737 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5738 set_gdbarch_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5739 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5740 tdep
->mips_default_saved_regsize
= 8;
5741 tdep
->mips_default_stack_argsize
= 8;
5742 tdep
->mips_fp_register_double
= 1;
5743 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5744 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5745 tdep
->gdb_target_is_mips64
= 1;
5746 tdep
->default_mask_address_p
= 0;
5747 set_gdbarch_long_bit (gdbarch
, 64);
5748 set_gdbarch_ptr_bit (gdbarch
, 64);
5749 set_gdbarch_long_long_bit (gdbarch
, 64);
5750 set_gdbarch_reg_struct_has_addr (gdbarch
,
5751 mips_eabi_reg_struct_has_addr
);
5752 set_gdbarch_use_struct_convention (gdbarch
,
5753 mips_eabi_use_struct_convention
);
5756 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5757 set_gdbarch_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5758 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5759 tdep
->mips_default_saved_regsize
= 8;
5760 tdep
->mips_default_stack_argsize
= 8;
5761 tdep
->mips_fp_register_double
= 1;
5762 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5763 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5764 tdep
->gdb_target_is_mips64
= 1;
5765 tdep
->default_mask_address_p
= 0;
5766 set_gdbarch_long_bit (gdbarch
, 32);
5767 set_gdbarch_ptr_bit (gdbarch
, 32);
5768 set_gdbarch_long_long_bit (gdbarch
, 64);
5770 /* Set up the disassembler info, so that we get the right
5771 register names from libopcodes. */
5772 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5773 tm_print_insn_info
.arch
= bfd_arch_mips
;
5774 if (info
.bfd_arch_info
!= NULL
5775 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5776 && info
.bfd_arch_info
->mach
)
5777 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5779 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5781 set_gdbarch_use_struct_convention (gdbarch
,
5782 mips_n32n64_use_struct_convention
);
5783 set_gdbarch_reg_struct_has_addr (gdbarch
,
5784 mips_n32n64_reg_struct_has_addr
);
5787 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5788 set_gdbarch_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5789 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5790 tdep
->mips_default_saved_regsize
= 8;
5791 tdep
->mips_default_stack_argsize
= 8;
5792 tdep
->mips_fp_register_double
= 1;
5793 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5794 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5795 tdep
->gdb_target_is_mips64
= 1;
5796 tdep
->default_mask_address_p
= 0;
5797 set_gdbarch_long_bit (gdbarch
, 64);
5798 set_gdbarch_ptr_bit (gdbarch
, 64);
5799 set_gdbarch_long_long_bit (gdbarch
, 64);
5801 /* Set up the disassembler info, so that we get the right
5802 register names from libopcodes. */
5803 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5804 tm_print_insn_info
.arch
= bfd_arch_mips
;
5805 if (info
.bfd_arch_info
!= NULL
5806 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5807 && info
.bfd_arch_info
->mach
)
5808 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5810 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5812 set_gdbarch_use_struct_convention (gdbarch
,
5813 mips_n32n64_use_struct_convention
);
5814 set_gdbarch_reg_struct_has_addr (gdbarch
,
5815 mips_n32n64_reg_struct_has_addr
);
5818 internal_error (__FILE__
, __LINE__
,
5819 "unknown ABI in switch");
5822 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5823 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5826 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5827 flag in object files because to do so would make it impossible to
5828 link with libraries compiled without "-gp32". This is
5829 unnecessarily restrictive.
5831 We could solve this problem by adding "-gp32" multilibs to gcc,
5832 but to set this flag before gcc is built with such multilibs will
5833 break too many systems.''
5835 But even more unhelpfully, the default linker output target for
5836 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5837 for 64-bit programs - you need to change the ABI to change this,
5838 and not all gcc targets support that currently. Therefore using
5839 this flag to detect 32-bit mode would do the wrong thing given
5840 the current gcc - it would make GDB treat these 64-bit programs
5841 as 32-bit programs by default. */
5843 /* enable/disable the MIPS FPU */
5844 if (!mips_fpu_type_auto
)
5845 tdep
->mips_fpu_type
= mips_fpu_type
;
5846 else if (info
.bfd_arch_info
!= NULL
5847 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5848 switch (info
.bfd_arch_info
->mach
)
5850 case bfd_mach_mips3900
:
5851 case bfd_mach_mips4100
:
5852 case bfd_mach_mips4111
:
5853 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
5855 case bfd_mach_mips4650
:
5856 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
5859 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5863 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5865 /* MIPS version of register names. NOTE: At present the MIPS
5866 register name management is part way between the old -
5867 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5868 Further work on it is required. */
5869 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5870 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5871 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
5872 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
5873 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5874 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
5876 /* Add/remove bits from an address. The MIPS needs be careful to
5877 ensure that all 32 bit addresses are sign extended to 64 bits. */
5878 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5880 /* There's a mess in stack frame creation. See comments in
5881 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5882 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
5883 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
5885 /* Map debug register numbers onto internal register numbers. */
5886 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5887 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
5889 /* Initialize a frame */
5890 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
5891 set_gdbarch_frame_init_saved_regs (gdbarch
, mips_frame_init_saved_regs
);
5893 /* MIPS version of CALL_DUMMY */
5895 set_gdbarch_call_dummy_p (gdbarch
, 1);
5896 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
5897 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
5898 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
5899 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
5900 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
5901 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
5902 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
5903 set_gdbarch_call_dummy_length (gdbarch
, 0);
5904 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
5905 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
5906 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
5907 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
5908 set_gdbarch_register_convertible (gdbarch
, mips_register_convertible
);
5909 set_gdbarch_register_convert_to_virtual (gdbarch
,
5910 mips_register_convert_to_virtual
);
5911 set_gdbarch_register_convert_to_raw (gdbarch
,
5912 mips_register_convert_to_raw
);
5914 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
5916 set_gdbarch_frame_chain (gdbarch
, mips_frame_chain
);
5917 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
5918 set_gdbarch_frameless_function_invocation (gdbarch
,
5919 generic_frameless_function_invocation_not
);
5920 set_gdbarch_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
5921 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
5922 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
5923 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
5924 set_gdbarch_frame_args_skip (gdbarch
, 0);
5926 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
5928 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5929 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5930 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
5932 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5933 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
5935 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5936 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5937 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5939 set_gdbarch_function_start_offset (gdbarch
, 0);
5941 /* There are MIPS targets which do not yet use this since they still
5942 define REGISTER_VIRTUAL_TYPE. */
5943 set_gdbarch_register_virtual_type (gdbarch
, mips_register_virtual_type
);
5944 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
5946 set_gdbarch_do_registers_info (gdbarch
, mips_do_registers_info
);
5947 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5949 /* Hook in OS ABI-specific overrides, if they have been registered. */
5950 gdbarch_init_osabi (info
, gdbarch
, osabi
);
5952 set_gdbarch_store_struct_return (gdbarch
, mips_store_struct_return
);
5953 set_gdbarch_extract_struct_value_address (gdbarch
,
5954 mips_extract_struct_value_address
);
5959 mips_abi_update (char *ignore_args
, int from_tty
,
5960 struct cmd_list_element
*c
)
5962 struct gdbarch_info info
;
5964 /* Force the architecture to update, and (if it's a MIPS architecture)
5965 mips_gdbarch_init will take care of the rest. */
5966 gdbarch_info_init (&info
);
5967 gdbarch_update_p (info
);
5971 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5973 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5977 int ef_mips_32bitmode
;
5978 /* determine the ISA */
5979 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5997 /* determine the size of a pointer */
5998 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5999 fprintf_unfiltered (file
,
6000 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6002 fprintf_unfiltered (file
,
6003 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6005 fprintf_unfiltered (file
,
6006 "mips_dump_tdep: ef_mips_arch = %d\n",
6008 fprintf_unfiltered (file
,
6009 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6011 mips_abi_strings
[tdep
->mips_abi
]);
6012 fprintf_unfiltered (file
,
6013 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6014 mips_mask_address_p (),
6015 tdep
->default_mask_address_p
);
6017 fprintf_unfiltered (file
,
6018 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6019 FP_REGISTER_DOUBLE
);
6020 fprintf_unfiltered (file
,
6021 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6022 MIPS_DEFAULT_FPU_TYPE
,
6023 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6024 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6025 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6027 fprintf_unfiltered (file
,
6028 "mips_dump_tdep: MIPS_EABI = %d\n",
6030 fprintf_unfiltered (file
,
6031 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6032 MIPS_LAST_FP_ARG_REGNUM
,
6033 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
6034 fprintf_unfiltered (file
,
6035 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6037 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6038 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6039 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6041 fprintf_unfiltered (file
,
6042 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6043 MIPS_DEFAULT_SAVED_REGSIZE
);
6044 fprintf_unfiltered (file
,
6045 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6046 FP_REGISTER_DOUBLE
);
6047 fprintf_unfiltered (file
,
6048 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6049 MIPS_DEFAULT_STACK_ARGSIZE
);
6050 fprintf_unfiltered (file
,
6051 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6052 MIPS_STACK_ARGSIZE
);
6053 fprintf_unfiltered (file
,
6054 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6056 fprintf_unfiltered (file
,
6057 "mips_dump_tdep: A0_REGNUM = %d\n",
6059 fprintf_unfiltered (file
,
6060 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6061 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6062 fprintf_unfiltered (file
,
6063 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6064 XSTRING (ATTACH_DETACH
));
6065 fprintf_unfiltered (file
,
6066 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6068 fprintf_unfiltered (file
,
6069 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
6070 fprintf_unfiltered (file
,
6071 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6073 fprintf_unfiltered (file
,
6074 "mips_dump_tdep: CPLUS_MARKER = %c\n",
6076 fprintf_unfiltered (file
,
6077 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
6079 fprintf_unfiltered (file
,
6080 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
6081 XSTRING (DO_REGISTERS_INFO
));
6082 fprintf_unfiltered (file
,
6083 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6084 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6085 fprintf_unfiltered (file
,
6086 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6087 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6088 fprintf_unfiltered (file
,
6089 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
6090 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
6091 fprintf_unfiltered (file
,
6092 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6094 fprintf_unfiltered (file
,
6095 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6097 fprintf_unfiltered (file
,
6098 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6099 FIRST_EMBED_REGNUM
);
6100 fprintf_unfiltered (file
,
6101 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6103 fprintf_unfiltered (file
,
6104 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6105 GDB_TARGET_IS_MIPS64
);
6106 fprintf_unfiltered (file
,
6107 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
6108 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
6109 fprintf_unfiltered (file
,
6110 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
6111 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
6112 fprintf_unfiltered (file
,
6113 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
6115 fprintf_unfiltered (file
,
6116 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6117 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
6118 fprintf_unfiltered (file
,
6119 "mips_dump_tdep: HI_REGNUM = %d\n",
6121 fprintf_unfiltered (file
,
6122 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
6123 fprintf_unfiltered (file
,
6124 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
6125 fprintf_unfiltered (file
,
6126 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6127 XSTRING (IGNORE_HELPER_CALL (PC
)));
6128 fprintf_unfiltered (file
,
6129 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6130 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6131 fprintf_unfiltered (file
,
6132 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6133 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6134 fprintf_unfiltered (file
,
6135 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
6136 fprintf_unfiltered (file
,
6137 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6139 fprintf_unfiltered (file
,
6140 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
6141 fprintf_unfiltered (file
,
6142 "mips_dump_tdep: LO_REGNUM = %d\n",
6144 #ifdef MACHINE_CPROC_FP_OFFSET
6145 fprintf_unfiltered (file
,
6146 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6147 MACHINE_CPROC_FP_OFFSET
);
6149 #ifdef MACHINE_CPROC_PC_OFFSET
6150 fprintf_unfiltered (file
,
6151 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6152 MACHINE_CPROC_PC_OFFSET
);
6154 #ifdef MACHINE_CPROC_SP_OFFSET
6155 fprintf_unfiltered (file
,
6156 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6157 MACHINE_CPROC_SP_OFFSET
);
6159 fprintf_unfiltered (file
,
6160 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
6161 fprintf_unfiltered (file
,
6162 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
6163 fprintf_unfiltered (file
,
6164 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6166 fprintf_unfiltered (file
,
6167 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
6168 fprintf_unfiltered (file
,
6169 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6170 fprintf_unfiltered (file
,
6171 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6172 fprintf_unfiltered (file
,
6173 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6175 fprintf_unfiltered (file
,
6176 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6177 MIPS_LAST_ARG_REGNUM
,
6178 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6179 fprintf_unfiltered (file
,
6180 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6182 fprintf_unfiltered (file
,
6183 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6184 fprintf_unfiltered (file
,
6185 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6186 MIPS_SAVED_REGSIZE
);
6187 fprintf_unfiltered (file
,
6188 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
6191 XSTRING (MSYMBOL_SIZE (MSYM
)));
6192 fprintf_unfiltered (file
,
6193 "mips_dump_tdep: OP_LDFPR = used?\n");
6194 fprintf_unfiltered (file
,
6195 "mips_dump_tdep: OP_LDGPR = used?\n");
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
6200 fprintf_unfiltered (file
,
6201 "mips_dump_tdep: PRID_REGNUM = %d\n",
6203 fprintf_unfiltered (file
,
6204 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6205 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
6206 fprintf_unfiltered (file
,
6207 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6208 fprintf_unfiltered (file
,
6209 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6212 fprintf_unfiltered (file
,
6213 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6214 fprintf_unfiltered (file
,
6215 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6218 fprintf_unfiltered (file
,
6219 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6220 fprintf_unfiltered (file
,
6221 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6222 fprintf_unfiltered (file
,
6223 "mips_dump_tdep: PROC_PC_REG = function?\n");
6224 fprintf_unfiltered (file
,
6225 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6226 fprintf_unfiltered (file
,
6227 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6228 fprintf_unfiltered (file
,
6229 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: PS_REGNUM = %d\n",
6233 fprintf_unfiltered (file
,
6234 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
6236 fprintf_unfiltered (file
,
6237 "mips_dump_tdep: RA_REGNUM = %d\n",
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6241 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6244 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
6245 fprintf_unfiltered (file
,
6246 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6247 fprintf_unfiltered (file
,
6248 "mips_dump_tdep: ROUND_DOWN = function?\n");
6249 fprintf_unfiltered (file
,
6250 "mips_dump_tdep: ROUND_UP = function?\n");
6252 fprintf_unfiltered (file
,
6253 "mips_dump_tdep: SAVED_BYTES = %d\n",
6257 fprintf_unfiltered (file
,
6258 "mips_dump_tdep: SAVED_FP = %d\n",
6262 fprintf_unfiltered (file
,
6263 "mips_dump_tdep: SAVED_PC = %d\n",
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6268 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6271 fprintf_unfiltered (file
,
6272 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6276 SIGFRAME_FPREGSAVE_OFF
);
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6282 SIGFRAME_REGSAVE_OFF
);
6283 fprintf_unfiltered (file
,
6284 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6288 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6291 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6292 fprintf_unfiltered (file
,
6293 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6294 SOFTWARE_SINGLE_STEP_P ());
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6297 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6298 #ifdef STACK_END_ADDR
6299 fprintf_unfiltered (file
,
6300 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6303 fprintf_unfiltered (file
,
6304 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6305 XSTRING (STEP_SKIPS_DELAY (PC
)));
6306 fprintf_unfiltered (file
,
6307 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6308 STEP_SKIPS_DELAY_P
);
6309 fprintf_unfiltered (file
,
6310 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6311 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6312 fprintf_unfiltered (file
,
6313 "mips_dump_tdep: T9_REGNUM = %d\n",
6315 fprintf_unfiltered (file
,
6316 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6317 fprintf_unfiltered (file
,
6318 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6319 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6320 fprintf_unfiltered (file
,
6321 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6322 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6323 fprintf_unfiltered (file
,
6324 "mips_dump_tdep: TARGET_MIPS = used?\n");
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
6327 XSTRING (TM_PRINT_INSN_MACH
));
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6331 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6334 fprintf_unfiltered (file
,
6335 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6338 #ifdef TRACE_FLAVOR_SIZE
6339 fprintf_unfiltered (file
,
6340 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6344 fprintf_unfiltered (file
,
6345 "mips_dump_tdep: TRACE_SET # %s\n",
6346 XSTRING (TRACE_SET (X
,STATE
)));
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
6350 #ifdef UNUSED_REGNUM
6351 fprintf_unfiltered (file
,
6352 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: V0_REGNUM = %d\n",
6358 fprintf_unfiltered (file
,
6359 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6360 (long) VM_MIN_ADDRESS
);
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6366 fprintf_unfiltered (file
,
6367 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6369 fprintf_unfiltered (file
,
6370 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6373 fprintf_unfiltered (file
,
6374 "mips_dump_tdep: OS ABI = %s\n",
6375 gdbarch_osabi_name (tdep
->osabi
));
6379 _initialize_mips_tdep (void)
6381 static struct cmd_list_element
*mipsfpulist
= NULL
;
6382 struct cmd_list_element
*c
;
6384 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6385 if (MIPS_ABI_LAST
+ 1
6386 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6387 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6389 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6390 if (!tm_print_insn
) /* Someone may have already set it */
6391 tm_print_insn
= gdb_print_insn_mips
;
6393 /* Add root prefix command for all "set mips"/"show mips" commands */
6394 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6395 "Various MIPS specific commands.",
6396 &setmipscmdlist
, "set mips ", 0, &setlist
);
6398 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6399 "Various MIPS specific commands.",
6400 &showmipscmdlist
, "show mips ", 0, &showlist
);
6402 /* Allow the user to override the saved register size. */
6403 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6406 &mips_saved_regsize_string
, "\
6407 Set size of general purpose registers saved on the stack.\n\
6408 This option can be set to one of:\n\
6409 32 - Force GDB to treat saved GP registers as 32-bit\n\
6410 64 - Force GDB to treat saved GP registers as 64-bit\n\
6411 auto - Allow GDB to use the target's default setting or autodetect the\n\
6412 saved GP register size from information contained in the executable.\n\
6417 /* Allow the user to override the argument stack size. */
6418 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6421 &mips_stack_argsize_string
, "\
6422 Set the amount of stack space reserved for each argument.\n\
6423 This option can be set to one of:\n\
6424 32 - Force GDB to allocate 32-bit chunks per argument\n\
6425 64 - Force GDB to allocate 64-bit chunks per argument\n\
6426 auto - Allow GDB to determine the correct setting from the current\n\
6427 target and executable (default)",
6431 /* Allow the user to override the ABI. */
6432 c
= add_set_enum_cmd
6433 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6434 "Set the ABI used by this program.\n"
6435 "This option can be set to one of:\n"
6436 " auto - the default ABI associated with the current binary\n"
6444 add_show_from_set (c
, &showmipscmdlist
);
6445 set_cmd_sfunc (c
, mips_abi_update
);
6447 /* Let the user turn off floating point and set the fence post for
6448 heuristic_proc_start. */
6450 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6451 "Set use of MIPS floating-point coprocessor.",
6452 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6453 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6454 "Select single-precision MIPS floating-point coprocessor.",
6456 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6457 "Select double-precision MIPS floating-point coprocessor.",
6459 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6460 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6461 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6462 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6463 "Select no MIPS floating-point coprocessor.",
6465 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6466 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6467 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6468 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6469 "Select MIPS floating-point coprocessor automatically.",
6471 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6472 "Show current use of MIPS floating-point coprocessor target.",
6475 /* We really would like to have both "0" and "unlimited" work, but
6476 command.c doesn't deal with that. So make it a var_zinteger
6477 because the user can always use "999999" or some such for unlimited. */
6478 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6479 (char *) &heuristic_fence_post
,
6481 Set the distance searched for the start of a function.\n\
6482 If you are debugging a stripped executable, GDB needs to search through the\n\
6483 program for the start of a function. This command sets the distance of the\n\
6484 search. The only need to set it is when debugging a stripped executable.",
6486 /* We need to throw away the frame cache when we set this, since it
6487 might change our ability to get backtraces. */
6488 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6489 add_show_from_set (c
, &showlist
);
6491 /* Allow the user to control whether the upper bits of 64-bit
6492 addresses should be zeroed. */
6493 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6494 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6495 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6496 allow GDB to determine the correct value.\n", "\
6497 Show zeroing of upper 32 bits of 64-bit addresses.",
6498 NULL
, show_mask_address
,
6499 &setmipscmdlist
, &showmipscmdlist
);
6501 /* Allow the user to control the size of 32 bit registers within the
6502 raw remote packet. */
6503 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6506 (char *)&mips64_transfers_32bit_regs_p
, "\
6507 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6508 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6509 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6510 64 bits for others. Use \"off\" to disable compatibility mode",
6514 /* Debug this files internals. */
6515 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6516 &mips_debug
, "Set mips debugging.\n\
6517 When non-zero, mips specific debugging is enabled.", &setdebuglist
),