1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_regs_have_home_p
;
142 int mips_default_stack_argsize
;
143 int gdb_target_is_mips64
;
144 int default_mask_address_p
;
146 enum gdb_osabi osabi
;
149 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
150 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
152 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
154 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
156 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
158 /* Return the currently configured (or set) saved register size. */
160 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 static const char *mips_saved_regsize_string
= size_auto
;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string
== size_auto
)
170 return MIPS_DEFAULT_SAVED_REGSIZE
;
171 else if (mips_saved_regsize_string
== size_64
)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
178 compatiblity mode. A return value of 1 means that we have
179 physical 64-bit registers, but should treat them as 32-bit registers. */
182 mips2_fp_compat (void)
184 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
186 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
190 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
191 in all the places we deal with FP registers. PR gdb/413. */
192 /* Otherwise check the FR bit in the status register - it controls
193 the FP compatiblity mode. If it is clear we are in compatibility
195 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
202 /* Indicate that the ABI makes use of double-precision registers
203 provided by the FPU (rather than combining pairs of registers to
204 form double-precision values). Do not use "TARGET_IS_MIPS64" to
205 determine if the ABI is using double-precision registers. See also
207 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
209 /* Does the caller allocate a ``home'' for each register used in the
210 function call? The N32 ABI and MIPS_EABI do not, the others do. */
212 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
214 /* The amount of space reserved on the stack for registers. This is
215 different to MIPS_SAVED_REGSIZE as it determines the alignment of
216 data allocated after the registers have run out. */
218 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
220 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
222 static const char *mips_stack_argsize_string
= size_auto
;
225 mips_stack_argsize (void)
227 if (mips_stack_argsize_string
== size_auto
)
228 return MIPS_DEFAULT_STACK_ARGSIZE
;
229 else if (mips_stack_argsize_string
== size_64
)
231 else /* if (mips_stack_argsize_string == size_32) */
235 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
237 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
239 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
241 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
243 static void mips_print_register (int, int);
245 static mips_extra_func_info_t
246 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
248 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
250 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
252 int mips_set_processor_type (char *);
254 static void mips_show_processor_type_command (char *, int);
256 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
258 static mips_extra_func_info_t
259 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
261 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
262 mips_extra_func_info_t proc_desc
);
264 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
265 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
267 static struct type
*mips_float_register_type (void);
268 static struct type
*mips_double_register_type (void);
270 /* This value is the model of MIPS in use. It is derived from the value
271 of the PrID register. */
273 char *mips_processor_type
;
275 char *tmp_mips_processor_type
;
277 /* The list of available "set mips " and "show mips " commands */
279 static struct cmd_list_element
*setmipscmdlist
= NULL
;
280 static struct cmd_list_element
*showmipscmdlist
= NULL
;
282 /* A set of original names, to be used when restoring back to generic
283 registers from a specific set. */
285 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
286 char **mips_processor_reg_names
= mips_generic_reg_names
;
289 mips_register_name (int i
)
291 return mips_processor_reg_names
[i
];
294 /* Names of IDT R3041 registers. */
296 char *mips_r3041_reg_names
[] = {
297 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
298 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
300 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
301 "sr", "lo", "hi", "bad", "cause","pc",
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
306 "fsr", "fir", "fp", "",
307 "", "", "bus", "ccfg", "", "", "", "",
308 "", "", "port", "cmp", "", "", "epc", "prid",
311 /* Names of IDT R3051 registers. */
313 char *mips_r3051_reg_names
[] = {
314 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
315 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
316 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
317 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
318 "sr", "lo", "hi", "bad", "cause","pc",
319 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
320 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
321 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
322 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
323 "fsr", "fir", "fp", "",
324 "inx", "rand", "elo", "", "ctxt", "", "", "",
325 "", "", "ehi", "", "", "", "epc", "prid",
328 /* Names of IDT R3081 registers. */
330 char *mips_r3081_reg_names
[] = {
331 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
332 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
334 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
335 "sr", "lo", "hi", "bad", "cause","pc",
336 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
337 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
338 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
339 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
340 "fsr", "fir", "fp", "",
341 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
342 "", "", "ehi", "", "", "", "epc", "prid",
345 /* Names of LSI 33k registers. */
347 char *mips_lsi33k_reg_names
[] = {
348 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
349 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
350 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
351 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
352 "epc", "hi", "lo", "sr", "cause","badvaddr",
353 "dcic", "bpc", "bda", "", "", "", "", "",
354 "", "", "", "", "", "", "", "",
355 "", "", "", "", "", "", "", "",
356 "", "", "", "", "", "", "", "",
358 "", "", "", "", "", "", "", "",
359 "", "", "", "", "", "", "", "",
365 } mips_processor_type_table
[] = {
366 { "generic", mips_generic_reg_names
},
367 { "r3041", mips_r3041_reg_names
},
368 { "r3051", mips_r3051_reg_names
},
369 { "r3071", mips_r3081_reg_names
},
370 { "r3081", mips_r3081_reg_names
},
371 { "lsi33k", mips_lsi33k_reg_names
},
379 /* Table to translate MIPS16 register field to actual register number. */
380 static int mips16_to_32_reg
[8] =
381 {16, 17, 2, 3, 4, 5, 6, 7};
383 /* Heuristic_proc_start may hunt through the text section for a long
384 time across a 2400 baud serial line. Allows the user to limit this
387 static unsigned int heuristic_fence_post
= 0;
389 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
390 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
391 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
392 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
393 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
394 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
395 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
396 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
397 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
398 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
399 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
400 this will corrupt pdr.iline. Fortunately we don't use it. */
401 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
402 #define _PROC_MAGIC_ 0x0F0F0F0F
403 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
404 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
406 struct linked_proc_info
408 struct mips_extra_func_info info
;
409 struct linked_proc_info
*next
;
411 *linked_proc_desc_table
= NULL
;
414 mips_print_extra_frame_info (struct frame_info
*fi
)
418 && fi
->extra_info
->proc_desc
419 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
420 printf_filtered (" frame pointer is at %s+%s\n",
421 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
422 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
425 /* Number of bytes of storage in the actual machine representation for
426 register N. NOTE: This indirectly defines the register size
427 transfered by the GDB protocol. */
429 static int mips64_transfers_32bit_regs_p
= 0;
432 mips_register_raw_size (int reg_nr
)
434 if (mips64_transfers_32bit_regs_p
)
435 return REGISTER_VIRTUAL_SIZE (reg_nr
);
436 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
437 && FP_REGISTER_DOUBLE
)
438 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
445 /* Convert between RAW and VIRTUAL registers. The RAW register size
446 defines the remote-gdb packet. */
449 mips_register_convertible (int reg_nr
)
451 if (mips64_transfers_32bit_regs_p
)
454 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
458 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
459 char *raw_buf
, char *virt_buf
)
461 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
463 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
464 TYPE_LENGTH (virtual_type
));
468 TYPE_LENGTH (virtual_type
));
472 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
473 char *virt_buf
, char *raw_buf
)
475 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
476 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
477 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
479 TYPE_LENGTH (virtual_type
));
483 TYPE_LENGTH (virtual_type
));
486 /* Return the GDB type object for the "standard" data type
487 of data in register REG.
489 Note: kevinb/2002-08-01: The definition below should faithfully
490 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
491 definitions found in config/mips/tm-*.h. I'm concerned about
492 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
493 though. In some cases FP_REGNUM is in this range, and I doubt
494 that this code is correct for the 64-bit case. */
497 mips_register_virtual_type (int reg
)
499 if (FP0_REGNUM
<= reg
&& reg
< FP0_REGNUM
+ 32)
501 /* Floating point registers... */
502 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
503 return builtin_type_ieee_double_big
;
505 return builtin_type_ieee_double_little
;
507 else if (reg
== PS_REGNUM
/* CR */)
508 return builtin_type_uint32
;
509 else if (FCRCS_REGNUM
<= reg
&& reg
<= LAST_EMBED_REGNUM
)
510 return builtin_type_uint32
;
513 /* Everything else...
514 Return type appropriate for width of register. */
515 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_uint64
))
516 return builtin_type_uint64
;
518 return builtin_type_uint32
;
522 /* Should the upper word of 64-bit addresses be zeroed? */
523 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
526 mips_mask_address_p (void)
528 switch (mask_address_var
)
530 case AUTO_BOOLEAN_TRUE
:
532 case AUTO_BOOLEAN_FALSE
:
535 case AUTO_BOOLEAN_AUTO
:
536 return MIPS_DEFAULT_MASK_ADDRESS_P
;
538 internal_error (__FILE__
, __LINE__
,
539 "mips_mask_address_p: bad switch");
545 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
547 switch (mask_address_var
)
549 case AUTO_BOOLEAN_TRUE
:
550 printf_filtered ("The 32 bit mips address mask is enabled\n");
552 case AUTO_BOOLEAN_FALSE
:
553 printf_filtered ("The 32 bit mips address mask is disabled\n");
555 case AUTO_BOOLEAN_AUTO
:
556 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
557 mips_mask_address_p () ? "enabled" : "disabled");
560 internal_error (__FILE__
, __LINE__
,
561 "show_mask_address: bad switch");
566 /* Should call_function allocate stack space for a struct return? */
569 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
571 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
575 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
577 return 1; /* Structures are returned by ref in extra arg0. */
581 mips_o32_use_struct_convention (int gcc_p
, struct type
*type
)
583 return 1; /* Structures are returned by ref in extra arg0. */
586 /* Should call_function pass struct by reference?
587 For each architecture, structs are passed either by
588 value or by reference, depending on their size. */
591 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
593 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
594 int len
= TYPE_LENGTH (check_typedef (type
));
596 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
597 return (len
> MIPS_SAVED_REGSIZE
);
603 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
605 return 0; /* Assumption: N32/N64 never passes struct by ref. */
609 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
611 return 0; /* Assumption: O32/O64 never passes struct by ref. */
614 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
617 pc_is_mips16 (bfd_vma memaddr
)
619 struct minimal_symbol
*sym
;
621 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
622 if (IS_MIPS16_ADDR (memaddr
))
625 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
626 the high bit of the info field. Use this to decide if the function is
627 MIPS16 or normal MIPS. */
628 sym
= lookup_minimal_symbol_by_pc (memaddr
);
630 return MSYMBOL_IS_SPECIAL (sym
);
635 /* MIPS believes that the PC has a sign extended value. Perhaphs the
636 all registers should be sign extended for simplicity? */
639 mips_read_pc (ptid_t ptid
)
641 return read_signed_register_pid (PC_REGNUM
, ptid
);
644 /* This returns the PC of the first inst after the prologue. If we can't
645 find the prologue, then return 0. */
648 after_prologue (CORE_ADDR pc
,
649 mips_extra_func_info_t proc_desc
)
651 struct symtab_and_line sal
;
652 CORE_ADDR func_addr
, func_end
;
654 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
655 to read the stack pointer from the current machine state, because
656 the current machine state has nothing to do with the information
657 we need from the proc_desc; and the process may or may not exist
660 proc_desc
= find_proc_desc (pc
, NULL
, 0);
664 /* If function is frameless, then we need to do it the hard way. I
665 strongly suspect that frameless always means prologueless... */
666 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
667 && PROC_FRAME_OFFSET (proc_desc
) == 0)
671 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
672 return 0; /* Unknown */
674 sal
= find_pc_line (func_addr
, 0);
676 if (sal
.end
< func_end
)
679 /* The line after the prologue is after the end of the function. In this
680 case, tell the caller to find the prologue the hard way. */
685 /* Decode a MIPS32 instruction that saves a register in the stack, and
686 set the appropriate bit in the general register mask or float register mask
687 to indicate which register is saved. This is a helper function
688 for mips_find_saved_regs. */
691 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
692 unsigned long *float_mask
)
696 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
697 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
698 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
700 /* It might be possible to use the instruction to
701 find the offset, rather than the code below which
702 is based on things being in a certain order in the
703 frame, but figuring out what the instruction's offset
704 is relative to might be a little tricky. */
705 reg
= (inst
& 0x001f0000) >> 16;
706 *gen_mask
|= (1 << reg
);
708 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
709 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
710 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
713 reg
= ((inst
& 0x001f0000) >> 16);
714 *float_mask
|= (1 << reg
);
718 /* Decode a MIPS16 instruction that saves a register in the stack, and
719 set the appropriate bit in the general register or float register mask
720 to indicate which register is saved. This is a helper function
721 for mips_find_saved_regs. */
724 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
726 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
728 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
729 *gen_mask
|= (1 << reg
);
731 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
733 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
734 *gen_mask
|= (1 << reg
);
736 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
737 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
738 *gen_mask
|= (1 << RA_REGNUM
);
742 /* Fetch and return instruction from the specified location. If the PC
743 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
746 mips_fetch_instruction (CORE_ADDR addr
)
748 char buf
[MIPS_INSTLEN
];
752 if (pc_is_mips16 (addr
))
754 instlen
= MIPS16_INSTLEN
;
755 addr
= UNMAKE_MIPS16_ADDR (addr
);
758 instlen
= MIPS_INSTLEN
;
759 status
= read_memory_nobpt (addr
, buf
, instlen
);
761 memory_error (status
, addr
);
762 return extract_unsigned_integer (buf
, instlen
);
766 /* These the fields of 32 bit mips instructions */
767 #define mips32_op(x) (x >> 26)
768 #define itype_op(x) (x >> 26)
769 #define itype_rs(x) ((x >> 21) & 0x1f)
770 #define itype_rt(x) ((x >> 16) & 0x1f)
771 #define itype_immediate(x) (x & 0xffff)
773 #define jtype_op(x) (x >> 26)
774 #define jtype_target(x) (x & 0x03ffffff)
776 #define rtype_op(x) (x >> 26)
777 #define rtype_rs(x) ((x >> 21) & 0x1f)
778 #define rtype_rt(x) ((x >> 16) & 0x1f)
779 #define rtype_rd(x) ((x >> 11) & 0x1f)
780 #define rtype_shamt(x) ((x >> 6) & 0x1f)
781 #define rtype_funct(x) (x & 0x3f)
784 mips32_relative_offset (unsigned long inst
)
787 x
= itype_immediate (inst
);
788 if (x
& 0x8000) /* sign bit set */
790 x
|= 0xffff0000; /* sign extension */
796 /* Determine whate to set a single step breakpoint while considering
799 mips32_next_pc (CORE_ADDR pc
)
803 inst
= mips_fetch_instruction (pc
);
804 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
806 if (itype_op (inst
) >> 2 == 5)
807 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
809 op
= (itype_op (inst
) & 0x03);
824 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
825 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
827 int tf
= itype_rt (inst
) & 0x01;
828 int cnum
= itype_rt (inst
) >> 2;
829 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
830 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
832 if (((cond
>> cnum
) & 0x01) == tf
)
833 pc
+= mips32_relative_offset (inst
) + 4;
838 pc
+= 4; /* Not a branch, next instruction is easy */
841 { /* This gets way messy */
843 /* Further subdivide into SPECIAL, REGIMM and other */
844 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
846 case 0: /* SPECIAL */
847 op
= rtype_funct (inst
);
852 /* Set PC to that address */
853 pc
= read_signed_register (rtype_rs (inst
));
859 break; /* end SPECIAL */
862 op
= itype_rt (inst
); /* branch condition */
867 case 16: /* BLTZAL */
868 case 18: /* BLTZALL */
870 if (read_signed_register (itype_rs (inst
)) < 0)
871 pc
+= mips32_relative_offset (inst
) + 4;
873 pc
+= 8; /* after the delay slot */
877 case 17: /* BGEZAL */
878 case 19: /* BGEZALL */
879 greater_equal_branch
:
880 if (read_signed_register (itype_rs (inst
)) >= 0)
881 pc
+= mips32_relative_offset (inst
) + 4;
883 pc
+= 8; /* after the delay slot */
885 /* All of the other instructions in the REGIMM category */
890 break; /* end REGIMM */
895 reg
= jtype_target (inst
) << 2;
896 /* Upper four bits get never changed... */
897 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
900 /* FIXME case JALX : */
903 reg
= jtype_target (inst
) << 2;
904 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
905 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
907 break; /* The new PC will be alternate mode */
908 case 4: /* BEQ, BEQL */
910 if (read_signed_register (itype_rs (inst
)) ==
911 read_signed_register (itype_rt (inst
)))
912 pc
+= mips32_relative_offset (inst
) + 4;
916 case 5: /* BNE, BNEL */
918 if (read_signed_register (itype_rs (inst
)) !=
919 read_signed_register (itype_rt (inst
)))
920 pc
+= mips32_relative_offset (inst
) + 4;
924 case 6: /* BLEZ, BLEZL */
926 if (read_signed_register (itype_rs (inst
) <= 0))
927 pc
+= mips32_relative_offset (inst
) + 4;
933 greater_branch
: /* BGTZ, BGTZL */
934 if (read_signed_register (itype_rs (inst
) > 0))
935 pc
+= mips32_relative_offset (inst
) + 4;
942 } /* mips32_next_pc */
944 /* Decoding the next place to set a breakpoint is irregular for the
945 mips 16 variant, but fortunately, there fewer instructions. We have to cope
946 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
947 We dont want to set a single step instruction on the extend instruction
951 /* Lots of mips16 instruction formats */
952 /* Predicting jumps requires itype,ritype,i8type
953 and their extensions extItype,extritype,extI8type
955 enum mips16_inst_fmts
957 itype
, /* 0 immediate 5,10 */
958 ritype
, /* 1 5,3,8 */
959 rrtype
, /* 2 5,3,3,5 */
960 rritype
, /* 3 5,3,3,5 */
961 rrrtype
, /* 4 5,3,3,3,2 */
962 rriatype
, /* 5 5,3,3,1,4 */
963 shifttype
, /* 6 5,3,3,3,2 */
964 i8type
, /* 7 5,3,8 */
965 i8movtype
, /* 8 5,3,3,5 */
966 i8mov32rtype
, /* 9 5,3,5,3 */
967 i64type
, /* 10 5,3,8 */
968 ri64type
, /* 11 5,3,3,5 */
969 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
970 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
971 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
972 extRRItype
, /* 15 5,5,5,5,3,3,5 */
973 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
974 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
975 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
976 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
977 extRi64type
, /* 20 5,6,5,5,3,3,5 */
978 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
980 /* I am heaping all the fields of the formats into one structure and
981 then, only the fields which are involved in instruction extension */
985 unsigned int regx
; /* Function in i8 type */
990 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
991 for the bits which make up the immediatate extension. */
994 extended_offset (unsigned int extension
)
997 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
999 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1001 value
|= extension
& 0x01f; /* extract 4:0 */
1005 /* Only call this function if you know that this is an extendable
1006 instruction, It wont malfunction, but why make excess remote memory references?
1007 If the immediate operands get sign extended or somthing, do it after
1008 the extension is performed.
1010 /* FIXME: Every one of these cases needs to worry about sign extension
1011 when the offset is to be used in relative addressing */
1015 fetch_mips_16 (CORE_ADDR pc
)
1018 pc
&= 0xfffffffe; /* clear the low order bit */
1019 target_read_memory (pc
, buf
, 2);
1020 return extract_unsigned_integer (buf
, 2);
1024 unpack_mips16 (CORE_ADDR pc
,
1025 unsigned int extension
,
1027 enum mips16_inst_fmts insn_format
,
1028 struct upk_mips16
*upk
)
1033 switch (insn_format
)
1040 value
= extended_offset (extension
);
1041 value
= value
<< 11; /* rom for the original value */
1042 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1046 value
= inst
& 0x7ff;
1047 /* FIXME : Consider sign extension */
1056 { /* A register identifier and an offset */
1057 /* Most of the fields are the same as I type but the
1058 immediate value is of a different length */
1062 value
= extended_offset (extension
);
1063 value
= value
<< 8; /* from the original instruction */
1064 value
|= inst
& 0xff; /* eleven bits from instruction */
1065 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1066 if (value
& 0x4000) /* test the sign bit , bit 26 */
1068 value
&= ~0x3fff; /* remove the sign bit */
1074 value
= inst
& 0xff; /* 8 bits */
1075 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1076 /* FIXME: Do sign extension , this format needs it */
1077 if (value
& 0x80) /* THIS CONFUSES ME */
1079 value
&= 0xef; /* remove the sign bit */
1089 unsigned long value
;
1090 unsigned int nexthalf
;
1091 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1092 value
= value
<< 16;
1093 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1101 internal_error (__FILE__
, __LINE__
,
1104 upk
->offset
= offset
;
1111 add_offset_16 (CORE_ADDR pc
, int offset
)
1113 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1118 extended_mips16_next_pc (CORE_ADDR pc
,
1119 unsigned int extension
,
1122 int op
= (insn
>> 11);
1125 case 2: /* Branch */
1128 struct upk_mips16 upk
;
1129 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1130 offset
= upk
.offset
;
1136 pc
+= (offset
<< 1) + 2;
1139 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1141 struct upk_mips16 upk
;
1142 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1143 pc
= add_offset_16 (pc
, upk
.offset
);
1144 if ((insn
>> 10) & 0x01) /* Exchange mode */
1145 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1152 struct upk_mips16 upk
;
1154 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1155 reg
= read_signed_register (upk
.regx
);
1157 pc
+= (upk
.offset
<< 1) + 2;
1164 struct upk_mips16 upk
;
1166 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1167 reg
= read_signed_register (upk
.regx
);
1169 pc
+= (upk
.offset
<< 1) + 2;
1174 case 12: /* I8 Formats btez btnez */
1176 struct upk_mips16 upk
;
1178 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1179 /* upk.regx contains the opcode */
1180 reg
= read_signed_register (24); /* Test register is 24 */
1181 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1182 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1183 /* pc = add_offset_16(pc,upk.offset) ; */
1184 pc
+= (upk
.offset
<< 1) + 2;
1189 case 29: /* RR Formats JR, JALR, JALR-RA */
1191 struct upk_mips16 upk
;
1192 /* upk.fmt = rrtype; */
1197 upk
.regx
= (insn
>> 8) & 0x07;
1198 upk
.regy
= (insn
>> 5) & 0x07;
1206 break; /* Function return instruction */
1212 break; /* BOGUS Guess */
1214 pc
= read_signed_register (reg
);
1221 /* This is an instruction extension. Fetch the real instruction
1222 (which follows the extension) and decode things based on
1226 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1239 mips16_next_pc (CORE_ADDR pc
)
1241 unsigned int insn
= fetch_mips_16 (pc
);
1242 return extended_mips16_next_pc (pc
, 0, insn
);
1245 /* The mips_next_pc function supports single_step when the remote
1246 target monitor or stub is not developed enough to do a single_step.
1247 It works by decoding the current instruction and predicting where a
1248 branch will go. This isnt hard because all the data is available.
1249 The MIPS32 and MIPS16 variants are quite different */
1251 mips_next_pc (CORE_ADDR pc
)
1254 return mips16_next_pc (pc
);
1256 return mips32_next_pc (pc
);
1259 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1263 mips_find_saved_regs (struct frame_info
*fci
)
1266 CORE_ADDR reg_position
;
1267 /* r0 bit means kernel trap */
1269 /* What registers have been saved? Bitmasks. */
1270 unsigned long gen_mask
, float_mask
;
1271 mips_extra_func_info_t proc_desc
;
1274 frame_saved_regs_zalloc (fci
);
1276 /* If it is the frame for sigtramp, the saved registers are located
1277 in a sigcontext structure somewhere on the stack.
1278 If the stack layout for sigtramp changes we might have to change these
1279 constants and the companion fixup_sigtramp in mdebugread.c */
1280 #ifndef SIGFRAME_BASE
1281 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1282 above the sigtramp frame. */
1283 #define SIGFRAME_BASE MIPS_REGSIZE
1284 /* FIXME! Are these correct?? */
1285 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1286 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1287 #define SIGFRAME_FPREGSAVE_OFF \
1288 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1290 #ifndef SIGFRAME_REG_SIZE
1291 /* FIXME! Is this correct?? */
1292 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1294 if (fci
->signal_handler_caller
)
1296 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1298 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1299 + ireg
* SIGFRAME_REG_SIZE
;
1300 fci
->saved_regs
[ireg
] = reg_position
;
1302 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1304 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1305 + ireg
* SIGFRAME_REG_SIZE
;
1306 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1308 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1312 proc_desc
= fci
->extra_info
->proc_desc
;
1313 if (proc_desc
== NULL
)
1314 /* I'm not sure how/whether this can happen. Normally when we can't
1315 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1316 and set the saved_regs right away. */
1319 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1320 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1321 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1323 if ( /* In any frame other than the innermost or a frame interrupted by
1324 a signal, we assume that all registers have been saved.
1325 This assumes that all register saves in a function happen before
1326 the first function call. */
1327 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1329 /* In a dummy frame we know exactly where things are saved. */
1330 && !PROC_DESC_IS_DUMMY (proc_desc
)
1332 /* Don't bother unless we are inside a function prologue. Outside the
1333 prologue, we know where everything is. */
1335 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1337 /* Not sure exactly what kernel_trap means, but if it means
1338 the kernel saves the registers without a prologue doing it,
1339 we better not examine the prologue to see whether registers
1340 have been saved yet. */
1343 /* We need to figure out whether the registers that the proc_desc
1344 claims are saved have been saved yet. */
1348 /* Bitmasks; set if we have found a save for the register. */
1349 unsigned long gen_save_found
= 0;
1350 unsigned long float_save_found
= 0;
1353 /* If the address is odd, assume this is MIPS16 code. */
1354 addr
= PROC_LOW_ADDR (proc_desc
);
1355 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1357 /* Scan through this function's instructions preceding the current
1358 PC, and look for those that save registers. */
1359 while (addr
< fci
->pc
)
1361 inst
= mips_fetch_instruction (addr
);
1362 if (pc_is_mips16 (addr
))
1363 mips16_decode_reg_save (inst
, &gen_save_found
);
1365 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1368 gen_mask
= gen_save_found
;
1369 float_mask
= float_save_found
;
1372 /* Fill in the offsets for the registers which gen_mask says
1374 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1375 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1376 if (gen_mask
& 0x80000000)
1378 fci
->saved_regs
[ireg
] = reg_position
;
1379 reg_position
-= MIPS_SAVED_REGSIZE
;
1382 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1383 of that normally used by gcc. Therefore, we have to fetch the first
1384 instruction of the function, and if it's an entry instruction that
1385 saves $s0 or $s1, correct their saved addresses. */
1386 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1388 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1389 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1392 int sreg_count
= (inst
>> 6) & 3;
1394 /* Check if the ra register was pushed on the stack. */
1395 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1397 reg_position
-= MIPS_SAVED_REGSIZE
;
1399 /* Check if the s0 and s1 registers were pushed on the stack. */
1400 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1402 fci
->saved_regs
[reg
] = reg_position
;
1403 reg_position
-= MIPS_SAVED_REGSIZE
;
1408 /* Fill in the offsets for the registers which float_mask says
1410 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1412 /* Apparently, the freg_offset gives the offset to the first 64 bit
1415 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1416 designates the first saved 64 bit register.
1418 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1419 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1420 FREG_OFFSET, designates the address of the lower register of the
1421 register pair. Adjust the offset so that it designates the upper
1422 register of the pair -- i.e., the address of the first saved 32
1425 if (MIPS_SAVED_REGSIZE
== 4)
1426 reg_position
+= MIPS_SAVED_REGSIZE
;
1428 /* Fill in the offsets for the float registers which float_mask says
1430 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1431 if (float_mask
& 0x80000000)
1433 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1434 reg_position
-= MIPS_SAVED_REGSIZE
;
1437 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1441 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1443 for (; fi
; fi
= fi
->next
)
1445 /* We have to get the saved sp from the sigcontext
1446 if it is a signal handler frame. */
1447 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1451 if (fi
->saved_regs
== NULL
)
1452 mips_find_saved_regs (fi
);
1453 if (fi
->saved_regs
[regno
])
1454 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1457 return read_signed_register (regno
);
1460 /* mips_addr_bits_remove - remove useless address bits */
1463 mips_addr_bits_remove (CORE_ADDR addr
)
1465 if (GDB_TARGET_IS_MIPS64
)
1467 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1469 /* This hack is a work-around for existing boards using
1470 PMON, the simulator, and any other 64-bit targets that
1471 doesn't have true 64-bit addressing. On these targets,
1472 the upper 32 bits of addresses are ignored by the
1473 hardware. Thus, the PC or SP are likely to have been
1474 sign extended to all 1s by instruction sequences that
1475 load 32-bit addresses. For example, a typical piece of
1476 code that loads an address is this:
1477 lui $r2, <upper 16 bits>
1478 ori $r2, <lower 16 bits>
1479 But the lui sign-extends the value such that the upper 32
1480 bits may be all 1s. The workaround is simply to mask off
1481 these bits. In the future, gcc may be changed to support
1482 true 64-bit addressing, and this masking will have to be
1484 addr
&= (CORE_ADDR
) 0xffffffff;
1487 else if (mips_mask_address_p ())
1489 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1490 masking off bits, instead, the actual target should be asking
1491 for the address to be converted to a valid pointer. */
1492 /* Even when GDB is configured for some 32-bit targets
1493 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1494 so CORE_ADDR is 64 bits. So we still have to mask off
1495 useless bits from addresses. */
1496 addr
&= (CORE_ADDR
) 0xffffffff;
1501 /* mips_software_single_step() is called just before we want to resume
1502 the inferior, if we want to single-step it but there is no hardware
1503 or kernel single-step support (MIPS on GNU/Linux for example). We find
1504 the target of the coming instruction and breakpoint it.
1506 single_step is also called just after the inferior stops. If we had
1507 set up a simulated single-step, we undo our damage. */
1510 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1512 static CORE_ADDR next_pc
;
1513 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1514 static binsn_quantum break_mem
;
1517 if (insert_breakpoints_p
)
1519 pc
= read_register (PC_REGNUM
);
1520 next_pc
= mips_next_pc (pc
);
1522 target_insert_breakpoint (next_pc
, break_mem
);
1525 target_remove_breakpoint (next_pc
, break_mem
);
1529 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1533 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1534 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1535 tmp
= mips_skip_stub (pc
);
1536 prev
->pc
= tmp
? tmp
: pc
;
1541 mips_frame_saved_pc (struct frame_info
*frame
)
1544 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1545 /* We have to get the saved pc from the sigcontext
1546 if it is a signal handler frame. */
1547 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1548 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1550 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1551 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1553 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1555 return ADDR_BITS_REMOVE (saved_pc
);
1558 static struct mips_extra_func_info temp_proc_desc
;
1559 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1561 /* Set a register's saved stack address in temp_saved_regs. If an address
1562 has already been set for this register, do nothing; this way we will
1563 only recognize the first save of a given register in a function prologue.
1564 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1567 set_reg_offset (int regno
, CORE_ADDR offset
)
1569 if (temp_saved_regs
[regno
] == 0)
1570 temp_saved_regs
[regno
] = offset
;
1574 /* Test whether the PC points to the return instruction at the
1575 end of a function. */
1578 mips_about_to_return (CORE_ADDR pc
)
1580 if (pc_is_mips16 (pc
))
1581 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1582 generates a "jr $ra"; other times it generates code to load
1583 the return address from the stack to an accessible register (such
1584 as $a3), then a "jr" using that register. This second case
1585 is almost impossible to distinguish from an indirect jump
1586 used for switch statements, so we don't even try. */
1587 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1589 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1593 /* This fencepost looks highly suspicious to me. Removing it also
1594 seems suspicious as it could affect remote debugging across serial
1598 heuristic_proc_start (CORE_ADDR pc
)
1605 pc
= ADDR_BITS_REMOVE (pc
);
1607 fence
= start_pc
- heuristic_fence_post
;
1611 if (heuristic_fence_post
== UINT_MAX
1612 || fence
< VM_MIN_ADDRESS
)
1613 fence
= VM_MIN_ADDRESS
;
1615 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1617 /* search back for previous return */
1618 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1619 if (start_pc
< fence
)
1621 /* It's not clear to me why we reach this point when
1622 stop_soon_quietly, but with this test, at least we
1623 don't print out warnings for every child forked (eg, on
1624 decstation). 22apr93 rich@cygnus.com. */
1625 if (!stop_soon_quietly
)
1627 static int blurb_printed
= 0;
1629 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1634 /* This actually happens frequently in embedded
1635 development, when you first connect to a board
1636 and your stack pointer and pc are nowhere in
1637 particular. This message needs to give people
1638 in that situation enough information to
1639 determine that it's no big deal. */
1640 printf_filtered ("\n\
1641 GDB is unable to find the start of the function at 0x%s\n\
1642 and thus can't determine the size of that function's stack frame.\n\
1643 This means that GDB may be unable to access that stack frame, or\n\
1644 the frames below it.\n\
1645 This problem is most likely caused by an invalid program counter or\n\
1647 However, if you think GDB should simply search farther back\n\
1648 from 0x%s for code which looks like the beginning of a\n\
1649 function, you can increase the range of the search using the `set\n\
1650 heuristic-fence-post' command.\n",
1651 paddr_nz (pc
), paddr_nz (pc
));
1658 else if (pc_is_mips16 (start_pc
))
1660 unsigned short inst
;
1662 /* On MIPS16, any one of the following is likely to be the
1663 start of a function:
1667 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1668 inst
= mips_fetch_instruction (start_pc
);
1669 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1670 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1671 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1672 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1674 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1675 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1680 else if (mips_about_to_return (start_pc
))
1682 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1689 /* Fetch the immediate value from a MIPS16 instruction.
1690 If the previous instruction was an EXTEND, use it to extend
1691 the upper bits of the immediate value. This is a helper function
1692 for mips16_heuristic_proc_desc. */
1695 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1696 unsigned short inst
, /* current instruction */
1697 int nbits
, /* number of bits in imm field */
1698 int scale
, /* scale factor to be applied to imm */
1699 int is_signed
) /* is the imm field signed? */
1703 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1705 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1706 if (offset
& 0x8000) /* check for negative extend */
1707 offset
= 0 - (0x10000 - (offset
& 0xffff));
1708 return offset
| (inst
& 0x1f);
1712 int max_imm
= 1 << nbits
;
1713 int mask
= max_imm
- 1;
1714 int sign_bit
= max_imm
>> 1;
1716 offset
= inst
& mask
;
1717 if (is_signed
&& (offset
& sign_bit
))
1718 offset
= 0 - (max_imm
- offset
);
1719 return offset
* scale
;
1724 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1725 stream from start_pc to limit_pc. */
1728 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1729 struct frame_info
*next_frame
, CORE_ADDR sp
)
1732 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1733 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1734 unsigned inst
= 0; /* current instruction */
1735 unsigned entry_inst
= 0; /* the entry instruction */
1738 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1739 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1741 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1743 /* Save the previous instruction. If it's an EXTEND, we'll extract
1744 the immediate offset extension from it in mips16_get_imm. */
1747 /* Fetch and decode the instruction. */
1748 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1749 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1750 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1752 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1753 if (offset
< 0) /* negative stack adjustment? */
1754 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1756 /* Exit loop if a positive stack adjustment is found, which
1757 usually means that the stack cleanup code in the function
1758 epilogue is reached. */
1761 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1763 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1764 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1765 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1766 set_reg_offset (reg
, sp
+ offset
);
1768 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1770 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1771 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1772 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1773 set_reg_offset (reg
, sp
+ offset
);
1775 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1777 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1778 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1779 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1781 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1783 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1784 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1785 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1787 else if (inst
== 0x673d) /* move $s1, $sp */
1790 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1792 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1794 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1795 frame_addr
= sp
+ offset
;
1796 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1797 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1799 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1801 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1802 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1803 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1804 set_reg_offset (reg
, frame_addr
+ offset
);
1806 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1808 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1809 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1810 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1811 set_reg_offset (reg
, frame_addr
+ offset
);
1813 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1814 entry_inst
= inst
; /* save for later processing */
1815 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1816 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1819 /* The entry instruction is typically the first instruction in a function,
1820 and it stores registers at offsets relative to the value of the old SP
1821 (before the prologue). But the value of the sp parameter to this
1822 function is the new SP (after the prologue has been executed). So we
1823 can't calculate those offsets until we've seen the entire prologue,
1824 and can calculate what the old SP must have been. */
1825 if (entry_inst
!= 0)
1827 int areg_count
= (entry_inst
>> 8) & 7;
1828 int sreg_count
= (entry_inst
>> 6) & 3;
1830 /* The entry instruction always subtracts 32 from the SP. */
1831 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1833 /* Now we can calculate what the SP must have been at the
1834 start of the function prologue. */
1835 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1837 /* Check if a0-a3 were saved in the caller's argument save area. */
1838 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1840 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1841 set_reg_offset (reg
, sp
+ offset
);
1842 offset
+= MIPS_SAVED_REGSIZE
;
1845 /* Check if the ra register was pushed on the stack. */
1847 if (entry_inst
& 0x20)
1849 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1850 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1851 offset
-= MIPS_SAVED_REGSIZE
;
1854 /* Check if the s0 and s1 registers were pushed on the stack. */
1855 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1857 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1858 set_reg_offset (reg
, sp
+ offset
);
1859 offset
-= MIPS_SAVED_REGSIZE
;
1865 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1866 struct frame_info
*next_frame
, CORE_ADDR sp
)
1869 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1871 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1872 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1873 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1874 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1876 unsigned long inst
, high_word
, low_word
;
1879 /* Fetch the instruction. */
1880 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1882 /* Save some code by pre-extracting some useful fields. */
1883 high_word
= (inst
>> 16) & 0xffff;
1884 low_word
= inst
& 0xffff;
1885 reg
= high_word
& 0x1f;
1887 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1888 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1889 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1891 if (low_word
& 0x8000) /* negative stack adjustment? */
1892 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1894 /* Exit loop if a positive stack adjustment is found, which
1895 usually means that the stack cleanup code in the function
1896 epilogue is reached. */
1899 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1901 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1902 set_reg_offset (reg
, sp
+ low_word
);
1904 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1906 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1907 but the register size used is only 32 bits. Make the address
1908 for the saved register point to the lower 32 bits. */
1909 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1910 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1912 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1914 /* Old gcc frame, r30 is virtual frame pointer. */
1915 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1916 frame_addr
= sp
+ low_word
;
1917 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1919 unsigned alloca_adjust
;
1920 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1921 frame_addr
= read_next_frame_reg (next_frame
, 30);
1922 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1923 if (alloca_adjust
> 0)
1925 /* FP > SP + frame_size. This may be because
1926 * of an alloca or somethings similar.
1927 * Fix sp to "pre-alloca" value, and try again.
1929 sp
+= alloca_adjust
;
1934 /* move $30,$sp. With different versions of gas this will be either
1935 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1936 Accept any one of these. */
1937 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1939 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1940 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1942 unsigned alloca_adjust
;
1943 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1944 frame_addr
= read_next_frame_reg (next_frame
, 30);
1945 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1946 if (alloca_adjust
> 0)
1948 /* FP > SP + frame_size. This may be because
1949 * of an alloca or somethings similar.
1950 * Fix sp to "pre-alloca" value, and try again.
1952 sp
+= alloca_adjust
;
1957 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1959 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1960 set_reg_offset (reg
, frame_addr
+ low_word
);
1965 static mips_extra_func_info_t
1966 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1967 struct frame_info
*next_frame
, int cur_frame
)
1972 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1978 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1979 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1980 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1981 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1982 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1984 if (start_pc
+ 200 < limit_pc
)
1985 limit_pc
= start_pc
+ 200;
1986 if (pc_is_mips16 (start_pc
))
1987 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1989 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1990 return &temp_proc_desc
;
1993 struct mips_objfile_private
1999 /* Global used to communicate between non_heuristic_proc_desc and
2000 compare_pdr_entries within qsort (). */
2001 static bfd
*the_bfd
;
2004 compare_pdr_entries (const void *a
, const void *b
)
2006 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2007 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2011 else if (lhs
== rhs
)
2017 static mips_extra_func_info_t
2018 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2020 CORE_ADDR startaddr
;
2021 mips_extra_func_info_t proc_desc
;
2022 struct block
*b
= block_for_pc (pc
);
2024 struct obj_section
*sec
;
2025 struct mips_objfile_private
*priv
;
2027 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
2030 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2032 *addrptr
= startaddr
;
2036 sec
= find_pc_section (pc
);
2039 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2041 /* Search the ".pdr" section generated by GAS. This includes most of
2042 the information normally found in ECOFF PDRs. */
2044 the_bfd
= sec
->objfile
->obfd
;
2046 && (the_bfd
->format
== bfd_object
2047 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2048 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2050 /* Right now GAS only outputs the address as a four-byte sequence.
2051 This means that we should not bother with this method on 64-bit
2052 targets (until that is fixed). */
2054 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2055 sizeof (struct mips_objfile_private
));
2057 sec
->objfile
->obj_private
= priv
;
2059 else if (priv
== NULL
)
2063 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2064 sizeof (struct mips_objfile_private
));
2066 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2069 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2070 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2072 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2073 priv
->contents
, 0, priv
->size
);
2075 /* In general, the .pdr section is sorted. However, in the
2076 presence of multiple code sections (and other corner cases)
2077 it can become unsorted. Sort it so that we can use a faster
2079 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2084 sec
->objfile
->obj_private
= priv
;
2088 if (priv
->size
!= 0)
2094 high
= priv
->size
/ 32;
2100 mid
= (low
+ high
) / 2;
2102 ptr
= priv
->contents
+ mid
* 32;
2103 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2104 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2105 SECT_OFF_TEXT (sec
->objfile
));
2106 if (pdr_pc
== startaddr
)
2108 if (pdr_pc
> startaddr
)
2113 while (low
!= high
);
2117 struct symbol
*sym
= find_pc_function (pc
);
2119 /* Fill in what we need of the proc_desc. */
2120 proc_desc
= (mips_extra_func_info_t
)
2121 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2122 sizeof (struct mips_extra_func_info
));
2123 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2125 /* Only used for dummy frames. */
2126 PROC_HIGH_ADDR (proc_desc
) = 0;
2128 PROC_FRAME_OFFSET (proc_desc
)
2129 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2130 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2132 PROC_FRAME_ADJUST (proc_desc
) = 0;
2133 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2135 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2137 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2139 PROC_FREG_OFFSET (proc_desc
)
2140 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2141 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2143 proc_desc
->pdr
.isym
= (long) sym
;
2153 if (startaddr
> BLOCK_START (b
))
2155 /* This is the "pathological" case referred to in a comment in
2156 print_frame_info. It might be better to move this check into
2161 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2163 /* If we never found a PDR for this function in symbol reading, then
2164 examine prologues to find the information. */
2167 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2168 if (PROC_FRAME_REG (proc_desc
) == -1)
2178 static mips_extra_func_info_t
2179 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2181 mips_extra_func_info_t proc_desc
;
2182 CORE_ADDR startaddr
;
2184 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2188 /* IF this is the topmost frame AND
2189 * (this proc does not have debugging information OR
2190 * the PC is in the procedure prologue)
2191 * THEN create a "heuristic" proc_desc (by analyzing
2192 * the actual code) to replace the "official" proc_desc.
2194 if (next_frame
== NULL
)
2196 struct symtab_and_line val
;
2197 struct symbol
*proc_symbol
=
2198 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2202 val
= find_pc_line (BLOCK_START
2203 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2205 val
.pc
= val
.end
? val
.end
: pc
;
2207 if (!proc_symbol
|| pc
< val
.pc
)
2209 mips_extra_func_info_t found_heuristic
=
2210 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2211 pc
, next_frame
, cur_frame
);
2212 if (found_heuristic
)
2213 proc_desc
= found_heuristic
;
2219 /* Is linked_proc_desc_table really necessary? It only seems to be used
2220 by procedure call dummys. However, the procedures being called ought
2221 to have their own proc_descs, and even if they don't,
2222 heuristic_proc_desc knows how to create them! */
2224 register struct linked_proc_info
*link
;
2226 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2227 if (PROC_LOW_ADDR (&link
->info
) <= pc
2228 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2232 startaddr
= heuristic_proc_start (pc
);
2235 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2241 get_frame_pointer (struct frame_info
*frame
,
2242 mips_extra_func_info_t proc_desc
)
2244 return ADDR_BITS_REMOVE (
2245 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2246 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2249 mips_extra_func_info_t cached_proc_desc
;
2252 mips_frame_chain (struct frame_info
*frame
)
2254 mips_extra_func_info_t proc_desc
;
2256 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2258 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2261 /* Check if the PC is inside a call stub. If it is, fetch the
2262 PC of the caller of that stub. */
2263 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2266 /* Look up the procedure descriptor for this PC. */
2267 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2271 cached_proc_desc
= proc_desc
;
2273 /* If no frame pointer and frame size is zero, we must be at end
2274 of stack (or otherwise hosed). If we don't check frame size,
2275 we loop forever if we see a zero size frame. */
2276 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2277 && PROC_FRAME_OFFSET (proc_desc
) == 0
2278 /* The previous frame from a sigtramp frame might be frameless
2279 and have frame size zero. */
2280 && !frame
->signal_handler_caller
)
2283 return get_frame_pointer (frame
, proc_desc
);
2287 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2291 /* Use proc_desc calculated in frame_chain */
2292 mips_extra_func_info_t proc_desc
=
2293 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2295 fci
->extra_info
= (struct frame_extra_info
*)
2296 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2298 fci
->saved_regs
= NULL
;
2299 fci
->extra_info
->proc_desc
=
2300 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2303 /* Fixup frame-pointer - only needed for top frame */
2304 /* This may not be quite right, if proc has a real frame register.
2305 Get the value of the frame relative sp, procedure might have been
2306 interrupted by a signal at it's very start. */
2307 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2308 && !PROC_DESC_IS_DUMMY (proc_desc
))
2309 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2311 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2313 if (proc_desc
== &temp_proc_desc
)
2317 /* Do not set the saved registers for a sigtramp frame,
2318 mips_find_saved_registers will do that for us.
2319 We can't use fci->signal_handler_caller, it is not yet set. */
2320 find_pc_partial_function (fci
->pc
, &name
,
2321 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2322 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2324 frame_saved_regs_zalloc (fci
);
2325 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2326 fci
->saved_regs
[PC_REGNUM
]
2327 = fci
->saved_regs
[RA_REGNUM
];
2331 /* hack: if argument regs are saved, guess these contain args */
2332 /* assume we can't tell how many args for now */
2333 fci
->extra_info
->num_args
= -1;
2334 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2336 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2338 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2345 /* MIPS stack frames are almost impenetrable. When execution stops,
2346 we basically have to look at symbol information for the function
2347 that we stopped in, which tells us *which* register (if any) is
2348 the base of the frame pointer, and what offset from that register
2349 the frame itself is at.
2351 This presents a problem when trying to examine a stack in memory
2352 (that isn't executing at the moment), using the "frame" command. We
2353 don't have a PC, nor do we have any registers except SP.
2355 This routine takes two arguments, SP and PC, and tries to make the
2356 cached frames look as if these two arguments defined a frame on the
2357 cache. This allows the rest of info frame to extract the important
2358 arguments without difficulty. */
2361 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2364 error ("MIPS frame specifications require two arguments: sp and pc");
2366 return create_new_frame (argv
[0], argv
[1]);
2369 /* According to the current ABI, should the type be passed in a
2370 floating-point register (assuming that there is space)? When there
2371 is no FPU, FP are not even considered as possibile candidates for
2372 FP registers and, consequently this returns false - forces FP
2373 arguments into integer registers. */
2376 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2378 return ((typecode
== TYPE_CODE_FLT
2380 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2381 && TYPE_NFIELDS (arg_type
) == 1
2382 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2383 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2386 /* On o32, argument passing in GPRs depends on the alignment of the type being
2387 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2390 mips_type_needs_double_align (struct type
*type
)
2392 enum type_code typecode
= TYPE_CODE (type
);
2394 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2396 else if (typecode
== TYPE_CODE_STRUCT
)
2398 if (TYPE_NFIELDS (type
) < 1)
2400 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2402 else if (typecode
== TYPE_CODE_UNION
)
2406 n
= TYPE_NFIELDS (type
);
2407 for (i
= 0; i
< n
; i
++)
2408 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2416 mips_push_arguments (int nargs
,
2417 struct value
**args
,
2420 CORE_ADDR struct_addr
)
2426 int stack_offset
= 0;
2427 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2429 /* Macros to round N up or down to the next A boundary; A must be
2431 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2432 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2434 /* First ensure that the stack and structure return address (if any)
2435 are properly aligned. The stack has to be at least 64-bit aligned
2436 even on 32-bit machines, because doubles must be 64-bit aligned.
2437 On at least one MIPS variant, stack frames need to be 128-bit
2438 aligned, so we round to this widest known alignment. */
2439 sp
= ROUND_DOWN (sp
, 16);
2440 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2442 /* Now make space on the stack for the args. We allocate more
2443 than necessary for EABI, because the first few arguments are
2444 passed in registers, but that's OK. */
2445 for (argnum
= 0; argnum
< nargs
; argnum
++)
2446 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2447 sp
-= ROUND_UP (len
, 16);
2450 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2451 (long) sp
, ROUND_UP (len
, 16));
2453 /* Initialize the integer and float register pointers. */
2455 float_argreg
= FPA0_REGNUM
;
2457 /* the struct_return pointer occupies the first parameter-passing reg */
2461 fprintf_unfiltered (gdb_stdlog
,
2462 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2463 argreg
, (long) struct_addr
);
2464 write_register (argreg
++, struct_addr
);
2465 if (MIPS_REGS_HAVE_HOME_P
)
2466 stack_offset
+= MIPS_STACK_ARGSIZE
;
2469 /* Now load as many as possible of the first arguments into
2470 registers, and push the rest onto the stack. Loop thru args
2471 from first to last. */
2472 for (argnum
= 0; argnum
< nargs
; argnum
++)
2475 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2476 struct value
*arg
= args
[argnum
];
2477 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2478 int len
= TYPE_LENGTH (arg_type
);
2479 enum type_code typecode
= TYPE_CODE (arg_type
);
2482 fprintf_unfiltered (gdb_stdlog
,
2483 "mips_push_arguments: %d len=%d type=%d",
2484 argnum
+ 1, len
, (int) typecode
);
2486 /* The EABI passes structures that do not fit in a register by
2487 reference. In all other cases, pass the structure by value. */
2489 && len
> MIPS_SAVED_REGSIZE
2490 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2492 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2493 typecode
= TYPE_CODE_PTR
;
2494 len
= MIPS_SAVED_REGSIZE
;
2497 fprintf_unfiltered (gdb_stdlog
, " push");
2500 val
= (char *) VALUE_CONTENTS (arg
);
2502 /* 32-bit ABIs always start floating point arguments in an
2503 even-numbered floating point register. Round the FP register
2504 up before the check to see if there are any FP registers
2505 left. Non MIPS_EABI targets also pass the FP in the integer
2506 registers so also round up normal registers. */
2507 if (!FP_REGISTER_DOUBLE
2508 && fp_register_arg_p (typecode
, arg_type
))
2510 if ((float_argreg
& 1))
2514 /* Floating point arguments passed in registers have to be
2515 treated specially. On 32-bit architectures, doubles
2516 are passed in register pairs; the even register gets
2517 the low word, and the odd register gets the high word.
2518 On non-EABI processors, the first two floating point arguments are
2519 also copied to general registers, because MIPS16 functions
2520 don't use float registers for arguments. This duplication of
2521 arguments in general registers can't hurt non-MIPS16 functions
2522 because those registers are normally skipped. */
2523 /* MIPS_EABI squeezes a struct that contains a single floating
2524 point value into an FP register instead of pushing it onto the
2526 if (fp_register_arg_p (typecode
, arg_type
)
2527 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2529 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2531 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2532 unsigned long regval
;
2534 /* Write the low word of the double to the even register(s). */
2535 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2537 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2538 float_argreg
, phex (regval
, 4));
2539 write_register (float_argreg
++, regval
);
2543 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2544 argreg
, phex (regval
, 4));
2545 write_register (argreg
++, regval
);
2548 /* Write the high word of the double to the odd register(s). */
2549 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2551 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2552 float_argreg
, phex (regval
, 4));
2553 write_register (float_argreg
++, regval
);
2557 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2558 argreg
, phex (regval
, 4));
2559 write_register (argreg
++, regval
);
2565 /* This is a floating point value that fits entirely
2566 in a single register. */
2567 /* On 32 bit ABI's the float_argreg is further adjusted
2568 above to ensure that it is even register aligned. */
2569 LONGEST regval
= extract_unsigned_integer (val
, len
);
2571 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2572 float_argreg
, phex (regval
, len
));
2573 write_register (float_argreg
++, regval
);
2576 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2577 registers for each argument. The below is (my
2578 guess) to ensure that the corresponding integer
2579 register has reserved the same space. */
2581 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2582 argreg
, phex (regval
, len
));
2583 write_register (argreg
, regval
);
2584 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2587 /* Reserve space for the FP register. */
2588 if (MIPS_REGS_HAVE_HOME_P
)
2589 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2593 /* Copy the argument to general registers or the stack in
2594 register-sized pieces. Large arguments are split between
2595 registers and stack. */
2596 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2597 are treated specially: Irix cc passes them in registers
2598 where gcc sometimes puts them on the stack. For maximum
2599 compatibility, we will put them in both places. */
2600 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2601 (len
% MIPS_SAVED_REGSIZE
!= 0));
2602 /* Structures should be aligned to eight bytes (even arg registers)
2603 on MIPS_ABI_O32 if their first member has double precision. */
2604 if (tdep
->mips_abi
== MIPS_ABI_O32
2605 && mips_type_needs_double_align (arg_type
))
2610 /* Note: Floating-point values that didn't fit into an FP
2611 register are only written to memory. */
2614 /* Rememer if the argument was written to the stack. */
2615 int stack_used_p
= 0;
2616 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2619 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2622 /* Write this portion of the argument to the stack. */
2623 if (argreg
> MIPS_LAST_ARG_REGNUM
2625 || fp_register_arg_p (typecode
, arg_type
))
2627 /* Should shorter than int integer values be
2628 promoted to int before being stored? */
2629 int longword_offset
= 0;
2632 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2634 if (MIPS_STACK_ARGSIZE
== 8 &&
2635 (typecode
== TYPE_CODE_INT
||
2636 typecode
== TYPE_CODE_PTR
||
2637 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2638 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2639 else if ((typecode
== TYPE_CODE_STRUCT
||
2640 typecode
== TYPE_CODE_UNION
) &&
2641 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2642 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2647 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2648 (long) stack_offset
);
2649 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2650 (long) longword_offset
);
2653 addr
= sp
+ stack_offset
+ longword_offset
;
2658 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2659 for (i
= 0; i
< partial_len
; i
++)
2661 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2664 write_memory (addr
, val
, partial_len
);
2667 /* Note!!! This is NOT an else clause. Odd sized
2668 structs may go thru BOTH paths. Floating point
2669 arguments will not. */
2670 /* Write this portion of the argument to a general
2671 purpose register. */
2672 if (argreg
<= MIPS_LAST_ARG_REGNUM
2673 && !fp_register_arg_p (typecode
, arg_type
))
2675 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2677 /* A non-floating-point argument being passed in a
2678 general register. If a struct or union, and if
2679 the remaining length is smaller than the register
2680 size, we have to adjust the register value on
2683 It does not seem to be necessary to do the
2684 same for integral types.
2686 Also don't do this adjustment on EABI and O64
2689 cagney/2001-07-23: gdb/179: Also, GCC, when
2690 outputting LE O32 with sizeof (struct) <
2691 MIPS_SAVED_REGSIZE, generates a left shift as
2692 part of storing the argument in a register a
2693 register (the left shift isn't generated when
2694 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2695 is quite possible that this is GCC contradicting
2696 the LE/O32 ABI, GDB has not been adjusted to
2697 accommodate this. Either someone needs to
2698 demonstrate that the LE/O32 ABI specifies such a
2699 left shift OR this new ABI gets identified as
2700 such and GDB gets tweaked accordingly. */
2703 && MIPS_SAVED_REGSIZE
< 8
2704 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2705 && partial_len
< MIPS_SAVED_REGSIZE
2706 && (typecode
== TYPE_CODE_STRUCT
||
2707 typecode
== TYPE_CODE_UNION
))
2708 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2712 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2714 phex (regval
, MIPS_SAVED_REGSIZE
));
2715 write_register (argreg
, regval
);
2718 /* If this is the old ABI, prevent subsequent floating
2719 point arguments from being passed in floating point
2722 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2728 /* Compute the the offset into the stack at which we
2729 will copy the next parameter.
2731 In older ABIs, the caller reserved space for
2732 registers that contained arguments. This was loosely
2733 refered to as their "home". Consequently, space is
2736 In the new EABI (and the NABI32), the stack_offset
2737 only needs to be adjusted when it has been used.. */
2739 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2740 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2744 fprintf_unfiltered (gdb_stdlog
, "\n");
2747 /* Return adjusted stack pointer. */
2752 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2754 /* Set the return address register to point to the entry
2755 point of the program, where a breakpoint lies in wait. */
2756 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2761 mips_push_register (CORE_ADDR
* sp
, int regno
)
2763 char buffer
[MAX_REGISTER_RAW_SIZE
];
2766 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2768 regsize
= MIPS_SAVED_REGSIZE
;
2769 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2770 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2775 regsize
= REGISTER_RAW_SIZE (regno
);
2779 read_register_gen (regno
, buffer
);
2780 write_memory (*sp
, buffer
+ offset
, regsize
);
2783 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2784 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2787 mips_push_dummy_frame (void)
2790 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2791 xmalloc (sizeof (struct linked_proc_info
));
2792 mips_extra_func_info_t proc_desc
= &link
->info
;
2793 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2794 CORE_ADDR old_sp
= sp
;
2795 link
->next
= linked_proc_desc_table
;
2796 linked_proc_desc_table
= link
;
2798 /* FIXME! are these correct ? */
2799 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2800 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2801 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2802 #define FLOAT_SINGLE_REG_SAVE_MASK \
2803 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2805 * The registers we must save are all those not preserved across
2806 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2807 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2808 * and FP Control/Status registers.
2811 * Dummy frame layout:
2814 * Saved MMHI, MMLO, FPC_CSR
2819 * Saved D18 (i.e. F19, F18)
2821 * Saved D0 (i.e. F1, F0)
2822 * Argument build area and stack arguments written via mips_push_arguments
2826 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2827 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2828 PROC_FRAME_OFFSET (proc_desc
) = 0;
2829 PROC_FRAME_ADJUST (proc_desc
) = 0;
2830 mips_push_register (&sp
, PC_REGNUM
);
2831 mips_push_register (&sp
, HI_REGNUM
);
2832 mips_push_register (&sp
, LO_REGNUM
);
2833 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2835 /* Save general CPU registers */
2836 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2837 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2838 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2839 for (ireg
= 32; --ireg
>= 0;)
2840 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2841 mips_push_register (&sp
, ireg
);
2843 /* Save floating point registers starting with high order word */
2844 PROC_FREG_MASK (proc_desc
) =
2845 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2846 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2847 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2849 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2850 for (ireg
= 32; --ireg
>= 0;)
2851 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2852 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2854 /* Update the frame pointer for the call dummy and the stack pointer.
2855 Set the procedure's starting and ending addresses to point to the
2856 call dummy address at the entry point. */
2857 write_register (PUSH_FP_REGNUM
, old_sp
);
2858 write_register (SP_REGNUM
, sp
);
2859 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2860 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2861 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2862 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2866 mips_pop_frame (void)
2868 register int regnum
;
2869 struct frame_info
*frame
= get_current_frame ();
2870 CORE_ADDR new_sp
= FRAME_FP (frame
);
2872 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2874 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2875 if (frame
->saved_regs
== NULL
)
2876 mips_find_saved_regs (frame
);
2877 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2879 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2880 && frame
->saved_regs
[regnum
])
2881 write_register (regnum
,
2882 read_memory_integer (frame
->saved_regs
[regnum
],
2883 MIPS_SAVED_REGSIZE
));
2885 write_register (SP_REGNUM
, new_sp
);
2886 flush_cached_frames ();
2888 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2890 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2892 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2894 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2896 if (&pi_ptr
->info
== proc_desc
)
2901 error ("Can't locate dummy extra frame info\n");
2903 if (prev_ptr
!= NULL
)
2904 prev_ptr
->next
= pi_ptr
->next
;
2906 linked_proc_desc_table
= pi_ptr
->next
;
2910 write_register (HI_REGNUM
,
2911 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2912 MIPS_SAVED_REGSIZE
));
2913 write_register (LO_REGNUM
,
2914 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2915 MIPS_SAVED_REGSIZE
));
2916 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2917 write_register (FCRCS_REGNUM
,
2918 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2919 MIPS_SAVED_REGSIZE
));
2923 /* Floating point register management.
2925 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2926 64bit operations, these early MIPS cpus treat fp register pairs
2927 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2928 registers and offer a compatibility mode that emulates the MIPS2 fp
2929 model. When operating in MIPS2 fp compat mode, later cpu's split
2930 double precision floats into two 32-bit chunks and store them in
2931 consecutive fp regs. To display 64-bit floats stored in this
2932 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2933 Throw in user-configurable endianness and you have a real mess.
2935 The way this works is:
2936 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2937 double-precision value will be split across two logical registers.
2938 The lower-numbered logical register will hold the low-order bits,
2939 regardless of the processor's endianness.
2940 - If we are on a 64-bit processor, and we are looking for a
2941 single-precision value, it will be in the low ordered bits
2942 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2943 save slot in memory.
2944 - If we are in 64-bit mode, everything is straightforward.
2946 Note that this code only deals with "live" registers at the top of the
2947 stack. We will attempt to deal with saved registers later, when
2948 the raw/cooked register interface is in place. (We need a general
2949 interface that can deal with dynamic saved register sizes -- fp
2950 regs could be 32 bits wide in one frame and 64 on the frame above
2953 static struct type
*
2954 mips_float_register_type (void)
2956 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2957 return builtin_type_ieee_single_big
;
2959 return builtin_type_ieee_single_little
;
2962 static struct type
*
2963 mips_double_register_type (void)
2965 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2966 return builtin_type_ieee_double_big
;
2968 return builtin_type_ieee_double_little
;
2971 /* Copy a 32-bit single-precision value from the current frame
2972 into rare_buffer. */
2975 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2977 int raw_size
= REGISTER_RAW_SIZE (regno
);
2978 char *raw_buffer
= alloca (raw_size
);
2980 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2981 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2984 /* We have a 64-bit value for this register. Find the low-order
2988 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2993 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2997 memcpy (rare_buffer
, raw_buffer
, 4);
3001 /* Copy a 64-bit double-precision value from the current frame into
3002 rare_buffer. This may include getting half of it from the next
3006 mips_read_fp_register_double (int regno
, char *rare_buffer
)
3008 int raw_size
= REGISTER_RAW_SIZE (regno
);
3010 if (raw_size
== 8 && !mips2_fp_compat ())
3012 /* We have a 64-bit value for this register, and we should use
3014 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
3015 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3019 if ((regno
- FP0_REGNUM
) & 1)
3020 internal_error (__FILE__
, __LINE__
,
3021 "mips_read_fp_register_double: bad access to "
3022 "odd-numbered FP register");
3024 /* mips_read_fp_register_single will find the correct 32 bits from
3026 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3028 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
3029 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
3033 mips_read_fp_register_single (regno
, rare_buffer
);
3034 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
3040 mips_print_register (int regnum
, int all
)
3042 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3044 /* Get the data in raw format. */
3045 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3047 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
3051 /* If we have a actual 32-bit floating point register (or we are in
3052 32-bit compatibility mode), and the register is even-numbered,
3053 also print it as a double (spanning two registers). */
3054 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
3055 && (REGISTER_RAW_SIZE (regnum
) == 4
3056 || mips2_fp_compat ())
3057 && !((regnum
- FP0_REGNUM
) & 1))
3059 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
3061 mips_read_fp_register_double (regnum
, dbuffer
);
3063 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
3064 val_print (mips_double_register_type (), dbuffer
, 0, 0,
3065 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3066 printf_filtered ("); ");
3068 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3070 /* The problem with printing numeric register names (r26, etc.) is that
3071 the user can't use them on input. Probably the best solution is to
3072 fix it so that either the numeric or the funky (a2, etc.) names
3073 are accepted on input. */
3074 if (regnum
< MIPS_NUMREGS
)
3075 printf_filtered ("(r%d): ", regnum
);
3077 printf_filtered (": ");
3079 /* If virtual format is floating, print it that way. */
3080 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3081 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
3083 /* We have a meaningful 64-bit value in this register. Show
3084 it as a 32-bit float and a 64-bit double. */
3085 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3087 printf_filtered (" (float) ");
3088 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3089 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3090 printf_filtered (", (double) ");
3091 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3092 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3095 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3096 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3097 /* Else print as integer in hex. */
3102 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3103 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3107 print_scalar_formatted (raw_buffer
+ offset
,
3108 REGISTER_VIRTUAL_TYPE (regnum
),
3109 'x', 0, gdb_stdout
);
3113 /* Replacement for generic do_registers_info.
3114 Print regs in pretty columns. */
3117 do_fp_register_row (int regnum
)
3118 { /* do values for FP (float) regs */
3120 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3121 int inv1
, inv2
, inv3
;
3123 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3125 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3127 /* 4-byte registers: we can fit two registers per row. */
3128 /* Also print every pair of 4-byte regs as an 8-byte double. */
3129 mips_read_fp_register_single (regnum
, raw_buffer
);
3130 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3132 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3133 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3135 mips_read_fp_register_double (regnum
, raw_buffer
);
3136 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3138 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
3140 printf_filtered (": <invalid float>");
3142 printf_filtered ("%-17.9g", flt1
);
3144 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
3146 printf_filtered (": <invalid float>");
3148 printf_filtered ("%-17.9g", flt2
);
3150 printf_filtered (" dbl: ");
3152 printf_filtered ("<invalid double>");
3154 printf_filtered ("%-24.17g", doub
);
3155 printf_filtered ("\n");
3157 /* may want to do hex display here (future enhancement) */
3162 /* Eight byte registers: print each one as float AND as double. */
3163 mips_read_fp_register_single (regnum
, raw_buffer
);
3164 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
3166 mips_read_fp_register_double (regnum
, raw_buffer
);
3167 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3169 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
3171 printf_filtered ("<invalid float>");
3173 printf_filtered ("flt: %-17.9g", flt1
);
3175 printf_filtered (" dbl: ");
3177 printf_filtered ("<invalid double>");
3179 printf_filtered ("%-24.17g", doub
);
3181 printf_filtered ("\n");
3182 /* may want to do hex display here (future enhancement) */
3188 /* Print a row's worth of GP (int) registers, with name labels above */
3191 do_gp_register_row (int regnum
)
3193 /* do values for GP (int) regs */
3194 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3195 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
3197 int start_regnum
= regnum
;
3198 int numregs
= NUM_REGS
;
3201 /* For GP registers, we print a separate row of names above the vals */
3202 printf_filtered (" ");
3203 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3205 if (*REGISTER_NAME (regnum
) == '\0')
3206 continue; /* unused register */
3207 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3208 break; /* end the row: reached FP register */
3209 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3210 REGISTER_NAME (regnum
));
3213 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3214 start_regnum
); /* print the R0 to R31 names */
3216 regnum
= start_regnum
; /* go back to start of row */
3217 /* now print the values in hex, 4 or 8 to the row */
3218 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3220 if (*REGISTER_NAME (regnum
) == '\0')
3221 continue; /* unused register */
3222 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3223 break; /* end row: reached FP register */
3224 /* OK: get the data in raw format. */
3225 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3226 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3227 /* pad small registers */
3228 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3229 printf_filtered (" ");
3230 /* Now print the register value in hex, endian order. */
3231 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3232 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3233 byte
< REGISTER_RAW_SIZE (regnum
);
3235 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3237 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3240 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3241 printf_filtered (" ");
3244 if (col
> 0) /* ie. if we actually printed anything... */
3245 printf_filtered ("\n");
3250 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3253 mips_do_registers_info (int regnum
, int fpregs
)
3255 if (regnum
!= -1) /* do one specified register */
3257 if (*(REGISTER_NAME (regnum
)) == '\0')
3258 error ("Not a valid register for the current processor type");
3260 mips_print_register (regnum
, 0);
3261 printf_filtered ("\n");
3264 /* do all (or most) registers */
3267 while (regnum
< NUM_REGS
)
3269 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3270 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3271 regnum
= do_fp_register_row (regnum
); /* FP regs */
3273 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3275 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3280 /* Return number of args passed to a frame. described by FIP.
3281 Can return -1, meaning no way to tell. */
3284 mips_frame_num_args (struct frame_info
*frame
)
3289 /* Is this a branch with a delay slot? */
3291 static int is_delayed (unsigned long);
3294 is_delayed (unsigned long insn
)
3297 for (i
= 0; i
< NUMOPCODES
; ++i
)
3298 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3299 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3301 return (i
< NUMOPCODES
3302 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3303 | INSN_COND_BRANCH_DELAY
3304 | INSN_COND_BRANCH_LIKELY
)));
3308 mips_step_skips_delay (CORE_ADDR pc
)
3310 char buf
[MIPS_INSTLEN
];
3312 /* There is no branch delay slot on MIPS16. */
3313 if (pc_is_mips16 (pc
))
3316 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3317 /* If error reading memory, guess that it is not a delayed branch. */
3319 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3323 /* Skip the PC past function prologue instructions (32-bit version).
3324 This is a helper function for mips_skip_prologue. */
3327 mips32_skip_prologue (CORE_ADDR pc
)
3331 int seen_sp_adjust
= 0;
3332 int load_immediate_bytes
= 0;
3334 /* Skip the typical prologue instructions. These are the stack adjustment
3335 instruction and the instructions that save registers on the stack
3336 or in the gcc frame. */
3337 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3339 unsigned long high_word
;
3341 inst
= mips_fetch_instruction (pc
);
3342 high_word
= (inst
>> 16) & 0xffff;
3344 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3345 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3347 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3348 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3350 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3351 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3352 && (inst
& 0x001F0000)) /* reg != $zero */
3355 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3357 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3359 continue; /* reg != $zero */
3361 /* move $s8,$sp. With different versions of gas this will be either
3362 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3363 Accept any one of these. */
3364 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3367 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3369 else if (high_word
== 0x3c1c) /* lui $gp,n */
3371 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3373 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3374 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3376 /* The following instructions load $at or $t0 with an immediate
3377 value in preparation for a stack adjustment via
3378 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3379 a local variable, so we accept them only before a stack adjustment
3380 instruction was seen. */
3381 else if (!seen_sp_adjust
)
3383 if (high_word
== 0x3c01 || /* lui $at,n */
3384 high_word
== 0x3c08) /* lui $t0,n */
3386 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3389 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3390 high_word
== 0x3508 || /* ori $t0,$t0,n */
3391 high_word
== 0x3401 || /* ori $at,$zero,n */
3392 high_word
== 0x3408) /* ori $t0,$zero,n */
3394 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3404 /* In a frameless function, we might have incorrectly
3405 skipped some load immediate instructions. Undo the skipping
3406 if the load immediate was not followed by a stack adjustment. */
3407 if (load_immediate_bytes
&& !seen_sp_adjust
)
3408 pc
-= load_immediate_bytes
;
3412 /* Skip the PC past function prologue instructions (16-bit version).
3413 This is a helper function for mips_skip_prologue. */
3416 mips16_skip_prologue (CORE_ADDR pc
)
3419 int extend_bytes
= 0;
3420 int prev_extend_bytes
;
3422 /* Table of instructions likely to be found in a function prologue. */
3425 unsigned short inst
;
3426 unsigned short mask
;
3433 , /* addiu $sp,offset */
3437 , /* daddiu $sp,offset */
3441 , /* sw reg,n($sp) */
3445 , /* sd reg,n($sp) */
3449 , /* sw $ra,n($sp) */
3453 , /* sd $ra,n($sp) */
3461 , /* sw $a0-$a3,n($s1) */
3465 , /* move reg,$a0-$a3 */
3469 , /* entry pseudo-op */
3473 , /* addiu $s1,$sp,n */
3476 } /* end of table marker */
3479 /* Skip the typical prologue instructions. These are the stack adjustment
3480 instruction and the instructions that save registers on the stack
3481 or in the gcc frame. */
3482 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3484 unsigned short inst
;
3487 inst
= mips_fetch_instruction (pc
);
3489 /* Normally we ignore an extend instruction. However, if it is
3490 not followed by a valid prologue instruction, we must adjust
3491 the pc back over the extend so that it won't be considered
3492 part of the prologue. */
3493 if ((inst
& 0xf800) == 0xf000) /* extend */
3495 extend_bytes
= MIPS16_INSTLEN
;
3498 prev_extend_bytes
= extend_bytes
;
3501 /* Check for other valid prologue instructions besides extend. */
3502 for (i
= 0; table
[i
].mask
!= 0; i
++)
3503 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3505 if (table
[i
].mask
!= 0) /* it was in table? */
3506 continue; /* ignore it */
3510 /* Return the current pc, adjusted backwards by 2 if
3511 the previous instruction was an extend. */
3512 return pc
- prev_extend_bytes
;
3518 /* To skip prologues, I use this predicate. Returns either PC itself
3519 if the code at PC does not look like a function prologue; otherwise
3520 returns an address that (if we're lucky) follows the prologue. If
3521 LENIENT, then we must skip everything which is involved in setting
3522 up the frame (it's OK to skip more, just so long as we don't skip
3523 anything which might clobber the registers which are being saved.
3524 We must skip more in the case where part of the prologue is in the
3525 delay slot of a non-prologue instruction). */
3528 mips_skip_prologue (CORE_ADDR pc
)
3530 /* See if we can determine the end of the prologue via the symbol table.
3531 If so, then return either PC, or the PC after the prologue, whichever
3534 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3536 if (post_prologue_pc
!= 0)
3537 return max (pc
, post_prologue_pc
);
3539 /* Can't determine prologue from the symbol table, need to examine
3542 if (pc_is_mips16 (pc
))
3543 return mips16_skip_prologue (pc
);
3545 return mips32_skip_prologue (pc
);
3548 /* Determine how a return value is stored within the MIPS register
3549 file, given the return type `valtype'. */
3551 struct return_value_word
3560 return_value_location (struct type
*valtype
,
3561 struct return_value_word
*hi
,
3562 struct return_value_word
*lo
)
3564 int len
= TYPE_LENGTH (valtype
);
3566 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3567 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3568 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3570 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3572 /* We need to break a 64bit float in two 32 bit halves and
3573 spread them across a floating-point register pair. */
3574 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3575 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3576 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3577 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3579 hi
->reg_offset
= lo
->reg_offset
;
3580 lo
->reg
= FP0_REGNUM
+ 0;
3581 hi
->reg
= FP0_REGNUM
+ 1;
3587 /* The floating point value fits in a single floating-point
3589 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3590 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3593 lo
->reg
= FP0_REGNUM
;
3604 /* Locate a result possibly spread across two registers. */
3606 lo
->reg
= regnum
+ 0;
3607 hi
->reg
= regnum
+ 1;
3608 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3609 && len
< MIPS_SAVED_REGSIZE
)
3611 /* "un-left-justify" the value in the low register */
3612 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3617 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3618 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3619 && len
< MIPS_SAVED_REGSIZE
* 2
3620 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3621 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3623 /* "un-left-justify" the value spread across two registers. */
3624 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3625 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3627 hi
->len
= len
- lo
->len
;
3631 /* Only perform a partial copy of the second register. */
3634 if (len
> MIPS_SAVED_REGSIZE
)
3636 lo
->len
= MIPS_SAVED_REGSIZE
;
3637 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3645 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3646 && REGISTER_RAW_SIZE (regnum
) == 8
3647 && MIPS_SAVED_REGSIZE
== 4)
3649 /* Account for the fact that only the least-signficant part
3650 of the register is being used */
3651 lo
->reg_offset
+= 4;
3652 hi
->reg_offset
+= 4;
3655 hi
->buf_offset
= lo
->len
;
3659 /* Given a return value in `regbuf' with a type `valtype', extract and
3660 copy its value into `valbuf'. */
3663 mips_extract_return_value (struct type
*valtype
,
3664 char regbuf
[REGISTER_BYTES
],
3667 struct return_value_word lo
;
3668 struct return_value_word hi
;
3669 return_value_location (valtype
, &hi
, &lo
);
3671 memcpy (valbuf
+ lo
.buf_offset
,
3672 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3676 memcpy (valbuf
+ hi
.buf_offset
,
3677 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3681 /* Given a return value in `valbuf' with a type `valtype', write it's
3682 value into the appropriate register. */
3685 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3687 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3688 struct return_value_word lo
;
3689 struct return_value_word hi
;
3690 return_value_location (valtype
, &hi
, &lo
);
3692 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3693 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3694 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3696 REGISTER_RAW_SIZE (lo
.reg
));
3700 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3701 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3702 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3704 REGISTER_RAW_SIZE (hi
.reg
));
3708 /* Exported procedure: Is PC in the signal trampoline code */
3711 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3713 if (sigtramp_address
== 0)
3715 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3718 /* Root of all "set mips "/"show mips " commands. This will eventually be
3719 used for all MIPS-specific commands. */
3722 show_mips_command (char *args
, int from_tty
)
3724 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3728 set_mips_command (char *args
, int from_tty
)
3730 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3731 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3734 /* Commands to show/set the MIPS FPU type. */
3737 show_mipsfpu_command (char *args
, int from_tty
)
3740 switch (MIPS_FPU_TYPE
)
3742 case MIPS_FPU_SINGLE
:
3743 fpu
= "single-precision";
3745 case MIPS_FPU_DOUBLE
:
3746 fpu
= "double-precision";
3749 fpu
= "absent (none)";
3752 internal_error (__FILE__
, __LINE__
, "bad switch");
3754 if (mips_fpu_type_auto
)
3755 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3758 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3764 set_mipsfpu_command (char *args
, int from_tty
)
3766 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3767 show_mipsfpu_command (args
, from_tty
);
3771 set_mipsfpu_single_command (char *args
, int from_tty
)
3773 mips_fpu_type
= MIPS_FPU_SINGLE
;
3774 mips_fpu_type_auto
= 0;
3775 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3779 set_mipsfpu_double_command (char *args
, int from_tty
)
3781 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3782 mips_fpu_type_auto
= 0;
3783 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3787 set_mipsfpu_none_command (char *args
, int from_tty
)
3789 mips_fpu_type
= MIPS_FPU_NONE
;
3790 mips_fpu_type_auto
= 0;
3791 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3795 set_mipsfpu_auto_command (char *args
, int from_tty
)
3797 mips_fpu_type_auto
= 1;
3800 /* Command to set the processor type. */
3803 mips_set_processor_type_command (char *args
, int from_tty
)
3807 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3809 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3810 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3811 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3813 /* Restore the value. */
3814 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3819 if (!mips_set_processor_type (tmp_mips_processor_type
))
3821 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3822 /* Restore its value. */
3823 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3828 mips_show_processor_type_command (char *args
, int from_tty
)
3832 /* Modify the actual processor type. */
3835 mips_set_processor_type (char *str
)
3842 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3844 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3846 mips_processor_type
= str
;
3847 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3849 /* FIXME tweak fpu flag too */
3856 /* Attempt to identify the particular processor model by reading the
3860 mips_read_processor_type (void)
3864 prid
= read_register (PRID_REGNUM
);
3866 if ((prid
& ~0xf) == 0x700)
3867 return savestring ("r3041", strlen ("r3041"));
3872 /* Just like reinit_frame_cache, but with the right arguments to be
3873 callable as an sfunc. */
3876 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3877 struct cmd_list_element
*c
)
3879 reinit_frame_cache ();
3883 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3885 mips_extra_func_info_t proc_desc
;
3887 /* Search for the function containing this address. Set the low bit
3888 of the address when searching, in case we were given an even address
3889 that is the start of a 16-bit function. If we didn't do this,
3890 the search would fail because the symbol table says the function
3891 starts at an odd address, i.e. 1 byte past the given address. */
3892 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3893 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3895 /* Make an attempt to determine if this is a 16-bit function. If
3896 the procedure descriptor exists and the address therein is odd,
3897 it's definitely a 16-bit function. Otherwise, we have to just
3898 guess that if the address passed in is odd, it's 16-bits. */
3900 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3901 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3903 info
->mach
= pc_is_mips16 (memaddr
) ?
3904 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3906 /* Round down the instruction address to the appropriate boundary. */
3907 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3909 /* Call the appropriate disassembler based on the target endian-ness. */
3910 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3911 return print_insn_big_mips (memaddr
, info
);
3913 return print_insn_little_mips (memaddr
, info
);
3916 /* Old-style breakpoint macros.
3917 The IDT board uses an unusual breakpoint value, and sometimes gets
3918 confused when it sees the usual MIPS breakpoint instruction. */
3920 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3921 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3922 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3923 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3924 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3925 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3926 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3927 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3929 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3930 counter value to determine whether a 16- or 32-bit breakpoint should be
3931 used. It returns a pointer to a string of bytes that encode a breakpoint
3932 instruction, stores the length of the string to *lenptr, and adjusts pc
3933 (if necessary) to point to the actual memory location where the
3934 breakpoint should be inserted. */
3936 const unsigned char *
3937 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3939 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3941 if (pc_is_mips16 (*pcptr
))
3943 static unsigned char mips16_big_breakpoint
[] =
3944 MIPS16_BIG_BREAKPOINT
;
3945 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3946 *lenptr
= sizeof (mips16_big_breakpoint
);
3947 return mips16_big_breakpoint
;
3951 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3952 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3953 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3955 *lenptr
= sizeof (big_breakpoint
);
3957 if (strcmp (target_shortname
, "mips") == 0)
3958 return idt_big_breakpoint
;
3959 else if (strcmp (target_shortname
, "ddb") == 0
3960 || strcmp (target_shortname
, "pmon") == 0
3961 || strcmp (target_shortname
, "lsi") == 0)
3962 return pmon_big_breakpoint
;
3964 return big_breakpoint
;
3969 if (pc_is_mips16 (*pcptr
))
3971 static unsigned char mips16_little_breakpoint
[] =
3972 MIPS16_LITTLE_BREAKPOINT
;
3973 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3974 *lenptr
= sizeof (mips16_little_breakpoint
);
3975 return mips16_little_breakpoint
;
3979 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3980 static unsigned char pmon_little_breakpoint
[] =
3981 PMON_LITTLE_BREAKPOINT
;
3982 static unsigned char idt_little_breakpoint
[] =
3983 IDT_LITTLE_BREAKPOINT
;
3985 *lenptr
= sizeof (little_breakpoint
);
3987 if (strcmp (target_shortname
, "mips") == 0)
3988 return idt_little_breakpoint
;
3989 else if (strcmp (target_shortname
, "ddb") == 0
3990 || strcmp (target_shortname
, "pmon") == 0
3991 || strcmp (target_shortname
, "lsi") == 0)
3992 return pmon_little_breakpoint
;
3994 return little_breakpoint
;
3999 /* If PC is in a mips16 call or return stub, return the address of the target
4000 PC, which is either the callee or the caller. There are several
4001 cases which must be handled:
4003 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4004 target PC is in $31 ($ra).
4005 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4006 and the target PC is in $2.
4007 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4008 before the jal instruction, this is effectively a call stub
4009 and the the target PC is in $2. Otherwise this is effectively
4010 a return stub and the target PC is in $18.
4012 See the source code for the stubs in gcc/config/mips/mips16.S for
4015 This function implements the SKIP_TRAMPOLINE_CODE macro.
4019 mips_skip_stub (CORE_ADDR pc
)
4022 CORE_ADDR start_addr
;
4024 /* Find the starting address and name of the function containing the PC. */
4025 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4028 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4029 target PC is in $31 ($ra). */
4030 if (strcmp (name
, "__mips16_ret_sf") == 0
4031 || strcmp (name
, "__mips16_ret_df") == 0)
4032 return read_signed_register (RA_REGNUM
);
4034 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4036 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4037 and the target PC is in $2. */
4038 if (name
[19] >= '0' && name
[19] <= '9')
4039 return read_signed_register (2);
4041 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4042 before the jal instruction, this is effectively a call stub
4043 and the the target PC is in $2. Otherwise this is effectively
4044 a return stub and the target PC is in $18. */
4045 else if (name
[19] == 's' || name
[19] == 'd')
4047 if (pc
== start_addr
)
4049 /* Check if the target of the stub is a compiler-generated
4050 stub. Such a stub for a function bar might have a name
4051 like __fn_stub_bar, and might look like this:
4056 la $1,bar (becomes a lui/addiu pair)
4058 So scan down to the lui/addi and extract the target
4059 address from those two instructions. */
4061 CORE_ADDR target_pc
= read_signed_register (2);
4065 /* See if the name of the target function is __fn_stub_*. */
4066 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
4068 if (strncmp (name
, "__fn_stub_", 10) != 0
4069 && strcmp (name
, "etext") != 0
4070 && strcmp (name
, "_etext") != 0)
4073 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4074 The limit on the search is arbitrarily set to 20
4075 instructions. FIXME. */
4076 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
4078 inst
= mips_fetch_instruction (target_pc
);
4079 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4080 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4081 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4082 return pc
| (inst
& 0xffff); /* low word */
4085 /* Couldn't find the lui/addui pair, so return stub address. */
4089 /* This is the 'return' part of a call stub. The return
4090 address is in $r18. */
4091 return read_signed_register (18);
4094 return 0; /* not a stub */
4098 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4099 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4102 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4104 CORE_ADDR start_addr
;
4106 /* Find the starting address of the function containing the PC. If the
4107 caller didn't give us a name, look it up at the same time. */
4108 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
4111 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4113 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4114 if (name
[19] >= '0' && name
[19] <= '9')
4116 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4117 before the jal instruction, this is effectively a call stub. */
4118 else if (name
[19] == 's' || name
[19] == 'd')
4119 return pc
== start_addr
;
4122 return 0; /* not a stub */
4126 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4127 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4130 mips_in_return_stub (CORE_ADDR pc
, char *name
)
4132 CORE_ADDR start_addr
;
4134 /* Find the starting address of the function containing the PC. */
4135 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4138 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4139 if (strcmp (name
, "__mips16_ret_sf") == 0
4140 || strcmp (name
, "__mips16_ret_df") == 0)
4143 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4144 i.e. after the jal instruction, this is effectively a return stub. */
4145 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4146 && (name
[19] == 's' || name
[19] == 'd')
4147 && pc
!= start_addr
)
4150 return 0; /* not a stub */
4154 /* Return non-zero if the PC is in a library helper function that should
4155 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4158 mips_ignore_helper (CORE_ADDR pc
)
4162 /* Find the starting address and name of the function containing the PC. */
4163 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4166 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4167 that we want to ignore. */
4168 return (strcmp (name
, "__mips16_ret_sf") == 0
4169 || strcmp (name
, "__mips16_ret_df") == 0);
4173 /* Return a location where we can set a breakpoint that will be hit
4174 when an inferior function call returns. This is normally the
4175 program's entry point. Executables that don't have an entry
4176 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4177 whose address is the location where the breakpoint should be placed. */
4180 mips_call_dummy_address (void)
4182 struct minimal_symbol
*sym
;
4184 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
4186 return SYMBOL_VALUE_ADDRESS (sym
);
4188 return entry_point_address ();
4192 /* If the current gcc for this target does not produce correct debugging
4193 information for float parameters, both prototyped and unprototyped, then
4194 define this macro. This forces gdb to always assume that floats are
4195 passed as doubles and then converted in the callee.
4197 For the mips chip, it appears that the debug info marks the parameters as
4198 floats regardless of whether the function is prototyped, but the actual
4199 values are passed as doubles for the non-prototyped case and floats for
4200 the prototyped case. Thus we choose to make the non-prototyped case work
4201 for C and break the prototyped case, since the non-prototyped case is
4202 probably much more common. (FIXME). */
4205 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4207 return current_language
->la_language
== language_c
;
4210 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4211 the register stored on the stack (32) is different to its real raw
4212 size (64). The below ensures that registers are fetched from the
4213 stack using their ABI size and then stored into the RAW_BUFFER
4214 using their raw size.
4216 The alternative to adding this function would be to add an ABI
4217 macro - REGISTER_STACK_SIZE(). */
4220 mips_get_saved_register (char *raw_buffer
,
4223 struct frame_info
*frame
,
4225 enum lval_type
*lval
)
4229 if (!target_has_registers
)
4230 error ("No registers.");
4232 /* Normal systems don't optimize out things with register numbers. */
4233 if (optimized
!= NULL
)
4235 addr
= find_saved_register (frame
, regnum
);
4239 *lval
= lval_memory
;
4240 if (regnum
== SP_REGNUM
)
4242 if (raw_buffer
!= NULL
)
4244 /* Put it back in target format. */
4245 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4252 if (raw_buffer
!= NULL
)
4256 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4258 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4260 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4261 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4267 *lval
= lval_register
;
4268 addr
= REGISTER_BYTE (regnum
);
4269 if (raw_buffer
!= NULL
)
4270 read_register_gen (regnum
, raw_buffer
);
4276 /* Immediately after a function call, return the saved pc.
4277 Can't always go through the frames for this because on some machines
4278 the new frame is not set up until the new function executes
4279 some instructions. */
4282 mips_saved_pc_after_call (struct frame_info
*frame
)
4284 return read_signed_register (RA_REGNUM
);
4288 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4292 mips_stab_reg_to_regnum (int num
)
4297 return num
+ FP0_REGNUM
- 38;
4300 /* Convert a ecoff register number to a gdb REGNUM */
4303 mips_ecoff_reg_to_regnum (int num
)
4308 return num
+ FP0_REGNUM
- 32;
4311 /* Convert an integer into an address. By first converting the value
4312 into a pointer and then extracting it signed, the address is
4313 guarenteed to be correctly sign extended. */
4316 mips_integer_to_address (struct type
*type
, void *buf
)
4318 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4319 LONGEST val
= unpack_long (type
, buf
);
4320 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4321 return extract_signed_integer (tmp
,
4322 TYPE_LENGTH (builtin_type_void_data_ptr
));
4326 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4328 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4329 const char *name
= bfd_get_section_name (abfd
, sect
);
4331 if (*abip
!= MIPS_ABI_UNKNOWN
)
4334 if (strncmp (name
, ".mdebug.", 8) != 0)
4337 if (strcmp (name
, ".mdebug.abi32") == 0)
4338 *abip
= MIPS_ABI_O32
;
4339 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4340 *abip
= MIPS_ABI_N32
;
4341 else if (strcmp (name
, ".mdebug.abiN64") == 0)
4342 *abip
= MIPS_ABI_N64
;
4343 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4344 *abip
= MIPS_ABI_O64
;
4345 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4346 *abip
= MIPS_ABI_EABI32
;
4347 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4348 *abip
= MIPS_ABI_EABI64
;
4350 warning ("unsupported ABI %s.", name
+ 8);
4353 static enum mips_abi
4354 global_mips_abi (void)
4358 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4359 if (mips_abi_strings
[i
] == mips_abi_string
)
4360 return (enum mips_abi
) i
;
4362 internal_error (__FILE__
, __LINE__
,
4363 "unknown ABI string");
4366 static struct gdbarch
*
4367 mips_gdbarch_init (struct gdbarch_info info
,
4368 struct gdbarch_list
*arches
)
4370 static LONGEST mips_call_dummy_words
[] =
4372 struct gdbarch
*gdbarch
;
4373 struct gdbarch_tdep
*tdep
;
4375 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4376 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4378 /* Reset the disassembly info, in case it was set to something
4380 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4381 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4382 tm_print_insn_info
.mach
= 0;
4388 /* First of all, extract the elf_flags, if available. */
4389 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4390 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4392 /* Try to determine the OS ABI of the object we are loading. If
4393 we end up with `unknown', just leave it that way. */
4394 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4397 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4398 switch ((elf_flags
& EF_MIPS_ABI
))
4400 case E_MIPS_ABI_O32
:
4401 mips_abi
= MIPS_ABI_O32
;
4403 case E_MIPS_ABI_O64
:
4404 mips_abi
= MIPS_ABI_O64
;
4406 case E_MIPS_ABI_EABI32
:
4407 mips_abi
= MIPS_ABI_EABI32
;
4409 case E_MIPS_ABI_EABI64
:
4410 mips_abi
= MIPS_ABI_EABI64
;
4413 if ((elf_flags
& EF_MIPS_ABI2
))
4414 mips_abi
= MIPS_ABI_N32
;
4416 mips_abi
= MIPS_ABI_UNKNOWN
;
4420 /* GCC creates a pseudo-section whose name describes the ABI. */
4421 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4422 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4424 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4425 Use the ABI from the last architecture if there is one. */
4426 if (info
.abfd
== NULL
&& arches
!= NULL
)
4427 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4429 /* Try the architecture for any hint of the correct ABI. */
4430 if (mips_abi
== MIPS_ABI_UNKNOWN
4431 && info
.bfd_arch_info
!= NULL
4432 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4434 switch (info
.bfd_arch_info
->mach
)
4436 case bfd_mach_mips3900
:
4437 mips_abi
= MIPS_ABI_EABI32
;
4439 case bfd_mach_mips4100
:
4440 case bfd_mach_mips5000
:
4441 mips_abi
= MIPS_ABI_EABI64
;
4443 case bfd_mach_mips8000
:
4444 case bfd_mach_mips10000
:
4445 /* On Irix, ELF64 executables use the N64 ABI. The
4446 pseudo-sections which describe the ABI aren't present
4447 on IRIX. (Even for executables created by gcc.) */
4448 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4449 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4450 mips_abi
= MIPS_ABI_N64
;
4452 mips_abi
= MIPS_ABI_N32
;
4457 #ifdef MIPS_DEFAULT_ABI
4458 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4459 mips_abi
= MIPS_DEFAULT_ABI
;
4462 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4463 mips_abi
= MIPS_ABI_O32
;
4465 /* Now that we have found what the ABI for this binary would be,
4466 check whether the user is overriding it. */
4467 found_abi
= mips_abi
;
4468 wanted_abi
= global_mips_abi ();
4469 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4470 mips_abi
= wanted_abi
;
4474 fprintf_unfiltered (gdb_stdlog
,
4475 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4477 fprintf_unfiltered (gdb_stdlog
,
4478 "mips_gdbarch_init: mips_abi = %d\n",
4480 fprintf_unfiltered (gdb_stdlog
,
4481 "mips_gdbarch_init: found_mips_abi = %d\n",
4485 /* try to find a pre-existing architecture */
4486 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4488 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4490 /* MIPS needs to be pedantic about which ABI the object is
4492 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4494 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4496 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
4497 return arches
->gdbarch
;
4500 /* Need a new architecture. Fill in a target specific vector. */
4501 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4502 gdbarch
= gdbarch_alloc (&info
, tdep
);
4503 tdep
->elf_flags
= elf_flags
;
4504 tdep
->osabi
= osabi
;
4506 /* Initially set everything according to the default ABI/ISA. */
4507 set_gdbarch_short_bit (gdbarch
, 16);
4508 set_gdbarch_int_bit (gdbarch
, 32);
4509 set_gdbarch_float_bit (gdbarch
, 32);
4510 set_gdbarch_double_bit (gdbarch
, 64);
4511 set_gdbarch_long_double_bit (gdbarch
, 64);
4512 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4513 tdep
->found_abi
= found_abi
;
4514 tdep
->mips_abi
= mips_abi
;
4519 tdep
->mips_default_saved_regsize
= 4;
4520 tdep
->mips_default_stack_argsize
= 4;
4521 tdep
->mips_fp_register_double
= 0;
4522 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4523 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4524 tdep
->mips_regs_have_home_p
= 1;
4525 tdep
->gdb_target_is_mips64
= 0;
4526 tdep
->default_mask_address_p
= 0;
4527 set_gdbarch_long_bit (gdbarch
, 32);
4528 set_gdbarch_ptr_bit (gdbarch
, 32);
4529 set_gdbarch_long_long_bit (gdbarch
, 64);
4530 set_gdbarch_reg_struct_has_addr (gdbarch
,
4531 mips_o32_reg_struct_has_addr
);
4532 set_gdbarch_use_struct_convention (gdbarch
,
4533 mips_o32_use_struct_convention
);
4536 tdep
->mips_default_saved_regsize
= 8;
4537 tdep
->mips_default_stack_argsize
= 8;
4538 tdep
->mips_fp_register_double
= 1;
4539 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4540 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4541 tdep
->mips_regs_have_home_p
= 1;
4542 tdep
->gdb_target_is_mips64
= 1;
4543 tdep
->default_mask_address_p
= 0;
4544 set_gdbarch_long_bit (gdbarch
, 32);
4545 set_gdbarch_ptr_bit (gdbarch
, 32);
4546 set_gdbarch_long_long_bit (gdbarch
, 64);
4547 set_gdbarch_reg_struct_has_addr (gdbarch
,
4548 mips_o32_reg_struct_has_addr
);
4549 set_gdbarch_use_struct_convention (gdbarch
,
4550 mips_o32_use_struct_convention
);
4552 case MIPS_ABI_EABI32
:
4553 tdep
->mips_default_saved_regsize
= 4;
4554 tdep
->mips_default_stack_argsize
= 4;
4555 tdep
->mips_fp_register_double
= 0;
4556 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4557 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4558 tdep
->mips_regs_have_home_p
= 0;
4559 tdep
->gdb_target_is_mips64
= 0;
4560 tdep
->default_mask_address_p
= 0;
4561 set_gdbarch_long_bit (gdbarch
, 32);
4562 set_gdbarch_ptr_bit (gdbarch
, 32);
4563 set_gdbarch_long_long_bit (gdbarch
, 64);
4564 set_gdbarch_reg_struct_has_addr (gdbarch
,
4565 mips_eabi_reg_struct_has_addr
);
4566 set_gdbarch_use_struct_convention (gdbarch
,
4567 mips_eabi_use_struct_convention
);
4569 case MIPS_ABI_EABI64
:
4570 tdep
->mips_default_saved_regsize
= 8;
4571 tdep
->mips_default_stack_argsize
= 8;
4572 tdep
->mips_fp_register_double
= 1;
4573 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4574 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4575 tdep
->mips_regs_have_home_p
= 0;
4576 tdep
->gdb_target_is_mips64
= 1;
4577 tdep
->default_mask_address_p
= 0;
4578 set_gdbarch_long_bit (gdbarch
, 64);
4579 set_gdbarch_ptr_bit (gdbarch
, 64);
4580 set_gdbarch_long_long_bit (gdbarch
, 64);
4581 set_gdbarch_reg_struct_has_addr (gdbarch
,
4582 mips_eabi_reg_struct_has_addr
);
4583 set_gdbarch_use_struct_convention (gdbarch
,
4584 mips_eabi_use_struct_convention
);
4587 tdep
->mips_default_saved_regsize
= 8;
4588 tdep
->mips_default_stack_argsize
= 8;
4589 tdep
->mips_fp_register_double
= 1;
4590 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4591 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4592 tdep
->mips_regs_have_home_p
= 0;
4593 tdep
->gdb_target_is_mips64
= 1;
4594 tdep
->default_mask_address_p
= 0;
4595 set_gdbarch_long_bit (gdbarch
, 32);
4596 set_gdbarch_ptr_bit (gdbarch
, 32);
4597 set_gdbarch_long_long_bit (gdbarch
, 64);
4599 /* Set up the disassembler info, so that we get the right
4600 register names from libopcodes. */
4601 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4602 tm_print_insn_info
.arch
= bfd_arch_mips
;
4603 if (info
.bfd_arch_info
!= NULL
4604 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4605 && info
.bfd_arch_info
->mach
)
4606 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4608 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4610 set_gdbarch_use_struct_convention (gdbarch
,
4611 mips_n32n64_use_struct_convention
);
4612 set_gdbarch_reg_struct_has_addr (gdbarch
,
4613 mips_n32n64_reg_struct_has_addr
);
4616 tdep
->mips_default_saved_regsize
= 8;
4617 tdep
->mips_default_stack_argsize
= 8;
4618 tdep
->mips_fp_register_double
= 1;
4619 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4620 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4621 tdep
->mips_regs_have_home_p
= 0;
4622 tdep
->gdb_target_is_mips64
= 1;
4623 tdep
->default_mask_address_p
= 0;
4624 set_gdbarch_long_bit (gdbarch
, 64);
4625 set_gdbarch_ptr_bit (gdbarch
, 64);
4626 set_gdbarch_long_long_bit (gdbarch
, 64);
4628 /* Set up the disassembler info, so that we get the right
4629 register names from libopcodes. */
4630 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4631 tm_print_insn_info
.arch
= bfd_arch_mips
;
4632 if (info
.bfd_arch_info
!= NULL
4633 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4634 && info
.bfd_arch_info
->mach
)
4635 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4637 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4639 set_gdbarch_use_struct_convention (gdbarch
,
4640 mips_n32n64_use_struct_convention
);
4641 set_gdbarch_reg_struct_has_addr (gdbarch
,
4642 mips_n32n64_reg_struct_has_addr
);
4645 internal_error (__FILE__
, __LINE__
,
4646 "unknown ABI in switch");
4649 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4650 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4653 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4654 flag in object files because to do so would make it impossible to
4655 link with libraries compiled without "-gp32". This is
4656 unnecessarily restrictive.
4658 We could solve this problem by adding "-gp32" multilibs to gcc,
4659 but to set this flag before gcc is built with such multilibs will
4660 break too many systems.''
4662 But even more unhelpfully, the default linker output target for
4663 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4664 for 64-bit programs - you need to change the ABI to change this,
4665 and not all gcc targets support that currently. Therefore using
4666 this flag to detect 32-bit mode would do the wrong thing given
4667 the current gcc - it would make GDB treat these 64-bit programs
4668 as 32-bit programs by default. */
4670 /* enable/disable the MIPS FPU */
4671 if (!mips_fpu_type_auto
)
4672 tdep
->mips_fpu_type
= mips_fpu_type
;
4673 else if (info
.bfd_arch_info
!= NULL
4674 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4675 switch (info
.bfd_arch_info
->mach
)
4677 case bfd_mach_mips3900
:
4678 case bfd_mach_mips4100
:
4679 case bfd_mach_mips4111
:
4680 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4682 case bfd_mach_mips4650
:
4683 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4686 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4690 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4692 /* MIPS version of register names. NOTE: At present the MIPS
4693 register name management is part way between the old -
4694 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4695 Further work on it is required. */
4696 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4697 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4698 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4699 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4700 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4701 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4703 /* Add/remove bits from an address. The MIPS needs be careful to
4704 ensure that all 32 bit addresses are sign extended to 64 bits. */
4705 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4707 /* There's a mess in stack frame creation. See comments in
4708 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4709 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4710 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4712 /* Map debug register numbers onto internal register numbers. */
4713 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4714 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4716 /* Initialize a frame */
4717 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4719 /* MIPS version of CALL_DUMMY */
4721 set_gdbarch_call_dummy_p (gdbarch
, 1);
4722 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4723 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4724 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4725 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4726 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4727 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4728 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4729 set_gdbarch_call_dummy_length (gdbarch
, 0);
4730 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4731 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4732 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4733 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4734 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4735 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4736 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4738 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4739 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4741 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4742 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4743 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4745 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4746 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4748 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4749 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4750 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4752 /* There are MIPS targets which do not yet use this since they still
4753 define REGISTER_VIRTUAL_TYPE. */
4754 set_gdbarch_register_virtual_type (gdbarch
, mips_register_virtual_type
);
4756 /* Hook in OS ABI-specific overrides, if they have been registered. */
4757 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4763 mips_abi_update (char *ignore_args
, int from_tty
,
4764 struct cmd_list_element
*c
)
4766 struct gdbarch_info info
;
4768 /* Force the architecture to update, and (if it's a MIPS architecture)
4769 mips_gdbarch_init will take care of the rest. */
4770 gdbarch_info_init (&info
);
4771 gdbarch_update_p (info
);
4775 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4777 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4781 int ef_mips_32bitmode
;
4782 /* determine the ISA */
4783 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4801 /* determine the size of a pointer */
4802 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4803 fprintf_unfiltered (file
,
4804 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4806 fprintf_unfiltered (file
,
4807 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4809 fprintf_unfiltered (file
,
4810 "mips_dump_tdep: ef_mips_arch = %d\n",
4812 fprintf_unfiltered (file
,
4813 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4815 mips_abi_strings
[tdep
->mips_abi
]);
4816 fprintf_unfiltered (file
,
4817 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4818 mips_mask_address_p (),
4819 tdep
->default_mask_address_p
);
4821 fprintf_unfiltered (file
,
4822 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4823 FP_REGISTER_DOUBLE
);
4824 fprintf_unfiltered (file
,
4825 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4826 MIPS_DEFAULT_FPU_TYPE
,
4827 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4828 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4829 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4831 fprintf_unfiltered (file
,
4832 "mips_dump_tdep: MIPS_EABI = %d\n",
4834 fprintf_unfiltered (file
,
4835 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4836 MIPS_LAST_FP_ARG_REGNUM
,
4837 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4838 fprintf_unfiltered (file
,
4839 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4841 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4842 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4843 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4845 fprintf_unfiltered (file
,
4846 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4847 MIPS_DEFAULT_SAVED_REGSIZE
);
4848 fprintf_unfiltered (file
,
4849 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4850 FP_REGISTER_DOUBLE
);
4851 fprintf_unfiltered (file
,
4852 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4853 MIPS_REGS_HAVE_HOME_P
);
4854 fprintf_unfiltered (file
,
4855 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4856 MIPS_DEFAULT_STACK_ARGSIZE
);
4857 fprintf_unfiltered (file
,
4858 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4859 MIPS_STACK_ARGSIZE
);
4860 fprintf_unfiltered (file
,
4861 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4863 fprintf_unfiltered (file
,
4864 "mips_dump_tdep: A0_REGNUM = %d\n",
4866 fprintf_unfiltered (file
,
4867 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4868 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4869 fprintf_unfiltered (file
,
4870 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4871 XSTRING (ATTACH_DETACH
));
4872 fprintf_unfiltered (file
,
4873 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4875 fprintf_unfiltered (file
,
4876 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4877 fprintf_unfiltered (file
,
4878 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4880 fprintf_unfiltered (file
,
4881 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4883 fprintf_unfiltered (file
,
4884 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4886 fprintf_unfiltered (file
,
4887 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4888 XSTRING (DO_REGISTERS_INFO
));
4889 fprintf_unfiltered (file
,
4890 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4891 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4892 fprintf_unfiltered (file
,
4893 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4894 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4895 fprintf_unfiltered (file
,
4896 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4897 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4898 fprintf_unfiltered (file
,
4899 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4901 fprintf_unfiltered (file
,
4902 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4904 fprintf_unfiltered (file
,
4905 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4906 FIRST_EMBED_REGNUM
);
4907 fprintf_unfiltered (file
,
4908 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4910 fprintf_unfiltered (file
,
4911 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4912 GDB_TARGET_IS_MIPS64
);
4913 fprintf_unfiltered (file
,
4914 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4915 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4916 fprintf_unfiltered (file
,
4917 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4918 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4919 fprintf_unfiltered (file
,
4920 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4922 fprintf_unfiltered (file
,
4923 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4924 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4925 fprintf_unfiltered (file
,
4926 "mips_dump_tdep: HI_REGNUM = %d\n",
4928 fprintf_unfiltered (file
,
4929 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4930 fprintf_unfiltered (file
,
4931 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4932 fprintf_unfiltered (file
,
4933 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4934 XSTRING (IGNORE_HELPER_CALL (PC
)));
4935 fprintf_unfiltered (file
,
4936 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4937 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4938 fprintf_unfiltered (file
,
4939 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4940 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4941 fprintf_unfiltered (file
,
4942 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4943 fprintf_unfiltered (file
,
4944 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4946 fprintf_unfiltered (file
,
4947 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4948 fprintf_unfiltered (file
,
4949 "mips_dump_tdep: LO_REGNUM = %d\n",
4951 #ifdef MACHINE_CPROC_FP_OFFSET
4952 fprintf_unfiltered (file
,
4953 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4954 MACHINE_CPROC_FP_OFFSET
);
4956 #ifdef MACHINE_CPROC_PC_OFFSET
4957 fprintf_unfiltered (file
,
4958 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4959 MACHINE_CPROC_PC_OFFSET
);
4961 #ifdef MACHINE_CPROC_SP_OFFSET
4962 fprintf_unfiltered (file
,
4963 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4964 MACHINE_CPROC_SP_OFFSET
);
4966 fprintf_unfiltered (file
,
4967 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4968 fprintf_unfiltered (file
,
4969 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4970 fprintf_unfiltered (file
,
4971 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4973 fprintf_unfiltered (file
,
4974 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4975 fprintf_unfiltered (file
,
4976 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4977 fprintf_unfiltered (file
,
4978 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4979 fprintf_unfiltered (file
,
4980 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4982 fprintf_unfiltered (file
,
4983 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4984 MIPS_LAST_ARG_REGNUM
,
4985 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4986 fprintf_unfiltered (file
,
4987 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4989 fprintf_unfiltered (file
,
4990 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4991 fprintf_unfiltered (file
,
4992 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4993 MIPS_SAVED_REGSIZE
);
4994 fprintf_unfiltered (file
,
4995 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4996 fprintf_unfiltered (file
,
4997 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4998 XSTRING (MSYMBOL_SIZE (MSYM
)));
4999 fprintf_unfiltered (file
,
5000 "mips_dump_tdep: OP_LDFPR = used?\n");
5001 fprintf_unfiltered (file
,
5002 "mips_dump_tdep: OP_LDGPR = used?\n");
5003 fprintf_unfiltered (file
,
5004 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
5005 fprintf_unfiltered (file
,
5006 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
5007 fprintf_unfiltered (file
,
5008 "mips_dump_tdep: PRID_REGNUM = %d\n",
5010 fprintf_unfiltered (file
,
5011 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
5012 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
5013 fprintf_unfiltered (file
,
5014 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5015 fprintf_unfiltered (file
,
5016 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5017 fprintf_unfiltered (file
,
5018 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5019 fprintf_unfiltered (file
,
5020 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5021 fprintf_unfiltered (file
,
5022 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5023 fprintf_unfiltered (file
,
5024 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5025 fprintf_unfiltered (file
,
5026 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5027 fprintf_unfiltered (file
,
5028 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5029 fprintf_unfiltered (file
,
5030 "mips_dump_tdep: PROC_PC_REG = function?\n");
5031 fprintf_unfiltered (file
,
5032 "mips_dump_tdep: PROC_REG_MASK = function?\n");
5033 fprintf_unfiltered (file
,
5034 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5035 fprintf_unfiltered (file
,
5036 "mips_dump_tdep: PROC_SYMBOL = function?\n");
5037 fprintf_unfiltered (file
,
5038 "mips_dump_tdep: PS_REGNUM = %d\n",
5040 fprintf_unfiltered (file
,
5041 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
5043 fprintf_unfiltered (file
,
5044 "mips_dump_tdep: RA_REGNUM = %d\n",
5046 fprintf_unfiltered (file
,
5047 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
5048 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
5049 fprintf_unfiltered (file
,
5050 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
5051 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
5052 fprintf_unfiltered (file
,
5053 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
5054 fprintf_unfiltered (file
,
5055 "mips_dump_tdep: ROUND_DOWN = function?\n");
5056 fprintf_unfiltered (file
,
5057 "mips_dump_tdep: ROUND_UP = function?\n");
5059 fprintf_unfiltered (file
,
5060 "mips_dump_tdep: SAVED_BYTES = %d\n",
5064 fprintf_unfiltered (file
,
5065 "mips_dump_tdep: SAVED_FP = %d\n",
5069 fprintf_unfiltered (file
,
5070 "mips_dump_tdep: SAVED_PC = %d\n",
5073 fprintf_unfiltered (file
,
5074 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5075 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
5076 fprintf_unfiltered (file
,
5077 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
5078 fprintf_unfiltered (file
,
5079 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
5081 fprintf_unfiltered (file
,
5082 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
5083 SIGFRAME_FPREGSAVE_OFF
);
5084 fprintf_unfiltered (file
,
5085 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
5087 fprintf_unfiltered (file
,
5088 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
5089 SIGFRAME_REGSAVE_OFF
);
5090 fprintf_unfiltered (file
,
5091 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
5093 fprintf_unfiltered (file
,
5094 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5095 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
5096 fprintf_unfiltered (file
,
5097 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5098 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5099 fprintf_unfiltered (file
,
5100 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5101 SOFTWARE_SINGLE_STEP_P ());
5102 fprintf_unfiltered (file
,
5103 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5104 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5105 #ifdef STACK_END_ADDR
5106 fprintf_unfiltered (file
,
5107 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5110 fprintf_unfiltered (file
,
5111 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5112 XSTRING (STEP_SKIPS_DELAY (PC
)));
5113 fprintf_unfiltered (file
,
5114 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5115 STEP_SKIPS_DELAY_P
);
5116 fprintf_unfiltered (file
,
5117 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5118 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5119 fprintf_unfiltered (file
,
5120 "mips_dump_tdep: T9_REGNUM = %d\n",
5122 fprintf_unfiltered (file
,
5123 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5124 fprintf_unfiltered (file
,
5125 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5126 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
5127 fprintf_unfiltered (file
,
5128 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5129 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
5130 fprintf_unfiltered (file
,
5131 "mips_dump_tdep: TARGET_MIPS = used?\n");
5132 fprintf_unfiltered (file
,
5133 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5134 XSTRING (TM_PRINT_INSN_MACH
));
5136 fprintf_unfiltered (file
,
5137 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5138 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5141 fprintf_unfiltered (file
,
5142 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5145 #ifdef TRACE_FLAVOR_SIZE
5146 fprintf_unfiltered (file
,
5147 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5151 fprintf_unfiltered (file
,
5152 "mips_dump_tdep: TRACE_SET # %s\n",
5153 XSTRING (TRACE_SET (X
,STATE
)));
5155 fprintf_unfiltered (file
,
5156 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5157 #ifdef UNUSED_REGNUM
5158 fprintf_unfiltered (file
,
5159 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5162 fprintf_unfiltered (file
,
5163 "mips_dump_tdep: V0_REGNUM = %d\n",
5165 fprintf_unfiltered (file
,
5166 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5167 (long) VM_MIN_ADDRESS
);
5169 fprintf_unfiltered (file
,
5170 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5173 fprintf_unfiltered (file
,
5174 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5176 fprintf_unfiltered (file
,
5177 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5180 fprintf_unfiltered (file
,
5181 "mips_dump_tdep: OS ABI = %s\n",
5182 gdbarch_osabi_name (tdep
->osabi
));
5186 _initialize_mips_tdep (void)
5188 static struct cmd_list_element
*mipsfpulist
= NULL
;
5189 struct cmd_list_element
*c
;
5191 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5192 if (MIPS_ABI_LAST
+ 1
5193 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5194 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5196 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5197 if (!tm_print_insn
) /* Someone may have already set it */
5198 tm_print_insn
= gdb_print_insn_mips
;
5200 /* Add root prefix command for all "set mips"/"show mips" commands */
5201 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5202 "Various MIPS specific commands.",
5203 &setmipscmdlist
, "set mips ", 0, &setlist
);
5205 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5206 "Various MIPS specific commands.",
5207 &showmipscmdlist
, "show mips ", 0, &showlist
);
5209 /* Allow the user to override the saved register size. */
5210 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5213 &mips_saved_regsize_string
, "\
5214 Set size of general purpose registers saved on the stack.\n\
5215 This option can be set to one of:\n\
5216 32 - Force GDB to treat saved GP registers as 32-bit\n\
5217 64 - Force GDB to treat saved GP registers as 64-bit\n\
5218 auto - Allow GDB to use the target's default setting or autodetect the\n\
5219 saved GP register size from information contained in the executable.\n\
5224 /* Allow the user to override the argument stack size. */
5225 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5228 &mips_stack_argsize_string
, "\
5229 Set the amount of stack space reserved for each argument.\n\
5230 This option can be set to one of:\n\
5231 32 - Force GDB to allocate 32-bit chunks per argument\n\
5232 64 - Force GDB to allocate 64-bit chunks per argument\n\
5233 auto - Allow GDB to determine the correct setting from the current\n\
5234 target and executable (default)",
5238 /* Allow the user to override the ABI. */
5239 c
= add_set_enum_cmd
5240 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5241 "Set the ABI used by this program.\n"
5242 "This option can be set to one of:\n"
5243 " auto - the default ABI associated with the current binary\n"
5251 add_show_from_set (c
, &showmipscmdlist
);
5252 set_cmd_sfunc (c
, mips_abi_update
);
5254 /* Let the user turn off floating point and set the fence post for
5255 heuristic_proc_start. */
5257 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5258 "Set use of MIPS floating-point coprocessor.",
5259 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5260 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5261 "Select single-precision MIPS floating-point coprocessor.",
5263 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5264 "Select double-precision MIPS floating-point coprocessor.",
5266 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5267 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5268 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5269 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5270 "Select no MIPS floating-point coprocessor.",
5272 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5273 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5274 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5275 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5276 "Select MIPS floating-point coprocessor automatically.",
5278 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5279 "Show current use of MIPS floating-point coprocessor target.",
5282 /* We really would like to have both "0" and "unlimited" work, but
5283 command.c doesn't deal with that. So make it a var_zinteger
5284 because the user can always use "999999" or some such for unlimited. */
5285 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
5286 (char *) &heuristic_fence_post
,
5288 Set the distance searched for the start of a function.\n\
5289 If you are debugging a stripped executable, GDB needs to search through the\n\
5290 program for the start of a function. This command sets the distance of the\n\
5291 search. The only need to set it is when debugging a stripped executable.",
5293 /* We need to throw away the frame cache when we set this, since it
5294 might change our ability to get backtraces. */
5295 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5296 add_show_from_set (c
, &showlist
);
5298 /* Allow the user to control whether the upper bits of 64-bit
5299 addresses should be zeroed. */
5300 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5301 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5302 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5303 allow GDB to determine the correct value.\n", "\
5304 Show zeroing of upper 32 bits of 64-bit addresses.",
5305 NULL
, show_mask_address
,
5306 &setmipscmdlist
, &showmipscmdlist
);
5308 /* Allow the user to control the size of 32 bit registers within the
5309 raw remote packet. */
5310 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5313 (char *)&mips64_transfers_32bit_regs_p
, "\
5314 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5315 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5316 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5317 64 bits for others. Use \"off\" to disable compatibility mode",
5321 /* Debug this files internals. */
5322 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5323 &mips_debug
, "Set mips debugging.\n\
5324 When non-zero, mips specific debugging is enabled.", &setdebuglist
),