gdb/nat/aarch64-linux-hw-point.c

   1 /* Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "common-defs.h"
  20 #include "break-common.h"
  21 #include "common-regcache.h"
  22 #include "nat/linux-nat.h"
  23 #include "aarch64-linux-hw-point.h"
  24
  25 #include <sys/uio.h>
  26 #include <asm/ptrace.h>
  27 #include <sys/ptrace.h>
  28 #include <elf.h>
  29
  30 /* Number of hardware breakpoints/watchpoints the target supports.
  31    They are initialized with values obtained via the ptrace calls
  32    with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively.  */
  33
  34 int aarch64_num_bp_regs;
  35 int aarch64_num_wp_regs;
  36
  37 /* Utility function that returns the length in bytes of a watchpoint
  38    according to the content of a hardware debug control register CTRL.
  39    Note that the kernel currently only supports the following Byte
  40    Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
  41    that for a hardware watchpoint, its valid length can only be 1
  42    byte, 2 bytes, 4 bytes or 8 bytes.  */
  43
  44 unsigned int
  45 aarch64_watchpoint_length (unsigned int ctrl)
  46 {
  47   switch (DR_CONTROL_LENGTH (ctrl))
  48     {
  49     case 0x01:
  50       return 1;
  51     case 0x03:
  52       return 2;
  53     case 0x0f:
  54       return 4;
  55     case 0xff:
  56       return 8;
  57     default:
  58       return 0;
  59     }
  60 }
  61
  62 /* Given the hardware breakpoint or watchpoint type TYPE and its
  63    length LEN, return the expected encoding for a hardware
  64    breakpoint/watchpoint control register.  */
  65
  66 static unsigned int
  67 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
  68 {
  69   unsigned int ctrl, ttype;
  70
  71   /* type */
  72   switch (type)
  73     {
  74     case hw_write:
  75       ttype = 2;
  76       break;
  77     case hw_read:
  78       ttype = 1;
  79       break;
  80     case hw_access:
  81       ttype = 3;
  82       break;
  83     case hw_execute:
  84       ttype = 0;
  85       break;
  86     default:
  87       perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
  88     }
  89
  90   ctrl = ttype << 3;
  91
  92   /* length bitmask */
  93   ctrl |= ((1 << len) - 1) << 5;
  94   /* enabled at el0 */
  95   ctrl |= (2 << 1) | 1;
  96
  97   return ctrl;
  98 }
  99
 100 /* Addresses to be written to the hardware breakpoint and watchpoint
 101    value registers need to be aligned; the alignment is 4-byte and
 102    8-type respectively.  Linux kernel rejects any non-aligned address
 103    it receives from the related ptrace call.  Furthermore, the kernel
 104    currently only supports the following Byte Address Select (BAS)
 105    values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
 106    watchpoint to be accepted by the kernel (via ptrace call), its
 107    valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
 108    Despite these limitations, the unaligned watchpoint is supported in
 109    this port.
 110
 111    Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise.  */
 112
 113 static int
 114 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
 115 {
 116   unsigned int alignment = 0;
 117
 118   if (is_watchpoint)
 119     alignment = AARCH64_HWP_ALIGNMENT;
 120   else
 121     {
 122       struct regcache *regcache
 123         = get_thread_regcache_for_ptid (current_lwp_ptid ());
 124
 125       /* Set alignment to 2 only if the current process is 32-bit,
 126          since thumb instruction can be 2-byte aligned.  Otherwise, set
 127          alignment to AARCH64_HBP_ALIGNMENT.  */
 128       if (regcache_register_size (regcache, 0) == 8)
 129         alignment = AARCH64_HBP_ALIGNMENT;
 130       else
 131         alignment = 2;
 132     }
 133
 134   if (addr & (alignment - 1))
 135     return 0;
 136
 137   if (len != 8 && len != 4 && len != 2 && len != 1)
 138     return 0;
 139
 140   return 1;
 141 }
 142
 143 /* Given the (potentially unaligned) watchpoint address in ADDR and
 144    length in LEN, return the aligned address and aligned length in
 145    *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively.  The returned
 146    aligned address and length will be valid values to write to the
 147    hardware watchpoint value and control registers.
 148
 149    The given watchpoint may get truncated if more than one hardware
 150    register is needed to cover the watched region.  *NEXT_ADDR_P
 151    and *NEXT_LEN_P, if non-NULL, will return the address and length
 152    of the remaining part of the watchpoint (which can be processed
 153    by calling this routine again to generate another aligned address
 154    and length pair.
 155
 156    Essentially, unaligned watchpoint is achieved by minimally
 157    enlarging the watched area to meet the alignment requirement, and
 158    if necessary, splitting the watchpoint over several hardware
 159    watchpoint registers.  The trade-off is that there will be
 160    false-positive hits for the read-type or the access-type hardware
 161    watchpoints; for the write type, which is more commonly used, there
 162    will be no such issues, as the higher-level breakpoint management
 163    in gdb always examines the exact watched region for any content
 164    change, and transparently resumes a thread from a watchpoint trap
 165    if there is no change to the watched region.
 166
 167    Another limitation is that because the watched region is enlarged,
 168    the watchpoint fault address returned by
 169    aarch64_stopped_data_address may be outside of the original watched
 170    region, especially when the triggering instruction is accessing a
 171    larger region.  When the fault address is not within any known
 172    range, watchpoints_triggered in gdb will get confused, as the
 173    higher-level watchpoint management is only aware of original
 174    watched regions, and will think that some unknown watchpoint has
 175    been triggered.  In such a case, gdb may stop without displaying
 176    any detailed information.
 177
 178    Once the kernel provides the full support for Byte Address Select
 179    (BAS) in the hardware watchpoint control register, these
 180    limitations can be largely relaxed with some further work.  */
 181
 182 static void
 183 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
 184                           int *aligned_len_p, CORE_ADDR *next_addr_p,
 185                           int *next_len_p)
 186 {
 187   int aligned_len;
 188   unsigned int offset;
 189   CORE_ADDR aligned_addr;
 190   const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
 191   const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
 192
 193   /* As assumed by the algorithm.  */
 194   gdb_assert (alignment == max_wp_len);
 195
 196   if (len <= 0)
 197     return;
 198
 199   /* Address to be put into the hardware watchpoint value register
 200      must be aligned.  */
 201   offset = addr & (alignment - 1);
 202   aligned_addr = addr - offset;
 203
 204   gdb_assert (offset >= 0 && offset < alignment);
 205   gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
 206   gdb_assert (offset + len > 0);
 207
 208   if (offset + len >= max_wp_len)
 209     {
 210       /* Need more than one watchpoint registers; truncate it at the
 211          alignment boundary.  */
 212       aligned_len = max_wp_len;
 213       len -= (max_wp_len - offset);
 214       addr += (max_wp_len - offset);
 215       gdb_assert ((addr & (alignment - 1)) == 0);
 216     }
 217   else
 218     {
 219       /* Find the smallest valid length that is large enough to
 220          accommodate this watchpoint.  */
 221       static const unsigned char
 222         aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
 223         { 1, 2, 4, 4, 8, 8, 8, 8 };
 224
 225       aligned_len = aligned_len_array[offset + len - 1];
 226       addr += len;
 227       len = 0;
 228     }
 229
 230   if (aligned_addr_p)
 231     *aligned_addr_p = aligned_addr;
 232   if (aligned_len_p)
 233     *aligned_len_p = aligned_len;
 234   if (next_addr_p)
 235     *next_addr_p = addr;
 236   if (next_len_p)
 237     *next_len_p = len;
 238 }
 239
 240 struct aarch64_dr_update_callback_param
 241 {
 242   int is_watchpoint;
 243   unsigned int idx;
 244 };
 245
 246 /* Callback for iterate_over_lwps.  Records the
 247    information about the change of one hardware breakpoint/watchpoint
 248    setting for the thread LWP.
 249    The information is passed in via PTR.
 250    N.B.  The actual updating of hardware debug registers is not
 251    carried out until the moment the thread is resumed.  */
 252
 253 static int
 254 debug_reg_change_callback (struct lwp_info *lwp, void *ptr)
 255 {
 256   struct aarch64_dr_update_callback_param *param_p
 257     = (struct aarch64_dr_update_callback_param *) ptr;
 258   int tid = ptid_get_lwp (ptid_of_lwp (lwp));
 259   int idx = param_p->idx;
 260   int is_watchpoint = param_p->is_watchpoint;
 261   struct arch_lwp_info *info = lwp_arch_private_info (lwp);
 262   dr_changed_t *dr_changed_ptr;
 263   dr_changed_t dr_changed;
 264
 265   if (info == NULL)
 266     {
 267       info = XCNEW (struct arch_lwp_info);
 268       lwp_set_arch_private_info (lwp, info);
 269     }
 270
 271   if (show_debug_regs)
 272     {
 273       debug_printf ("debug_reg_change_callback: \n\tOn entry:\n");
 274       debug_printf ("\ttid%d, dr_changed_bp=0x%s, "
 275                     "dr_changed_wp=0x%s\n", tid,
 276                     phex (info->dr_changed_bp, 8),
 277                     phex (info->dr_changed_wp, 8));
 278     }
 279
 280   dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
 281     : &info->dr_changed_bp;
 282   dr_changed = *dr_changed_ptr;
 283
 284   gdb_assert (idx >= 0
 285               && (idx <= (is_watchpoint ? aarch64_num_wp_regs
 286                           : aarch64_num_bp_regs)));
 287
 288   /* The actual update is done later just before resuming the lwp,
 289      we just mark that one register pair needs updating.  */
 290   DR_MARK_N_CHANGED (dr_changed, idx);
 291   *dr_changed_ptr = dr_changed;
 292
 293   /* If the lwp isn't stopped, force it to momentarily pause, so
 294      we can update its debug registers.  */
 295   if (!lwp_is_stopped (lwp))
 296     linux_stop_lwp (lwp);
 297
 298   if (show_debug_regs)
 299     {
 300       debug_printf ("\tOn exit:\n\ttid%d, dr_changed_bp=0x%s, "
 301                     "dr_changed_wp=0x%s\n", tid,
 302                     phex (info->dr_changed_bp, 8),
 303                     phex (info->dr_changed_wp, 8));
 304     }
 305
 306   return 0;
 307 }
 308
 309 /* Notify each thread that their IDXth breakpoint/watchpoint register
 310    pair needs to be updated.  The message will be recorded in each
 311    thread's arch-specific data area, the actual updating will be done
 312    when the thread is resumed.  */
 313
 314 static void
 315 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
 316                                  int is_watchpoint, unsigned int idx)
 317 {
 318   struct aarch64_dr_update_callback_param param;
 319   ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (current_lwp_ptid ()));
 320
 321   param.is_watchpoint = is_watchpoint;
 322   param.idx = idx;
 323
 324   iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) &param);
 325 }
 326
 327 /* Record the insertion of one breakpoint/watchpoint, as represented
 328    by ADDR and CTRL, in the process' arch-specific data area *STATE.  */
 329
 330 static int
 331 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
 332                                    enum target_hw_bp_type type,
 333                                    CORE_ADDR addr, int len)
 334 {
 335   int i, idx, num_regs, is_watchpoint;
 336   unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
 337   CORE_ADDR *dr_addr_p;
 338
 339   /* Set up state pointers.  */
 340   is_watchpoint = (type != hw_execute);
 341   gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
 342   if (is_watchpoint)
 343     {
 344       num_regs = aarch64_num_wp_regs;
 345       dr_addr_p = state->dr_addr_wp;
 346       dr_ctrl_p = state->dr_ctrl_wp;
 347       dr_ref_count = state->dr_ref_count_wp;
 348     }
 349   else
 350     {
 351       num_regs = aarch64_num_bp_regs;
 352       dr_addr_p = state->dr_addr_bp;
 353       dr_ctrl_p = state->dr_ctrl_bp;
 354       dr_ref_count = state->dr_ref_count_bp;
 355     }
 356
 357   ctrl = aarch64_point_encode_ctrl_reg (type, len);
 358
 359   /* Find an existing or free register in our cache.  */
 360   idx = -1;
 361   for (i = 0; i < num_regs; ++i)
 362     {
 363       if ((dr_ctrl_p[i] & 1) == 0)
 364         {
 365           gdb_assert (dr_ref_count[i] == 0);
 366           idx = i;
 367           /* no break; continue hunting for an exising one.  */
 368         }
 369       else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
 370         {
 371           gdb_assert (dr_ref_count[i] != 0);
 372           idx = i;
 373           break;
 374         }
 375     }
 376
 377   /* No space.  */
 378   if (idx == -1)
 379     return -1;
 380
 381   /* Update our cache.  */
 382   if ((dr_ctrl_p[idx] & 1) == 0)
 383     {
 384       /* new entry */
 385       dr_addr_p[idx] = addr;
 386       dr_ctrl_p[idx] = ctrl;
 387       dr_ref_count[idx] = 1;
 388       /* Notify the change.  */
 389       aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
 390     }
 391   else
 392     {
 393       /* existing entry */
 394       dr_ref_count[idx]++;
 395     }
 396
 397   return 0;
 398 }
 399
 400 /* Record the removal of one breakpoint/watchpoint, as represented by
 401    ADDR and CTRL, in the process' arch-specific data area *STATE.  */
 402
 403 static int
 404 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
 405                                    enum target_hw_bp_type type,
 406                                    CORE_ADDR addr, int len)
 407 {
 408   int i, num_regs, is_watchpoint;
 409   unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
 410   CORE_ADDR *dr_addr_p;
 411
 412   /* Set up state pointers.  */
 413   is_watchpoint = (type != hw_execute);
 414   gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
 415   if (is_watchpoint)
 416     {
 417       num_regs = aarch64_num_wp_regs;
 418       dr_addr_p = state->dr_addr_wp;
 419       dr_ctrl_p = state->dr_ctrl_wp;
 420       dr_ref_count = state->dr_ref_count_wp;
 421     }
 422   else
 423     {
 424       num_regs = aarch64_num_bp_regs;
 425       dr_addr_p = state->dr_addr_bp;
 426       dr_ctrl_p = state->dr_ctrl_bp;
 427       dr_ref_count = state->dr_ref_count_bp;
 428     }
 429
 430   ctrl = aarch64_point_encode_ctrl_reg (type, len);
 431
 432   /* Find the entry that matches the ADDR and CTRL.  */
 433   for (i = 0; i < num_regs; ++i)
 434     if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
 435       {
 436         gdb_assert (dr_ref_count[i] != 0);
 437         break;
 438       }
 439
 440   /* Not found.  */
 441   if (i == num_regs)
 442     return -1;
 443
 444   /* Clear our cache.  */
 445   if (--dr_ref_count[i] == 0)
 446     {
 447       /* Clear the enable bit.  */
 448       ctrl &= ~1;
 449       dr_addr_p[i] = 0;
 450       dr_ctrl_p[i] = ctrl;
 451       /* Notify the change.  */
 452       aarch64_notify_debug_reg_change (state, is_watchpoint, i);
 453     }
 454
 455   return 0;
 456 }
 457
 458 int
 459 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 460                            int len, int is_insert,
 461                            struct aarch64_debug_reg_state *state)
 462 {
 463   /* The hardware breakpoint on AArch64 should always be 4-byte
 464      aligned, but on AArch32, it can be 2-byte aligned.  */
 465   if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
 466     return -1;
 467
 468   if (is_insert)
 469     return aarch64_dr_state_insert_one_point (state, type, addr, len);
 470   else
 471     return aarch64_dr_state_remove_one_point (state, type, addr, len);
 472 }
 473
 474 /* This is essentially the same as aarch64_handle_breakpoint, apart
 475    from that it is an aligned watchpoint to be handled.  */
 476
 477 static int
 478 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
 479                                    CORE_ADDR addr, int len, int is_insert,
 480                                    struct aarch64_debug_reg_state *state)
 481 {
 482   if (is_insert)
 483     return aarch64_dr_state_insert_one_point (state, type, addr, len);
 484   else
 485     return aarch64_dr_state_remove_one_point (state, type, addr, len);
 486 }
 487
 488 /* Insert/remove unaligned watchpoint by calling
 489    aarch64_align_watchpoint repeatedly until the whole watched region,
 490    as represented by ADDR and LEN, has been properly aligned and ready
 491    to be written to one or more hardware watchpoint registers.
 492    IS_INSERT indicates whether this is an insertion or a deletion.
 493    Return 0 if succeed.  */
 494
 495 static int
 496 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
 497                                      CORE_ADDR addr, int len, int is_insert,
 498                                      struct aarch64_debug_reg_state *state)
 499 {
 500   while (len > 0)
 501     {
 502       CORE_ADDR aligned_addr;
 503       int aligned_len, ret;
 504
 505       aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
 506                                 &addr, &len);
 507
 508       if (is_insert)
 509         ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
 510                                                  aligned_len);
 511       else
 512         ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
 513                                                  aligned_len);
 514
 515       if (show_debug_regs)
 516         debug_printf ("handle_unaligned_watchpoint: is_insert: %d\n"
 517                       "                             "
 518                       "aligned_addr: %s, aligned_len: %d\n"
 519                       "                                "
 520                       "next_addr: %s,    next_len: %d\n",
 521                       is_insert, core_addr_to_string_nz (aligned_addr),
 522                       aligned_len, core_addr_to_string_nz (addr), len);
 523
 524       if (ret != 0)
 525         return ret;
 526     }
 527
 528   return 0;
 529 }
 530
 531 int
 532 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 533                            int len, int is_insert,
 534                            struct aarch64_debug_reg_state *state)
 535 {
 536   if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
 537     return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
 538                                               state);
 539   else
 540     return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
 541                                                 state);
 542 }
 543
 544 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
 545    registers with data from *STATE.  */
 546
 547 void
 548 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
 549                               int tid, int watchpoint)
 550 {
 551   int i, count;
 552   struct iovec iov;
 553   struct user_hwdebug_state regs;
 554   const CORE_ADDR *addr;
 555   const unsigned int *ctrl;
 556
 557   memset (&regs, 0, sizeof (regs));
 558   iov.iov_base = &regs;
 559   count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
 560   addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
 561   ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
 562   if (count == 0)
 563     return;
 564   iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
 565                  + sizeof (regs.dbg_regs [count - 1]));
 566
 567   for (i = 0; i < count; i++)
 568     {
 569       regs.dbg_regs[i].addr = addr[i];
 570       regs.dbg_regs[i].ctrl = ctrl[i];
 571     }
 572
 573   if (ptrace (PTRACE_SETREGSET, tid,
 574               watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
 575               (void *) &iov))
 576     error (_("Unexpected error setting hardware debug registers"));
 577 }
 578
 579 /* Print the values of the cached breakpoint/watchpoint registers.  */
 580
 581 void
 582 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
 583                               const char *func, CORE_ADDR addr,
 584                               int len, enum target_hw_bp_type type)
 585 {
 586   int i;
 587
 588   debug_printf ("%s", func);
 589   if (addr || len)
 590     debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
 591                   (unsigned long) addr, len,
 592                   type == hw_write ? "hw-write-watchpoint"
 593                   : (type == hw_read ? "hw-read-watchpoint"
 594                      : (type == hw_access ? "hw-access-watchpoint"
 595                         : (type == hw_execute ? "hw-breakpoint"
 596                            : "??unknown??"))));
 597   debug_printf (":\n");
 598
 599   debug_printf ("\tBREAKPOINTs:\n");
 600   for (i = 0; i < aarch64_num_bp_regs; i++)
 601     debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
 602                   i, core_addr_to_string_nz (state->dr_addr_bp[i]),
 603                   state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
 604
 605   debug_printf ("\tWATCHPOINTs:\n");
 606   for (i = 0; i < aarch64_num_wp_regs; i++)
 607     debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
 608                   i, core_addr_to_string_nz (state->dr_addr_wp[i]),
 609                   state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
 610 }
 611
 612 /* Get the hardware debug register capacity information from the
 613    process represented by TID.  */
 614
 615 void
 616 aarch64_linux_get_debug_reg_capacity (int tid)
 617 {
 618   struct iovec iov;
 619   struct user_hwdebug_state dreg_state;
 620
 621   iov.iov_base = &dreg_state;
 622   iov.iov_len = sizeof (dreg_state);
 623
 624   /* Get hardware watchpoint register info.  */
 625   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
 626       && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
 627     {
 628       aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
 629       if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
 630         {
 631           warning (_("Unexpected number of hardware watchpoint registers"
 632                      " reported by ptrace, got %d, expected %d."),
 633                    aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
 634           aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
 635         }
 636     }
 637   else
 638     {
 639       warning (_("Unable to determine the number of hardware watchpoints"
 640                  " available."));
 641       aarch64_num_wp_regs = 0;
 642     }
 643
 644   /* Get hardware breakpoint register info.  */
 645   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
 646       && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
 647     {
 648       aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
 649       if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
 650         {
 651           warning (_("Unexpected number of hardware breakpoint registers"
 652                      " reported by ptrace, got %d, expected %d."),
 653                    aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
 654           aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
 655         }
 656     }
 657   else
 658     {
 659       warning (_("Unable to determine the number of hardware breakpoints"
 660                  " available."));
 661       aarch64_num_bp_regs = 0;
 662     }
 663 }
 664
 665 /* Return true if we can watch a memory region that starts address
 666    ADDR and whose length is LEN in bytes.  */
 667
 668 int
 669 aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr, int len)
 670 {
 671   CORE_ADDR aligned_addr;
 672
 673   /* Can not set watchpoints for zero or negative lengths.  */
 674   if (len <= 0)
 675     return 0;
 676
 677   /* Must have hardware watchpoint debug register(s).  */
 678   if (aarch64_num_wp_regs == 0)
 679     return 0;
 680
 681   /* We support unaligned watchpoint address and arbitrary length,
 682      as long as the size of the whole watched area after alignment
 683      doesn't exceed size of the total area that all watchpoint debug
 684      registers can watch cooperatively.
 685
 686      This is a very relaxed rule, but unfortunately there are
 687      limitations, e.g. false-positive hits, due to limited support of
 688      hardware debug registers in the kernel.  See comment above
 689      aarch64_align_watchpoint for more information.  */
 690
 691   aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1);
 692   if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG
 693       < addr + len)
 694     return 0;
 695
 696   /* All tests passed so we are likely to be able to set the watchpoint.
 697      The reason that it is 'likely' rather than 'must' is because
 698      we don't check the current usage of the watchpoint registers, and
 699      there may not be enough registers available for this watchpoint.
 700      Ideally we should check the cached debug register state, however
 701      the checking is costly.  */
 702   return 1;
 703 }