gdb/nat/aarch64-linux-hw-point.h

   1 /* Copyright (C) 2009-2024 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef NAT_AARCH64_LINUX_HW_POINT_H
  20 #define NAT_AARCH64_LINUX_HW_POINT_H
  21
  22 #include "gdbsupport/break-common.h"
  23
  24 #include "nat/aarch64-hw-point.h"
  25
  26 /* ptrace hardware breakpoint resource info is formatted as follows:
  27
  28    31             24             16               8              0
  29    +---------------+--------------+---------------+---------------+
  30    |   RESERVED    |   RESERVED   |   DEBUG_ARCH  |  NUM_SLOTS    |
  31    +---------------+--------------+---------------+---------------+  */
  32
  33
  34 /* Macros to extract fields from the hardware debug information word.  */
  35 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
  36 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
  37
  38 /* Each bit of a variable of this type is used to indicate whether a
  39    hardware breakpoint or watchpoint setting has been changed since
  40    the last update.
  41
  42    Bit N corresponds to the Nth hardware breakpoint or watchpoint
  43    setting which is managed in aarch64_debug_reg_state, where N is
  44    valid between 0 and the total number of the hardware breakpoint or
  45    watchpoint debug registers minus 1.
  46
  47    When bit N is 1, the corresponding breakpoint or watchpoint setting
  48    has changed, and therefore the corresponding hardware debug
  49    register needs to be updated via the ptrace interface.
  50
  51    In the per-thread arch-specific data area, we define two such
  52    variables for per-thread hardware breakpoint and watchpoint
  53    settings respectively.
  54
  55    This type is part of the mechanism which helps reduce the number of
  56    ptrace calls to the kernel, i.e. avoid asking the kernel to write
  57    to the debug registers with unchanged values.  */
  58
  59 typedef ULONGEST dr_changed_t;
  60
  61 /* Set each of the lower M bits of X to 1; assert X is wide enough.  */
  62
  63 #define DR_MARK_ALL_CHANGED(x, m)                                       \
  64   do                                                                    \
  65     {                                                                   \
  66       gdb_assert (sizeof ((x)) * 8 >= (m));                             \
  67       (x) = (((dr_changed_t)1 << (m)) - 1);                             \
  68     } while (0)
  69
  70 #define DR_MARK_N_CHANGED(x, n)                                         \
  71   do                                                                    \
  72     {                                                                   \
  73       (x) |= ((dr_changed_t)1 << (n));                                  \
  74     } while (0)
  75
  76 #define DR_CLEAR_CHANGED(x)                                             \
  77   do                                                                    \
  78     {                                                                   \
  79       (x) = 0;                                                          \
  80     } while (0)
  81
  82 #define DR_HAS_CHANGED(x) ((x) != 0)
  83 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
  84
  85 /* Per-thread arch-specific data we want to keep.  */
  86
  87 struct arch_lwp_info
  88 {
  89   /* When bit N is 1, it indicates the Nth hardware breakpoint or
  90      watchpoint register pair needs to be updated when the thread is
  91      resumed; see aarch64_linux_prepare_to_resume.  */
  92   dr_changed_t dr_changed_bp;
  93   dr_changed_t dr_changed_wp;
  94 };
  95
  96 /* True if this kernel does not have the bug described by PR
  97    external/20207 (Linux >= 4.10).  A fixed kernel supports any
  98    contiguous range of bits in 8-bit byte DR_CONTROL_MASK.  A buggy
  99    kernel supports only 0x01, 0x03, 0x0f and 0xff.  We start by
 100    assuming the bug is fixed, and then detect the bug at
 101    PTRACE_SETREGSET time.  */
 102
 103 extern bool kernel_supports_any_contiguous_range;
 104
 105 void aarch64_linux_set_debug_regs (struct aarch64_debug_reg_state *state,
 106                                    int tid, int watchpoint);
 107
 108 void aarch64_linux_get_debug_reg_capacity (int tid);
 109
 110 struct aarch64_debug_reg_state *aarch64_get_debug_reg_state (pid_t pid);
 111
 112 #endif /* NAT_AARCH64_LINUX_HW_POINT_H */