1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2023 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2/frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
46 #include "features/nds32.c"
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
58 /* Use an invalid address value as 'not available' marker. */
59 enum { REG_UNAVAIL
= (CORE_ADDR
) -1 };
61 /* Use an impossible value as invalid offset. */
62 enum { INVALID_OFFSET
= (CORE_ADDR
) -1 };
64 /* Instruction groups for NDS32 epilogue analysis. */
67 /* Instructions used everywhere, not only in epilogue. */
69 /* Instructions used to reset sp for local vars, arguments, etc. */
71 /* Instructions used to recover saved regs and to recover padding. */
73 /* Instructions used to return to the caller. */
75 /* Instructions used to recover saved regs and to return to the caller. */
79 static const char *const nds32_register_names
[] =
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
90 static const char *const nds32_fdr_register_names
[] =
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98 static const char *const nds32_fsr_register_names
[] =
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106 /* The number of registers for four FPU configuration options. */
107 const int num_fdr_map
[] = { 4, 8, 16, 32 };
108 const int num_fsr_map
[] = { 8, 16, 32, 32 };
110 /* Aliases for registers. */
115 } nds32_register_aliases
[] =
131 {"cr6", "fucop_exist"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
153 {"ir19", "int_ctrl"},
155 {"ir21", "sp_priv1"},
157 {"ir23", "sp_priv2"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
261 {"secur3", "p_isign"},
264 /* Value of a register alias. BATON is the regnum of the corresponding
267 static struct value
*
268 value_of_nds32_reg (frame_info_ptr frame
, const void *baton
)
270 return value_of_register ((int) (intptr_t) baton
, frame
);
273 /* Implement the "frame_align" gdbarch method. */
276 nds32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
278 /* 8-byte aligned. */
279 return align_down (sp
, 8);
282 /* The same insn machine code is used for little-endian and big-endian. */
283 constexpr gdb_byte nds32_break_insn
[] = { 0xEA, 0x00 };
285 typedef BP_MANIPULATION (nds32_break_insn
) nds32_breakpoint
;
287 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
290 nds32_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
292 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
294 const int FDR
= FSR
+ 32;
296 if (num
>= 0 && num
< 32)
298 /* General-purpose registers (R0 - R31). */
301 else if (num
>= FSR
&& num
< FSR
+ 32)
303 /* Single precision floating-point registers (FS0 - FS31). */
304 return num
- FSR
+ tdep
->fs0_regnum
;
306 else if (num
>= FDR
&& num
< FDR
+ 32)
308 /* Double precision floating-point registers (FD0 - FD31). */
309 return num
- FDR
+ NDS32_FD0_REGNUM
;
312 /* No match, return a inaccessible register number. */
316 /* NDS32 register groups. */
317 static const reggroup
*nds32_cr_reggroup
;
318 static const reggroup
*nds32_ir_reggroup
;
319 static const reggroup
*nds32_mr_reggroup
;
320 static const reggroup
*nds32_dr_reggroup
;
321 static const reggroup
*nds32_pfr_reggroup
;
322 static const reggroup
*nds32_hspr_reggroup
;
323 static const reggroup
*nds32_dmar_reggroup
;
324 static const reggroup
*nds32_racr_reggroup
;
325 static const reggroup
*nds32_idr_reggroup
;
326 static const reggroup
*nds32_secur_reggroup
;
329 nds32_init_reggroups (void)
331 nds32_cr_reggroup
= reggroup_new ("cr", USER_REGGROUP
);
332 nds32_ir_reggroup
= reggroup_new ("ir", USER_REGGROUP
);
333 nds32_mr_reggroup
= reggroup_new ("mr", USER_REGGROUP
);
334 nds32_dr_reggroup
= reggroup_new ("dr", USER_REGGROUP
);
335 nds32_pfr_reggroup
= reggroup_new ("pfr", USER_REGGROUP
);
336 nds32_hspr_reggroup
= reggroup_new ("hspr", USER_REGGROUP
);
337 nds32_dmar_reggroup
= reggroup_new ("dmar", USER_REGGROUP
);
338 nds32_racr_reggroup
= reggroup_new ("racr", USER_REGGROUP
);
339 nds32_idr_reggroup
= reggroup_new ("idr", USER_REGGROUP
);
340 nds32_secur_reggroup
= reggroup_new ("secur", USER_REGGROUP
);
344 nds32_add_reggroups (struct gdbarch
*gdbarch
)
346 /* Add NDS32 register groups. */
347 reggroup_add (gdbarch
, nds32_cr_reggroup
);
348 reggroup_add (gdbarch
, nds32_ir_reggroup
);
349 reggroup_add (gdbarch
, nds32_mr_reggroup
);
350 reggroup_add (gdbarch
, nds32_dr_reggroup
);
351 reggroup_add (gdbarch
, nds32_pfr_reggroup
);
352 reggroup_add (gdbarch
, nds32_hspr_reggroup
);
353 reggroup_add (gdbarch
, nds32_dmar_reggroup
);
354 reggroup_add (gdbarch
, nds32_racr_reggroup
);
355 reggroup_add (gdbarch
, nds32_idr_reggroup
);
356 reggroup_add (gdbarch
, nds32_secur_reggroup
);
359 /* Implement the "register_reggroup_p" gdbarch method. */
362 nds32_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
363 const struct reggroup
*reggroup
)
365 const char *reg_name
;
366 const char *group_name
;
369 if (reggroup
== all_reggroup
)
372 /* General reggroup contains only GPRs and PC. */
373 if (reggroup
== general_reggroup
)
374 return regnum
<= NDS32_PC_REGNUM
;
376 if (reggroup
== float_reggroup
|| reggroup
== save_reggroup
377 || reggroup
== restore_reggroup
)
379 ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
383 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
386 if (reggroup
== system_reggroup
)
387 return (regnum
> NDS32_PC_REGNUM
)
388 && !nds32_register_reggroup_p (gdbarch
, regnum
, float_reggroup
);
390 /* The NDS32 reggroup contains registers whose name is prefixed
392 reg_name
= gdbarch_register_name (gdbarch
, regnum
);
393 group_name
= reggroup
->name ();
394 return !strncmp (reg_name
, group_name
, strlen (group_name
));
397 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
400 nds32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
402 regnum
-= gdbarch_num_regs (gdbarch
);
404 /* Currently, only FSRs could be defined as pseudo registers. */
405 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
406 return arch_float_type (gdbarch
, -1, "builtin_type_ieee_single",
407 floatformats_ieee_single
);
409 warning (_("Unknown nds32 pseudo register %d."), regnum
);
413 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
416 nds32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
418 regnum
-= gdbarch_num_regs (gdbarch
);
420 /* Currently, only FSRs could be defined as pseudo registers. */
421 gdb_assert (regnum
< gdbarch_num_pseudo_regs (gdbarch
));
422 return nds32_fsr_register_names
[regnum
];
425 /* Implement the "pseudo_register_read" gdbarch method. */
427 static enum register_status
428 nds32_pseudo_register_read (struct gdbarch
*gdbarch
,
429 readable_regcache
*regcache
, int regnum
,
432 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
434 int offset
, fdr_regnum
;
435 enum register_status status
;
437 /* This function is registered in nds32_gdbarch_init only after these are
439 gdb_assert (tdep
->fpu_freg
!= -1);
440 gdb_assert (tdep
->use_pseudo_fsrs
!= 0);
442 regnum
-= gdbarch_num_regs (gdbarch
);
444 /* Currently, only FSRs could be defined as pseudo registers. */
445 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
447 /* fs0 is always the most significant half of fd0. */
448 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
449 offset
= (regnum
& 1) ? 4 : 0;
451 offset
= (regnum
& 1) ? 0 : 4;
453 fdr_regnum
= NDS32_FD0_REGNUM
+ (regnum
>> 1);
454 status
= regcache
->raw_read (fdr_regnum
, reg_buf
);
455 if (status
== REG_VALID
)
456 memcpy (buf
, reg_buf
+ offset
, 4);
461 gdb_assert_not_reached ("invalid pseudo register number");
464 /* Implement the "pseudo_register_write" gdbarch method. */
467 nds32_pseudo_register_write (struct gdbarch
*gdbarch
,
468 struct regcache
*regcache
, int regnum
,
471 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
473 int offset
, fdr_regnum
;
475 /* This function is registered in nds32_gdbarch_init only after these are
477 gdb_assert (tdep
->fpu_freg
!= -1);
478 gdb_assert (tdep
->use_pseudo_fsrs
!= 0);
480 regnum
-= gdbarch_num_regs (gdbarch
);
482 /* Currently, only FSRs could be defined as pseudo registers. */
483 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
485 /* fs0 is always the most significant half of fd0. */
486 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
487 offset
= (regnum
& 1) ? 4 : 0;
489 offset
= (regnum
& 1) ? 0 : 4;
491 fdr_regnum
= NDS32_FD0_REGNUM
+ (regnum
>> 1);
492 regcache
->raw_read (fdr_regnum
, reg_buf
);
493 memcpy (reg_buf
+ offset
, buf
, 4);
494 regcache
->raw_write (fdr_regnum
, reg_buf
);
498 gdb_assert_not_reached ("invalid pseudo register number");
501 /* Helper function for NDS32 ABI. Return true if FPRs can be used
502 to pass function arguments and return value. */
505 nds32_abi_use_fpr (int elf_abi
)
507 return elf_abi
== E_NDS_ABI_V2FP_PLUS
;
510 /* Helper function for NDS32 ABI. Return true if GPRs and stack
511 can be used together to pass an argument. */
514 nds32_abi_split (int elf_abi
)
516 return elf_abi
== E_NDS_ABI_AABI
;
519 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
521 struct nds32_frame_cache
523 /* The previous frame's inner most stack address. Used as this
524 frame ID's stack_addr. */
527 /* The frame's base, optionally used by the high-level debug info. */
530 /* During prologue analysis, keep how far the SP and FP have been offset
531 from the start of the stack frame (as defined by the previous frame's
533 During epilogue analysis, keep how far the SP has been offset from the
534 current stack pointer. */
538 /* The address of the first instruction in this function. */
541 /* Saved registers. */
542 CORE_ADDR saved_regs
[NDS32_NUM_SAVED_REGS
];
545 /* Allocate and initialize a frame cache. */
547 static struct nds32_frame_cache
*
548 nds32_alloc_frame_cache (void)
550 struct nds32_frame_cache
*cache
;
553 cache
= FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache
);
555 /* Initialize fp_offset to check if FP is set in prologue. */
556 cache
->fp_offset
= INVALID_OFFSET
;
558 /* Saved registers. We initialize these to -1 since zero is a valid
560 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
561 cache
->saved_regs
[i
] = REG_UNAVAIL
;
566 /* Helper function for instructions used to push multiple words. */
569 nds32_push_multiple_words (struct nds32_frame_cache
*cache
, int rb
, int re
,
572 CORE_ADDR sp_offset
= cache
->sp_offset
;
575 /* Check LP, GP, FP in enable4. */
576 for (i
= 1; i
<= 3; i
++)
578 if ((enable4
>> i
) & 0x1)
581 cache
->saved_regs
[NDS32_SP_REGNUM
- i
] = sp_offset
;
585 /* Skip case where re == rb == sp. */
586 if ((rb
< REG_FP
) && (re
< REG_FP
))
588 for (i
= re
; i
>= rb
; i
--)
591 cache
->saved_regs
[i
] = sp_offset
;
595 /* For sp, update the offset. */
596 cache
->sp_offset
= sp_offset
;
599 /* Analyze the instructions within the given address range. If CACHE
600 is non-NULL, fill it in. Return the first address beyond the given
601 address range. If CACHE is NULL, return the first address not
602 recognized as a prologue instruction. */
605 nds32_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
606 CORE_ADDR limit_pc
, struct nds32_frame_cache
*cache
)
608 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
609 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
610 /* Current scanning status. */
611 int in_prologue_bb
= 0;
613 uint32_t insn
, insn_len
;
615 for (; pc
< limit_pc
; pc
+= insn_len
)
617 insn
= read_memory_unsigned_integer (pc
, 4, BFD_ENDIAN_BIG
);
619 if ((insn
& 0x80000000) == 0)
621 /* 32-bit instruction */
624 if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_SP
, 0))
626 /* addi $sp, $sp, imm15s */
627 int imm15s
= N32_IMM15S (insn
);
632 cache
->sp_offset
+= -imm15s
;
638 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_FP
, REG_SP
, 0))
640 /* addi $fp, $sp, imm15s */
641 int imm15s
= N32_IMM15S (insn
);
646 cache
->fp_offset
= cache
->sp_offset
- imm15s
;
652 else if ((insn
& ~(__MASK (19) << 6)) == N32_SMW_ADM
653 && N32_RA5 (insn
) == REG_SP
)
655 /* smw.adm Rb, [$sp], Re, enable4 */
657 nds32_push_multiple_words (cache
, N32_RT5 (insn
),
659 N32_LSMW_ENABLE4 (insn
));
663 else if (insn
== N32_ALU1 (ADD
, REG_SP
, REG_SP
, REG_TA
)
664 || insn
== N32_ALU1 (ADD
, REG_SP
, REG_TA
, REG_SP
))
666 /* add $sp, $sp, $ta */
667 /* add $sp, $ta, $sp */
671 cache
->sp_offset
+= -val_ta
;
677 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (MOVI
, REG_TA
, 0))
679 /* movi $ta, imm20s */
681 val_ta
= N32_IMM20S (insn
);
685 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (SETHI
, REG_TA
, 0))
687 /* sethi $ta, imm20u */
689 val_ta
= N32_IMM20U (insn
) << 12;
693 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ORI
, REG_TA
, REG_TA
, 0))
695 /* ori $ta, $ta, imm15u */
697 val_ta
|= N32_IMM15U (insn
);
701 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_TA
, REG_TA
, 0))
703 /* addi $ta, $ta, imm15s */
705 val_ta
+= N32_IMM15S (insn
);
709 if (insn
== N32_ALU1 (ADD
, REG_GP
, REG_TA
, REG_GP
)
710 || insn
== N32_ALU1 (ADD
, REG_GP
, REG_GP
, REG_TA
))
712 /* add $gp, $ta, $gp */
713 /* add $gp, $gp, $ta */
717 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (MOVI
, REG_GP
, 0))
719 /* movi $gp, imm20s */
723 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (SETHI
, REG_GP
, 0))
725 /* sethi $gp, imm20u */
729 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ORI
, REG_GP
, REG_GP
, 0))
731 /* ori $gp, $gp, imm15u */
737 /* Jump/Branch insns never appear in prologue basic block.
738 The loop can be escaped early when these insns are met. */
739 if (in_prologue_bb
== 1)
741 int op
= N32_OP6 (insn
);
744 || op
== N32_OP6_JREG
747 || op
== N32_OP6_BR3
)
752 if (abi_use_fpr
&& N32_OP6 (insn
) == N32_OP6_SDC
753 && __GF (insn
, 12, 3) == 0)
755 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
756 normal form (bit [12] == 0) is used. */
758 /* fsdi FDt, [$sp + (imm12s << 2)] */
759 if (N32_RA5 (insn
) == REG_SP
)
763 /* The optimizer might shove anything into the prologue, if
764 we build up cache (cache != NULL) from analyzing prologue,
765 we just skip what we don't recognize and analyze further to
766 make cache as complete as possible. However, if we skip
767 prologue, we'll stop immediately on unrecognized
774 /* 16-bit instruction */
779 if (CHOP_BITS (insn
, 10) == N16_TYPE10 (ADDI10S
, 0))
782 int imm10s
= N16_IMM10S (insn
);
787 cache
->sp_offset
+= -imm10s
;
793 else if (__GF (insn
, 7, 8) == N16_T25_PUSH25
)
798 int imm8u
= (insn
& 0x1f) << 3;
799 int re
= (insn
>> 5) & 0x3;
800 const int reg_map
[] = { 6, 8, 10, 14 };
802 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
803 nds32_push_multiple_words (cache
, 6, reg_map
[re
], 0xe);
805 /* Operation 2 -- sp = sp - (imm5u << 3) */
806 cache
->sp_offset
+= imm8u
;
812 else if (insn
== N16_TYPE5 (ADD5PC
, REG_GP
))
818 else if (CHOP_BITS (insn
, 5) == N16_TYPE55 (MOVI55
, REG_GP
, 0))
820 /* movi55 $gp, imm5s */
826 /* Jump/Branch insns never appear in prologue basic block.
827 The loop can be escaped early when these insns are met. */
828 if (in_prologue_bb
== 1)
830 uint32_t insn5
= CHOP_BITS (insn
, 5);
831 uint32_t insn8
= CHOP_BITS (insn
, 8);
832 uint32_t insn38
= CHOP_BITS (insn
, 11);
834 if (insn5
== N16_TYPE5 (JR5
, 0)
835 || insn5
== N16_TYPE5 (JRAL5
, 0)
836 || insn5
== N16_TYPE5 (RET5
, 0)
837 || insn8
== N16_TYPE8 (J8
, 0)
838 || insn8
== N16_TYPE8 (BEQZS8
, 0)
839 || insn8
== N16_TYPE8 (BNEZS8
, 0)
840 || insn38
== N16_TYPE38 (BEQZ38
, 0, 0)
841 || insn38
== N16_TYPE38 (BNEZ38
, 0, 0)
842 || insn38
== N16_TYPE38 (BEQS38
, 0, 0)
843 || insn38
== N16_TYPE38 (BNES38
, 0, 0))
848 /* The optimizer might shove anything into the prologue, if
849 we build up cache (cache != NULL) from analyzing prologue,
850 we just skip what we don't recognize and analyze further to
851 make cache as complete as possible. However, if we skip
852 prologue, we'll stop immediately on unrecognized
862 /* Implement the "skip_prologue" gdbarch method.
864 Find the end of function prologue. */
867 nds32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
869 CORE_ADDR func_addr
, limit_pc
;
871 /* See if we can determine the end of the prologue via the symbol table.
872 If so, then return either PC, or the PC after the prologue, whichever
874 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
876 CORE_ADDR post_prologue_pc
877 = skip_prologue_using_sal (gdbarch
, func_addr
);
878 if (post_prologue_pc
!= 0)
879 return std::max (pc
, post_prologue_pc
);
882 /* Can't determine prologue from the symbol table, need to examine
885 /* Find an upper limit on the function prologue using the debug
886 information. If the debug information could not be used to provide
887 that bound, then use an arbitrary large number as the upper bound. */
888 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
890 limit_pc
= pc
+ 128; /* Magic. */
892 /* Find the end of prologue. */
893 return nds32_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
896 /* Allocate and fill in *THIS_CACHE with information about the prologue of
897 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
898 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
900 static struct nds32_frame_cache
*
901 nds32_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
903 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
904 struct nds32_frame_cache
*cache
;
905 CORE_ADDR current_pc
;
911 return (struct nds32_frame_cache
*) *this_cache
;
913 cache
= nds32_alloc_frame_cache ();
916 cache
->pc
= get_frame_func (this_frame
);
917 current_pc
= get_frame_pc (this_frame
);
918 nds32_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
);
920 /* Compute the previous frame's stack pointer (which is also the
921 frame's ID's stack address), and this frame's base pointer. */
922 if (cache
->fp_offset
!= INVALID_OFFSET
)
924 /* FP is set in prologue, so it can be used to calculate other info. */
925 this_base
= get_frame_register_unsigned (this_frame
, NDS32_FP_REGNUM
);
926 prev_sp
= this_base
+ cache
->fp_offset
;
930 this_base
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
931 prev_sp
= this_base
+ cache
->sp_offset
;
934 cache
->prev_sp
= prev_sp
;
935 cache
->base
= this_base
;
937 /* Adjust all the saved registers such that they contain addresses
938 instead of offsets. */
939 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
940 if (cache
->saved_regs
[i
] != REG_UNAVAIL
)
941 cache
->saved_regs
[i
] = cache
->prev_sp
- cache
->saved_regs
[i
];
946 /* Implement the "this_id" frame_unwind method.
948 Our frame ID for a normal frame is the current function's starting
949 PC and the caller's SP when we were called. */
952 nds32_frame_this_id (frame_info_ptr this_frame
,
953 void **this_cache
, struct frame_id
*this_id
)
955 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
957 /* This marks the outermost frame. */
958 if (cache
->prev_sp
== 0)
961 *this_id
= frame_id_build (cache
->prev_sp
, cache
->pc
);
964 /* Implement the "prev_register" frame_unwind method. */
966 static struct value
*
967 nds32_frame_prev_register (frame_info_ptr this_frame
, void **this_cache
,
970 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
972 if (regnum
== NDS32_SP_REGNUM
)
973 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
975 /* The PC of the previous frame is stored in the LP register of
976 the current frame. */
977 if (regnum
== NDS32_PC_REGNUM
)
978 regnum
= NDS32_LP_REGNUM
;
980 if (regnum
< NDS32_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != REG_UNAVAIL
)
981 return frame_unwind_got_memory (this_frame
, regnum
,
982 cache
->saved_regs
[regnum
]);
984 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
987 static const struct frame_unwind nds32_frame_unwind
=
991 default_frame_unwind_stop_reason
,
993 nds32_frame_prev_register
,
995 default_frame_sniffer
,
998 /* Return the frame base address of *THIS_FRAME. */
1001 nds32_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
1003 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
1008 static const struct frame_base nds32_frame_base
=
1010 &nds32_frame_unwind
,
1011 nds32_frame_base_address
,
1012 nds32_frame_base_address
,
1013 nds32_frame_base_address
1016 /* Helper function for instructions used to pop multiple words. */
1019 nds32_pop_multiple_words (struct nds32_frame_cache
*cache
, int rb
, int re
,
1022 CORE_ADDR sp_offset
= cache
->sp_offset
;
1025 /* Skip case where re == rb == sp. */
1026 if ((rb
< REG_FP
) && (re
< REG_FP
))
1028 for (i
= rb
; i
<= re
; i
++)
1030 cache
->saved_regs
[i
] = sp_offset
;
1035 /* Check FP, GP, LP in enable4. */
1036 for (i
= 3; i
>= 1; i
--)
1038 if ((enable4
>> i
) & 0x1)
1040 cache
->saved_regs
[NDS32_SP_REGNUM
- i
] = sp_offset
;
1045 /* For sp, update the offset. */
1046 cache
->sp_offset
= sp_offset
;
1049 /* The instruction sequences in NDS32 epilogue are
1051 INSN_RESET_SP (optional)
1052 (If exists, this must be the first instruction in epilogue
1053 and the stack has not been destroyed.).
1054 INSN_RECOVER (optional).
1055 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1057 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1058 the necessary information will be recorded. */
1061 nds32_analyze_epilogue_insn32 (int abi_use_fpr
, uint32_t insn
,
1062 struct nds32_frame_cache
*cache
)
1064 if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_SP
, 0)
1065 && N32_IMM15S (insn
) > 0)
1066 /* addi $sp, $sp, imm15s */
1067 return INSN_RESET_SP
;
1068 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_FP
, 0)
1069 && N32_IMM15S (insn
) < 0)
1070 /* addi $sp, $fp, imm15s */
1071 return INSN_RESET_SP
;
1072 else if ((insn
& ~(__MASK (19) << 6)) == N32_LMW_BIM
1073 && N32_RA5 (insn
) == REG_SP
)
1075 /* lmw.bim Rb, [$sp], Re, enable4 */
1077 nds32_pop_multiple_words (cache
, N32_RT5 (insn
),
1078 N32_RB5 (insn
), N32_LSMW_ENABLE4 (insn
));
1080 return INSN_RECOVER
;
1082 else if (insn
== N32_JREG (JR
, 0, REG_LP
, 0, 1))
1085 else if (insn
== N32_ALU1 (ADD
, REG_SP
, REG_SP
, REG_TA
)
1086 || insn
== N32_ALU1 (ADD
, REG_SP
, REG_TA
, REG_SP
))
1087 /* add $sp, $sp, $ta */
1088 /* add $sp, $ta, $sp */
1089 return INSN_RESET_SP
;
1090 else if (abi_use_fpr
1091 && (insn
& ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP
)
1093 if (__GF (insn
, 12, 1) == 0)
1094 /* fldi FDt, [$sp + (imm12s << 2)] */
1095 return INSN_RECOVER
;
1098 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1099 int offset
= N32_IMM12S (insn
) << 2;
1101 if (offset
== 8 || offset
== 12)
1104 cache
->sp_offset
+= offset
;
1106 return INSN_RECOVER
;
1114 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1115 the necessary information will be recorded. */
1118 nds32_analyze_epilogue_insn16 (uint32_t insn
, struct nds32_frame_cache
*cache
)
1120 if (insn
== N16_TYPE5 (RET5
, REG_LP
))
1123 else if (CHOP_BITS (insn
, 10) == N16_TYPE10 (ADDI10S
, 0))
1126 int imm10s
= N16_IMM10S (insn
);
1131 cache
->sp_offset
+= imm10s
;
1133 return INSN_RECOVER
;
1136 else if (__GF (insn
, 7, 8) == N16_T25_POP25
)
1141 int imm8u
= (insn
& 0x1f) << 3;
1142 int re
= (insn
>> 5) & 0x3;
1143 const int reg_map
[] = { 6, 8, 10, 14 };
1145 /* Operation 1 -- sp = sp + (imm5u << 3) */
1146 cache
->sp_offset
+= imm8u
;
1148 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1149 nds32_pop_multiple_words (cache
, 6, reg_map
[re
], 0xe);
1152 /* Operation 3 -- ret $lp */
1153 return INSN_RECOVER_RETURN
;
1159 /* Analyze a reasonable amount of instructions from the given PC to find
1160 the instruction used to return to the caller. Return 1 if the 'return'
1161 instruction could be found, 0 otherwise.
1163 If CACHE is non-NULL, fill it in. */
1166 nds32_analyze_epilogue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1167 struct nds32_frame_cache
*cache
)
1169 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
1170 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1172 uint32_t insn
, insn_len
;
1173 int insn_type
= INSN_NORMAL
;
1180 for (; pc
< limit_pc
; pc
+= insn_len
)
1182 insn
= read_memory_unsigned_integer (pc
, 4, BFD_ENDIAN_BIG
);
1184 if ((insn
& 0x80000000) == 0)
1186 /* 32-bit instruction */
1189 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, cache
);
1190 if (insn_type
== INSN_RETURN
)
1192 else if (insn_type
== INSN_RECOVER
)
1197 /* 16-bit instruction */
1201 insn_type
= nds32_analyze_epilogue_insn16 (insn
, cache
);
1202 if (insn_type
== INSN_RETURN
|| insn_type
== INSN_RECOVER_RETURN
)
1204 else if (insn_type
== INSN_RECOVER
)
1208 /* Stop the scan if this is an unexpected instruction. */
1215 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1218 nds32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1220 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
1221 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1222 int insn_type
= INSN_NORMAL
;
1226 insn
= read_memory_unsigned_integer (addr
, 4, BFD_ENDIAN_BIG
);
1228 if ((insn
& 0x80000000) == 0)
1230 /* 32-bit instruction */
1232 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, NULL
);
1236 /* 16-bit instruction */
1239 insn_type
= nds32_analyze_epilogue_insn16 (insn
, NULL
);
1242 if (insn_type
== INSN_NORMAL
|| insn_type
== INSN_RESET_SP
)
1245 /* Search the required 'return' instruction within the following reasonable
1247 ret_found
= nds32_analyze_epilogue (gdbarch
, addr
, NULL
);
1251 /* Scan backwards to make sure that the last instruction has adjusted
1252 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1253 just a heuristic, so the false positives will be acceptable. */
1254 insn
= read_memory_unsigned_integer (addr
- 2, 4, BFD_ENDIAN_BIG
);
1256 /* Only 16-bit instructions are possible at addr - 2. */
1257 if ((insn
& 0x80000000) != 0)
1259 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1261 insn_type
= nds32_analyze_epilogue_insn16 (insn
>> 16, NULL
);
1262 if (insn_type
== INSN_RECOVER
)
1266 insn
= read_memory_unsigned_integer (addr
- 4, 4, BFD_ENDIAN_BIG
);
1268 /* If this is a 16-bit instruction at addr - 4, then there must be another
1269 16-bit instruction at addr - 2, so only 32-bit instructions need to
1270 be analyzed here. */
1271 if ((insn
& 0x80000000) == 0)
1273 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1275 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, NULL
);
1276 if (insn_type
== INSN_RECOVER
|| insn_type
== INSN_RESET_SP
)
1283 /* Implement the "sniffer" frame_unwind method. */
1286 nds32_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1287 frame_info_ptr this_frame
, void **this_cache
)
1289 if (frame_relative_level (this_frame
) == 0)
1290 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame
),
1291 get_frame_pc (this_frame
));
1296 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1297 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1298 allocated. Return a pointer to the current nds32_frame_cache in
1301 static struct nds32_frame_cache
*
1302 nds32_epilogue_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
1304 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1305 struct nds32_frame_cache
*cache
;
1306 CORE_ADDR current_pc
, current_sp
;
1310 return (struct nds32_frame_cache
*) *this_cache
;
1312 cache
= nds32_alloc_frame_cache ();
1313 *this_cache
= cache
;
1315 cache
->pc
= get_frame_func (this_frame
);
1316 current_pc
= get_frame_pc (this_frame
);
1317 nds32_analyze_epilogue (gdbarch
, current_pc
, cache
);
1319 current_sp
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
1320 cache
->prev_sp
= current_sp
+ cache
->sp_offset
;
1322 /* Adjust all the saved registers such that they contain addresses
1323 instead of offsets. */
1324 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
1325 if (cache
->saved_regs
[i
] != REG_UNAVAIL
)
1326 cache
->saved_regs
[i
] = current_sp
+ cache
->saved_regs
[i
];
1331 /* Implement the "this_id" frame_unwind method. */
1334 nds32_epilogue_frame_this_id (frame_info_ptr this_frame
,
1335 void **this_cache
, struct frame_id
*this_id
)
1337 struct nds32_frame_cache
*cache
1338 = nds32_epilogue_frame_cache (this_frame
, this_cache
);
1340 /* This marks the outermost frame. */
1341 if (cache
->prev_sp
== 0)
1344 *this_id
= frame_id_build (cache
->prev_sp
, cache
->pc
);
1347 /* Implement the "prev_register" frame_unwind method. */
1349 static struct value
*
1350 nds32_epilogue_frame_prev_register (frame_info_ptr this_frame
,
1351 void **this_cache
, int regnum
)
1353 struct nds32_frame_cache
*cache
1354 = nds32_epilogue_frame_cache (this_frame
, this_cache
);
1356 if (regnum
== NDS32_SP_REGNUM
)
1357 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
1359 /* The PC of the previous frame is stored in the LP register of
1360 the current frame. */
1361 if (regnum
== NDS32_PC_REGNUM
)
1362 regnum
= NDS32_LP_REGNUM
;
1364 if (regnum
< NDS32_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != REG_UNAVAIL
)
1365 return frame_unwind_got_memory (this_frame
, regnum
,
1366 cache
->saved_regs
[regnum
]);
1368 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1371 static const struct frame_unwind nds32_epilogue_frame_unwind
=
1375 default_frame_unwind_stop_reason
,
1376 nds32_epilogue_frame_this_id
,
1377 nds32_epilogue_frame_prev_register
,
1379 nds32_epilogue_frame_sniffer
1383 /* Floating type and struct type that has only one floating type member
1384 can pass value using FPU registers (when FPU ABI is used). */
1387 nds32_check_calling_use_fpr (struct type
*type
)
1390 enum type_code typecode
;
1395 t
= check_typedef (t
);
1396 typecode
= t
->code ();
1397 if (typecode
!= TYPE_CODE_STRUCT
)
1399 else if (t
->num_fields () != 1)
1402 t
= t
->field (0).type ();
1405 return typecode
== TYPE_CODE_FLT
;
1408 /* Implement the "push_dummy_call" gdbarch method. */
1411 nds32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1412 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1413 int nargs
, struct value
**args
, CORE_ADDR sp
,
1414 function_call_return_method return_method
,
1415 CORE_ADDR struct_addr
)
1417 const int REND
= 6; /* End for register offset. */
1418 int goff
= 0; /* Current gpr offset for argument. */
1419 int foff
= 0; /* Current fpr offset for argument. */
1420 int soff
= 0; /* Current stack offset for argument. */
1423 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1424 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
1425 struct type
*func_type
= value_type (function
);
1426 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1427 int abi_split
= nds32_abi_split (tdep
->elf_abi
);
1429 /* Set the return address. For the NDS32, the return breakpoint is
1430 always at BP_ADDR. */
1431 regcache_cooked_write_unsigned (regcache
, NDS32_LP_REGNUM
, bp_addr
);
1433 /* If STRUCT_RETURN is true, then the struct return address (in
1434 STRUCT_ADDR) will consume the first argument-passing register.
1435 Both adjust the register count and store that value. */
1436 if (return_method
== return_method_struct
)
1438 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, struct_addr
);
1442 /* Now make sure there's space on the stack */
1443 for (i
= 0; i
< nargs
; i
++)
1445 struct type
*type
= value_type (args
[i
]);
1446 int align
= type_align (type
);
1448 /* If align is zero, it may be an empty struct.
1449 Just ignore the argument of empty struct. */
1453 sp
-= type
->length ();
1454 sp
= align_down (sp
, align
);
1457 /* Stack must be 8-byte aligned. */
1458 sp
= align_down (sp
, 8);
1461 for (i
= 0; i
< nargs
; i
++)
1463 const gdb_byte
*val
;
1466 int calling_use_fpr
;
1469 type
= value_type (args
[i
]);
1470 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1471 len
= type
->length ();
1472 align
= type_align (type
);
1473 val
= value_contents (args
[i
]).data ();
1475 /* The size of a composite type larger than 4 bytes will be rounded
1476 up to the nearest multiple of 4. */
1478 len
= align_up (len
, 4);
1480 /* Variadic functions are handled differently between AABI and ABI2FP+.
1482 For AABI, the caller pushes arguments in registers, callee stores
1483 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1484 Therefore, we don't have to handle variadic functions specially.
1486 For ABI2FP+, the caller pushes only named arguments in registers
1487 and pushes all unnamed arguments in stack. */
1489 if (abi_use_fpr
&& func_type
->has_varargs ()
1490 && i
>= func_type
->num_fields ())
1493 /* Try to use FPRs to pass arguments only when
1494 1. The program is built using toolchain with FPU support.
1495 2. The type of this argument can use FPR to pass value. */
1496 use_fpr
= abi_use_fpr
&& calling_use_fpr
;
1500 if (tdep
->fpu_freg
== -1)
1503 /* Adjust alignment. */
1504 if ((align
>> 2) > 0)
1505 foff
= align_up (foff
, align
>> 2);
1512 regcache
->cooked_write (tdep
->fs0_regnum
+ foff
, val
);
1516 regcache
->cooked_write (NDS32_FD0_REGNUM
+ (foff
>> 1), val
);
1521 internal_error ("Do not know how to handle %d-byte double.\n",
1531 When passing arguments using GPRs,
1533 * A composite type not larger than 4 bytes is passed in $rN.
1534 The format is as if the value is loaded with load instruction
1535 of corresponding size (e.g., LB, LH, LW).
1544 * Otherwise, a composite type is passed in consecutive registers.
1545 The size is rounded up to the nearest multiple of 4.
1546 The successive registers hold the parts of the argument as if
1547 were loaded using lmw instructions.
1553 LITTLE: [d c b a] [x x x e]
1554 BIG: [a b c d] [e x x x]
1557 /* Adjust alignment. */
1558 if ((align
>> 2) > 0)
1559 goff
= align_up (goff
, align
>> 2);
1561 if (len
<= (REND
- goff
) * 4)
1563 /* This argument can be passed wholly via GPRs. */
1566 regval
= extract_unsigned_integer (val
, (len
> 4) ? 4 : len
,
1568 regcache_cooked_write_unsigned (regcache
,
1569 NDS32_R0_REGNUM
+ goff
,
1579 /* Some parts of this argument can be passed via GPRs. */
1582 regval
= extract_unsigned_integer (val
, (len
> 4) ? 4 : len
,
1584 regcache_cooked_write_unsigned (regcache
,
1585 NDS32_R0_REGNUM
+ goff
,
1596 When pushing (split parts of) an argument into stack,
1598 * A composite type not larger than 4 bytes is copied to different
1600 In little-endian, the first byte of this argument is aligned
1601 at the low address of the next free word.
1602 In big-endian, the last byte of this argument is aligned
1603 at the high address of the next free word.
1614 /* Adjust alignment. */
1615 soff
= align_up (soff
, align
);
1619 int rlen
= (len
> 4) ? 4 : len
;
1621 if (byte_order
== BFD_ENDIAN_BIG
)
1622 write_memory (sp
+ soff
+ 4 - rlen
, val
, rlen
);
1624 write_memory (sp
+ soff
, val
, rlen
);
1632 /* Finally, update the SP register. */
1633 regcache_cooked_write_unsigned (regcache
, NDS32_SP_REGNUM
, sp
);
1638 /* If use_fpr, but no floating-point register exists,
1639 then it is an error. */
1640 error (_("Fail to call. FPU registers are required."));
1643 /* Read, for architecture GDBARCH, a function return value of TYPE
1644 from REGCACHE, and copy that into VALBUF. */
1647 nds32_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1648 struct regcache
*regcache
, gdb_byte
*valbuf
)
1650 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1651 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
1652 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1653 int calling_use_fpr
;
1656 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1657 len
= type
->length ();
1659 if (abi_use_fpr
&& calling_use_fpr
)
1662 regcache
->cooked_read (tdep
->fs0_regnum
, valbuf
);
1664 regcache
->cooked_read (NDS32_FD0_REGNUM
, valbuf
);
1666 internal_error (_("Cannot extract return value of %d bytes "
1667 "long floating-point."), len
);
1672 When returning result,
1674 * A composite type not larger than 4 bytes is returned in $r0.
1675 The format is as if the result is loaded with load instruction
1676 of corresponding size (e.g., LB, LH, LW).
1685 * Otherwise, a composite type not larger than 8 bytes is returned
1687 In little-endian, the first word is loaded in $r0.
1688 In big-endian, the last word is loaded in $r1.
1694 LITTLE: [d c b a] [x x x e]
1695 BIG: [x x x a] [b c d e]
1702 /* By using store_unsigned_integer we avoid having to do
1703 anything special for small big-endian values. */
1704 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
, &tmp
);
1705 store_unsigned_integer (valbuf
, len
, byte_order
, tmp
);
1709 regcache
->cooked_read (NDS32_R0_REGNUM
, valbuf
);
1715 len1
= byte_order
== BFD_ENDIAN_BIG
? len
- 4 : 4;
1718 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
, &tmp
);
1719 store_unsigned_integer (valbuf
, len1
, byte_order
, tmp
);
1721 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
+ 1, &tmp
);
1722 store_unsigned_integer (valbuf
+ len1
, len2
, byte_order
, tmp
);
1726 regcache
->cooked_read (NDS32_R0_REGNUM
, valbuf
);
1727 regcache
->cooked_read (NDS32_R0_REGNUM
+ 1, valbuf
+ 4);
1732 /* Write, for architecture GDBARCH, a function return value of TYPE
1733 from VALBUF into REGCACHE. */
1736 nds32_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1737 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1739 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1740 nds32_gdbarch_tdep
*tdep
= gdbarch_tdep
<nds32_gdbarch_tdep
> (gdbarch
);
1741 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1742 int calling_use_fpr
;
1745 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1746 len
= type
->length ();
1748 if (abi_use_fpr
&& calling_use_fpr
)
1751 regcache
->cooked_write (tdep
->fs0_regnum
, valbuf
);
1753 regcache
->cooked_write (NDS32_FD0_REGNUM
, valbuf
);
1755 internal_error (_("Cannot store return value of %d bytes "
1756 "long floating-point."), len
);
1764 regval
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1765 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, regval
);
1769 regcache
->cooked_write (NDS32_R0_REGNUM
, valbuf
);
1775 len1
= byte_order
== BFD_ENDIAN_BIG
? len
- 4 : 4;
1778 regval
= extract_unsigned_integer (valbuf
, len1
, byte_order
);
1779 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, regval
);
1781 regval
= extract_unsigned_integer (valbuf
+ len1
, len2
, byte_order
);
1782 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
+ 1,
1787 regcache
->cooked_write (NDS32_R0_REGNUM
, valbuf
);
1788 regcache
->cooked_write (NDS32_R0_REGNUM
+ 1, valbuf
+ 4);
1793 /* Implement the "return_value" gdbarch method.
1795 Determine, for architecture GDBARCH, how a return value of TYPE
1796 should be returned. If it is supposed to be returned in registers,
1797 and READBUF is non-zero, read the appropriate value from REGCACHE,
1798 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1799 from WRITEBUF into REGCACHE. */
1801 static enum return_value_convention
1802 nds32_return_value (struct gdbarch
*gdbarch
, struct value
*func_type
,
1803 struct type
*type
, struct regcache
*regcache
,
1804 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1806 if (type
->length () > 8)
1808 return RETURN_VALUE_STRUCT_CONVENTION
;
1812 if (readbuf
!= NULL
)
1813 nds32_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
1814 if (writebuf
!= NULL
)
1815 nds32_store_return_value (gdbarch
, type
, regcache
, writebuf
);
1817 return RETURN_VALUE_REGISTER_CONVENTION
;
1821 /* Implement the "get_longjmp_target" gdbarch method. */
1824 nds32_get_longjmp_target (frame_info_ptr frame
, CORE_ADDR
*pc
)
1828 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1829 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1831 jb_addr
= get_frame_register_unsigned (frame
, NDS32_R0_REGNUM
);
1833 if (target_read_memory (jb_addr
+ 11 * 4, buf
, 4))
1836 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1840 /* Validate the given TDESC, and fixed-number some registers in it.
1841 Return 0 if the given TDESC does not contain the required feature
1842 or not contain required registers. */
1845 nds32_validate_tdesc_p (const struct target_desc
*tdesc
,
1846 struct tdesc_arch_data
*tdesc_data
,
1847 int *fpu_freg
, int *use_pseudo_fsrs
)
1849 const struct tdesc_feature
*feature
;
1852 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nds32.core");
1853 if (feature
== NULL
)
1857 /* Validate and fixed-number R0-R10. */
1858 for (i
= NDS32_R0_REGNUM
; i
<= NDS32_R0_REGNUM
+ 10; i
++)
1859 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1860 nds32_register_names
[i
]);
1863 valid_p
&= tdesc_unnumbered_register (feature
,
1864 nds32_register_names
[NDS32_TA_REGNUM
]);
1866 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1867 for (i
= NDS32_FP_REGNUM
; i
<= NDS32_PC_REGNUM
; i
++)
1868 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1869 nds32_register_names
[i
]);
1874 /* Fixed-number R11-R27. */
1875 for (i
= NDS32_R0_REGNUM
+ 11; i
<= NDS32_R0_REGNUM
+ 27; i
++)
1876 tdesc_numbered_register (feature
, tdesc_data
, i
, nds32_register_names
[i
]);
1878 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nds32.fpu");
1879 if (feature
!= NULL
)
1881 int num_fdr_regs
, num_fsr_regs
, fs0_regnum
, num_listed_fsr
;
1884 /* Guess FPU configuration via listed registers. */
1885 if (tdesc_unnumbered_register (feature
, "fd31"))
1887 else if (tdesc_unnumbered_register (feature
, "fd15"))
1889 else if (tdesc_unnumbered_register (feature
, "fd7"))
1891 else if (tdesc_unnumbered_register (feature
, "fd3"))
1895 /* Required FDR is not found. */
1900 /* Validate and fixed-number required FDRs. */
1901 num_fdr_regs
= num_fdr_map
[freg
];
1902 for (i
= 0; i
< num_fdr_regs
; i
++)
1903 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1904 NDS32_FD0_REGNUM
+ i
,
1905 nds32_fdr_register_names
[i
]);
1909 /* Count the number of listed FSRs, and fixed-number them if present. */
1910 num_fsr_regs
= num_fsr_map
[freg
];
1911 fs0_regnum
= NDS32_FD0_REGNUM
+ num_fdr_regs
;
1913 for (i
= 0; i
< num_fsr_regs
; i
++)
1914 num_listed_fsr
+= tdesc_numbered_register (feature
, tdesc_data
,
1916 nds32_fsr_register_names
[i
]);
1918 if (num_listed_fsr
== 0)
1919 /* No required FSRs are listed explicitly, make them pseudo registers
1921 *use_pseudo_fsrs
= 1;
1922 else if (num_listed_fsr
== num_fsr_regs
)
1923 /* All required FSRs are listed explicitly. */
1924 *use_pseudo_fsrs
= 0;
1926 /* Some required FSRs are missing. */
1933 /* Initialize the current architecture based on INFO. If possible,
1934 re-use an architecture from ARCHES, which is a list of
1935 architectures already created during this debugging session.
1937 Called e.g. at program startup, when reading a core file, and when
1938 reading a binary file. */
1940 static struct gdbarch
*
1941 nds32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1943 struct gdbarch
*gdbarch
;
1944 struct gdbarch_list
*best_arch
;
1945 tdesc_arch_data_up tdesc_data
;
1946 const struct target_desc
*tdesc
= info
.target_desc
;
1947 int elf_abi
= E_NDS_ABI_AABI
;
1949 int use_pseudo_fsrs
= 0;
1950 int i
, num_regs
, maxregs
;
1952 /* Extract the elf_flags if available. */
1953 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1954 elf_abi
= elf_elfheader (info
.abfd
)->e_flags
& EF_NDS_ABI
;
1956 /* If there is already a candidate, use it. */
1957 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
1959 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
1961 nds32_gdbarch_tdep
*idep
1962 = gdbarch_tdep
<nds32_gdbarch_tdep
> (best_arch
->gdbarch
);
1964 if (idep
->elf_abi
!= elf_abi
)
1967 /* Found a match. */
1971 if (best_arch
!= NULL
)
1972 return best_arch
->gdbarch
;
1974 if (!tdesc_has_registers (tdesc
))
1975 tdesc
= tdesc_nds32
;
1977 tdesc_data
= tdesc_data_alloc ();
1979 if (!nds32_validate_tdesc_p (tdesc
, tdesc_data
.get (), &fpu_freg
,
1983 /* Allocate space for the new architecture. */
1984 nds32_gdbarch_tdep
*tdep
= new nds32_gdbarch_tdep
;
1985 tdep
->fpu_freg
= fpu_freg
;
1986 tdep
->use_pseudo_fsrs
= use_pseudo_fsrs
;
1987 tdep
->fs0_regnum
= -1;
1988 tdep
->elf_abi
= elf_abi
;
1990 gdbarch
= gdbarch_alloc (&info
, tdep
);
1992 set_gdbarch_wchar_bit (gdbarch
, 16);
1993 set_gdbarch_wchar_signed (gdbarch
, 0);
1996 num_regs
= NDS32_NUM_REGS
;
1997 else if (use_pseudo_fsrs
== 1)
1999 set_gdbarch_pseudo_register_read (gdbarch
, nds32_pseudo_register_read
);
2000 set_gdbarch_pseudo_register_write (gdbarch
, nds32_pseudo_register_write
);
2001 set_tdesc_pseudo_register_name (gdbarch
, nds32_pseudo_register_name
);
2002 set_tdesc_pseudo_register_type (gdbarch
, nds32_pseudo_register_type
);
2003 set_gdbarch_num_pseudo_regs (gdbarch
, num_fsr_map
[fpu_freg
]);
2005 num_regs
= NDS32_NUM_REGS
+ num_fdr_map
[fpu_freg
];
2008 num_regs
= NDS32_NUM_REGS
+ num_fdr_map
[fpu_freg
] + num_fsr_map
[fpu_freg
];
2010 set_gdbarch_num_regs (gdbarch
, num_regs
);
2011 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
2013 /* Cache the register number of fs0. */
2015 tdep
->fs0_regnum
= user_reg_map_name_to_regnum (gdbarch
, "fs0", -1);
2017 /* Add NDS32 register aliases. To avoid search in user register name space,
2018 user_reg_map_name_to_regnum is not used. */
2019 maxregs
= gdbarch_num_cooked_regs (gdbarch
);
2020 for (i
= 0; i
< ARRAY_SIZE (nds32_register_aliases
); i
++)
2025 /* Search register name space. */
2026 for (j
= 0; j
< maxregs
; j
++)
2028 const char *regname
= gdbarch_register_name (gdbarch
, j
);
2030 if (strcmp (regname
, nds32_register_aliases
[i
].name
) == 0)
2037 /* Try next alias entry if the given name can not be found in register
2042 user_reg_add (gdbarch
, nds32_register_aliases
[i
].alias
,
2043 value_of_nds32_reg
, (const void *) (intptr_t) regnum
);
2046 nds32_add_reggroups (gdbarch
);
2048 /* Hook in ABI-specific overrides, if they have been registered. */
2049 info
.tdesc_data
= tdesc_data
.get ();
2050 gdbarch_init_osabi (info
, gdbarch
);
2052 /* Override tdesc_register callbacks for system registers. */
2053 set_gdbarch_register_reggroup_p (gdbarch
, nds32_register_reggroup_p
);
2055 set_gdbarch_sp_regnum (gdbarch
, NDS32_SP_REGNUM
);
2056 set_gdbarch_pc_regnum (gdbarch
, NDS32_PC_REGNUM
);
2057 set_gdbarch_stack_frame_destroyed_p (gdbarch
, nds32_stack_frame_destroyed_p
);
2058 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, nds32_dwarf2_reg_to_regnum
);
2060 set_gdbarch_push_dummy_call (gdbarch
, nds32_push_dummy_call
);
2061 set_gdbarch_return_value (gdbarch
, nds32_return_value
);
2063 set_gdbarch_skip_prologue (gdbarch
, nds32_skip_prologue
);
2064 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2065 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
2066 nds32_breakpoint::kind_from_pc
);
2067 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
2068 nds32_breakpoint::bp_from_kind
);
2070 set_gdbarch_frame_align (gdbarch
, nds32_frame_align
);
2071 frame_base_set_default (gdbarch
, &nds32_frame_base
);
2073 /* Handle longjmp. */
2074 set_gdbarch_get_longjmp_target (gdbarch
, nds32_get_longjmp_target
);
2076 /* The order of appending is the order it check frame. */
2077 dwarf2_append_unwinders (gdbarch
);
2078 frame_unwind_append_unwinder (gdbarch
, &nds32_epilogue_frame_unwind
);
2079 frame_unwind_append_unwinder (gdbarch
, &nds32_frame_unwind
);
2084 void _initialize_nds32_tdep ();
2086 _initialize_nds32_tdep ()
2088 /* Initialize gdbarch. */
2089 gdbarch_register (bfd_arch_nds32
, nds32_gdbarch_init
);
2091 initialize_tdesc_nds32 ();
2092 nds32_init_reggroups ();