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1 /* Target-dependent code for GDB, the GNU debugger.
2
3 Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #ifndef PPC_TDEP_H
22 #define PPC_TDEP_H
23
24 struct gdbarch;
25 struct frame_info;
26 struct value;
27 struct regcache;
28 struct type;
29
30 /* From ppc-linux-tdep.c... */
31 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
32 struct type *func_type,
33 struct type *valtype,
34 struct regcache *regcache,
35 gdb_byte *readbuf,
36 const gdb_byte *writebuf);
37 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
38 struct type *func_type,
39 struct type *valtype,
40 struct regcache *regcache,
41 gdb_byte *readbuf,
42 const gdb_byte *writebuf);
43 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
44 struct value *function,
45 struct regcache *regcache,
46 CORE_ADDR bp_addr, int nargs,
47 struct value **args, CORE_ADDR sp,
48 int struct_return,
49 CORE_ADDR struct_addr);
50 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
51 struct value *function,
52 struct regcache *regcache,
53 CORE_ADDR bp_addr, int nargs,
54 struct value **args, CORE_ADDR sp,
55 int struct_return,
56 CORE_ADDR struct_addr);
57 CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
58 CORE_ADDR bpaddr);
59 int ppc_linux_memory_remove_breakpoint (struct gdbarch *, struct bp_target_info *);
60 struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
61 const struct regset *ppc_linux_gregset (int);
62 const struct regset *ppc_linux_fpregset (void);
63
64 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
65 struct type *func_type,
66 struct type *valtype,
67 struct regcache *regcache,
68 gdb_byte *readbuf,
69 const gdb_byte *writebuf);
70
71 /* From rs6000-tdep.c... */
72 int altivec_register_p (struct gdbarch *gdbarch, int regno);
73 int spe_register_p (struct gdbarch *gdbarch, int regno);
74
75 /* Return non-zero if the architecture described by GDBARCH has
76 floating-point registers (f0 --- f31 and fpscr). */
77 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
78
79 /* Return non-zero if the architecture described by GDBARCH has
80 Altivec registers (vr0 --- vr31, vrsave and vscr). */
81 int ppc_altivec_support_p (struct gdbarch *gdbarch);
82
83 /* Register set description. */
84
85 struct ppc_reg_offsets
86 {
87 /* General-purpose registers. */
88 int r0_offset;
89 int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
90 int xr_size; /* size for cr, xer, mq. */
91 int pc_offset;
92 int ps_offset;
93 int cr_offset;
94 int lr_offset;
95 int ctr_offset;
96 int xer_offset;
97 int mq_offset;
98
99 /* Floating-point registers. */
100 int f0_offset;
101 int fpscr_offset;
102 int fpscr_size;
103
104 /* AltiVec registers. */
105 int vr0_offset;
106 int vscr_offset;
107 int vrsave_offset;
108 };
109
110 /* Supply register REGNUM in the general-purpose register set REGSET
111 from the buffer specified by GREGS and LEN to register cache
112 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
113
114 extern void ppc_supply_gregset (const struct regset *regset,
115 struct regcache *regcache,
116 int regnum, const void *gregs, size_t len);
117
118 /* Supply register REGNUM in the floating-point register set REGSET
119 from the buffer specified by FPREGS and LEN to register cache
120 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
121
122 extern void ppc_supply_fpregset (const struct regset *regset,
123 struct regcache *regcache,
124 int regnum, const void *fpregs, size_t len);
125
126 /* Supply register REGNUM in the Altivec register set REGSET
127 from the buffer specified by VRREGS and LEN to register cache
128 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
129
130 extern void ppc_supply_vrregset (const struct regset *regset,
131 struct regcache *regcache,
132 int regnum, const void *vrregs, size_t len);
133
134 /* Collect register REGNUM in the general-purpose register set
135 REGSET. from register cache REGCACHE into the buffer specified by
136 GREGS and LEN. If REGNUM is -1, do this for all registers in
137 REGSET. */
138
139 extern void ppc_collect_gregset (const struct regset *regset,
140 const struct regcache *regcache,
141 int regnum, void *gregs, size_t len);
142
143 /* Collect register REGNUM in the floating-point register set
144 REGSET. from register cache REGCACHE into the buffer specified by
145 FPREGS and LEN. If REGNUM is -1, do this for all registers in
146 REGSET. */
147
148 extern void ppc_collect_fpregset (const struct regset *regset,
149 const struct regcache *regcache,
150 int regnum, void *fpregs, size_t len);
151
152 /* Collect register REGNUM in the Altivec register set
153 REGSET from register cache REGCACHE into the buffer specified by
154 VRREGS and LEN. If REGNUM is -1, do this for all registers in
155 REGSET. */
156
157 extern void ppc_collect_vrregset (const struct regset *regset,
158 const struct regcache *regcache,
159 int regnum, void *vrregs, size_t len);
160
161 /* Private data that this module attaches to struct gdbarch. */
162
163 /* Vector ABI used by the inferior. */
164 enum powerpc_vector_abi
165 {
166 POWERPC_VEC_AUTO,
167 POWERPC_VEC_GENERIC,
168 POWERPC_VEC_ALTIVEC,
169 POWERPC_VEC_SPE,
170 POWERPC_VEC_LAST
171 };
172
173 struct gdbarch_tdep
174 {
175 int wordsize; /* Size in bytes of fixed-point word. */
176 int soft_float; /* Avoid FP registers for arguments? */
177
178 /* How to pass vector arguments. Never set to AUTO or LAST. */
179 enum powerpc_vector_abi vector_abi;
180
181 int ppc_gp0_regnum; /* GPR register 0 */
182 int ppc_toc_regnum; /* TOC register */
183 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
184 int ppc_cr_regnum; /* Condition register */
185 int ppc_lr_regnum; /* Link register */
186 int ppc_ctr_regnum; /* Count register */
187 int ppc_xer_regnum; /* Integer exception register */
188
189 /* Not all PPC and RS6000 variants will have the registers
190 represented below. A -1 is used to indicate that the register
191 is not present in this variant. */
192
193 /* Floating-point registers. */
194 int ppc_fp0_regnum; /* floating-point register 0 */
195 int ppc_fpscr_regnum; /* fp status and condition register */
196
197 /* Multiplier-Quotient Register (older POWER architectures only). */
198 int ppc_mq_regnum;
199
200 /* Altivec registers. */
201 int ppc_vr0_regnum; /* First AltiVec register */
202 int ppc_vrsave_regnum; /* Last AltiVec register */
203
204 /* SPE registers. */
205 int ppc_ev0_upper_regnum; /* First GPR upper half register */
206 int ppc_ev0_regnum; /* First ev register */
207 int ppc_acc_regnum; /* SPE 'acc' register */
208 int ppc_spefscr_regnum; /* SPE 'spefscr' register */
209
210 /* Decimal 128 registers. */
211 int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
212
213 /* Offset to ABI specific location where link register is saved. */
214 int lr_frame_offset;
215
216 /* An array of integers, such that sim_regno[I] is the simulator
217 register number for GDB register number I, or -1 if the
218 simulator does not implement that register. */
219 int *sim_regno;
220
221 /* Minimum possible text address. */
222 CORE_ADDR text_segment_base;
223
224 /* ISA-specific types. */
225 struct type *ppc_builtin_type_vec64;
226 };
227
228
229 /* Constants for register set sizes. */
230 enum
231 {
232 ppc_num_gprs = 32, /* 32 general-purpose registers */
233 ppc_num_fprs = 32, /* 32 floating-point registers */
234 ppc_num_srs = 16, /* 16 segment registers */
235 ppc_num_vrs = 32 /* 32 Altivec vector registers */
236 };
237
238
239 /* Register number constants. These are GDB internal register
240 numbers; they are not used for the simulator or remote targets.
241 Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
242 numbers above PPC_NUM_REGS. So are segment registers and other
243 target-defined registers. */
244 enum {
245 PPC_R0_REGNUM = 0,
246 PPC_F0_REGNUM = 32,
247 PPC_PC_REGNUM = 64,
248 PPC_MSR_REGNUM = 65,
249 PPC_CR_REGNUM = 66,
250 PPC_LR_REGNUM = 67,
251 PPC_CTR_REGNUM = 68,
252 PPC_XER_REGNUM = 69,
253 PPC_FPSCR_REGNUM = 70,
254 PPC_MQ_REGNUM = 71,
255 PPC_SPE_UPPER_GP0_REGNUM = 72,
256 PPC_SPE_ACC_REGNUM = 104,
257 PPC_SPE_FSCR_REGNUM = 105,
258 PPC_VR0_REGNUM = 106,
259 PPC_VSCR_REGNUM = 138,
260 PPC_VRSAVE_REGNUM = 139,
261 PPC_NUM_REGS
262 };
263
264
265 /* Instruction size. */
266 #define PPC_INSN_SIZE 4
267
268 /* Estimate for the maximum number of instrctions in a function epilogue. */
269 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
270
271 extern struct target_desc *tdesc_powerpc_e500;
272
273 #endif /* ppc-tdep.h */