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Remove GDBARCH_BREAKPOINT_MANIPULATION and SET_GDBARCH_BREAKPOINT_MANIPULATION
[thirdparty/binutils-gdb.git] / gdb / rl78-tdep.c
1 /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
3 Copyright (C) 2011-2016 Free Software Foundation, Inc.
4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "defs.h"
23 #include "arch-utils.h"
24 #include "prologue-value.h"
25 #include "target.h"
26 #include "regcache.h"
27 #include "opcode/rl78.h"
28 #include "dis-asm.h"
29 #include "gdbtypes.h"
30 #include "frame.h"
31 #include "frame-unwind.h"
32 #include "frame-base.h"
33 #include "value.h"
34 #include "gdbcore.h"
35 #include "dwarf2-frame.h"
36 #include "reggroups.h"
37
38 #include "elf/rl78.h"
39 #include "elf-bfd.h"
40
41 /* Register Banks. */
42
43 enum
44 {
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51 };
52
53 /* Register Numbers. */
54
55 enum
56 {
57 /* All general purpose registers are 8 bits wide. */
58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
108 RL78_PC_REGNUM = RL78_NUM_REGS,
109 RL78_SP_REGNUM,
110
111 RL78_X_REGNUM,
112 RL78_A_REGNUM,
113 RL78_C_REGNUM,
114 RL78_B_REGNUM,
115 RL78_E_REGNUM,
116 RL78_D_REGNUM,
117 RL78_L_REGNUM,
118 RL78_H_REGNUM,
119
120 RL78_AX_REGNUM,
121 RL78_BC_REGNUM,
122 RL78_DE_REGNUM,
123 RL78_HL_REGNUM,
124
125 RL78_BANK0_R0_REGNUM,
126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
133
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
142
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
151
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
160
161 RL78_BANK0_RP0_REGNUM,
162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
165
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
170
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
175
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
180
181 /* These are the same as the above 16 registers, but have
182 a pointer type for use as base registers in expression
183 evaluation. These are not user visible registers. */
184 RL78_BANK0_RP0_PTR_REGNUM,
185 RL78_BANK0_RP1_PTR_REGNUM,
186 RL78_BANK0_RP2_PTR_REGNUM,
187 RL78_BANK0_RP3_PTR_REGNUM,
188
189 RL78_BANK1_RP0_PTR_REGNUM,
190 RL78_BANK1_RP1_PTR_REGNUM,
191 RL78_BANK1_RP2_PTR_REGNUM,
192 RL78_BANK1_RP3_PTR_REGNUM,
193
194 RL78_BANK2_RP0_PTR_REGNUM,
195 RL78_BANK2_RP1_PTR_REGNUM,
196 RL78_BANK2_RP2_PTR_REGNUM,
197 RL78_BANK2_RP3_PTR_REGNUM,
198
199 RL78_BANK3_RP0_PTR_REGNUM,
200 RL78_BANK3_RP1_PTR_REGNUM,
201 RL78_BANK3_RP2_PTR_REGNUM,
202 RL78_BANK3_RP3_PTR_REGNUM,
203
204 RL78_NUM_TOTAL_REGS,
205 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
206 };
207
208 #define RL78_SP_ADDR 0xffff8
209
210 /* Architecture specific data. */
211
212 struct gdbarch_tdep
213 {
214 /* The ELF header flags specify the multilib used. */
215 int elf_flags;
216
217 struct type *rl78_void,
218 *rl78_uint8,
219 *rl78_int8,
220 *rl78_uint16,
221 *rl78_int16,
222 *rl78_uint32,
223 *rl78_int32,
224 *rl78_data_pointer,
225 *rl78_code_pointer,
226 *rl78_psw_type;
227 };
228
229 /* This structure holds the results of a prologue analysis. */
230
231 struct rl78_prologue
232 {
233 /* The offset from the frame base to the stack pointer --- always
234 zero or negative.
235
236 Calling this a "size" is a bit misleading, but given that the
237 stack grows downwards, using offsets for everything keeps one
238 from going completely sign-crazy: you never change anything's
239 sign for an ADD instruction; always change the second operand's
240 sign for a SUB instruction; and everything takes care of
241 itself. */
242 int frame_size;
243
244 /* Non-zero if this function has initialized the frame pointer from
245 the stack pointer, zero otherwise. */
246 int has_frame_ptr;
247
248 /* If has_frame_ptr is non-zero, this is the offset from the frame
249 base to where the frame pointer points. This is always zero or
250 negative. */
251 int frame_ptr_offset;
252
253 /* The address of the first instruction at which the frame has been
254 set up and the arguments are where the debug info says they are
255 --- as best as we can tell. */
256 CORE_ADDR prologue_end;
257
258 /* reg_offset[R] is the offset from the CFA at which register R is
259 saved, or 1 if register R has not been saved. (Real values are
260 always zero or negative.) */
261 int reg_offset[RL78_NUM_TOTAL_REGS];
262 };
263
264 /* Implement the "register_type" gdbarch method. */
265
266 static struct type *
267 rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
268 {
269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270
271 if (reg_nr == RL78_PC_REGNUM)
272 return tdep->rl78_code_pointer;
273 else if (reg_nr == RL78_RAW_PC_REGNUM)
274 return tdep->rl78_uint32;
275 else if (reg_nr == RL78_PSW_REGNUM)
276 return (tdep->rl78_psw_type);
277 else if (reg_nr <= RL78_MEM_REGNUM
278 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
279 || (RL78_BANK0_R0_REGNUM <= reg_nr
280 && reg_nr <= RL78_BANK3_R7_REGNUM))
281 return tdep->rl78_int8;
282 else if (reg_nr == RL78_SP_REGNUM
283 || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
284 && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
285 return tdep->rl78_data_pointer;
286 else
287 return tdep->rl78_int16;
288 }
289
290 /* Implement the "register_name" gdbarch method. */
291
292 static const char *
293 rl78_register_name (struct gdbarch *gdbarch, int regnr)
294 {
295 static const char *const reg_names[] =
296 {
297 "", /* bank0_r0 */
298 "", /* bank0_r1 */
299 "", /* bank0_r2 */
300 "", /* bank0_r3 */
301 "", /* bank0_r4 */
302 "", /* bank0_r5 */
303 "", /* bank0_r6 */
304 "", /* bank0_r7 */
305
306 "", /* bank1_r0 */
307 "", /* bank1_r1 */
308 "", /* bank1_r2 */
309 "", /* bank1_r3 */
310 "", /* bank1_r4 */
311 "", /* bank1_r5 */
312 "", /* bank1_r6 */
313 "", /* bank1_r7 */
314
315 "", /* bank2_r0 */
316 "", /* bank2_r1 */
317 "", /* bank2_r2 */
318 "", /* bank2_r3 */
319 "", /* bank2_r4 */
320 "", /* bank2_r5 */
321 "", /* bank2_r6 */
322 "", /* bank2_r7 */
323
324 "", /* bank3_r0 */
325 "", /* bank3_r1 */
326 "", /* bank3_r2 */
327 "", /* bank3_r3 */
328 "", /* bank3_r4 */
329 "", /* bank3_r5 */
330 "", /* bank3_r6 */
331 "", /* bank3_r7 */
332
333 "psw",
334 "es",
335 "cs",
336 "",
337
338 "", /* spl */
339 "", /* sph */
340 "pmc",
341 "mem",
342
343 "pc",
344 "sp",
345
346 "x",
347 "a",
348 "c",
349 "b",
350 "e",
351 "d",
352 "l",
353 "h",
354
355 "ax",
356 "bc",
357 "de",
358 "hl",
359
360 "bank0_r0",
361 "bank0_r1",
362 "bank0_r2",
363 "bank0_r3",
364 "bank0_r4",
365 "bank0_r5",
366 "bank0_r6",
367 "bank0_r7",
368
369 "bank1_r0",
370 "bank1_r1",
371 "bank1_r2",
372 "bank1_r3",
373 "bank1_r4",
374 "bank1_r5",
375 "bank1_r6",
376 "bank1_r7",
377
378 "bank2_r0",
379 "bank2_r1",
380 "bank2_r2",
381 "bank2_r3",
382 "bank2_r4",
383 "bank2_r5",
384 "bank2_r6",
385 "bank2_r7",
386
387 "bank3_r0",
388 "bank3_r1",
389 "bank3_r2",
390 "bank3_r3",
391 "bank3_r4",
392 "bank3_r5",
393 "bank3_r6",
394 "bank3_r7",
395
396 "bank0_rp0",
397 "bank0_rp1",
398 "bank0_rp2",
399 "bank0_rp3",
400
401 "bank1_rp0",
402 "bank1_rp1",
403 "bank1_rp2",
404 "bank1_rp3",
405
406 "bank2_rp0",
407 "bank2_rp1",
408 "bank2_rp2",
409 "bank2_rp3",
410
411 "bank3_rp0",
412 "bank3_rp1",
413 "bank3_rp2",
414 "bank3_rp3",
415
416 /* The 16 register slots would be named
417 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
418 want these to be user visible registers. */
419 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
420 };
421
422 return reg_names[regnr];
423 }
424
425 /* Implement the "register_name" gdbarch method for the g10 variant. */
426
427 static const char *
428 rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
429 {
430 static const char *const reg_names[] =
431 {
432 "", /* bank0_r0 */
433 "", /* bank0_r1 */
434 "", /* bank0_r2 */
435 "", /* bank0_r3 */
436 "", /* bank0_r4 */
437 "", /* bank0_r5 */
438 "", /* bank0_r6 */
439 "", /* bank0_r7 */
440
441 "", /* bank1_r0 */
442 "", /* bank1_r1 */
443 "", /* bank1_r2 */
444 "", /* bank1_r3 */
445 "", /* bank1_r4 */
446 "", /* bank1_r5 */
447 "", /* bank1_r6 */
448 "", /* bank1_r7 */
449
450 "", /* bank2_r0 */
451 "", /* bank2_r1 */
452 "", /* bank2_r2 */
453 "", /* bank2_r3 */
454 "", /* bank2_r4 */
455 "", /* bank2_r5 */
456 "", /* bank2_r6 */
457 "", /* bank2_r7 */
458
459 "", /* bank3_r0 */
460 "", /* bank3_r1 */
461 "", /* bank3_r2 */
462 "", /* bank3_r3 */
463 "", /* bank3_r4 */
464 "", /* bank3_r5 */
465 "", /* bank3_r6 */
466 "", /* bank3_r7 */
467
468 "psw",
469 "es",
470 "cs",
471 "",
472
473 "", /* spl */
474 "", /* sph */
475 "pmc",
476 "mem",
477
478 "pc",
479 "sp",
480
481 "x",
482 "a",
483 "c",
484 "b",
485 "e",
486 "d",
487 "l",
488 "h",
489
490 "ax",
491 "bc",
492 "de",
493 "hl",
494
495 "bank0_r0",
496 "bank0_r1",
497 "bank0_r2",
498 "bank0_r3",
499 "bank0_r4",
500 "bank0_r5",
501 "bank0_r6",
502 "bank0_r7",
503
504 "",
505 "",
506 "",
507 "",
508 "",
509 "",
510 "",
511 "",
512
513 "",
514 "",
515 "",
516 "",
517 "",
518 "",
519 "",
520 "",
521
522 "",
523 "",
524 "",
525 "",
526 "",
527 "",
528 "",
529 "",
530
531 "bank0_rp0",
532 "bank0_rp1",
533 "bank0_rp2",
534 "bank0_rp3",
535
536 "",
537 "",
538 "",
539 "",
540
541 "",
542 "",
543 "",
544 "",
545
546 "",
547 "",
548 "",
549 "",
550
551 /* The 16 register slots would be named
552 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
553 want these to be user visible registers. */
554 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
555 };
556
557 return reg_names[regnr];
558 }
559
560 /* Implement the "register_reggroup_p" gdbarch method. */
561
562 static int
563 rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
564 struct reggroup *group)
565 {
566 if (group == all_reggroup)
567 return 1;
568
569 /* All other registers are saved and restored. */
570 if (group == save_reggroup || group == restore_reggroup)
571 {
572 if ((regnum < RL78_NUM_REGS
573 && regnum != RL78_SPL_REGNUM
574 && regnum != RL78_SPH_REGNUM
575 && regnum != RL78_RAW_PC_REGNUM)
576 || regnum == RL78_SP_REGNUM
577 || regnum == RL78_PC_REGNUM)
578 return 1;
579 else
580 return 0;
581 }
582
583 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
584 || regnum == RL78_ES_REGNUM
585 || regnum == RL78_CS_REGNUM
586 || regnum == RL78_SPL_REGNUM
587 || regnum == RL78_SPH_REGNUM
588 || regnum == RL78_PMC_REGNUM
589 || regnum == RL78_MEM_REGNUM
590 || regnum == RL78_RAW_PC_REGNUM
591 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
592 return group == system_reggroup;
593
594 return group == general_reggroup;
595 }
596
597 /* Strip bits to form an instruction address. (When fetching a
598 32-bit address from the stack, the high eight bits are garbage.
599 This function strips off those unused bits.) */
600
601 static CORE_ADDR
602 rl78_make_instruction_address (CORE_ADDR addr)
603 {
604 return addr & 0xffffff;
605 }
606
607 /* Set / clear bits necessary to make a data address. */
608
609 static CORE_ADDR
610 rl78_make_data_address (CORE_ADDR addr)
611 {
612 return (addr & 0xffff) | 0xf0000;
613 }
614
615 /* Implement the "pseudo_register_read" gdbarch method. */
616
617 static enum register_status
618 rl78_pseudo_register_read (struct gdbarch *gdbarch,
619 struct regcache *regcache,
620 int reg, gdb_byte *buffer)
621 {
622 enum register_status status;
623
624 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
625 {
626 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
627 + (reg - RL78_BANK0_R0_REGNUM);
628
629 status = regcache_raw_read (regcache, raw_regnum, buffer);
630 }
631 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
632 {
633 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
634 + RL78_RAW_BANK0_R0_REGNUM;
635
636 status = regcache_raw_read (regcache, raw_regnum, buffer);
637 if (status == REG_VALID)
638 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
639 }
640 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
641 {
642 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
643 + RL78_RAW_BANK0_R0_REGNUM;
644
645 status = regcache_raw_read (regcache, raw_regnum, buffer);
646 if (status == REG_VALID)
647 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
648 }
649 else if (reg == RL78_SP_REGNUM)
650 {
651 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
652 if (status == REG_VALID)
653 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
654 }
655 else if (reg == RL78_PC_REGNUM)
656 {
657 gdb_byte rawbuf[4];
658
659 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
660 memcpy (buffer, rawbuf, 3);
661 }
662 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
663 {
664 ULONGEST psw;
665
666 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
667 if (status == REG_VALID)
668 {
669 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
670 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
671 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
672 + (reg - RL78_X_REGNUM);
673 status = regcache_raw_read (regcache, raw_regnum, buffer);
674 }
675 }
676 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
677 {
678 ULONGEST psw;
679
680 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
681 if (status == REG_VALID)
682 {
683 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
684 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
685 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
686 + 2 * (reg - RL78_AX_REGNUM);
687 status = regcache_raw_read (regcache, raw_regnum, buffer);
688 if (status == REG_VALID)
689 status = regcache_raw_read (regcache, raw_regnum + 1,
690 buffer + 1);
691 }
692 }
693 else
694 gdb_assert_not_reached ("invalid pseudo register number");
695 return status;
696 }
697
698 /* Implement the "pseudo_register_write" gdbarch method. */
699
700 static void
701 rl78_pseudo_register_write (struct gdbarch *gdbarch,
702 struct regcache *regcache,
703 int reg, const gdb_byte *buffer)
704 {
705 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
706 {
707 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
708 + (reg - RL78_BANK0_R0_REGNUM);
709
710 regcache_raw_write (regcache, raw_regnum, buffer);
711 }
712 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
713 {
714 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
715 + RL78_RAW_BANK0_R0_REGNUM;
716
717 regcache_raw_write (regcache, raw_regnum, buffer);
718 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
719 }
720 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
721 {
722 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
723 + RL78_RAW_BANK0_R0_REGNUM;
724
725 regcache_raw_write (regcache, raw_regnum, buffer);
726 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
727 }
728 else if (reg == RL78_SP_REGNUM)
729 {
730 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
731 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
732 }
733 else if (reg == RL78_PC_REGNUM)
734 {
735 gdb_byte rawbuf[4];
736
737 memcpy (rawbuf, buffer, 3);
738 rawbuf[3] = 0;
739 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
740 }
741 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
742 {
743 ULONGEST psw;
744 int bank;
745 int raw_regnum;
746
747 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
748 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
749 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
750 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
751 + (reg - RL78_X_REGNUM);
752 regcache_raw_write (regcache, raw_regnum, buffer);
753 }
754 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
755 {
756 ULONGEST psw;
757 int bank, raw_regnum;
758
759 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
760 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
761 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
762 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
763 + 2 * (reg - RL78_AX_REGNUM);
764 regcache_raw_write (regcache, raw_regnum, buffer);
765 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
766 }
767 else
768 gdb_assert_not_reached ("invalid pseudo register number");
769 }
770
771 /* The documented BRK instruction is actually a two byte sequence,
772 {0x61, 0xcc}, but instructions may be as short as one byte.
773 Correspondence with Renesas revealed that the one byte sequence
774 0xff is used when a one byte breakpoint instruction is required. */
775 constexpr gdb_byte rl78_break_insn[] = { 0xff };
776
777 typedef BP_MANIPULATION (rl78_break_insn) rl78_breakpoint;
778
779 /* Define a "handle" struct for fetching the next opcode. */
780
781 struct rl78_get_opcode_byte_handle
782 {
783 CORE_ADDR pc;
784 };
785
786 static int
787 opc_reg_to_gdb_regnum (int opcreg)
788 {
789 switch (opcreg)
790 {
791 case RL78_Reg_X:
792 return RL78_X_REGNUM;
793 case RL78_Reg_A:
794 return RL78_A_REGNUM;
795 case RL78_Reg_C:
796 return RL78_C_REGNUM;
797 case RL78_Reg_B:
798 return RL78_B_REGNUM;
799 case RL78_Reg_E:
800 return RL78_E_REGNUM;
801 case RL78_Reg_D:
802 return RL78_D_REGNUM;
803 case RL78_Reg_L:
804 return RL78_L_REGNUM;
805 case RL78_Reg_H:
806 return RL78_H_REGNUM;
807 case RL78_Reg_AX:
808 return RL78_AX_REGNUM;
809 case RL78_Reg_BC:
810 return RL78_BC_REGNUM;
811 case RL78_Reg_DE:
812 return RL78_DE_REGNUM;
813 case RL78_Reg_HL:
814 return RL78_HL_REGNUM;
815 case RL78_Reg_SP:
816 return RL78_SP_REGNUM;
817 case RL78_Reg_PSW:
818 return RL78_PSW_REGNUM;
819 case RL78_Reg_CS:
820 return RL78_CS_REGNUM;
821 case RL78_Reg_ES:
822 return RL78_ES_REGNUM;
823 case RL78_Reg_PMC:
824 return RL78_PMC_REGNUM;
825 case RL78_Reg_MEM:
826 return RL78_MEM_REGNUM;
827 default:
828 internal_error (__FILE__, __LINE__,
829 _("Undefined mapping for opc reg %d"),
830 opcreg);
831 }
832
833 /* Not reached. */
834 return 0;
835 }
836
837 /* Fetch a byte on behalf of the opcode decoder. HANDLE contains
838 the memory address of the next byte to fetch. If successful,
839 the address in the handle is updated and the byte fetched is
840 returned as the value of the function. If not successful, -1
841 is returned. */
842
843 static int
844 rl78_get_opcode_byte (void *handle)
845 {
846 struct rl78_get_opcode_byte_handle *opcdata
847 = (struct rl78_get_opcode_byte_handle *) handle;
848 int status;
849 gdb_byte byte;
850
851 status = target_read_memory (opcdata->pc, &byte, 1);
852 if (status == 0)
853 {
854 opcdata->pc += 1;
855 return byte;
856 }
857 else
858 return -1;
859 }
860
861 /* Function for finding saved registers in a 'struct pv_area'; this
862 function is passed to pv_area_scan.
863
864 If VALUE is a saved register, ADDR says it was saved at a constant
865 offset from the frame base, and SIZE indicates that the whole
866 register was saved, record its offset. */
867
868 static void
869 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
870 pv_t value)
871 {
872 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
873
874 if (value.kind == pvk_register
875 && value.k == 0
876 && pv_is_register (addr, RL78_SP_REGNUM)
877 && size == register_size (target_gdbarch (), value.reg))
878 result->reg_offset[value.reg] = addr.k;
879 }
880
881 /* Analyze a prologue starting at START_PC, going no further than
882 LIMIT_PC. Fill in RESULT as appropriate. */
883
884 static void
885 rl78_analyze_prologue (CORE_ADDR start_pc,
886 CORE_ADDR limit_pc, struct rl78_prologue *result)
887 {
888 CORE_ADDR pc, next_pc;
889 int rn;
890 pv_t reg[RL78_NUM_TOTAL_REGS];
891 struct pv_area *stack;
892 struct cleanup *back_to;
893 CORE_ADDR after_last_frame_setup_insn = start_pc;
894 int bank = 0;
895
896 memset (result, 0, sizeof (*result));
897
898 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
899 {
900 reg[rn] = pv_register (rn, 0);
901 result->reg_offset[rn] = 1;
902 }
903
904 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
905 back_to = make_cleanup_free_pv_area (stack);
906
907 /* The call instruction has saved the return address on the stack. */
908 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
909 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
910
911 pc = start_pc;
912 while (pc < limit_pc)
913 {
914 int bytes_read;
915 struct rl78_get_opcode_byte_handle opcode_handle;
916 RL78_Opcode_Decoded opc;
917
918 opcode_handle.pc = pc;
919 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
920 &opcode_handle, RL78_ISA_DEFAULT);
921 next_pc = pc + bytes_read;
922
923 if (opc.id == RLO_sel)
924 {
925 bank = opc.op[1].addend;
926 }
927 else if (opc.id == RLO_mov
928 && opc.op[0].type == RL78_Operand_PreDec
929 && opc.op[0].reg == RL78_Reg_SP
930 && opc.op[1].type == RL78_Operand_Register)
931 {
932 int rsrc = (bank * RL78_REGS_PER_BANK)
933 + 2 * (opc.op[1].reg - RL78_Reg_AX);
934
935 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
936 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
937 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
938 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
939 after_last_frame_setup_insn = next_pc;
940 }
941 else if (opc.id == RLO_sub
942 && opc.op[0].type == RL78_Operand_Register
943 && opc.op[0].reg == RL78_Reg_SP
944 && opc.op[1].type == RL78_Operand_Immediate)
945 {
946 int addend = opc.op[1].addend;
947
948 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
949 -addend);
950 after_last_frame_setup_insn = next_pc;
951 }
952 else if (opc.id == RLO_mov
953 && opc.size == RL78_Word
954 && opc.op[0].type == RL78_Operand_Register
955 && opc.op[1].type == RL78_Operand_Indirect
956 && opc.op[1].addend == RL78_SP_ADDR)
957 {
958 reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
959 = reg[RL78_SP_REGNUM];
960 }
961 else if (opc.id == RLO_sub
962 && opc.size == RL78_Word
963 && opc.op[0].type == RL78_Operand_Register
964 && opc.op[1].type == RL78_Operand_Immediate)
965 {
966 int addend = opc.op[1].addend;
967 int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
968
969 reg[regnum] = pv_add_constant (reg[regnum], -addend);
970 }
971 else if (opc.id == RLO_mov
972 && opc.size == RL78_Word
973 && opc.op[0].type == RL78_Operand_Indirect
974 && opc.op[0].addend == RL78_SP_ADDR
975 && opc.op[1].type == RL78_Operand_Register)
976 {
977 reg[RL78_SP_REGNUM]
978 = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
979 after_last_frame_setup_insn = next_pc;
980 }
981 else
982 {
983 /* Terminate the prologue scan. */
984 break;
985 }
986
987 pc = next_pc;
988 }
989
990 /* Is the frame size (offset, really) a known constant? */
991 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
992 result->frame_size = reg[RL78_SP_REGNUM].k;
993
994 /* Record where all the registers were saved. */
995 pv_area_scan (stack, check_for_saved, (void *) result);
996
997 result->prologue_end = after_last_frame_setup_insn;
998
999 do_cleanups (back_to);
1000 }
1001
1002 /* Implement the "addr_bits_remove" gdbarch method. */
1003
1004 static CORE_ADDR
1005 rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
1006 {
1007 return addr & 0xffffff;
1008 }
1009
1010 /* Implement the "address_to_pointer" gdbarch method. */
1011
1012 static void
1013 rl78_address_to_pointer (struct gdbarch *gdbarch,
1014 struct type *type, gdb_byte *buf, CORE_ADDR addr)
1015 {
1016 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1017
1018 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
1019 addr & 0xffffff);
1020 }
1021
1022 /* Implement the "pointer_to_address" gdbarch method. */
1023
1024 static CORE_ADDR
1025 rl78_pointer_to_address (struct gdbarch *gdbarch,
1026 struct type *type, const gdb_byte *buf)
1027 {
1028 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1029 CORE_ADDR addr
1030 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
1031
1032 /* Is it a code address? */
1033 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
1034 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
1035 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
1036 || TYPE_LENGTH (type) == 4)
1037 return rl78_make_instruction_address (addr);
1038 else
1039 return rl78_make_data_address (addr);
1040 }
1041
1042 /* Implement the "skip_prologue" gdbarch method. */
1043
1044 static CORE_ADDR
1045 rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1046 {
1047 const char *name;
1048 CORE_ADDR func_addr, func_end;
1049 struct rl78_prologue p;
1050
1051 /* Try to find the extent of the function that contains PC. */
1052 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1053 return pc;
1054
1055 rl78_analyze_prologue (pc, func_end, &p);
1056 return p.prologue_end;
1057 }
1058
1059 /* Implement the "unwind_pc" gdbarch method. */
1060
1061 static CORE_ADDR
1062 rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1063 {
1064 return rl78_addr_bits_remove
1065 (arch, frame_unwind_register_unsigned (next_frame,
1066 RL78_PC_REGNUM));
1067 }
1068
1069 /* Implement the "unwind_sp" gdbarch method. */
1070
1071 static CORE_ADDR
1072 rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1073 {
1074 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
1075 }
1076
1077 /* Given a frame described by THIS_FRAME, decode the prologue of its
1078 associated function if there is not cache entry as specified by
1079 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
1080 return that struct as the value of this function. */
1081
1082 static struct rl78_prologue *
1083 rl78_analyze_frame_prologue (struct frame_info *this_frame,
1084 void **this_prologue_cache)
1085 {
1086 if (!*this_prologue_cache)
1087 {
1088 CORE_ADDR func_start, stop_addr;
1089
1090 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
1091
1092 func_start = get_frame_func (this_frame);
1093 stop_addr = get_frame_pc (this_frame);
1094
1095 /* If we couldn't find any function containing the PC, then
1096 just initialize the prologue cache, but don't do anything. */
1097 if (!func_start)
1098 stop_addr = func_start;
1099
1100 rl78_analyze_prologue (func_start, stop_addr,
1101 (struct rl78_prologue *) *this_prologue_cache);
1102 }
1103
1104 return (struct rl78_prologue *) *this_prologue_cache;
1105 }
1106
1107 /* Given a frame and a prologue cache, return this frame's base. */
1108
1109 static CORE_ADDR
1110 rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1111 {
1112 struct rl78_prologue *p
1113 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1114 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
1115
1116 return rl78_make_data_address (sp - p->frame_size);
1117 }
1118
1119 /* Implement the "frame_this_id" method for unwinding frames. */
1120
1121 static void
1122 rl78_this_id (struct frame_info *this_frame,
1123 void **this_prologue_cache, struct frame_id *this_id)
1124 {
1125 *this_id = frame_id_build (rl78_frame_base (this_frame,
1126 this_prologue_cache),
1127 get_frame_func (this_frame));
1128 }
1129
1130 /* Implement the "frame_prev_register" method for unwinding frames. */
1131
1132 static struct value *
1133 rl78_prev_register (struct frame_info *this_frame,
1134 void **this_prologue_cache, int regnum)
1135 {
1136 struct rl78_prologue *p
1137 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1138 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1139
1140 if (regnum == RL78_SP_REGNUM)
1141 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1142
1143 else if (regnum == RL78_SPL_REGNUM)
1144 return frame_unwind_got_constant (this_frame, regnum,
1145 (frame_base & 0xff));
1146
1147 else if (regnum == RL78_SPH_REGNUM)
1148 return frame_unwind_got_constant (this_frame, regnum,
1149 ((frame_base >> 8) & 0xff));
1150
1151 /* If prologue analysis says we saved this register somewhere,
1152 return a description of the stack slot holding it. */
1153 else if (p->reg_offset[regnum] != 1)
1154 {
1155 struct value *rv =
1156 frame_unwind_got_memory (this_frame, regnum,
1157 frame_base + p->reg_offset[regnum]);
1158
1159 if (regnum == RL78_PC_REGNUM)
1160 {
1161 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1162
1163 return frame_unwind_got_constant (this_frame, regnum, pc);
1164 }
1165 return rv;
1166 }
1167
1168 /* Otherwise, presume we haven't changed the value of this
1169 register, and get it from the next frame. */
1170 else
1171 return frame_unwind_got_register (this_frame, regnum, regnum);
1172 }
1173
1174 static const struct frame_unwind rl78_unwind =
1175 {
1176 NORMAL_FRAME,
1177 default_frame_unwind_stop_reason,
1178 rl78_this_id,
1179 rl78_prev_register,
1180 NULL,
1181 default_frame_sniffer
1182 };
1183
1184 /* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1185
1186 static int
1187 rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1188 {
1189 if (0 <= reg && reg <= 31)
1190 {
1191 if ((reg & 1) == 0)
1192 /* Map even registers to their 16-bit counterparts which have a
1193 pointer type. This is usually what is required from the DWARF
1194 info. */
1195 return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
1196 else
1197 return reg;
1198 }
1199 else if (reg == 32)
1200 return RL78_SP_REGNUM;
1201 else if (reg == 33)
1202 return -1; /* ap */
1203 else if (reg == 34)
1204 return RL78_PSW_REGNUM;
1205 else if (reg == 35)
1206 return RL78_ES_REGNUM;
1207 else if (reg == 36)
1208 return RL78_CS_REGNUM;
1209 else if (reg == 37)
1210 return RL78_PC_REGNUM;
1211 else
1212 return -1;
1213 }
1214
1215 /* Implement the `register_sim_regno' gdbarch method. */
1216
1217 static int
1218 rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1219 {
1220 gdb_assert (regnum < RL78_NUM_REGS);
1221
1222 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1223 just want to override the default here which disallows register
1224 numbers which have no names. */
1225 return regnum;
1226 }
1227
1228 /* Implement the "return_value" gdbarch method. */
1229
1230 static enum return_value_convention
1231 rl78_return_value (struct gdbarch *gdbarch,
1232 struct value *function,
1233 struct type *valtype,
1234 struct regcache *regcache,
1235 gdb_byte *readbuf, const gdb_byte *writebuf)
1236 {
1237 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1238 ULONGEST valtype_len = TYPE_LENGTH (valtype);
1239 int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
1240
1241 if (valtype_len > 8)
1242 return RETURN_VALUE_STRUCT_CONVENTION;
1243
1244 if (readbuf)
1245 {
1246 ULONGEST u;
1247 int argreg = RL78_RAW_BANK1_R0_REGNUM;
1248 CORE_ADDR g10_raddr = 0xffec8;
1249 int offset = 0;
1250
1251 while (valtype_len > 0)
1252 {
1253 if (is_g10)
1254 u = read_memory_integer (g10_raddr, 1,
1255 gdbarch_byte_order (gdbarch));
1256 else
1257 regcache_cooked_read_unsigned (regcache, argreg, &u);
1258 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1259 valtype_len -= 1;
1260 offset += 1;
1261 argreg++;
1262 g10_raddr++;
1263 }
1264 }
1265
1266 if (writebuf)
1267 {
1268 ULONGEST u;
1269 int argreg = RL78_RAW_BANK1_R0_REGNUM;
1270 CORE_ADDR g10_raddr = 0xffec8;
1271 int offset = 0;
1272
1273 while (valtype_len > 0)
1274 {
1275 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
1276 if (is_g10) {
1277 gdb_byte b = u & 0xff;
1278 write_memory (g10_raddr, &b, 1);
1279 }
1280 else
1281 regcache_cooked_write_unsigned (regcache, argreg, u);
1282 valtype_len -= 1;
1283 offset += 1;
1284 argreg++;
1285 g10_raddr++;
1286 }
1287 }
1288
1289 return RETURN_VALUE_REGISTER_CONVENTION;
1290 }
1291
1292
1293 /* Implement the "frame_align" gdbarch method. */
1294
1295 static CORE_ADDR
1296 rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1297 {
1298 return rl78_make_data_address (align_down (sp, 2));
1299 }
1300
1301
1302 /* Implement the "dummy_id" gdbarch method. */
1303
1304 static struct frame_id
1305 rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1306 {
1307 return
1308 frame_id_build (rl78_make_data_address
1309 (get_frame_register_unsigned
1310 (this_frame, RL78_SP_REGNUM)),
1311 get_frame_pc (this_frame));
1312 }
1313
1314
1315 /* Implement the "push_dummy_call" gdbarch method. */
1316
1317 static CORE_ADDR
1318 rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1319 struct regcache *regcache, CORE_ADDR bp_addr,
1320 int nargs, struct value **args, CORE_ADDR sp,
1321 int struct_return, CORE_ADDR struct_addr)
1322 {
1323 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1324 gdb_byte buf[4];
1325 int i;
1326
1327 /* Push arguments in reverse order. */
1328 for (i = nargs - 1; i >= 0; i--)
1329 {
1330 struct type *value_type = value_enclosing_type (args[i]);
1331 int len = TYPE_LENGTH (value_type);
1332 int container_len = (len + 1) & ~1;
1333
1334 sp -= container_len;
1335 write_memory (rl78_make_data_address (sp),
1336 value_contents_all (args[i]), len);
1337 }
1338
1339 /* Store struct value address. */
1340 if (struct_return)
1341 {
1342 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1343 sp -= 2;
1344 write_memory (rl78_make_data_address (sp), buf, 2);
1345 }
1346
1347 /* Store return address. */
1348 sp -= 4;
1349 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1350 write_memory (rl78_make_data_address (sp), buf, 4);
1351
1352 /* Finally, update the stack pointer... */
1353 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1354
1355 /* DWARF2/GCC uses the stack address *before* the function call as a
1356 frame's CFA. */
1357 return rl78_make_data_address (sp + 4);
1358 }
1359
1360 /* Allocate and initialize a gdbarch object. */
1361
1362 static struct gdbarch *
1363 rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1364 {
1365 struct gdbarch *gdbarch;
1366 struct gdbarch_tdep *tdep;
1367 int elf_flags;
1368
1369 /* Extract the elf_flags if available. */
1370 if (info.abfd != NULL
1371 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1372 elf_flags = elf_elfheader (info.abfd)->e_flags;
1373 else
1374 elf_flags = 0;
1375
1376
1377 /* Try to find the architecture in the list of already defined
1378 architectures. */
1379 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1380 arches != NULL;
1381 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1382 {
1383 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1384 continue;
1385
1386 return arches->gdbarch;
1387 }
1388
1389 /* None found, create a new architecture from the information
1390 provided. */
1391 tdep = XNEW (struct gdbarch_tdep);
1392 gdbarch = gdbarch_alloc (&info, tdep);
1393 tdep->elf_flags = elf_flags;
1394
1395 /* Initialize types. */
1396 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1397 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1398 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1399 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1400 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1401 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1402 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1403
1404 tdep->rl78_data_pointer
1405 = arch_pointer_type (gdbarch, 16, "rl78_data_addr_t", tdep->rl78_void);
1406 tdep->rl78_code_pointer
1407 = arch_pointer_type (gdbarch, 32, "rl78_code_addr_t", tdep->rl78_void);
1408
1409 tdep->rl78_psw_type = arch_flags_type (gdbarch, "builtin_type_rl78_psw", 1);
1410 append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
1411 append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
1412 append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
1413 append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
1414 append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
1415 append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
1416 append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
1417 append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
1418
1419 /* Registers. */
1420 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1421 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
1422 if (tdep->elf_flags & E_FLAG_RL78_G10)
1423 set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1424 else
1425 set_gdbarch_register_name (gdbarch, rl78_register_name);
1426 set_gdbarch_register_type (gdbarch, rl78_register_type);
1427 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1428 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1429 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1430 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1431 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
1432 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1433 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
1434
1435 /* Data types. */
1436 set_gdbarch_char_signed (gdbarch, 0);
1437 set_gdbarch_short_bit (gdbarch, 16);
1438 set_gdbarch_int_bit (gdbarch, 16);
1439 set_gdbarch_long_bit (gdbarch, 32);
1440 set_gdbarch_long_long_bit (gdbarch, 64);
1441 set_gdbarch_ptr_bit (gdbarch, 16);
1442 set_gdbarch_addr_bit (gdbarch, 32);
1443 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
1444 set_gdbarch_float_bit (gdbarch, 32);
1445 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1446 set_gdbarch_double_bit (gdbarch, 32);
1447 set_gdbarch_long_double_bit (gdbarch, 64);
1448 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1449 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1450 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1451 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1452 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1453
1454 /* Breakpoints. */
1455 set_gdbarch_breakpoint_kind_from_pc (gdbarch, rl78_breakpoint::kind_from_pc);
1456 set_gdbarch_sw_breakpoint_from_kind (gdbarch, rl78_breakpoint::bp_from_kind);
1457 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1458
1459 /* Disassembly. */
1460 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1461
1462 /* Frames, prologues, etc. */
1463 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1464 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1465 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1466 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1467 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
1468
1469 dwarf2_append_unwinders (gdbarch);
1470 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1471
1472 /* Dummy frames, return values. */
1473 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1474 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1475 set_gdbarch_return_value (gdbarch, rl78_return_value);
1476
1477 /* Virtual tables. */
1478 set_gdbarch_vbit_in_delta (gdbarch, 1);
1479
1480 return gdbarch;
1481 }
1482
1483 /* -Wmissing-prototypes */
1484 extern initialize_file_ftype _initialize_rl78_tdep;
1485
1486 /* Register the above initialization routine. */
1487
1488 void
1489 _initialize_rl78_tdep (void)
1490 {
1491 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1492 }
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