1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 struct ppc_inferior_data
160 /* This is an optional in case we add more fields to ppc_inferior_data, we
161 don't want it instantiated as soon as we get the ppc_inferior_data for an
163 gdb::optional
<displaced_step_buffers
> disp_step_buf
;
166 static inferior_key
<ppc_inferior_data
> ppc_inferior_data_key
;
168 /* Get the per-inferior PowerPC data for INF. */
170 static ppc_inferior_data
*
171 get_ppc_per_inferior (inferior
*inf
)
173 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
175 if (per_inf
== nullptr)
176 per_inf
= ppc_inferior_data_key
.emplace (inf
);
181 /* To be used by skip_prologue. */
183 struct rs6000_framedata
185 int offset
; /* total size of frame --- the distance
186 by which we decrement sp to allocate
188 int saved_gpr
; /* smallest # of saved gpr */
189 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
190 int saved_fpr
; /* smallest # of saved fpr */
191 int saved_vr
; /* smallest # of saved vr */
192 int saved_ev
; /* smallest # of saved ev */
193 int alloca_reg
; /* alloca register number (frame ptr) */
194 char frameless
; /* true if frameless functions. */
195 char nosavedpc
; /* true if pc not saved. */
196 char used_bl
; /* true if link register clobbered */
197 int gpr_offset
; /* offset of saved gprs from prev sp */
198 int fpr_offset
; /* offset of saved fprs from prev sp */
199 int vr_offset
; /* offset of saved vrs from prev sp */
200 int ev_offset
; /* offset of saved evs from prev sp */
201 int lr_offset
; /* offset of saved lr */
202 int lr_register
; /* register of saved lr, if trustworthy */
203 int cr_offset
; /* offset of saved cr */
204 int vrsave_offset
; /* offset of saved vrsave register */
208 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
210 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
213 if (tdep
->ppc_vsr0_regnum
< 0)
216 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
217 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
220 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
222 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
228 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
232 /* Return true if REGNO is an SPE register, false otherwise. */
234 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* Is it a reference to EV0 -- EV31, and do we have those? */
239 if (IS_SPE_PSEUDOREG (tdep
, regno
))
242 /* Is it a reference to one of the raw upper GPR halves? */
243 if (tdep
->ppc_ev0_upper_regnum
>= 0
244 && tdep
->ppc_ev0_upper_regnum
<= regno
245 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
248 /* Is it a reference to the 64-bit accumulator, and do we have that? */
249 if (tdep
->ppc_acc_regnum
>= 0
250 && tdep
->ppc_acc_regnum
== regno
)
253 /* Is it a reference to the SPE floating-point status and control register,
254 and do we have that? */
255 if (tdep
->ppc_spefscr_regnum
>= 0
256 && tdep
->ppc_spefscr_regnum
== regno
)
263 /* Return non-zero if the architecture described by GDBARCH has
264 floating-point registers (f0 --- f31 and fpscr). */
266 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 return (tdep
->ppc_fp0_regnum
>= 0
271 && tdep
->ppc_fpscr_regnum
>= 0);
274 /* Return non-zero if the architecture described by GDBARCH has
275 Altivec registers (vr0 --- vr31, vrsave and vscr). */
277 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
281 return (tdep
->ppc_vr0_regnum
>= 0
282 && tdep
->ppc_vrsave_regnum
>= 0);
285 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
288 This is a helper function for init_sim_regno_table, constructing
289 the table mapping GDB register numbers to sim register numbers; we
290 initialize every element in that table to -1 before we start
293 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
295 /* Make sure we don't try to assign any given GDB register a sim
296 register number more than once. */
297 gdb_assert (table
[gdb_regno
] == -1);
298 table
[gdb_regno
] = sim_regno
;
302 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
303 numbers to simulator register numbers, based on the values placed
304 in the ARCH->tdep->ppc_foo_regnum members. */
306 init_sim_regno_table (struct gdbarch
*arch
)
308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
309 int total_regs
= gdbarch_num_regs (arch
);
310 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
312 static const char *const segment_regs
[] = {
313 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
314 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
317 /* Presume that all registers not explicitly mentioned below are
318 unavailable from the sim. */
319 for (i
= 0; i
< total_regs
; i
++)
322 /* General-purpose registers. */
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
326 /* Floating-point registers. */
327 if (tdep
->ppc_fp0_regnum
>= 0)
328 for (i
= 0; i
< ppc_num_fprs
; i
++)
329 set_sim_regno (sim_regno
,
330 tdep
->ppc_fp0_regnum
+ i
,
331 sim_ppc_f0_regnum
+ i
);
332 if (tdep
->ppc_fpscr_regnum
>= 0)
333 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
335 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
336 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
337 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
339 /* Segment registers. */
340 for (i
= 0; i
< ppc_num_srs
; i
++)
344 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
346 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
349 /* Altivec registers. */
350 if (tdep
->ppc_vr0_regnum
>= 0)
352 for (i
= 0; i
< ppc_num_vrs
; i
++)
353 set_sim_regno (sim_regno
,
354 tdep
->ppc_vr0_regnum
+ i
,
355 sim_ppc_vr0_regnum
+ i
);
357 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
358 we can treat this more like the other cases. */
359 set_sim_regno (sim_regno
,
360 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
361 sim_ppc_vscr_regnum
);
363 /* vsave is a special-purpose register, so the code below handles it. */
365 /* SPE APU (E500) registers. */
366 if (tdep
->ppc_ev0_upper_regnum
>= 0)
367 for (i
= 0; i
< ppc_num_gprs
; i
++)
368 set_sim_regno (sim_regno
,
369 tdep
->ppc_ev0_upper_regnum
+ i
,
370 sim_ppc_rh0_regnum
+ i
);
371 if (tdep
->ppc_acc_regnum
>= 0)
372 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
373 /* spefscr is a special-purpose register, so the code below handles it. */
376 /* Now handle all special-purpose registers. Verify that they
377 haven't mistakenly been assigned numbers by any of the above
379 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
381 const char *spr_name
= sim_spr_register_name (i
);
384 if (spr_name
!= NULL
)
385 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
388 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
392 /* Drop the initialized array into place. */
393 tdep
->sim_regno
= sim_regno
;
397 /* Given a GDB register number REG, return the corresponding SIM
400 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
405 if (tdep
->sim_regno
== NULL
)
406 init_sim_regno_table (gdbarch
);
408 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
409 sim_regno
= tdep
->sim_regno
[reg
];
414 return LEGACY_SIM_REGNO_IGNORE
;
419 /* Register set support functions. */
421 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
422 Write the register to REGCACHE. */
425 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
426 const gdb_byte
*regs
, size_t offset
, int regsize
)
428 if (regnum
!= -1 && offset
!= -1)
432 struct gdbarch
*gdbarch
= regcache
->arch ();
433 int gdb_regsize
= register_size (gdbarch
, regnum
);
434 if (gdb_regsize
< regsize
435 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
436 offset
+= regsize
- gdb_regsize
;
438 regcache
->raw_supply (regnum
, regs
+ offset
);
442 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
443 in a field REGSIZE wide. Zero pad as necessary. */
446 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
447 gdb_byte
*regs
, size_t offset
, int regsize
)
449 if (regnum
!= -1 && offset
!= -1)
453 struct gdbarch
*gdbarch
= regcache
->arch ();
454 int gdb_regsize
= register_size (gdbarch
, regnum
);
455 if (gdb_regsize
< regsize
)
457 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
459 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
460 offset
+= regsize
- gdb_regsize
;
463 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
464 regsize
- gdb_regsize
);
467 regcache
->raw_collect (regnum
, regs
+ offset
);
472 ppc_greg_offset (struct gdbarch
*gdbarch
,
473 struct gdbarch_tdep
*tdep
,
474 const struct ppc_reg_offsets
*offsets
,
478 *regsize
= offsets
->gpr_size
;
479 if (regnum
>= tdep
->ppc_gp0_regnum
480 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
481 return (offsets
->r0_offset
482 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
484 if (regnum
== gdbarch_pc_regnum (gdbarch
))
485 return offsets
->pc_offset
;
487 if (regnum
== tdep
->ppc_ps_regnum
)
488 return offsets
->ps_offset
;
490 if (regnum
== tdep
->ppc_lr_regnum
)
491 return offsets
->lr_offset
;
493 if (regnum
== tdep
->ppc_ctr_regnum
)
494 return offsets
->ctr_offset
;
496 *regsize
= offsets
->xr_size
;
497 if (regnum
== tdep
->ppc_cr_regnum
)
498 return offsets
->cr_offset
;
500 if (regnum
== tdep
->ppc_xer_regnum
)
501 return offsets
->xer_offset
;
503 if (regnum
== tdep
->ppc_mq_regnum
)
504 return offsets
->mq_offset
;
510 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
511 const struct ppc_reg_offsets
*offsets
,
514 if (regnum
>= tdep
->ppc_fp0_regnum
515 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
516 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
518 if (regnum
== tdep
->ppc_fpscr_regnum
)
519 return offsets
->fpscr_offset
;
524 /* Supply register REGNUM in the general-purpose register set REGSET
525 from the buffer specified by GREGS and LEN to register cache
526 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
529 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
530 int regnum
, const void *gregs
, size_t len
)
532 struct gdbarch
*gdbarch
= regcache
->arch ();
533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 const struct ppc_reg_offsets
*offsets
535 = (const struct ppc_reg_offsets
*) regset
->regmap
;
542 int gpr_size
= offsets
->gpr_size
;
544 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
545 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
546 i
++, offset
+= gpr_size
)
547 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
550 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
551 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
552 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
553 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
554 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
555 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
556 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
558 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
559 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
561 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
562 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
564 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
565 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
570 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
571 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
574 /* Supply register REGNUM in the floating-point register set REGSET
575 from the buffer specified by FPREGS and LEN to register cache
576 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
579 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
580 int regnum
, const void *fpregs
, size_t len
)
582 struct gdbarch
*gdbarch
= regcache
->arch ();
583 struct gdbarch_tdep
*tdep
;
584 const struct ppc_reg_offsets
*offsets
;
587 if (!ppc_floating_point_unit_p (gdbarch
))
590 tdep
= gdbarch_tdep (gdbarch
);
591 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
596 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
597 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
599 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
601 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
602 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
603 offsets
->fpscr_size
);
607 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
608 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
609 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
612 /* Collect register REGNUM in the general-purpose register set
613 REGSET from register cache REGCACHE into the buffer specified by
614 GREGS and LEN. If REGNUM is -1, do this for all registers in
618 ppc_collect_gregset (const struct regset
*regset
,
619 const struct regcache
*regcache
,
620 int regnum
, void *gregs
, size_t len
)
622 struct gdbarch
*gdbarch
= regcache
->arch ();
623 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
624 const struct ppc_reg_offsets
*offsets
625 = (const struct ppc_reg_offsets
*) regset
->regmap
;
632 int gpr_size
= offsets
->gpr_size
;
634 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
635 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
636 i
++, offset
+= gpr_size
)
637 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
639 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
640 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
641 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
642 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
643 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
644 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
645 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
646 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
647 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
648 (gdb_byte
*) gregs
, offsets
->cr_offset
,
650 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
651 (gdb_byte
*) gregs
, offsets
->xer_offset
,
653 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
654 (gdb_byte
*) gregs
, offsets
->mq_offset
,
659 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
660 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
663 /* Collect register REGNUM in the floating-point register set
664 REGSET from register cache REGCACHE into the buffer specified by
665 FPREGS and LEN. If REGNUM is -1, do this for all registers in
669 ppc_collect_fpregset (const struct regset
*regset
,
670 const struct regcache
*regcache
,
671 int regnum
, void *fpregs
, size_t len
)
673 struct gdbarch
*gdbarch
= regcache
->arch ();
674 struct gdbarch_tdep
*tdep
;
675 const struct ppc_reg_offsets
*offsets
;
678 if (!ppc_floating_point_unit_p (gdbarch
))
681 tdep
= gdbarch_tdep (gdbarch
);
682 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
687 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
688 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
690 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
692 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
693 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
694 offsets
->fpscr_size
);
698 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
699 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
700 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
704 insn_changes_sp_or_jumps (unsigned long insn
)
706 int opcode
= (insn
>> 26) & 0x03f;
707 int sd
= (insn
>> 21) & 0x01f;
708 int a
= (insn
>> 16) & 0x01f;
709 int subcode
= (insn
>> 1) & 0x3ff;
711 /* Changes the stack pointer. */
713 /* NOTE: There are many ways to change the value of a given register.
714 The ways below are those used when the register is R1, the SP,
715 in a funtion's epilogue. */
717 if (opcode
== 31 && subcode
== 444 && a
== 1)
718 return 1; /* mr R1,Rn */
719 if (opcode
== 14 && sd
== 1)
720 return 1; /* addi R1,Rn,simm */
721 if (opcode
== 58 && sd
== 1)
722 return 1; /* ld R1,ds(Rn) */
724 /* Transfers control. */
730 if (opcode
== 19 && subcode
== 16)
732 if (opcode
== 19 && subcode
== 528)
733 return 1; /* bcctr */
738 /* Return true if we are in the function's epilogue, i.e. after the
739 instruction that destroyed the function's stack frame.
741 1) scan forward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer
743 or transfers control (except a return), execution is not in
745 b) Stop scanning if you find a return instruction or reach the
746 end of the function or reach the hard limit for the size of
748 2) scan backward from the point of execution:
749 a) If you find an instruction that modifies the stack pointer,
750 execution *is* in an epilogue, return.
751 b) Stop scanning if you reach an instruction that transfers
752 control or the beginning of the function or reach the hard
753 limit for the size of an epilogue. */
756 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
757 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
759 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
760 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
761 bfd_byte insn_buf
[PPC_INSN_SIZE
];
762 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
765 /* Find the search limits based on function boundaries and hard limit. */
767 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
770 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
771 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
773 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
774 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
776 /* Scan forward until next 'blr'. */
778 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
780 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
781 {insn_buf
, PPC_INSN_SIZE
}))
783 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
784 if (insn
== 0x4e800020)
786 /* Assume a bctr is a tail call unless it points strictly within
788 if (insn
== 0x4e800420)
790 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
791 tdep
->ppc_ctr_regnum
);
792 if (ctr
> func_start
&& ctr
< func_end
)
797 if (insn_changes_sp_or_jumps (insn
))
801 /* Scan backward until adjustment to stack pointer (R1). */
803 for (scan_pc
= pc
- PPC_INSN_SIZE
;
804 scan_pc
>= epilogue_start
;
805 scan_pc
-= PPC_INSN_SIZE
)
807 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
808 {insn_buf
, PPC_INSN_SIZE
}))
810 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
811 if (insn_changes_sp_or_jumps (insn
))
818 /* Implement the stack_frame_destroyed_p gdbarch method. */
821 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
823 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
827 /* Get the ith function argument for the current function. */
829 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
832 return get_frame_register_unsigned (frame
, 3 + argi
);
835 /* Sequence of bytes for breakpoint instruction. */
837 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
838 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
840 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
843 /* Instruction masks for displaced stepping. */
844 #define OP_MASK 0xfc000000
845 #define BP_MASK 0xFC0007FE
846 #define B_INSN 0x48000000
847 #define BC_INSN 0x40000000
848 #define BXL_INSN 0x4c000000
849 #define BP_INSN 0x7C000008
851 /* Instruction masks used during single-stepping of atomic
853 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
854 #define LWARX_INSTRUCTION 0x7c000028
855 #define LDARX_INSTRUCTION 0x7c0000A8
856 #define LBARX_INSTRUCTION 0x7c000068
857 #define LHARX_INSTRUCTION 0x7c0000e8
858 #define LQARX_INSTRUCTION 0x7c000228
859 #define STORE_CONDITIONAL_MASK 0xfc0007ff
860 #define STWCX_INSTRUCTION 0x7c00012d
861 #define STDCX_INSTRUCTION 0x7c0001ad
862 #define STBCX_INSTRUCTION 0x7c00056d
863 #define STHCX_INSTRUCTION 0x7c0005ad
864 #define STQCX_INSTRUCTION 0x7c00016d
866 /* Instruction masks for single-stepping of addpcis/lnia. */
867 #define ADDPCIS_INSN 0x4c000004
868 #define ADDPCIS_INSN_MASK 0xfc00003e
869 #define ADDPCIS_TARGET_REGISTER 0x03F00000
870 #define ADDPCIS_INSN_REGSHIFT 21
872 #define PNOP_MASK 0xfff3ffff
873 #define PNOP_INSN 0x07000000
874 #define R_MASK 0x00100000
875 #define R_ZERO 0x00000000
877 /* Check if insn is one of the Load And Reserve instructions used for atomic
879 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
880 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
881 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
882 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
883 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
884 /* Check if insn is one of the Store Conditional instructions used for atomic
886 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
887 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
888 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
889 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
890 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
892 typedef buf_displaced_step_copy_insn_closure
893 ppc_displaced_step_copy_insn_closure
;
895 /* We can't displaced step atomic sequences. */
897 static displaced_step_copy_insn_closure_up
898 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
899 CORE_ADDR from
, CORE_ADDR to
,
900 struct regcache
*regs
)
902 size_t len
= gdbarch_max_insn_length (gdbarch
);
903 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
904 (new ppc_displaced_step_copy_insn_closure (len
));
905 gdb_byte
*buf
= closure
->buf
.data ();
906 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
909 len
= target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY
, NULL
,
911 if ((ssize_t
) len
< PPC_INSN_SIZE
)
912 memory_error (TARGET_XFER_E_IO
, from
);
914 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
916 /* Check for PNOP and for prefixed instructions with R=0. Those
917 instructions are safe to displace. Prefixed instructions with R=1
918 will read/write data to/from locations relative to the current PC.
919 We would not be able to fixup after an instruction has written data
920 into a displaced location, so decline to displace those instructions. */
921 if ((insn
& OP_MASK
) == 1 << 26)
923 if (((insn
& PNOP_MASK
) != PNOP_INSN
)
924 && ((insn
& R_MASK
) != R_ZERO
))
926 displaced_debug_printf ("Not displacing prefixed instruction %08x at %s",
927 insn
, paddress (gdbarch
, from
));
932 /* Non-prefixed instructions.. */
934 /* Set the instruction length to 4 to match the actual instruction
939 /* Assume all atomic sequences start with a Load and Reserve instruction. */
940 if (IS_LOAD_AND_RESERVE_INSN (insn
))
942 displaced_debug_printf ("can't displaced step atomic sequence at %s",
943 paddress (gdbarch
, from
));
948 write_memory (to
, buf
, len
);
950 displaced_debug_printf ("copy %s->%s: %s",
951 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
952 displaced_step_dump_bytes (buf
, len
).c_str ());
954 /* This is a work around for a problem with g++ 4.8. */
955 return displaced_step_copy_insn_closure_up (closure
.release ());
958 /* Fix up the state of registers and memory after having single-stepped
959 a displaced instruction. */
961 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
962 struct displaced_step_copy_insn_closure
*closure_
,
963 CORE_ADDR from
, CORE_ADDR to
,
964 struct regcache
*regs
)
966 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
967 /* Our closure is a copy of the instruction. */
968 ppc_displaced_step_copy_insn_closure
*closure
969 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
970 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
971 PPC_INSN_SIZE
, byte_order
);
973 /* Offset for non PC-relative instructions. */
976 opcode
= insn
& OP_MASK
;
978 /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
979 if ((opcode
) == 1 << 26)
980 offset
= 2 * PPC_INSN_SIZE
;
982 offset
= PPC_INSN_SIZE
;
984 displaced_debug_printf ("(ppc) fixup (%s, %s)",
985 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
987 /* Handle the addpcis/lnia instruction. */
988 if ((insn
& ADDPCIS_INSN_MASK
) == ADDPCIS_INSN
)
990 LONGEST displaced_offset
;
991 ULONGEST current_val
;
992 /* Measure the displacement. */
993 displaced_offset
= from
- to
;
994 /* Identify the target register that was updated by the instruction. */
995 int regnum
= (insn
& ADDPCIS_TARGET_REGISTER
) >> ADDPCIS_INSN_REGSHIFT
;
996 /* Read and update the target value. */
997 regcache_cooked_read_unsigned (regs
, regnum
, ¤t_val
);
998 displaced_debug_printf ("addpcis target regnum %d was %s now %s",
999 regnum
, paddress (gdbarch
, current_val
),
1000 paddress (gdbarch
, current_val
1001 + displaced_offset
));
1002 regcache_cooked_write_unsigned (regs
, regnum
,
1003 current_val
+ displaced_offset
);
1004 /* point the PC back at the non-displaced instruction. */
1005 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1008 /* Handle PC-relative branch instructions. */
1009 else if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1011 ULONGEST current_pc
;
1013 /* Read the current PC value after the instruction has been executed
1014 in a displaced location. Calculate the offset to be applied to the
1015 original PC value before the displaced stepping. */
1016 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1018 offset
= current_pc
- to
;
1020 if (opcode
!= BXL_INSN
)
1022 /* Check for AA bit indicating whether this is an absolute
1023 addressing or PC-relative (1: absolute, 0: relative). */
1026 /* PC-relative addressing is being used in the branch. */
1027 displaced_debug_printf ("(ppc) branch instruction: %s",
1028 paddress (gdbarch
, insn
));
1029 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
1030 paddress (gdbarch
, current_pc
),
1031 paddress (gdbarch
, from
+ offset
));
1033 regcache_cooked_write_unsigned (regs
,
1034 gdbarch_pc_regnum (gdbarch
),
1040 /* If we're here, it means we have a branch to LR or CTR. If the
1041 branch was taken, the offset is probably greater than 4 (the next
1042 instruction), so it's safe to assume that an offset of 4 means we
1043 did not take the branch. */
1044 if (offset
== PPC_INSN_SIZE
)
1045 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1046 from
+ PPC_INSN_SIZE
);
1049 /* Check for LK bit indicating whether we should set the link
1050 register to point to the next instruction
1051 (1: Set, 0: Don't set). */
1054 /* Link register needs to be set to the next instruction's PC. */
1055 regcache_cooked_write_unsigned (regs
,
1056 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1057 from
+ PPC_INSN_SIZE
);
1058 displaced_debug_printf ("(ppc) adjusted LR to %s",
1059 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1063 /* Check for breakpoints in the inferior. If we've found one, place the PC
1064 right at the breakpoint instruction. */
1065 else if ((insn
& BP_MASK
) == BP_INSN
)
1066 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1069 /* Handle any other instructions that do not fit in the categories
1071 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1076 /* Implementation of gdbarch_displaced_step_prepare. */
1078 static displaced_step_prepare_status
1079 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1080 CORE_ADDR
&displaced_pc
)
1082 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1084 if (!per_inferior
->disp_step_buf
.has_value ())
1086 /* Figure out where the displaced step buffer is. */
1087 CORE_ADDR disp_step_buf_addr
1088 = displaced_step_at_entry_point (thread
->inf
->gdbarch
);
1090 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1093 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1096 /* Implementation of gdbarch_displaced_step_finish. */
1098 static displaced_step_finish_status
1099 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1102 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1104 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1106 return per_inferior
->disp_step_buf
->finish (arch
, thread
, sig
);
1109 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1112 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1114 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1116 if (per_inferior
== nullptr
1117 || !per_inferior
->disp_step_buf
.has_value ())
1120 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1123 /* Always use hardware single-stepping to execute the
1124 displaced instruction. */
1126 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1131 /* Checks for an atomic sequence of instructions beginning with a
1132 Load And Reserve instruction and ending with a Store Conditional
1133 instruction. If such a sequence is found, attempt to step through it.
1134 A breakpoint is placed at the end of the sequence. */
1135 std::vector
<CORE_ADDR
>
1136 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1138 struct gdbarch
*gdbarch
= regcache
->arch ();
1139 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1140 CORE_ADDR pc
= regcache_read_pc (regcache
);
1141 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1143 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1144 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1147 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1148 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1149 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1151 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1152 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1155 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1157 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1159 if ((insn
& OP_MASK
) == 1 << 26)
1160 loc
+= 2 * PPC_INSN_SIZE
;
1162 loc
+= PPC_INSN_SIZE
;
1163 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1165 /* Assume that there is at most one conditional branch in the atomic
1166 sequence. If a conditional branch is found, put a breakpoint in
1167 its destination address. */
1168 if ((insn
& OP_MASK
) == BC_INSN
)
1170 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1171 int absolute
= insn
& 2;
1173 if (bc_insn_count
>= 1)
1174 return {}; /* More than one conditional branch found, fallback
1175 to the standard single-step code. */
1178 breaks
[1] = immediate
;
1180 breaks
[1] = loc
+ immediate
;
1186 if (IS_STORE_CONDITIONAL_INSN (insn
))
1190 /* Assume that the atomic sequence ends with a Store Conditional
1192 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1196 loc
+= PPC_INSN_SIZE
;
1198 /* Insert a breakpoint right after the end of the atomic sequence. */
1201 /* Check for duplicated breakpoints. Check also for a breakpoint
1202 placed (branch instruction's destination) anywhere in sequence. */
1204 && (breaks
[1] == breaks
[0]
1205 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1206 last_breakpoint
= 0;
1208 std::vector
<CORE_ADDR
> next_pcs
;
1210 for (index
= 0; index
<= last_breakpoint
; index
++)
1211 next_pcs
.push_back (breaks
[index
]);
1217 #define SIGNED_SHORT(x) \
1218 ((sizeof (short) == 2) \
1219 ? ((int)(short)(x)) \
1220 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1222 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1224 /* Limit the number of skipped non-prologue instructions, as the examining
1225 of the prologue is expensive. */
1226 static int max_skip_non_prologue_insns
= 10;
1228 /* Return nonzero if the given instruction OP can be part of the prologue
1229 of a function and saves a parameter on the stack. FRAMEP should be
1230 set if one of the previous instructions in the function has set the
1234 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1236 /* Move parameters from argument registers to temporary register. */
1237 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1239 /* Rx must be scratch register r0. */
1240 const int rx_regno
= (op
>> 16) & 31;
1241 /* Ry: Only r3 - r10 are used for parameter passing. */
1242 const int ry_regno
= GET_SRC_REG (op
);
1244 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1246 *r0_contains_arg
= 1;
1253 /* Save a General Purpose Register on stack. */
1255 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1256 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1258 /* Rx: Only r3 - r10 are used for parameter passing. */
1259 const int rx_regno
= GET_SRC_REG (op
);
1261 return (rx_regno
>= 3 && rx_regno
<= 10);
1264 /* Save a General Purpose Register on stack via the Frame Pointer. */
1267 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1268 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1269 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1271 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1272 However, the compiler sometimes uses r0 to hold an argument. */
1273 const int rx_regno
= GET_SRC_REG (op
);
1275 return ((rx_regno
>= 3 && rx_regno
<= 10)
1276 || (rx_regno
== 0 && *r0_contains_arg
));
1279 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1281 /* Only f2 - f8 are used for parameter passing. */
1282 const int src_regno
= GET_SRC_REG (op
);
1284 return (src_regno
>= 2 && src_regno
<= 8);
1287 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1289 /* Only f2 - f8 are used for parameter passing. */
1290 const int src_regno
= GET_SRC_REG (op
);
1292 return (src_regno
>= 2 && src_regno
<= 8);
1295 /* Not an insn that saves a parameter on stack. */
1299 /* Assuming that INSN is a "bl" instruction located at PC, return
1300 nonzero if the destination of the branch is a "blrl" instruction.
1302 This sequence is sometimes found in certain function prologues.
1303 It allows the function to load the LR register with a value that
1304 they can use to access PIC data using PC-relative offsets. */
1307 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1314 absolute
= (int) ((insn
>> 1) & 1);
1315 immediate
= ((insn
& ~3) << 6) >> 6;
1319 dest
= pc
+ immediate
;
1321 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1322 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1328 /* Return true if OP is a stw or std instruction with
1329 register operands RS and RA and any immediate offset.
1331 If WITH_UPDATE is true, also return true if OP is
1332 a stwu or stdu instruction with the same operands.
1334 Return false otherwise.
1337 store_insn_p (unsigned long op
, unsigned long rs
,
1338 unsigned long ra
, bool with_update
)
1343 if (/* std RS, SIMM(RA) */
1344 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1345 /* stw RS, SIMM(RA) */
1346 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1351 if (/* stdu RS, SIMM(RA) */
1352 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1353 /* stwu RS, SIMM(RA) */
1354 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1361 /* Masks for decoding a branch-and-link (bl) instruction.
1363 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1364 The former is anded with the opcode in question; if the result of
1365 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1366 question is a ``bl'' instruction.
1368 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1369 the branch displacement. */
1371 #define BL_MASK 0xfc000001
1372 #define BL_INSTRUCTION 0x48000001
1373 #define BL_DISPLACEMENT_MASK 0x03fffffc
1375 static unsigned long
1376 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1378 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1382 /* Fetch the instruction and convert it to an integer. */
1383 if (target_read_memory (pc
, buf
, 4))
1385 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1390 /* GCC generates several well-known sequences of instructions at the begining
1391 of each function prologue when compiling with -fstack-check. If one of
1392 such sequences starts at START_PC, then return the address of the
1393 instruction immediately past this sequence. Otherwise, return START_PC. */
1396 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1398 CORE_ADDR pc
= start_pc
;
1399 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1401 /* First possible sequence: A small number of probes.
1402 stw 0, -<some immediate>(1)
1403 [repeat this instruction any (small) number of times]. */
1405 if ((op
& 0xffff0000) == 0x90010000)
1407 while ((op
& 0xffff0000) == 0x90010000)
1410 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1415 /* Second sequence: A probing loop.
1416 addi 12,1,-<some immediate>
1417 lis 0,-<some immediate>
1418 [possibly ori 0,0,<some immediate>]
1422 addi 12,12,-<some immediate>
1425 [possibly one last probe: stw 0,<some immediate>(12)]. */
1429 /* addi 12,1,-<some immediate> */
1430 if ((op
& 0xffff0000) != 0x39810000)
1433 /* lis 0,-<some immediate> */
1435 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1436 if ((op
& 0xffff0000) != 0x3c000000)
1440 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1441 /* [possibly ori 0,0,<some immediate>] */
1442 if ((op
& 0xffff0000) == 0x60000000)
1445 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1448 if (op
!= 0x7c0c0214)
1453 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1454 if (op
!= 0x7c0c0000)
1459 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1460 if ((op
& 0xff9f0001) != 0x41820000)
1463 /* addi 12,12,-<some immediate> */
1465 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1466 if ((op
& 0xffff0000) != 0x398c0000)
1471 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1472 if (op
!= 0x900c0000)
1477 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1478 if ((op
& 0xfc000001) != 0x48000000)
1481 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1483 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1484 if ((op
& 0xffff0000) == 0x900c0000)
1487 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1490 /* We found a valid stack-check sequence, return the new PC. */
1494 /* Third sequence: No probe; instead, a comparison between the stack size
1495 limit (saved in a run-time global variable) and the current stack
1498 addi 0,1,-<some immediate>
1499 lis 12,__gnat_stack_limit@ha
1500 lwz 12,__gnat_stack_limit@l(12)
1503 or, with a small variant in the case of a bigger stack frame:
1504 addis 0,1,<some immediate>
1505 addic 0,0,-<some immediate>
1506 lis 12,__gnat_stack_limit@ha
1507 lwz 12,__gnat_stack_limit@l(12)
1512 /* addi 0,1,-<some immediate> */
1513 if ((op
& 0xffff0000) != 0x38010000)
1515 /* small stack frame variant not recognized; try the
1516 big stack frame variant: */
1518 /* addis 0,1,<some immediate> */
1519 if ((op
& 0xffff0000) != 0x3c010000)
1522 /* addic 0,0,-<some immediate> */
1524 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1525 if ((op
& 0xffff0000) != 0x30000000)
1529 /* lis 12,<some immediate> */
1531 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1532 if ((op
& 0xffff0000) != 0x3d800000)
1535 /* lwz 12,<some immediate>(12) */
1537 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1538 if ((op
& 0xffff0000) != 0x818c0000)
1543 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1544 if ((op
& 0xfffffffe) != 0x7c406008)
1547 /* We found a valid stack-check sequence, return the new PC. */
1551 /* No stack check code in our prologue, return the start_pc. */
1555 /* return pc value after skipping a function prologue and also return
1556 information about a function frame.
1558 in struct rs6000_framedata fdata:
1559 - frameless is TRUE, if function does not have a frame.
1560 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1561 - offset is the initial size of this stack frame --- the amount by
1562 which we decrement the sp to allocate the frame.
1563 - saved_gpr is the number of the first saved gpr.
1564 - saved_fpr is the number of the first saved fpr.
1565 - saved_vr is the number of the first saved vr.
1566 - saved_ev is the number of the first saved ev.
1567 - alloca_reg is the number of the register used for alloca() handling.
1569 - gpr_offset is the offset of the first saved gpr from the previous frame.
1570 - fpr_offset is the offset of the first saved fpr from the previous frame.
1571 - vr_offset is the offset of the first saved vr from the previous frame.
1572 - ev_offset is the offset of the first saved ev from the previous frame.
1573 - lr_offset is the offset of the saved lr
1574 - cr_offset is the offset of the saved cr
1575 - vrsave_offset is the offset of the saved vrsave register. */
1578 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1579 struct rs6000_framedata
*fdata
)
1581 CORE_ADDR orig_pc
= pc
;
1582 CORE_ADDR last_prologue_pc
= pc
;
1583 CORE_ADDR li_found_pc
= 0;
1587 long alloca_reg_offset
= 0;
1588 long vr_saved_offset
= 0;
1594 int vrsave_reg
= -1;
1597 int minimal_toc_loaded
= 0;
1598 int prev_insn_was_prologue_insn
= 1;
1599 int num_skip_non_prologue_insns
= 0;
1600 int r0_contains_arg
= 0;
1601 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1603 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1605 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1606 fdata
->saved_gpr
= -1;
1607 fdata
->saved_fpr
= -1;
1608 fdata
->saved_vr
= -1;
1609 fdata
->saved_ev
= -1;
1610 fdata
->alloca_reg
= -1;
1611 fdata
->frameless
= 1;
1612 fdata
->nosavedpc
= 1;
1613 fdata
->lr_register
= -1;
1615 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1621 /* Sometimes it isn't clear if an instruction is a prologue
1622 instruction or not. When we encounter one of these ambiguous
1623 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1624 Otherwise, we'll assume that it really is a prologue instruction. */
1625 if (prev_insn_was_prologue_insn
)
1626 last_prologue_pc
= pc
;
1628 /* Stop scanning if we've hit the limit. */
1632 prev_insn_was_prologue_insn
= 1;
1634 /* Fetch the instruction and convert it to an integer. */
1635 if (target_read_memory (pc
, buf
, 4))
1637 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1639 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1641 /* Since shared library / PIC code, which needs to get its
1642 address at runtime, can appear to save more than one link
1656 remember just the first one, but skip over additional
1659 lr_reg
= (op
& 0x03e00000) >> 21;
1661 r0_contains_arg
= 0;
1664 else if ((op
& 0xfc1fffff) == 0x7c000026)
1666 cr_reg
= (op
& 0x03e00000) >> 21;
1668 r0_contains_arg
= 0;
1672 else if ((op
& 0xfc1f0000) == 0xd8010000)
1673 { /* stfd Rx,NUM(r1) */
1674 reg
= GET_SRC_REG (op
);
1675 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1677 fdata
->saved_fpr
= reg
;
1678 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1683 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1684 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1685 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1686 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1689 reg
= GET_SRC_REG (op
);
1690 if ((op
& 0xfc1f0000) == 0xbc010000)
1691 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1693 fdata
->gpr_mask
|= 1U << reg
;
1694 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1696 fdata
->saved_gpr
= reg
;
1697 if ((op
& 0xfc1f0003) == 0xf8010000)
1699 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1704 else if ((op
& 0xffff0000) == 0x3c4c0000
1705 || (op
& 0xffff0000) == 0x3c400000
1706 || (op
& 0xffff0000) == 0x38420000)
1708 /* . 0: addis 2,12,.TOC.-0b@ha
1709 . addi 2,2,.TOC.-0b@l
1713 used by ELFv2 global entry points to set up r2. */
1716 else if (op
== 0x60000000)
1719 /* Allow nops in the prologue, but do not consider them to
1720 be part of the prologue unless followed by other prologue
1722 prev_insn_was_prologue_insn
= 0;
1726 else if ((op
& 0xffff0000) == 0x3c000000)
1727 { /* addis 0,0,NUM, used for >= 32k frames */
1728 fdata
->offset
= (op
& 0x0000ffff) << 16;
1729 fdata
->frameless
= 0;
1730 r0_contains_arg
= 0;
1734 else if ((op
& 0xffff0000) == 0x60000000)
1735 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1736 fdata
->offset
|= (op
& 0x0000ffff);
1737 fdata
->frameless
= 0;
1738 r0_contains_arg
= 0;
1742 else if (lr_reg
>= 0 &&
1743 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1745 (store_insn_p (op
, lr_reg
,
1746 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1749 if (store_insn_p (op
, lr_reg
, 1, true))
1750 fdata
->lr_offset
= offset
;
1751 else /* LR save through frame pointer. */
1752 fdata
->lr_offset
= alloca_reg_offset
;
1754 fdata
->nosavedpc
= 0;
1755 /* Invalidate lr_reg, but don't set it to -1.
1756 That would mean that it had never been set. */
1758 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1759 (op
& 0xfc000000) == 0x90000000) /* stw */
1761 /* Does not update r1, so add displacement to lr_offset. */
1762 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1767 else if (cr_reg
>= 0 &&
1768 (store_insn_p (op
, cr_reg
, 1, true)))
1770 fdata
->cr_offset
= offset
;
1771 /* Invalidate cr_reg, but don't set it to -1.
1772 That would mean that it had never been set. */
1774 if ((op
& 0xfc000003) == 0xf8000000 ||
1775 (op
& 0xfc000000) == 0x90000000)
1777 /* Does not update r1, so add displacement to cr_offset. */
1778 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1783 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1785 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1786 prediction bits. If the LR has already been saved, we can
1790 else if (op
== 0x48000005)
1797 else if (op
== 0x48000004)
1802 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1803 in V.4 -mminimal-toc */
1804 (op
& 0xffff0000) == 0x3bde0000)
1805 { /* addi 30,30,foo@l */
1809 else if ((op
& 0xfc000001) == 0x48000001)
1813 fdata
->frameless
= 0;
1815 /* If the return address has already been saved, we can skip
1816 calls to blrl (for PIC). */
1817 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1823 /* Don't skip over the subroutine call if it is not within
1824 the first three instructions of the prologue and either
1825 we have no line table information or the line info tells
1826 us that the subroutine call is not part of the line
1827 associated with the prologue. */
1828 if ((pc
- orig_pc
) > 8)
1830 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1831 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1833 if ((prologue_sal
.line
== 0)
1834 || (prologue_sal
.line
!= this_sal
.line
))
1838 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1840 /* At this point, make sure this is not a trampoline
1841 function (a function that simply calls another functions,
1842 and nothing else). If the next is not a nop, this branch
1843 was part of the function prologue. */
1845 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1846 break; /* Don't skip over
1852 /* update stack pointer */
1853 else if ((op
& 0xfc1f0000) == 0x94010000)
1854 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1855 fdata
->frameless
= 0;
1856 fdata
->offset
= SIGNED_SHORT (op
);
1857 offset
= fdata
->offset
;
1860 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1861 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1862 /* No way to figure out what r1 is going to be. */
1863 fdata
->frameless
= 0;
1864 offset
= fdata
->offset
;
1867 else if ((op
& 0xfc1f0003) == 0xf8010001)
1868 { /* stdu rX,NUM(r1) */
1869 fdata
->frameless
= 0;
1870 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1871 offset
= fdata
->offset
;
1874 else if ((op
& 0xffff0000) == 0x38210000)
1875 { /* addi r1,r1,SIMM */
1876 fdata
->frameless
= 0;
1877 fdata
->offset
+= SIGNED_SHORT (op
);
1878 offset
= fdata
->offset
;
1881 /* Load up minimal toc pointer. Do not treat an epilogue restore
1882 of r31 as a minimal TOC load. */
1883 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1884 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1886 && !minimal_toc_loaded
)
1888 minimal_toc_loaded
= 1;
1891 /* move parameters from argument registers to local variable
1894 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1895 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1896 (((op
>> 21) & 31) <= 10) &&
1897 ((long) ((op
>> 16) & 31)
1898 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1902 /* store parameters in stack */
1904 /* Move parameters from argument registers to temporary register. */
1905 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1909 /* Set up frame pointer */
1911 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1913 fdata
->frameless
= 0;
1915 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1916 alloca_reg_offset
= offset
;
1919 /* Another way to set up the frame pointer. */
1921 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1922 || op
== 0x7c3f0b78)
1924 fdata
->frameless
= 0;
1926 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1927 alloca_reg_offset
= offset
;
1930 /* Another way to set up the frame pointer. */
1932 else if ((op
& 0xfc1fffff) == 0x38010000)
1933 { /* addi rX, r1, 0x0 */
1934 fdata
->frameless
= 0;
1936 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1937 + ((op
& ~0x38010000) >> 21));
1938 alloca_reg_offset
= offset
;
1941 /* AltiVec related instructions. */
1942 /* Store the vrsave register (spr 256) in another register for
1943 later manipulation, or load a register into the vrsave
1944 register. 2 instructions are used: mfvrsave and
1945 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1946 and mtspr SPR256, Rn. */
1947 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1948 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1949 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1951 vrsave_reg
= GET_SRC_REG (op
);
1954 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1958 /* Store the register where vrsave was saved to onto the stack:
1959 rS is the register where vrsave was stored in a previous
1961 /* 100100 sssss 00001 dddddddd dddddddd */
1962 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1964 if (vrsave_reg
== GET_SRC_REG (op
))
1966 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1971 /* Compute the new value of vrsave, by modifying the register
1972 where vrsave was saved to. */
1973 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1974 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1978 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1979 in a pair of insns to save the vector registers on the
1981 /* 001110 00000 00000 iiii iiii iiii iiii */
1982 /* 001110 01110 00000 iiii iiii iiii iiii */
1983 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1984 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1986 if ((op
& 0xffff0000) == 0x38000000)
1987 r0_contains_arg
= 0;
1989 vr_saved_offset
= SIGNED_SHORT (op
);
1991 /* This insn by itself is not part of the prologue, unless
1992 if part of the pair of insns mentioned above. So do not
1993 record this insn as part of the prologue yet. */
1994 prev_insn_was_prologue_insn
= 0;
1996 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1997 /* 011111 sssss 11111 00000 00111001110 */
1998 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2000 if (pc
== (li_found_pc
+ 4))
2002 vr_reg
= GET_SRC_REG (op
);
2003 /* If this is the first vector reg to be saved, or if
2004 it has a lower number than others previously seen,
2005 reupdate the frame info. */
2006 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2008 fdata
->saved_vr
= vr_reg
;
2009 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2011 vr_saved_offset
= -1;
2016 /* End AltiVec related instructions. */
2018 /* Start BookE related instructions. */
2019 /* Store gen register S at (r31+uimm).
2020 Any register less than r13 is volatile, so we don't care. */
2021 /* 000100 sssss 11111 iiiii 01100100001 */
2022 else if (arch_info
->mach
== bfd_mach_ppc_e500
2023 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2025 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2028 ev_reg
= GET_SRC_REG (op
);
2029 imm
= (op
>> 11) & 0x1f;
2030 ev_offset
= imm
* 8;
2031 /* If this is the first vector reg to be saved, or if
2032 it has a lower number than others previously seen,
2033 reupdate the frame info. */
2034 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2036 fdata
->saved_ev
= ev_reg
;
2037 fdata
->ev_offset
= ev_offset
+ offset
;
2042 /* Store gen register rS at (r1+rB). */
2043 /* 000100 sssss 00001 bbbbb 01100100000 */
2044 else if (arch_info
->mach
== bfd_mach_ppc_e500
2045 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2047 if (pc
== (li_found_pc
+ 4))
2049 ev_reg
= GET_SRC_REG (op
);
2050 /* If this is the first vector reg to be saved, or if
2051 it has a lower number than others previously seen,
2052 reupdate the frame info. */
2053 /* We know the contents of rB from the previous instruction. */
2054 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2056 fdata
->saved_ev
= ev_reg
;
2057 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2059 vr_saved_offset
= -1;
2065 /* Store gen register r31 at (rA+uimm). */
2066 /* 000100 11111 aaaaa iiiii 01100100001 */
2067 else if (arch_info
->mach
== bfd_mach_ppc_e500
2068 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2070 /* Wwe know that the source register is 31 already, but
2071 it can't hurt to compute it. */
2072 ev_reg
= GET_SRC_REG (op
);
2073 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2074 /* If this is the first vector reg to be saved, or if
2075 it has a lower number than others previously seen,
2076 reupdate the frame info. */
2077 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2079 fdata
->saved_ev
= ev_reg
;
2080 fdata
->ev_offset
= ev_offset
+ offset
;
2085 /* Store gen register S at (r31+r0).
2086 Store param on stack when offset from SP bigger than 4 bytes. */
2087 /* 000100 sssss 11111 00000 01100100000 */
2088 else if (arch_info
->mach
== bfd_mach_ppc_e500
2089 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2091 if (pc
== (li_found_pc
+ 4))
2093 if ((op
& 0x03e00000) >= 0x01a00000)
2095 ev_reg
= GET_SRC_REG (op
);
2096 /* If this is the first vector reg to be saved, or if
2097 it has a lower number than others previously seen,
2098 reupdate the frame info. */
2099 /* We know the contents of r0 from the previous
2101 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2103 fdata
->saved_ev
= ev_reg
;
2104 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2108 vr_saved_offset
= -1;
2113 /* End BookE related instructions. */
2117 /* Not a recognized prologue instruction.
2118 Handle optimizer code motions into the prologue by continuing
2119 the search if we have no valid frame yet or if the return
2120 address is not yet saved in the frame. Also skip instructions
2121 if some of the GPRs expected to be saved are not yet saved. */
2122 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2123 && fdata
->saved_gpr
!= -1)
2125 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2127 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2131 if (op
== 0x4e800020 /* blr */
2132 || op
== 0x4e800420) /* bctr */
2133 /* Do not scan past epilogue in frameless functions or
2136 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2137 /* Never skip branches. */
2140 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2141 /* Do not scan too many insns, scanning insns is expensive with
2145 /* Continue scanning. */
2146 prev_insn_was_prologue_insn
= 0;
2152 /* I have problems with skipping over __main() that I need to address
2153 * sometime. Previously, I used to use misc_function_vector which
2154 * didn't work as well as I wanted to be. -MGO */
2156 /* If the first thing after skipping a prolog is a branch to a function,
2157 this might be a call to an initializer in main(), introduced by gcc2.
2158 We'd like to skip over it as well. Fortunately, xlc does some extra
2159 work before calling a function right after a prologue, thus we can
2160 single out such gcc2 behaviour. */
2163 if ((op
& 0xfc000001) == 0x48000001)
2164 { /* bl foo, an initializer function? */
2165 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2167 if (op
== 0x4def7b82)
2168 { /* cror 0xf, 0xf, 0xf (nop) */
2170 /* Check and see if we are in main. If so, skip over this
2171 initializer function as well. */
2173 tmp
= find_pc_misc_function (pc
);
2175 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2181 if (pc
== lim_pc
&& lr_reg
>= 0)
2182 fdata
->lr_register
= lr_reg
;
2184 fdata
->offset
= -fdata
->offset
;
2185 return last_prologue_pc
;
2189 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2191 struct rs6000_framedata frame
;
2192 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2194 /* See if we can determine the end of the prologue via the symbol table.
2195 If so, then return either PC, or the PC after the prologue, whichever
2197 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2199 CORE_ADDR post_prologue_pc
2200 = skip_prologue_using_sal (gdbarch
, func_addr
);
2201 if (post_prologue_pc
!= 0)
2202 return std::max (pc
, post_prologue_pc
);
2205 /* Can't determine prologue from the symbol table, need to examine
2208 /* Find an upper limit on the function prologue using the debug
2209 information. If the debug information could not be used to provide
2210 that bound, then use an arbitrary large number as the upper bound. */
2211 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2213 limit_pc
= pc
+ 100; /* Magic. */
2215 /* Do not allow limit_pc to be past the function end, if we know
2216 where that end is... */
2217 if (func_end_addr
&& limit_pc
> func_end_addr
)
2218 limit_pc
= func_end_addr
;
2220 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2224 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2225 in the prologue of main().
2227 The function below examines the code pointed at by PC and checks to
2228 see if it corresponds to a call to __eabi. If so, it returns the
2229 address of the instruction following that call. Otherwise, it simply
2233 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2235 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2239 if (target_read_memory (pc
, buf
, 4))
2241 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2243 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2245 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2246 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2247 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2249 /* We check for ___eabi (three leading underscores) in addition
2250 to __eabi in case the GCC option "-fleading-underscore" was
2251 used to compile the program. */
2252 if (s
.minsym
!= NULL
2253 && s
.minsym
->linkage_name () != NULL
2254 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2255 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2261 /* All the ABI's require 16 byte alignment. */
2263 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2265 return (addr
& -16);
2268 /* Return whether handle_inferior_event() should proceed through code
2269 starting at PC in function NAME when stepping.
2271 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2272 handle memory references that are too distant to fit in instructions
2273 generated by the compiler. For example, if 'foo' in the following
2278 is greater than 32767, the linker might replace the lwz with a branch to
2279 somewhere in @FIX1 that does the load in 2 instructions and then branches
2280 back to where execution should continue.
2282 GDB should silently step over @FIX code, just like AIX dbx does.
2283 Unfortunately, the linker uses the "b" instruction for the
2284 branches, meaning that the link register doesn't get set.
2285 Therefore, GDB's usual step_over_function () mechanism won't work.
2287 Instead, use the gdbarch_skip_trampoline_code and
2288 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2292 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2293 CORE_ADDR pc
, const char *name
)
2295 return name
&& startswith (name
, "@FIX");
2298 /* Skip code that the user doesn't want to see when stepping:
2300 1. Indirect function calls use a piece of trampoline code to do context
2301 switching, i.e. to set the new TOC table. Skip such code if we are on
2302 its first instruction (as when we have single-stepped to here).
2304 2. Skip shared library trampoline code (which is different from
2305 indirect function call trampolines).
2307 3. Skip bigtoc fixup code.
2309 Result is desired PC to step until, or NULL if we are not in
2310 code that should be skipped. */
2313 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2315 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2317 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2318 unsigned int ii
, op
;
2320 CORE_ADDR solib_target_pc
;
2321 struct bound_minimal_symbol msymbol
;
2323 static unsigned trampoline_code
[] =
2325 0x800b0000, /* l r0,0x0(r11) */
2326 0x90410014, /* st r2,0x14(r1) */
2327 0x7c0903a6, /* mtctr r0 */
2328 0x804b0004, /* l r2,0x4(r11) */
2329 0x816b0008, /* l r11,0x8(r11) */
2330 0x4e800420, /* bctr */
2331 0x4e800020, /* br */
2335 /* Check for bigtoc fixup code. */
2336 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2338 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2339 msymbol
.minsym
->linkage_name ()))
2341 /* Double-check that the third instruction from PC is relative "b". */
2342 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2343 if ((op
& 0xfc000003) == 0x48000000)
2345 /* Extract bits 6-29 as a signed 24-bit relative word address and
2346 add it to the containing PC. */
2347 rel
= ((int)(op
<< 6) >> 6);
2348 return pc
+ 8 + rel
;
2352 /* If pc is in a shared library trampoline, return its target. */
2353 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2354 if (solib_target_pc
)
2355 return solib_target_pc
;
2357 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2359 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2360 if (op
!= trampoline_code
[ii
])
2363 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2365 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2369 /* ISA-specific vector types. */
2371 static struct type
*
2372 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2374 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2376 if (!tdep
->ppc_builtin_type_vec64
)
2378 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2380 /* The type we're building is this: */
2382 union __gdb_builtin_type_vec64
2386 int32_t v2_int32
[2];
2387 int16_t v4_int16
[4];
2394 t
= arch_composite_type (gdbarch
,
2395 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2396 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2397 append_composite_type_field (t
, "v2_float",
2398 init_vector_type (bt
->builtin_float
, 2));
2399 append_composite_type_field (t
, "v2_int32",
2400 init_vector_type (bt
->builtin_int32
, 2));
2401 append_composite_type_field (t
, "v4_int16",
2402 init_vector_type (bt
->builtin_int16
, 4));
2403 append_composite_type_field (t
, "v8_int8",
2404 init_vector_type (bt
->builtin_int8
, 8));
2406 t
->set_is_vector (true);
2407 t
->set_name ("ppc_builtin_type_vec64");
2408 tdep
->ppc_builtin_type_vec64
= t
;
2411 return tdep
->ppc_builtin_type_vec64
;
2414 /* Vector 128 type. */
2416 static struct type
*
2417 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2421 if (!tdep
->ppc_builtin_type_vec128
)
2423 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2425 /* The type we're building is this
2427 type = union __ppc_builtin_type_vec128 {
2428 float128_t float128;
2430 double v2_double[2];
2432 int32_t v4_int32[4];
2433 int16_t v8_int16[8];
2434 int8_t v16_int8[16];
2438 /* PPC specific type for IEEE 128-bit float field */
2439 struct type
*t_float128
2440 = arch_float_type (gdbarch
, 128, "float128_t", floatformats_ia64_quad
);
2444 t
= arch_composite_type (gdbarch
,
2445 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2446 append_composite_type_field (t
, "float128", t_float128
);
2447 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2448 append_composite_type_field (t
, "v2_double",
2449 init_vector_type (bt
->builtin_double
, 2));
2450 append_composite_type_field (t
, "v4_float",
2451 init_vector_type (bt
->builtin_float
, 4));
2452 append_composite_type_field (t
, "v4_int32",
2453 init_vector_type (bt
->builtin_int32
, 4));
2454 append_composite_type_field (t
, "v8_int16",
2455 init_vector_type (bt
->builtin_int16
, 8));
2456 append_composite_type_field (t
, "v16_int8",
2457 init_vector_type (bt
->builtin_int8
, 16));
2459 t
->set_is_vector (true);
2460 t
->set_name ("ppc_builtin_type_vec128");
2461 tdep
->ppc_builtin_type_vec128
= t
;
2464 return tdep
->ppc_builtin_type_vec128
;
2467 /* Return the name of register number REGNO, or the empty string if it
2468 is an anonymous register. */
2471 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2473 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2475 /* The upper half "registers" have names in the XML description,
2476 but we present only the low GPRs and the full 64-bit registers
2478 if (tdep
->ppc_ev0_upper_regnum
>= 0
2479 && tdep
->ppc_ev0_upper_regnum
<= regno
2480 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2483 /* Hide the upper halves of the vs0~vs31 registers. */
2484 if (tdep
->ppc_vsr0_regnum
>= 0
2485 && tdep
->ppc_vsr0_upper_regnum
<= regno
2486 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2489 /* Hide the upper halves of the cvs0~cvs31 registers. */
2490 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2491 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2494 /* Check if the SPE pseudo registers are available. */
2495 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2497 static const char *const spe_regnames
[] = {
2498 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2499 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2500 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2501 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2503 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2506 /* Check if the decimal128 pseudo-registers are available. */
2507 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2509 static const char *const dfp128_regnames
[] = {
2510 "dl0", "dl1", "dl2", "dl3",
2511 "dl4", "dl5", "dl6", "dl7",
2512 "dl8", "dl9", "dl10", "dl11",
2513 "dl12", "dl13", "dl14", "dl15"
2515 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2518 /* Check if this is a vX alias for a raw vrX vector register. */
2519 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2521 static const char *const vector_alias_regnames
[] = {
2522 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2523 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2524 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2525 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2527 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2530 /* Check if this is a VSX pseudo-register. */
2531 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2533 static const char *const vsx_regnames
[] = {
2534 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2535 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2536 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2537 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2538 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2539 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2540 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2541 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2542 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2544 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2547 /* Check if the this is a Extended FP pseudo-register. */
2548 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2550 static const char *const efpr_regnames
[] = {
2551 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2552 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2553 "f46", "f47", "f48", "f49", "f50", "f51",
2554 "f52", "f53", "f54", "f55", "f56", "f57",
2555 "f58", "f59", "f60", "f61", "f62", "f63"
2557 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2560 /* Check if this is a Checkpointed DFP pseudo-register. */
2561 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2563 static const char *const cdfp128_regnames
[] = {
2564 "cdl0", "cdl1", "cdl2", "cdl3",
2565 "cdl4", "cdl5", "cdl6", "cdl7",
2566 "cdl8", "cdl9", "cdl10", "cdl11",
2567 "cdl12", "cdl13", "cdl14", "cdl15"
2569 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2572 /* Check if this is a Checkpointed VSX pseudo-register. */
2573 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2575 static const char *const cvsx_regnames
[] = {
2576 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2577 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2578 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2579 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2580 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2581 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2582 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2583 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2584 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2586 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2589 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2590 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2592 static const char *const cefpr_regnames
[] = {
2593 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2594 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2595 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2596 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2597 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2599 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2602 return tdesc_register_name (gdbarch
, regno
);
2605 /* Return the GDB type object for the "standard" data type of data in
2608 static struct type
*
2609 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2611 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2613 /* These are the e500 pseudo-registers. */
2614 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2615 return rs6000_builtin_type_vec64 (gdbarch
);
2616 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2617 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2618 /* PPC decimal128 pseudo-registers. */
2619 return builtin_type (gdbarch
)->builtin_declong
;
2620 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2621 return gdbarch_register_type (gdbarch
,
2622 tdep
->ppc_vr0_regnum
2624 - tdep
->ppc_v0_alias_regnum
));
2625 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2626 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2627 /* POWER7 VSX pseudo-registers. */
2628 return rs6000_builtin_type_vec128 (gdbarch
);
2629 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2630 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2631 /* POWER7 Extended FP pseudo-registers. */
2632 return builtin_type (gdbarch
)->builtin_double
;
2634 internal_error (__FILE__
, __LINE__
,
2635 _("rs6000_pseudo_register_type: "
2636 "called on unexpected register '%s' (%d)"),
2637 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2640 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2641 the vX aliases for the vector registers by always returning false
2642 to avoid duplicated information in "info register vector/all",
2643 since the raw vrX registers will already show in these cases. For
2644 other pseudo-registers we use the default membership function. */
2647 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2648 struct reggroup
*group
)
2650 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2652 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2655 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2658 /* The register format for RS/6000 floating point registers is always
2659 double, we need a conversion if the memory format is float. */
2662 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2665 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2667 return (tdep
->ppc_fp0_regnum
>= 0
2668 && regnum
>= tdep
->ppc_fp0_regnum
2669 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2670 && type
->code () == TYPE_CODE_FLT
2671 && TYPE_LENGTH (type
)
2672 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2676 rs6000_register_to_value (struct frame_info
*frame
,
2680 int *optimizedp
, int *unavailablep
)
2682 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2683 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2685 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2687 if (!get_frame_register_bytes (frame
, regnum
, 0,
2688 gdb::make_array_view (from
,
2689 register_size (gdbarch
,
2691 optimizedp
, unavailablep
))
2694 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2696 *optimizedp
= *unavailablep
= 0;
2701 rs6000_value_to_register (struct frame_info
*frame
,
2704 const gdb_byte
*from
)
2706 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2707 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2709 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2711 target_float_convert (from
, type
,
2712 to
, builtin_type (gdbarch
)->builtin_double
);
2713 put_frame_register (frame
, regnum
, to
);
2716 /* The type of a function that moves the value of REG between CACHE
2717 or BUF --- in either direction. */
2718 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2721 /* Move SPE vector register values between a 64-bit buffer and the two
2722 32-bit raw register halves in a regcache. This function handles
2723 both splitting a 64-bit value into two 32-bit halves, and joining
2724 two halves into a whole 64-bit value, depending on the function
2725 passed as the MOVE argument.
2727 EV_REG must be the number of an SPE evN vector register --- a
2728 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2731 Call MOVE once for each 32-bit half of that register, passing
2732 REGCACHE, the number of the raw register corresponding to that
2733 half, and the address of the appropriate half of BUFFER.
2735 For example, passing 'regcache_raw_read' as the MOVE function will
2736 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2737 'regcache_raw_supply' will supply the contents of BUFFER to the
2738 appropriate pair of raw registers in REGCACHE.
2740 You may need to cast away some 'const' qualifiers when passing
2741 MOVE, since this function can't tell at compile-time which of
2742 REGCACHE or BUFFER is acting as the source of the data. If C had
2743 co-variant type qualifiers, ... */
2745 static enum register_status
2746 e500_move_ev_register (move_ev_register_func move
,
2747 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2749 struct gdbarch
*arch
= regcache
->arch ();
2750 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2752 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2753 enum register_status status
;
2755 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2757 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2759 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2761 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2763 if (status
== REG_VALID
)
2764 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2769 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2770 if (status
== REG_VALID
)
2771 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2778 static enum register_status
2779 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2781 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2786 static enum register_status
2787 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2788 int ev_reg
, gdb_byte
*buffer
)
2790 struct gdbarch
*arch
= regcache
->arch ();
2791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2793 enum register_status status
;
2795 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2797 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2799 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2801 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2803 if (status
== REG_VALID
)
2804 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2809 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2810 if (status
== REG_VALID
)
2811 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2820 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2821 int reg_nr
, const gdb_byte
*buffer
)
2823 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2824 reg_nr
, (void *) buffer
);
2827 /* Read method for DFP pseudo-registers. */
2828 static enum register_status
2829 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2830 int reg_nr
, gdb_byte
*buffer
)
2832 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2834 enum register_status status
;
2836 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2838 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2839 fp0
= PPC_F0_REGNUM
;
2843 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2845 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2846 fp0
= PPC_CF0_REGNUM
;
2849 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2851 /* Read two FP registers to form a whole dl register. */
2852 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2853 if (status
== REG_VALID
)
2854 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2859 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2860 if (status
== REG_VALID
)
2861 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2867 /* Write method for DFP pseudo-registers. */
2869 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2870 int reg_nr
, const gdb_byte
*buffer
)
2872 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2875 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2877 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2878 fp0
= PPC_F0_REGNUM
;
2882 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2884 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2885 fp0
= PPC_CF0_REGNUM
;
2888 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2890 /* Write each half of the dl register into a separate
2892 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2893 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2897 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2898 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2902 /* Read method for the vX aliases for the raw vrX registers. */
2904 static enum register_status
2905 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2906 readable_regcache
*regcache
, int reg_nr
,
2909 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2910 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2912 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2913 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2917 /* Write method for the vX aliases for the raw vrX registers. */
2920 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2921 struct regcache
*regcache
,
2922 int reg_nr
, const gdb_byte
*buffer
)
2924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2925 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2927 regcache
->raw_write (tdep
->ppc_vr0_regnum
2928 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2931 /* Read method for POWER7 VSX pseudo-registers. */
2932 static enum register_status
2933 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2934 int reg_nr
, gdb_byte
*buffer
)
2936 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2937 int reg_index
, vr0
, fp0
, vsr0_upper
;
2938 enum register_status status
;
2940 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2942 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2943 vr0
= PPC_VR0_REGNUM
;
2944 fp0
= PPC_F0_REGNUM
;
2945 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2949 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2951 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2952 vr0
= PPC_CVR0_REGNUM
;
2953 fp0
= PPC_CF0_REGNUM
;
2954 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2957 /* Read the portion that overlaps the VMX registers. */
2959 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2961 /* Read the portion that overlaps the FPR registers. */
2962 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2964 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2965 if (status
== REG_VALID
)
2966 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2971 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2972 if (status
== REG_VALID
)
2973 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2979 /* Write method for POWER7 VSX pseudo-registers. */
2981 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2982 int reg_nr
, const gdb_byte
*buffer
)
2984 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2985 int reg_index
, vr0
, fp0
, vsr0_upper
;
2987 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2989 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2990 vr0
= PPC_VR0_REGNUM
;
2991 fp0
= PPC_F0_REGNUM
;
2992 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2996 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2998 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2999 vr0
= PPC_CVR0_REGNUM
;
3000 fp0
= PPC_CF0_REGNUM
;
3001 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3004 /* Write the portion that overlaps the VMX registers. */
3006 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
3008 /* Write the portion that overlaps the FPR registers. */
3009 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3011 regcache
->raw_write (fp0
+ reg_index
, buffer
);
3012 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
3016 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
3017 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
3021 /* Read method for POWER7 Extended FP pseudo-registers. */
3022 static enum register_status
3023 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
3024 int reg_nr
, gdb_byte
*buffer
)
3026 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3029 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3031 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3032 vr0
= PPC_VR0_REGNUM
;
3036 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3038 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3039 vr0
= PPC_CVR0_REGNUM
;
3042 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3044 /* Read the portion that overlaps the VMX register. */
3045 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
3046 register_size (gdbarch
, reg_nr
),
3050 /* Write method for POWER7 Extended FP pseudo-registers. */
3052 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3053 int reg_nr
, const gdb_byte
*buffer
)
3055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3057 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3059 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3061 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3062 vr0
= PPC_VR0_REGNUM
;
3066 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3068 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3069 vr0
= PPC_CVR0_REGNUM
;
3071 /* The call to raw_write_part fails silently if the initial read
3072 of the read-update-write sequence returns an invalid status,
3073 so we check this manually and throw an error if needed. */
3074 regcache
->raw_update (vr0
+ reg_index
);
3075 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
3076 error (_("Cannot write to the checkpointed EFP register, "
3077 "the corresponding vector register is unavailable."));
3080 /* Write the portion that overlaps the VMX register. */
3081 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3082 register_size (gdbarch
, reg_nr
), buffer
);
3085 static enum register_status
3086 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3087 readable_regcache
*regcache
,
3088 int reg_nr
, gdb_byte
*buffer
)
3090 struct gdbarch
*regcache_arch
= regcache
->arch ();
3091 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3093 gdb_assert (regcache_arch
== gdbarch
);
3095 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3096 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3097 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3098 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3099 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3100 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3101 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3103 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3104 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3105 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3106 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3107 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3108 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3110 internal_error (__FILE__
, __LINE__
,
3111 _("rs6000_pseudo_register_read: "
3112 "called on unexpected register '%s' (%d)"),
3113 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3117 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3118 struct regcache
*regcache
,
3119 int reg_nr
, const gdb_byte
*buffer
)
3121 struct gdbarch
*regcache_arch
= regcache
->arch ();
3122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3124 gdb_assert (regcache_arch
== gdbarch
);
3126 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3127 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3128 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3129 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3130 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3131 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3132 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3133 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3134 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3135 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3136 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3137 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3138 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3140 internal_error (__FILE__
, __LINE__
,
3141 _("rs6000_pseudo_register_write: "
3142 "called on unexpected register '%s' (%d)"),
3143 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3146 /* Set the register mask in AX with the registers that form the DFP or
3147 checkpointed DFP pseudo-register REG_NR. */
3150 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3151 struct agent_expr
*ax
, int reg_nr
)
3153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3156 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3158 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3159 fp0
= PPC_F0_REGNUM
;
3163 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3165 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3166 fp0
= PPC_CF0_REGNUM
;
3169 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3170 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3173 /* Set the register mask in AX with the raw vector register that
3174 corresponds to its REG_NR alias. */
3177 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3178 struct agent_expr
*ax
, int reg_nr
)
3180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3181 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3183 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3184 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3187 /* Set the register mask in AX with the registers that form the VSX or
3188 checkpointed VSX pseudo-register REG_NR. */
3191 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3192 struct agent_expr
*ax
, int reg_nr
)
3194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3195 int reg_index
, vr0
, fp0
, vsr0_upper
;
3197 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3199 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3200 vr0
= PPC_VR0_REGNUM
;
3201 fp0
= PPC_F0_REGNUM
;
3202 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3206 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3208 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3209 vr0
= PPC_CVR0_REGNUM
;
3210 fp0
= PPC_CF0_REGNUM
;
3211 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3216 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3220 ax_reg_mask (ax
, fp0
+ reg_index
);
3221 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3225 /* Set the register mask in AX with the register that corresponds to
3226 the EFP or checkpointed EFP pseudo-register REG_NR. */
3229 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3230 struct agent_expr
*ax
, int reg_nr
)
3232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3235 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3237 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3238 vr0
= PPC_VR0_REGNUM
;
3242 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3244 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3245 vr0
= PPC_CVR0_REGNUM
;
3248 ax_reg_mask (ax
, vr0
+ reg_index
);
3252 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3253 struct agent_expr
*ax
, int reg_nr
)
3255 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3256 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3258 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3259 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3260 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3262 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3263 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3265 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3267 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3269 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3271 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3272 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3274 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3276 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3277 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3279 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3282 internal_error (__FILE__
, __LINE__
,
3283 _("rs6000_pseudo_register_collect: "
3284 "called on unexpected register '%s' (%d)"),
3285 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3291 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3292 struct agent_expr
*ax
, struct axs_value
*value
,
3295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3296 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3297 value
->kind
= axs_lvalue_register
;
3298 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3302 /* Convert a DBX STABS register number to a GDB register number. */
3304 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3306 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3308 if (0 <= num
&& num
<= 31)
3309 return tdep
->ppc_gp0_regnum
+ num
;
3310 else if (32 <= num
&& num
<= 63)
3311 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3312 specifies registers the architecture doesn't have? Our
3313 callers don't check the value we return. */
3314 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3315 else if (77 <= num
&& num
<= 108)
3316 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3317 else if (1200 <= num
&& num
< 1200 + 32)
3318 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3323 return tdep
->ppc_mq_regnum
;
3325 return tdep
->ppc_lr_regnum
;
3327 return tdep
->ppc_ctr_regnum
;
3329 return tdep
->ppc_xer_regnum
;
3331 return tdep
->ppc_vrsave_regnum
;
3333 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3335 return tdep
->ppc_acc_regnum
;
3337 return tdep
->ppc_spefscr_regnum
;
3344 /* Convert a Dwarf 2 register number to a GDB register number. */
3346 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3348 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3350 if (0 <= num
&& num
<= 31)
3351 return tdep
->ppc_gp0_regnum
+ num
;
3352 else if (32 <= num
&& num
<= 63)
3353 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3354 specifies registers the architecture doesn't have? Our
3355 callers don't check the value we return. */
3356 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3357 else if (1124 <= num
&& num
< 1124 + 32)
3358 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3359 else if (1200 <= num
&& num
< 1200 + 32)
3360 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3365 return tdep
->ppc_cr_regnum
;
3367 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3369 return tdep
->ppc_acc_regnum
;
3371 return tdep
->ppc_mq_regnum
;
3373 return tdep
->ppc_xer_regnum
;
3375 return tdep
->ppc_lr_regnum
;
3377 return tdep
->ppc_ctr_regnum
;
3379 return tdep
->ppc_vrsave_regnum
;
3381 return tdep
->ppc_spefscr_regnum
;
3384 /* Unknown DWARF register number. */
3388 /* Translate a .eh_frame register to DWARF register, or adjust a
3389 .debug_frame register. */
3392 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3394 /* GCC releases before 3.4 use GCC internal register numbering in
3395 .debug_frame (and .debug_info, et cetera). The numbering is
3396 different from the standard SysV numbering for everything except
3397 for GPRs and FPRs. We can not detect this problem in most cases
3398 - to get accurate debug info for variables living in lr, ctr, v0,
3399 et cetera, use a newer version of GCC. But we must detect
3400 one important case - lr is in column 65 in .debug_frame output,
3403 GCC 3.4, and the "hammer" branch, have a related problem. They
3404 record lr register saves in .debug_frame as 108, but still record
3405 the return column as 65. We fix that up too.
3407 We can do this because 65 is assigned to fpsr, and GCC never
3408 generates debug info referring to it. To add support for
3409 handwritten debug info that restores fpsr, we would need to add a
3410 producer version check to this. */
3419 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3420 internal register numbering; translate that to the standard DWARF2
3421 register numbering. */
3422 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3424 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3425 return num
- 68 + 86;
3426 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3427 return num
- 77 + 1124;
3439 case 109: /* vrsave */
3441 case 110: /* vscr */
3443 case 111: /* spe_acc */
3445 case 112: /* spefscr */
3453 /* Handling the various POWER/PowerPC variants. */
3455 /* Information about a particular processor variant. */
3459 /* Name of this variant. */
3462 /* English description of the variant. */
3463 const char *description
;
3465 /* bfd_arch_info.arch corresponding to variant. */
3466 enum bfd_architecture arch
;
3468 /* bfd_arch_info.mach corresponding to variant. */
3471 /* Target description for this variant. */
3472 struct target_desc
**tdesc
;
3475 static struct ppc_variant variants
[] =
3477 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3478 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3479 {"power", "POWER user-level", bfd_arch_rs6000
,
3480 bfd_mach_rs6k
, &tdesc_rs6000
},
3481 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3482 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3483 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3484 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3485 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3486 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3487 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3488 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3489 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3490 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3491 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3492 604, &tdesc_powerpc_604
},
3493 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3494 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3495 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3496 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3497 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3498 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3499 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3500 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3501 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3502 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3503 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3504 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3507 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3508 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3509 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3510 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3511 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3512 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3513 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3514 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3515 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3516 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3517 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3518 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3520 /* FIXME: I haven't checked the register sets of the following. */
3521 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3522 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3523 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3524 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3525 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3526 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3528 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3531 /* Return the variant corresponding to architecture ARCH and machine number
3532 MACH. If no such variant exists, return null. */
3534 static const struct ppc_variant
*
3535 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3537 const struct ppc_variant
*v
;
3539 for (v
= variants
; v
->name
; v
++)
3540 if (arch
== v
->arch
&& mach
== v
->mach
)
3548 struct rs6000_frame_cache
3551 CORE_ADDR initial_sp
;
3552 trad_frame_saved_reg
*saved_regs
;
3554 /* Set BASE_P to true if this frame cache is properly initialized.
3555 Otherwise set to false because some registers or memory cannot
3558 /* Cache PC for building unavailable frame. */
3562 static struct rs6000_frame_cache
*
3563 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3565 struct rs6000_frame_cache
*cache
;
3566 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3567 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3568 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3569 struct rs6000_framedata fdata
;
3570 int wordsize
= tdep
->wordsize
;
3571 CORE_ADDR func
= 0, pc
= 0;
3573 if ((*this_cache
) != NULL
)
3574 return (struct rs6000_frame_cache
*) (*this_cache
);
3575 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3576 (*this_cache
) = cache
;
3578 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3582 func
= get_frame_func (this_frame
);
3584 pc
= get_frame_pc (this_frame
);
3585 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3587 /* Figure out the parent's stack pointer. */
3589 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3590 address of the current frame. Things might be easier if the
3591 ->frame pointed to the outer-most address of the frame. In
3592 the mean time, the address of the prev frame is used as the
3593 base address of this frame. */
3594 cache
->base
= get_frame_register_unsigned
3595 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3597 catch (const gdb_exception_error
&ex
)
3599 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3601 return (struct rs6000_frame_cache
*) (*this_cache
);
3604 /* If the function appears to be frameless, check a couple of likely
3605 indicators that we have simply failed to find the frame setup.
3606 Two common cases of this are missing symbols (i.e.
3607 get_frame_func returns the wrong address or 0), and assembly
3608 stubs which have a fast exit path but set up a frame on the slow
3611 If the LR appears to return to this function, then presume that
3612 we have an ABI compliant frame that we failed to find. */
3613 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3618 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3619 if (func
== 0 && saved_lr
== pc
)
3623 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3624 if (func
== saved_func
)
3630 fdata
.frameless
= 0;
3631 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3635 if (!fdata
.frameless
)
3637 /* Frameless really means stackless. */
3640 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3641 byte_order
, &backchain
))
3642 cache
->base
= (CORE_ADDR
) backchain
;
3645 cache
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->base
);
3647 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3648 All fpr's from saved_fpr to fp31 are saved. */
3650 if (fdata
.saved_fpr
>= 0)
3653 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3655 /* If skip_prologue says floating-point registers were saved,
3656 but the current architecture has no floating-point registers,
3657 then that's strange. But we have no indices to even record
3658 the addresses under, so we just ignore it. */
3659 if (ppc_floating_point_unit_p (gdbarch
))
3660 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3662 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3667 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3668 All gpr's from saved_gpr to gpr31 are saved (except during the
3671 if (fdata
.saved_gpr
>= 0)
3674 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3675 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3677 if (fdata
.gpr_mask
& (1U << i
))
3678 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3679 gpr_addr
+= wordsize
;
3683 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3684 All vr's from saved_vr to vr31 are saved. */
3685 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3687 if (fdata
.saved_vr
>= 0)
3690 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3691 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3693 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3694 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3699 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3700 All vr's from saved_ev to ev31 are saved. ????? */
3701 if (tdep
->ppc_ev0_regnum
!= -1)
3703 if (fdata
.saved_ev
>= 0)
3706 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3707 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3709 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3711 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3712 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3714 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3719 /* If != 0, fdata.cr_offset is the offset from the frame that
3721 if (fdata
.cr_offset
!= 0)
3722 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3725 /* If != 0, fdata.lr_offset is the offset from the frame that
3727 if (fdata
.lr_offset
!= 0)
3728 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3730 else if (fdata
.lr_register
!= -1)
3731 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3732 /* The PC is found in the link register. */
3733 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3734 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3736 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3737 holds the VRSAVE. */
3738 if (fdata
.vrsave_offset
!= 0)
3739 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3740 + fdata
.vrsave_offset
);
3742 if (fdata
.alloca_reg
< 0)
3743 /* If no alloca register used, then fi->frame is the value of the
3744 %sp for this frame, and it is good enough. */
3746 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3749 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3756 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3757 struct frame_id
*this_id
)
3759 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3764 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3768 /* This marks the outermost frame. */
3769 if (info
->base
== 0)
3772 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3775 static struct value
*
3776 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3777 void **this_cache
, int regnum
)
3779 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3781 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3784 static const struct frame_unwind rs6000_frame_unwind
=
3787 default_frame_unwind_stop_reason
,
3788 rs6000_frame_this_id
,
3789 rs6000_frame_prev_register
,
3791 default_frame_sniffer
3794 /* Allocate and initialize a frame cache for an epilogue frame.
3795 SP is restored and prev-PC is stored in LR. */
3797 static struct rs6000_frame_cache
*
3798 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3800 struct rs6000_frame_cache
*cache
;
3801 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3805 return (struct rs6000_frame_cache
*) *this_cache
;
3807 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3808 (*this_cache
) = cache
;
3809 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3813 /* At this point the stack looks as if we just entered the
3814 function, and the return address is stored in LR. */
3817 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3818 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3821 cache
->initial_sp
= sp
;
3823 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)].set_value (lr
);
3825 catch (const gdb_exception_error
&ex
)
3827 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3834 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3835 Return the frame ID of an epilogue frame. */
3838 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3839 void **this_cache
, struct frame_id
*this_id
)
3842 struct rs6000_frame_cache
*info
=
3843 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3845 pc
= get_frame_func (this_frame
);
3846 if (info
->base
== 0)
3847 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3849 (*this_id
) = frame_id_build (info
->base
, pc
);
3852 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3853 Return the register value of REGNUM in previous frame. */
3855 static struct value
*
3856 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3857 void **this_cache
, int regnum
)
3859 struct rs6000_frame_cache
*info
=
3860 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3861 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3864 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3865 Check whether this an epilogue frame. */
3868 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3869 struct frame_info
*this_frame
,
3870 void **this_prologue_cache
)
3872 if (frame_relative_level (this_frame
) == 0)
3873 return rs6000_in_function_epilogue_frame_p (this_frame
,
3874 get_frame_arch (this_frame
),
3875 get_frame_pc (this_frame
));
3880 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3881 a function without debug information. */
3883 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3886 default_frame_unwind_stop_reason
,
3887 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3889 rs6000_epilogue_frame_sniffer
3894 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3896 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3898 return info
->initial_sp
;
3901 static const struct frame_base rs6000_frame_base
= {
3902 &rs6000_frame_unwind
,
3903 rs6000_frame_base_address
,
3904 rs6000_frame_base_address
,
3905 rs6000_frame_base_address
3908 static const struct frame_base
*
3909 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3911 return &rs6000_frame_base
;
3914 /* DWARF-2 frame support. Used to handle the detection of
3915 clobbered registers during function calls. */
3918 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3919 struct dwarf2_frame_state_reg
*reg
,
3920 struct frame_info
*this_frame
)
3922 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3924 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3925 non-volatile registers. We will use the same code for both. */
3927 /* Call-saved GP registers. */
3928 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3929 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3930 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3931 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3933 /* Call-clobbered GP registers. */
3934 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3935 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3936 || (regnum
== tdep
->ppc_gp0_regnum
))
3937 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3939 /* Deal with FP registers, if supported. */
3940 if (tdep
->ppc_fp0_regnum
>= 0)
3942 /* Call-saved FP registers. */
3943 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3944 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3945 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3947 /* Call-clobbered FP registers. */
3948 if ((regnum
>= tdep
->ppc_fp0_regnum
3949 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3950 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3953 /* Deal with ALTIVEC registers, if supported. */
3954 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3956 /* Call-saved Altivec registers. */
3957 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3958 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3959 || regnum
== tdep
->ppc_vrsave_regnum
)
3960 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3962 /* Call-clobbered Altivec registers. */
3963 if ((regnum
>= tdep
->ppc_vr0_regnum
3964 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3965 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3968 /* Handle PC register and Stack Pointer correctly. */
3969 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3970 reg
->how
= DWARF2_FRAME_REG_RA
;
3971 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3972 reg
->how
= DWARF2_FRAME_REG_CFA
;
3976 /* Return true if a .gnu_attributes section exists in BFD and it
3977 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3978 section exists in BFD and it indicates that SPE extensions are in
3979 use. Check the .gnu.attributes section first, as the binary might be
3980 compiled for SPE, but not actually using SPE instructions. */
3983 bfd_uses_spe_extensions (bfd
*abfd
)
3986 gdb_byte
*contents
= NULL
;
3995 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3996 could be using the SPE vector abi without actually using any spe
3997 bits whatsoever. But it's close enough for now. */
3998 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3999 Tag_GNU_Power_ABI_Vector
);
4000 if (vector_abi
== 3)
4004 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
4008 size
= bfd_section_size (sect
);
4009 contents
= (gdb_byte
*) xmalloc (size
);
4010 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
4016 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
4022 char name[name_len rounded up to 4-byte alignment];
4023 char data[data_len];
4026 Technically, there's only supposed to be one such structure in a
4027 given apuinfo section, but the linker is not always vigilant about
4028 merging apuinfo sections from input files. Just go ahead and parse
4029 them all, exiting early when we discover the binary uses SPE
4032 It's not specified in what endianness the information in this
4033 section is stored. Assume that it's the endianness of the BFD. */
4037 unsigned int name_len
;
4038 unsigned int data_len
;
4041 /* If we can't read the first three fields, we're done. */
4045 name_len
= bfd_get_32 (abfd
, ptr
);
4046 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
4047 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
4048 type
= bfd_get_32 (abfd
, ptr
+ 8);
4051 /* The name must be "APUinfo\0". */
4053 && strcmp ((const char *) ptr
, "APUinfo") != 0)
4057 /* The type must be 2. */
4061 /* The data is stored as a series of uint32. The upper half of
4062 each uint32 indicates the particular APU used and the lower
4063 half indicates the revision of that APU. We just care about
4066 /* Not 4-byte quantities. */
4072 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
4073 unsigned int apu
= apuinfo
>> 16;
4077 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4079 if (apu
== 0x100 || apu
== 0x101)
4094 /* These are macros for parsing instruction fields (I.1.6.28) */
4096 #define PPC_FIELD(value, from, len) \
4097 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4098 #define PPC_SEXT(v, bs) \
4099 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4100 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4101 - ((CORE_ADDR) 1 << ((bs) - 1)))
4102 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4103 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4104 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4105 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4106 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4107 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4108 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4109 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4110 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4111 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4112 | (PPC_FIELD (insn, 16, 5) << 5))
4113 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4114 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4115 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4116 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4117 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4118 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4119 #define PPC_OE(insn) PPC_BIT (insn, 21)
4120 #define PPC_RC(insn) PPC_BIT (insn, 31)
4121 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4122 #define PPC_LK(insn) PPC_BIT (insn, 31)
4123 #define PPC_TX(insn) PPC_BIT (insn, 31)
4124 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4126 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4127 #define PPC_XER_NB(xer) (xer & 0x7f)
4129 /* Record Vector-Scalar Registers.
4130 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4131 Otherwise, it's just a VR register. Record them accordingly. */
4134 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
4136 if (vsr
< 0 || vsr
>= 64)
4141 if (tdep
->ppc_vr0_regnum
>= 0)
4142 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4146 if (tdep
->ppc_fp0_regnum
>= 0)
4147 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4148 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4149 record_full_arch_list_add_reg (regcache
,
4150 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4156 /* Parse and record instructions primary opcode-4 at ADDR.
4157 Return 0 if successful. */
4160 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4161 CORE_ADDR addr
, uint32_t insn
)
4163 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4164 int ext
= PPC_FIELD (insn
, 21, 11);
4165 int vra
= PPC_FIELD (insn
, 11, 5);
4169 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4170 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4171 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4172 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4173 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4175 case 42: /* Vector Select */
4176 case 43: /* Vector Permute */
4177 case 59: /* Vector Permute Right-indexed */
4178 case 44: /* Vector Shift Left Double by Octet Immediate */
4179 case 45: /* Vector Permute and Exclusive-OR */
4180 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4181 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4182 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4183 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4184 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4185 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4186 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4187 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4188 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4189 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4190 case 46: /* Vector Multiply-Add Single-Precision */
4191 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4192 record_full_arch_list_add_reg (regcache
,
4193 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4196 case 48: /* Multiply-Add High Doubleword */
4197 case 49: /* Multiply-Add High Doubleword Unsigned */
4198 case 51: /* Multiply-Add Low Doubleword */
4199 record_full_arch_list_add_reg (regcache
,
4200 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4204 switch ((ext
& 0x1ff))
4207 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4208 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4209 && vra
!= 4 /* Decimal Convert To Zoned */
4210 && vra
!= 5 /* Decimal Convert To National */
4211 && vra
!= 6 /* Decimal Convert From Zoned */
4212 && vra
!= 7 /* Decimal Convert From National */
4213 && vra
!= 31) /* Decimal Set Sign */
4216 /* 5.16 Decimal Integer Arithmetic Instructions */
4217 case 1: /* Decimal Add Modulo */
4218 case 65: /* Decimal Subtract Modulo */
4220 case 193: /* Decimal Shift */
4221 case 129: /* Decimal Unsigned Shift */
4222 case 449: /* Decimal Shift and Round */
4224 case 257: /* Decimal Truncate */
4225 case 321: /* Decimal Unsigned Truncate */
4227 /* Bit-21 should be set. */
4228 if (!PPC_BIT (insn
, 21))
4231 record_full_arch_list_add_reg (regcache
,
4232 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4233 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4237 /* Bit-21 is used for RC */
4238 switch (ext
& 0x3ff)
4240 case 6: /* Vector Compare Equal To Unsigned Byte */
4241 case 70: /* Vector Compare Equal To Unsigned Halfword */
4242 case 134: /* Vector Compare Equal To Unsigned Word */
4243 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4244 case 774: /* Vector Compare Greater Than Signed Byte */
4245 case 838: /* Vector Compare Greater Than Signed Halfword */
4246 case 902: /* Vector Compare Greater Than Signed Word */
4247 case 967: /* Vector Compare Greater Than Signed Doubleword */
4248 case 518: /* Vector Compare Greater Than Unsigned Byte */
4249 case 646: /* Vector Compare Greater Than Unsigned Word */
4250 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4251 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4252 case 966: /* Vector Compare Bounds Single-Precision */
4253 case 198: /* Vector Compare Equal To Single-Precision */
4254 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4255 case 710: /* Vector Compare Greater Than Single-Precision */
4256 case 7: /* Vector Compare Not Equal Byte */
4257 case 71: /* Vector Compare Not Equal Halfword */
4258 case 135: /* Vector Compare Not Equal Word */
4259 case 263: /* Vector Compare Not Equal or Zero Byte */
4260 case 327: /* Vector Compare Not Equal or Zero Halfword */
4261 case 391: /* Vector Compare Not Equal or Zero Word */
4263 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4264 record_full_arch_list_add_reg (regcache
,
4265 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4273 case 0: /* Vector Count Leading Zero Least-Significant Bits
4275 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4277 record_full_arch_list_add_reg (regcache
,
4278 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4281 case 6: /* Vector Negate Word */
4282 case 7: /* Vector Negate Doubleword */
4283 case 8: /* Vector Parity Byte Word */
4284 case 9: /* Vector Parity Byte Doubleword */
4285 case 10: /* Vector Parity Byte Quadword */
4286 case 16: /* Vector Extend Sign Byte To Word */
4287 case 17: /* Vector Extend Sign Halfword To Word */
4288 case 24: /* Vector Extend Sign Byte To Doubleword */
4289 case 25: /* Vector Extend Sign Halfword To Doubleword */
4290 case 26: /* Vector Extend Sign Word To Doubleword */
4291 case 28: /* Vector Count Trailing Zeros Byte */
4292 case 29: /* Vector Count Trailing Zeros Halfword */
4293 case 30: /* Vector Count Trailing Zeros Word */
4294 case 31: /* Vector Count Trailing Zeros Doubleword */
4295 record_full_arch_list_add_reg (regcache
,
4296 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4303 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4304 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4305 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4306 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4307 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4308 case 462: /* Vector Pack Signed Word Signed Saturate */
4309 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4310 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4311 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4312 case 512: /* Vector Add Unsigned Byte Saturate */
4313 case 576: /* Vector Add Unsigned Halfword Saturate */
4314 case 640: /* Vector Add Unsigned Word Saturate */
4315 case 768: /* Vector Add Signed Byte Saturate */
4316 case 832: /* Vector Add Signed Halfword Saturate */
4317 case 896: /* Vector Add Signed Word Saturate */
4318 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4319 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4320 case 1664: /* Vector Subtract Unsigned Word Saturate */
4321 case 1792: /* Vector Subtract Signed Byte Saturate */
4322 case 1856: /* Vector Subtract Signed Halfword Saturate */
4323 case 1920: /* Vector Subtract Signed Word Saturate */
4325 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4326 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4327 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4328 case 1672: /* Vector Sum across Half Signed Word Saturate */
4329 case 1928: /* Vector Sum across Signed Word Saturate */
4330 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4331 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4332 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4334 case 12: /* Vector Merge High Byte */
4335 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4336 case 76: /* Vector Merge High Halfword */
4337 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4338 case 140: /* Vector Merge High Word */
4339 case 268: /* Vector Merge Low Byte */
4340 case 332: /* Vector Merge Low Halfword */
4341 case 396: /* Vector Merge Low Word */
4342 case 526: /* Vector Unpack High Signed Byte */
4343 case 590: /* Vector Unpack High Signed Halfword */
4344 case 654: /* Vector Unpack Low Signed Byte */
4345 case 718: /* Vector Unpack Low Signed Halfword */
4346 case 782: /* Vector Pack Pixel */
4347 case 846: /* Vector Unpack High Pixel */
4348 case 974: /* Vector Unpack Low Pixel */
4349 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4350 case 1614: /* Vector Unpack High Signed Word */
4351 case 1676: /* Vector Merge Odd Word */
4352 case 1742: /* Vector Unpack Low Signed Word */
4353 case 1932: /* Vector Merge Even Word */
4354 case 524: /* Vector Splat Byte */
4355 case 588: /* Vector Splat Halfword */
4356 case 652: /* Vector Splat Word */
4357 case 780: /* Vector Splat Immediate Signed Byte */
4358 case 844: /* Vector Splat Immediate Signed Halfword */
4359 case 908: /* Vector Splat Immediate Signed Word */
4360 case 452: /* Vector Shift Left */
4361 case 708: /* Vector Shift Right */
4362 case 1036: /* Vector Shift Left by Octet */
4363 case 1100: /* Vector Shift Right by Octet */
4364 case 0: /* Vector Add Unsigned Byte Modulo */
4365 case 64: /* Vector Add Unsigned Halfword Modulo */
4366 case 128: /* Vector Add Unsigned Word Modulo */
4367 case 192: /* Vector Add Unsigned Doubleword Modulo */
4368 case 256: /* Vector Add Unsigned Quadword Modulo */
4369 case 320: /* Vector Add & write Carry Unsigned Quadword */
4370 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4371 case 8: /* Vector Multiply Odd Unsigned Byte */
4372 case 72: /* Vector Multiply Odd Unsigned Halfword */
4373 case 136: /* Vector Multiply Odd Unsigned Word */
4374 case 264: /* Vector Multiply Odd Signed Byte */
4375 case 328: /* Vector Multiply Odd Signed Halfword */
4376 case 392: /* Vector Multiply Odd Signed Word */
4377 case 520: /* Vector Multiply Even Unsigned Byte */
4378 case 584: /* Vector Multiply Even Unsigned Halfword */
4379 case 648: /* Vector Multiply Even Unsigned Word */
4380 case 776: /* Vector Multiply Even Signed Byte */
4381 case 840: /* Vector Multiply Even Signed Halfword */
4382 case 904: /* Vector Multiply Even Signed Word */
4383 case 137: /* Vector Multiply Unsigned Word Modulo */
4384 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4385 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4386 case 1152: /* Vector Subtract Unsigned Word Modulo */
4387 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4388 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4389 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4390 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4391 case 1282: /* Vector Average Signed Byte */
4392 case 1346: /* Vector Average Signed Halfword */
4393 case 1410: /* Vector Average Signed Word */
4394 case 1026: /* Vector Average Unsigned Byte */
4395 case 1090: /* Vector Average Unsigned Halfword */
4396 case 1154: /* Vector Average Unsigned Word */
4397 case 258: /* Vector Maximum Signed Byte */
4398 case 322: /* Vector Maximum Signed Halfword */
4399 case 386: /* Vector Maximum Signed Word */
4400 case 450: /* Vector Maximum Signed Doubleword */
4401 case 2: /* Vector Maximum Unsigned Byte */
4402 case 66: /* Vector Maximum Unsigned Halfword */
4403 case 130: /* Vector Maximum Unsigned Word */
4404 case 194: /* Vector Maximum Unsigned Doubleword */
4405 case 770: /* Vector Minimum Signed Byte */
4406 case 834: /* Vector Minimum Signed Halfword */
4407 case 898: /* Vector Minimum Signed Word */
4408 case 962: /* Vector Minimum Signed Doubleword */
4409 case 514: /* Vector Minimum Unsigned Byte */
4410 case 578: /* Vector Minimum Unsigned Halfword */
4411 case 642: /* Vector Minimum Unsigned Word */
4412 case 706: /* Vector Minimum Unsigned Doubleword */
4413 case 1028: /* Vector Logical AND */
4414 case 1668: /* Vector Logical Equivalent */
4415 case 1092: /* Vector Logical AND with Complement */
4416 case 1412: /* Vector Logical NAND */
4417 case 1348: /* Vector Logical OR with Complement */
4418 case 1156: /* Vector Logical OR */
4419 case 1284: /* Vector Logical NOR */
4420 case 1220: /* Vector Logical XOR */
4421 case 4: /* Vector Rotate Left Byte */
4422 case 132: /* Vector Rotate Left Word VX-form */
4423 case 68: /* Vector Rotate Left Halfword */
4424 case 196: /* Vector Rotate Left Doubleword */
4425 case 260: /* Vector Shift Left Byte */
4426 case 388: /* Vector Shift Left Word */
4427 case 324: /* Vector Shift Left Halfword */
4428 case 1476: /* Vector Shift Left Doubleword */
4429 case 516: /* Vector Shift Right Byte */
4430 case 644: /* Vector Shift Right Word */
4431 case 580: /* Vector Shift Right Halfword */
4432 case 1732: /* Vector Shift Right Doubleword */
4433 case 772: /* Vector Shift Right Algebraic Byte */
4434 case 900: /* Vector Shift Right Algebraic Word */
4435 case 836: /* Vector Shift Right Algebraic Halfword */
4436 case 964: /* Vector Shift Right Algebraic Doubleword */
4437 case 10: /* Vector Add Single-Precision */
4438 case 74: /* Vector Subtract Single-Precision */
4439 case 1034: /* Vector Maximum Single-Precision */
4440 case 1098: /* Vector Minimum Single-Precision */
4441 case 842: /* Vector Convert From Signed Fixed-Point Word */
4442 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4443 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4444 case 522: /* Vector Round to Single-Precision Integer Nearest */
4445 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4446 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4447 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4448 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4449 case 266: /* Vector Reciprocal Estimate Single-Precision */
4450 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4451 case 1288: /* Vector AES Cipher */
4452 case 1289: /* Vector AES Cipher Last */
4453 case 1352: /* Vector AES Inverse Cipher */
4454 case 1353: /* Vector AES Inverse Cipher Last */
4455 case 1480: /* Vector AES SubBytes */
4456 case 1730: /* Vector SHA-512 Sigma Doubleword */
4457 case 1666: /* Vector SHA-256 Sigma Word */
4458 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4459 case 1160: /* Vector Polynomial Multiply-Sum Word */
4460 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4461 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4462 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4463 case 1794: /* Vector Count Leading Zeros Byte */
4464 case 1858: /* Vector Count Leading Zeros Halfword */
4465 case 1922: /* Vector Count Leading Zeros Word */
4466 case 1986: /* Vector Count Leading Zeros Doubleword */
4467 case 1795: /* Vector Population Count Byte */
4468 case 1859: /* Vector Population Count Halfword */
4469 case 1923: /* Vector Population Count Word */
4470 case 1987: /* Vector Population Count Doubleword */
4471 case 1356: /* Vector Bit Permute Quadword */
4472 case 1484: /* Vector Bit Permute Doubleword */
4473 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4474 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4476 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4477 case 65: /* Vector Multiply-by-10 Extended & write Carry
4478 Unsigned Quadword */
4479 case 1027: /* Vector Absolute Difference Unsigned Byte */
4480 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4481 case 1155: /* Vector Absolute Difference Unsigned Word */
4482 case 1796: /* Vector Shift Right Variable */
4483 case 1860: /* Vector Shift Left Variable */
4484 case 133: /* Vector Rotate Left Word then Mask Insert */
4485 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4486 case 389: /* Vector Rotate Left Word then AND with Mask */
4487 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4488 case 525: /* Vector Extract Unsigned Byte */
4489 case 589: /* Vector Extract Unsigned Halfword */
4490 case 653: /* Vector Extract Unsigned Word */
4491 case 717: /* Vector Extract Doubleword */
4492 case 781: /* Vector Insert Byte */
4493 case 845: /* Vector Insert Halfword */
4494 case 909: /* Vector Insert Word */
4495 case 973: /* Vector Insert Doubleword */
4496 record_full_arch_list_add_reg (regcache
,
4497 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4500 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4501 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4502 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4503 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4504 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4505 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4506 record_full_arch_list_add_reg (regcache
,
4507 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4510 case 1604: /* Move To Vector Status and Control Register */
4511 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4513 case 1540: /* Move From Vector Status and Control Register */
4514 record_full_arch_list_add_reg (regcache
,
4515 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4517 case 833: /* Decimal Copy Sign */
4518 record_full_arch_list_add_reg (regcache
,
4519 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4520 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4524 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4525 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4529 /* Parse and record instructions of primary opcode-19 at ADDR.
4530 Return 0 if successful. */
4533 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4534 CORE_ADDR addr
, uint32_t insn
)
4536 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4537 int ext
= PPC_EXTOP (insn
);
4539 switch (ext
& 0x01f)
4541 case 2: /* Add PC Immediate Shifted */
4542 record_full_arch_list_add_reg (regcache
,
4543 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4549 case 0: /* Move Condition Register Field */
4550 case 33: /* Condition Register NOR */
4551 case 129: /* Condition Register AND with Complement */
4552 case 193: /* Condition Register XOR */
4553 case 225: /* Condition Register NAND */
4554 case 257: /* Condition Register AND */
4555 case 289: /* Condition Register Equivalent */
4556 case 417: /* Condition Register OR with Complement */
4557 case 449: /* Condition Register OR */
4558 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4561 case 16: /* Branch Conditional */
4562 case 560: /* Branch Conditional to Branch Target Address Register */
4563 if ((PPC_BO (insn
) & 0x4) == 0)
4564 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4566 case 528: /* Branch Conditional to Count Register */
4568 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4571 case 150: /* Instruction Synchronize */
4576 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4577 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4581 /* Parse and record instructions of primary opcode-31 at ADDR.
4582 Return 0 if successful. */
4585 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4586 CORE_ADDR addr
, uint32_t insn
)
4588 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4589 int ext
= PPC_EXTOP (insn
);
4591 CORE_ADDR at_dcsz
, ea
= 0;
4592 ULONGEST rb
, ra
, xer
;
4595 /* These instructions have OE bit. */
4596 switch (ext
& 0x1ff)
4598 /* These write RT and XER. Update CR if RC is set. */
4599 case 8: /* Subtract from carrying */
4600 case 10: /* Add carrying */
4601 case 136: /* Subtract from extended */
4602 case 138: /* Add extended */
4603 case 200: /* Subtract from zero extended */
4604 case 202: /* Add to zero extended */
4605 case 232: /* Subtract from minus one extended */
4606 case 234: /* Add to minus one extended */
4607 /* CA is always altered, but SO/OV are only altered when OE=1.
4608 In any case, XER is always altered. */
4609 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4611 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4612 record_full_arch_list_add_reg (regcache
,
4613 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4616 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4617 case 40: /* Subtract from */
4618 case 104: /* Negate */
4619 case 233: /* Multiply low doubleword */
4620 case 235: /* Multiply low word */
4622 case 393: /* Divide Doubleword Extended Unsigned */
4623 case 395: /* Divide Word Extended Unsigned */
4624 case 425: /* Divide Doubleword Extended */
4625 case 427: /* Divide Word Extended */
4626 case 457: /* Divide Doubleword Unsigned */
4627 case 459: /* Divide Word Unsigned */
4628 case 489: /* Divide Doubleword */
4629 case 491: /* Divide Word */
4631 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4633 case 9: /* Multiply High Doubleword Unsigned */
4634 case 11: /* Multiply High Word Unsigned */
4635 case 73: /* Multiply High Doubleword */
4636 case 75: /* Multiply High Word */
4638 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4639 record_full_arch_list_add_reg (regcache
,
4640 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4644 if ((ext
& 0x1f) == 15)
4646 /* Integer Select. bit[16:20] is used for BC. */
4647 record_full_arch_list_add_reg (regcache
,
4648 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4652 if ((ext
& 0xff) == 170)
4654 /* Add Extended using alternate carry bits */
4655 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4656 record_full_arch_list_add_reg (regcache
,
4657 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4663 case 78: /* Determine Leftmost Zero Byte */
4665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4666 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4667 record_full_arch_list_add_reg (regcache
,
4668 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4671 /* These only write RT. */
4672 case 19: /* Move from condition register */
4673 /* Move From One Condition Register Field */
4674 case 74: /* Add and Generate Sixes */
4675 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4676 case 302: /* Move From Branch History Rolling Buffer */
4677 case 339: /* Move From Special Purpose Register */
4678 case 371: /* Move From Time Base [Phased-Out] */
4679 case 309: /* Load Doubleword Monitored Indexed */
4680 case 128: /* Set Boolean */
4681 case 755: /* Deliver A Random Number */
4682 record_full_arch_list_add_reg (regcache
,
4683 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4686 /* These only write to RA. */
4687 case 51: /* Move From VSR Doubleword */
4688 case 115: /* Move From VSR Word and Zero */
4689 case 122: /* Population count bytes */
4690 case 378: /* Population count words */
4691 case 506: /* Population count doublewords */
4692 case 154: /* Parity Word */
4693 case 186: /* Parity Doubleword */
4694 case 252: /* Bit Permute Doubleword */
4695 case 282: /* Convert Declets To Binary Coded Decimal */
4696 case 314: /* Convert Binary Coded Decimal To Declets */
4697 case 508: /* Compare bytes */
4698 case 307: /* Move From VSR Lower Doubleword */
4699 record_full_arch_list_add_reg (regcache
,
4700 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4703 /* These write CR and optional RA. */
4704 case 792: /* Shift Right Algebraic Word */
4705 case 794: /* Shift Right Algebraic Doubleword */
4706 case 824: /* Shift Right Algebraic Word Immediate */
4707 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4708 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4709 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4710 record_full_arch_list_add_reg (regcache
,
4711 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4713 case 0: /* Compare */
4714 case 32: /* Compare logical */
4715 case 144: /* Move To Condition Register Fields */
4716 /* Move To One Condition Register Field */
4717 case 192: /* Compare Ranged Byte */
4718 case 224: /* Compare Equal Byte */
4719 case 576: /* Move XER to CR Extended */
4720 case 902: /* Paste (should always fail due to single-stepping and
4721 the memory location might not be accessible, so
4723 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4726 /* These write to RT. Update RA if 'update indexed.' */
4727 case 53: /* Load Doubleword with Update Indexed */
4728 case 119: /* Load Byte and Zero with Update Indexed */
4729 case 311: /* Load Halfword and Zero with Update Indexed */
4730 case 55: /* Load Word and Zero with Update Indexed */
4731 case 375: /* Load Halfword Algebraic with Update Indexed */
4732 case 373: /* Load Word Algebraic with Update Indexed */
4733 record_full_arch_list_add_reg (regcache
,
4734 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4736 case 21: /* Load Doubleword Indexed */
4737 case 52: /* Load Byte And Reserve Indexed */
4738 case 116: /* Load Halfword And Reserve Indexed */
4739 case 20: /* Load Word And Reserve Indexed */
4740 case 84: /* Load Doubleword And Reserve Indexed */
4741 case 87: /* Load Byte and Zero Indexed */
4742 case 279: /* Load Halfword and Zero Indexed */
4743 case 23: /* Load Word and Zero Indexed */
4744 case 343: /* Load Halfword Algebraic Indexed */
4745 case 341: /* Load Word Algebraic Indexed */
4746 case 790: /* Load Halfword Byte-Reverse Indexed */
4747 case 534: /* Load Word Byte-Reverse Indexed */
4748 case 532: /* Load Doubleword Byte-Reverse Indexed */
4749 case 582: /* Load Word Atomic */
4750 case 614: /* Load Doubleword Atomic */
4751 case 265: /* Modulo Unsigned Doubleword */
4752 case 777: /* Modulo Signed Doubleword */
4753 case 267: /* Modulo Unsigned Word */
4754 case 779: /* Modulo Signed Word */
4755 record_full_arch_list_add_reg (regcache
,
4756 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4759 case 597: /* Load String Word Immediate */
4760 case 533: /* Load String Word Indexed */
4769 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4770 nr
= PPC_XER_NB (xer
);
4775 /* If n=0, the contents of register RT are undefined. */
4779 for (i
= 0; i
< nr
; i
++)
4780 record_full_arch_list_add_reg (regcache
,
4781 tdep
->ppc_gp0_regnum
4782 + ((PPC_RT (insn
) + i
) & 0x1f));
4785 case 276: /* Load Quadword And Reserve Indexed */
4786 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4787 record_full_arch_list_add_reg (regcache
, tmp
);
4788 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4791 /* These write VRT. */
4792 case 6: /* Load Vector for Shift Left Indexed */
4793 case 38: /* Load Vector for Shift Right Indexed */
4794 case 7: /* Load Vector Element Byte Indexed */
4795 case 39: /* Load Vector Element Halfword Indexed */
4796 case 71: /* Load Vector Element Word Indexed */
4797 case 103: /* Load Vector Indexed */
4798 case 359: /* Load Vector Indexed LRU */
4799 record_full_arch_list_add_reg (regcache
,
4800 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4803 /* These write FRT. Update RA if 'update indexed.' */
4804 case 567: /* Load Floating-Point Single with Update Indexed */
4805 case 631: /* Load Floating-Point Double with Update Indexed */
4806 record_full_arch_list_add_reg (regcache
,
4807 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4809 case 535: /* Load Floating-Point Single Indexed */
4810 case 599: /* Load Floating-Point Double Indexed */
4811 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4812 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4813 record_full_arch_list_add_reg (regcache
,
4814 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4817 case 791: /* Load Floating-Point Double Pair Indexed */
4818 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4819 record_full_arch_list_add_reg (regcache
, tmp
);
4820 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4823 case 179: /* Move To VSR Doubleword */
4824 case 211: /* Move To VSR Word Algebraic */
4825 case 243: /* Move To VSR Word and Zero */
4826 case 588: /* Load VSX Scalar Doubleword Indexed */
4827 case 524: /* Load VSX Scalar Single-Precision Indexed */
4828 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4829 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4830 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4831 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4832 case 780: /* Load VSX Vector Word*4 Indexed */
4833 case 268: /* Load VSX Vector Indexed */
4834 case 364: /* Load VSX Vector Word & Splat Indexed */
4835 case 812: /* Load VSX Vector Halfword*8 Indexed */
4836 case 876: /* Load VSX Vector Byte*16 Indexed */
4837 case 269: /* Load VSX Vector with Length */
4838 case 301: /* Load VSX Vector Left-justified with Length */
4839 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4840 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4841 case 403: /* Move To VSR Word & Splat */
4842 case 435: /* Move To VSR Double Doubleword */
4843 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4846 /* These write RA. Update CR if RC is set. */
4847 case 24: /* Shift Left Word */
4848 case 26: /* Count Leading Zeros Word */
4849 case 27: /* Shift Left Doubleword */
4851 case 58: /* Count Leading Zeros Doubleword */
4852 case 60: /* AND with Complement */
4854 case 284: /* Equivalent */
4856 case 476: /* NAND */
4857 case 412: /* OR with Complement */
4859 case 536: /* Shift Right Word */
4860 case 539: /* Shift Right Doubleword */
4861 case 922: /* Extend Sign Halfword */
4862 case 954: /* Extend Sign Byte */
4863 case 986: /* Extend Sign Word */
4864 case 538: /* Count Trailing Zeros Word */
4865 case 570: /* Count Trailing Zeros Doubleword */
4866 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4867 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4869 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4870 && (PPC_RS (insn
) == PPC_RA (insn
))
4871 && (PPC_RA (insn
) == PPC_RB (insn
))
4874 /* or Rx,Rx,Rx alters PRI in PPR. */
4875 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4880 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4881 record_full_arch_list_add_reg (regcache
,
4882 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4886 case 181: /* Store Doubleword with Update Indexed */
4887 case 183: /* Store Word with Update Indexed */
4888 case 247: /* Store Byte with Update Indexed */
4889 case 439: /* Store Half Word with Update Indexed */
4890 case 695: /* Store Floating-Point Single with Update Indexed */
4891 case 759: /* Store Floating-Point Double with Update Indexed */
4892 record_full_arch_list_add_reg (regcache
,
4893 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4895 case 135: /* Store Vector Element Byte Indexed */
4896 case 167: /* Store Vector Element Halfword Indexed */
4897 case 199: /* Store Vector Element Word Indexed */
4898 case 231: /* Store Vector Indexed */
4899 case 487: /* Store Vector Indexed LRU */
4900 case 716: /* Store VSX Scalar Doubleword Indexed */
4901 case 140: /* Store VSX Scalar as Integer Word Indexed */
4902 case 652: /* Store VSX Scalar Single-Precision Indexed */
4903 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4904 case 908: /* Store VSX Vector Word*4 Indexed */
4905 case 149: /* Store Doubleword Indexed */
4906 case 151: /* Store Word Indexed */
4907 case 215: /* Store Byte Indexed */
4908 case 407: /* Store Half Word Indexed */
4909 case 694: /* Store Byte Conditional Indexed */
4910 case 726: /* Store Halfword Conditional Indexed */
4911 case 150: /* Store Word Conditional Indexed */
4912 case 214: /* Store Doubleword Conditional Indexed */
4913 case 182: /* Store Quadword Conditional Indexed */
4914 case 662: /* Store Word Byte-Reverse Indexed */
4915 case 918: /* Store Halfword Byte-Reverse Indexed */
4916 case 660: /* Store Doubleword Byte-Reverse Indexed */
4917 case 663: /* Store Floating-Point Single Indexed */
4918 case 727: /* Store Floating-Point Double Indexed */
4919 case 919: /* Store Floating-Point Double Pair Indexed */
4920 case 983: /* Store Floating-Point as Integer Word Indexed */
4921 case 396: /* Store VSX Vector Indexed */
4922 case 940: /* Store VSX Vector Halfword*8 Indexed */
4923 case 1004: /* Store VSX Vector Byte*16 Indexed */
4924 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4925 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4926 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4927 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4930 if (PPC_RA (insn
) != 0)
4931 regcache_raw_read_unsigned (regcache
,
4932 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4933 regcache_raw_read_unsigned (regcache
,
4934 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4939 case 183: /* Store Word with Update Indexed */
4940 case 199: /* Store Vector Element Word Indexed */
4941 case 140: /* Store VSX Scalar as Integer Word Indexed */
4942 case 652: /* Store VSX Scalar Single-Precision Indexed */
4943 case 151: /* Store Word Indexed */
4944 case 150: /* Store Word Conditional Indexed */
4945 case 662: /* Store Word Byte-Reverse Indexed */
4946 case 663: /* Store Floating-Point Single Indexed */
4947 case 695: /* Store Floating-Point Single with Update Indexed */
4948 case 983: /* Store Floating-Point as Integer Word Indexed */
4951 case 247: /* Store Byte with Update Indexed */
4952 case 135: /* Store Vector Element Byte Indexed */
4953 case 215: /* Store Byte Indexed */
4954 case 694: /* Store Byte Conditional Indexed */
4955 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4958 case 439: /* Store Halfword with Update Indexed */
4959 case 167: /* Store Vector Element Halfword Indexed */
4960 case 407: /* Store Halfword Indexed */
4961 case 726: /* Store Halfword Conditional Indexed */
4962 case 918: /* Store Halfword Byte-Reverse Indexed */
4963 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4966 case 181: /* Store Doubleword with Update Indexed */
4967 case 716: /* Store VSX Scalar Doubleword Indexed */
4968 case 149: /* Store Doubleword Indexed */
4969 case 214: /* Store Doubleword Conditional Indexed */
4970 case 660: /* Store Doubleword Byte-Reverse Indexed */
4971 case 727: /* Store Floating-Point Double Indexed */
4972 case 759: /* Store Floating-Point Double with Update Indexed */
4975 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4976 case 908: /* Store VSX Vector Word*4 Indexed */
4977 case 182: /* Store Quadword Conditional Indexed */
4978 case 231: /* Store Vector Indexed */
4979 case 487: /* Store Vector Indexed LRU */
4980 case 919: /* Store Floating-Point Double Pair Indexed */
4981 case 396: /* Store VSX Vector Indexed */
4982 case 940: /* Store VSX Vector Halfword*8 Indexed */
4983 case 1004: /* Store VSX Vector Byte*16 Indexed */
4990 /* Align address for Store Vector instructions. */
4993 case 167: /* Store Vector Element Halfword Indexed */
4994 addr
= addr
& ~0x1ULL
;
4997 case 199: /* Store Vector Element Word Indexed */
4998 addr
= addr
& ~0x3ULL
;
5001 case 231: /* Store Vector Indexed */
5002 case 487: /* Store Vector Indexed LRU */
5003 addr
= addr
& ~0xfULL
;
5007 record_full_arch_list_add_mem (addr
, size
);
5010 case 397: /* Store VSX Vector with Length */
5011 case 429: /* Store VSX Vector Left-justified with Length */
5013 if (PPC_RA (insn
) != 0)
5014 regcache_raw_read_unsigned (regcache
,
5015 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5017 regcache_raw_read_unsigned (regcache
,
5018 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5019 /* Store up to 16 bytes. */
5020 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
5022 record_full_arch_list_add_mem (ea
, nb
);
5025 case 710: /* Store Word Atomic */
5026 case 742: /* Store Doubleword Atomic */
5028 if (PPC_RA (insn
) != 0)
5029 regcache_raw_read_unsigned (regcache
,
5030 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5034 case 710: /* Store Word Atomic */
5037 case 742: /* Store Doubleword Atomic */
5043 record_full_arch_list_add_mem (ea
, size
);
5046 case 725: /* Store String Word Immediate */
5048 if (PPC_RA (insn
) != 0)
5049 regcache_raw_read_unsigned (regcache
,
5050 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5057 record_full_arch_list_add_mem (ea
, nb
);
5061 case 661: /* Store String Word Indexed */
5063 if (PPC_RA (insn
) != 0)
5064 regcache_raw_read_unsigned (regcache
,
5065 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5068 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5069 nb
= PPC_XER_NB (xer
);
5073 regcache_raw_read_unsigned (regcache
,
5074 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
5077 record_full_arch_list_add_mem (ea
, nb
);
5082 case 467: /* Move To Special Purpose Register */
5083 switch (PPC_SPR (insn
))
5086 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5089 if (tdep
->ppc_dscr_regnum
>= 0)
5090 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5093 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5096 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5098 case 256: /* VRSAVE */
5099 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5102 if (tdep
->ppc_tar_regnum
>= 0)
5103 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5107 if (tdep
->ppc_ppr_regnum
>= 0)
5108 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5114 case 147: /* Move To Split Little Endian */
5115 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5118 case 512: /* Move to Condition Register from XER */
5119 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5120 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5123 case 4: /* Trap Word */
5124 case 68: /* Trap Doubleword */
5125 case 430: /* Clear BHRB */
5126 case 598: /* Synchronize */
5127 case 62: /* Wait for Interrupt */
5129 case 22: /* Instruction Cache Block Touch */
5130 case 854: /* Enforce In-order Execution of I/O */
5131 case 246: /* Data Cache Block Touch for Store */
5132 case 54: /* Data Cache Block Store */
5133 case 86: /* Data Cache Block Flush */
5134 case 278: /* Data Cache Block Touch */
5135 case 758: /* Data Cache Block Allocate */
5136 case 982: /* Instruction Cache Block Invalidate */
5137 case 774: /* Copy */
5138 case 838: /* CP_Abort */
5141 case 654: /* Transaction Begin */
5142 case 686: /* Transaction End */
5143 case 750: /* Transaction Suspend or Resume */
5144 case 782: /* Transaction Abort Word Conditional */
5145 case 814: /* Transaction Abort Doubleword Conditional */
5146 case 846: /* Transaction Abort Word Conditional Immediate */
5147 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5148 case 910: /* Transaction Abort */
5149 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5151 case 718: /* Transaction Check */
5152 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5155 case 1014: /* Data Cache Block set to Zero */
5156 if (target_auxv_search (current_inferior ()->top_target (),
5157 AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5159 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5162 if (PPC_RA (insn
) != 0)
5163 regcache_raw_read_unsigned (regcache
,
5164 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5165 regcache_raw_read_unsigned (regcache
,
5166 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5167 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5168 record_full_arch_list_add_mem (ea
, at_dcsz
);
5173 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5174 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5178 /* Parse and record instructions of primary opcode-59 at ADDR.
5179 Return 0 if successful. */
5182 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5183 CORE_ADDR addr
, uint32_t insn
)
5185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5186 int ext
= PPC_EXTOP (insn
);
5190 case 18: /* Floating Divide */
5191 case 20: /* Floating Subtract */
5192 case 21: /* Floating Add */
5193 case 22: /* Floating Square Root */
5194 case 24: /* Floating Reciprocal Estimate */
5195 case 25: /* Floating Multiply */
5196 case 26: /* Floating Reciprocal Square Root Estimate */
5197 case 28: /* Floating Multiply-Subtract */
5198 case 29: /* Floating Multiply-Add */
5199 case 30: /* Floating Negative Multiply-Subtract */
5200 case 31: /* Floating Negative Multiply-Add */
5201 record_full_arch_list_add_reg (regcache
,
5202 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5204 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5205 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5212 case 2: /* DFP Add */
5213 case 3: /* DFP Quantize */
5214 case 34: /* DFP Multiply */
5215 case 35: /* DFP Reround */
5216 case 67: /* DFP Quantize Immediate */
5217 case 99: /* DFP Round To FP Integer With Inexact */
5218 case 227: /* DFP Round To FP Integer Without Inexact */
5219 case 258: /* DFP Convert To DFP Long! */
5220 case 290: /* DFP Convert To Fixed */
5221 case 514: /* DFP Subtract */
5222 case 546: /* DFP Divide */
5223 case 770: /* DFP Round To DFP Short! */
5224 case 802: /* DFP Convert From Fixed */
5225 case 834: /* DFP Encode BCD To DPD */
5227 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5228 record_full_arch_list_add_reg (regcache
,
5229 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5230 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5233 case 130: /* DFP Compare Ordered */
5234 case 162: /* DFP Test Exponent */
5235 case 194: /* DFP Test Data Class */
5236 case 226: /* DFP Test Data Group */
5237 case 642: /* DFP Compare Unordered */
5238 case 674: /* DFP Test Significance */
5239 case 675: /* DFP Test Significance Immediate */
5240 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5241 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5244 case 66: /* DFP Shift Significand Left Immediate */
5245 case 98: /* DFP Shift Significand Right Immediate */
5246 case 322: /* DFP Decode DPD To BCD */
5247 case 354: /* DFP Extract Biased Exponent */
5248 case 866: /* DFP Insert Biased Exponent */
5249 record_full_arch_list_add_reg (regcache
,
5250 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5252 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5255 case 846: /* Floating Convert From Integer Doubleword Single */
5256 case 974: /* Floating Convert From Integer Doubleword Unsigned
5258 record_full_arch_list_add_reg (regcache
,
5259 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5261 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5262 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5267 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5268 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5272 /* Parse and record instructions of primary opcode-60 at ADDR.
5273 Return 0 if successful. */
5276 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5277 CORE_ADDR addr
, uint32_t insn
)
5279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5280 int ext
= PPC_EXTOP (insn
);
5284 case 0: /* VSX Scalar Add Single-Precision */
5285 case 32: /* VSX Scalar Add Double-Precision */
5286 case 24: /* VSX Scalar Divide Single-Precision */
5287 case 56: /* VSX Scalar Divide Double-Precision */
5288 case 176: /* VSX Scalar Copy Sign Double-Precision */
5289 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5290 case 41: /* ditto */
5291 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5293 case 160: /* VSX Scalar Maximum Double-Precision */
5294 case 168: /* VSX Scalar Minimum Double-Precision */
5295 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5296 case 57: /* ditto */
5297 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5298 case 25: /* ditto */
5299 case 48: /* VSX Scalar Multiply Double-Precision */
5300 case 16: /* VSX Scalar Multiply Single-Precision */
5301 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5302 case 169: /* ditto */
5303 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5304 case 137: /* ditto */
5305 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5306 case 185: /* ditto */
5307 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5308 case 153: /* ditto */
5309 case 40: /* VSX Scalar Subtract Double-Precision */
5310 case 8: /* VSX Scalar Subtract Single-Precision */
5311 case 96: /* VSX Vector Add Double-Precision */
5312 case 64: /* VSX Vector Add Single-Precision */
5313 case 120: /* VSX Vector Divide Double-Precision */
5314 case 88: /* VSX Vector Divide Single-Precision */
5315 case 97: /* VSX Vector Multiply-Add Double-Precision */
5316 case 105: /* ditto */
5317 case 65: /* VSX Vector Multiply-Add Single-Precision */
5318 case 73: /* ditto */
5319 case 224: /* VSX Vector Maximum Double-Precision */
5320 case 192: /* VSX Vector Maximum Single-Precision */
5321 case 232: /* VSX Vector Minimum Double-Precision */
5322 case 200: /* VSX Vector Minimum Single-Precision */
5323 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5324 case 121: /* ditto */
5325 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5326 case 89: /* ditto */
5327 case 112: /* VSX Vector Multiply Double-Precision */
5328 case 80: /* VSX Vector Multiply Single-Precision */
5329 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5330 case 233: /* ditto */
5331 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5332 case 201: /* ditto */
5333 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5334 case 249: /* ditto */
5335 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5336 case 217: /* ditto */
5337 case 104: /* VSX Vector Subtract Double-Precision */
5338 case 72: /* VSX Vector Subtract Single-Precision */
5339 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5340 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5341 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5342 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5343 case 3: /* VSX Scalar Compare Equal Double-Precision */
5344 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5345 case 19: /* VSX Scalar Compare Greater Than or Equal
5347 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5349 case 240: /* VSX Vector Copy Sign Double-Precision */
5350 case 208: /* VSX Vector Copy Sign Single-Precision */
5351 case 130: /* VSX Logical AND */
5352 case 138: /* VSX Logical AND with Complement */
5353 case 186: /* VSX Logical Equivalence */
5354 case 178: /* VSX Logical NAND */
5355 case 170: /* VSX Logical OR with Complement */
5356 case 162: /* VSX Logical NOR */
5357 case 146: /* VSX Logical OR */
5358 case 154: /* VSX Logical XOR */
5359 case 18: /* VSX Merge High Word */
5360 case 50: /* VSX Merge Low Word */
5361 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5362 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5363 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5364 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5365 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5366 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5367 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5368 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5369 case 216: /* VSX Vector Insert Exponent Single-Precision */
5370 case 248: /* VSX Vector Insert Exponent Double-Precision */
5371 case 26: /* VSX Vector Permute */
5372 case 58: /* VSX Vector Permute Right-indexed */
5373 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5374 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5375 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5376 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5377 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5380 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5381 case 125: /* VSX Vector Test for software Divide Double-Precision */
5382 case 93: /* VSX Vector Test for software Divide Single-Precision */
5383 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5386 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5387 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5388 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5389 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5390 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5394 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5396 case 99: /* VSX Vector Compare Equal To Double-Precision */
5397 case 67: /* VSX Vector Compare Equal To Single-Precision */
5398 case 115: /* VSX Vector Compare Greater Than or
5399 Equal To Double-Precision */
5400 case 83: /* VSX Vector Compare Greater Than or
5401 Equal To Single-Precision */
5402 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5403 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5405 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5406 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5407 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5413 case 265: /* VSX Scalar round Double-Precision to
5414 Single-Precision and Convert to
5415 Single-Precision format */
5416 case 344: /* VSX Scalar truncate Double-Precision to
5417 Integer and Convert to Signed Integer
5418 Doubleword format with Saturate */
5419 case 88: /* VSX Scalar truncate Double-Precision to
5420 Integer and Convert to Signed Integer Word
5421 Format with Saturate */
5422 case 328: /* VSX Scalar truncate Double-Precision integer
5423 and Convert to Unsigned Integer Doubleword
5424 Format with Saturate */
5425 case 72: /* VSX Scalar truncate Double-Precision to
5426 Integer and Convert to Unsigned Integer Word
5427 Format with Saturate */
5428 case 329: /* VSX Scalar Convert Single-Precision to
5429 Double-Precision format */
5430 case 376: /* VSX Scalar Convert Signed Integer
5431 Doubleword to floating-point format and
5432 Round to Double-Precision format */
5433 case 312: /* VSX Scalar Convert Signed Integer
5434 Doubleword to floating-point format and
5435 round to Single-Precision */
5436 case 360: /* VSX Scalar Convert Unsigned Integer
5437 Doubleword to floating-point format and
5438 Round to Double-Precision format */
5439 case 296: /* VSX Scalar Convert Unsigned Integer
5440 Doubleword to floating-point format and
5441 Round to Single-Precision */
5442 case 73: /* VSX Scalar Round to Double-Precision Integer
5443 Using Round to Nearest Away */
5444 case 107: /* VSX Scalar Round to Double-Precision Integer
5445 Exact using Current rounding mode */
5446 case 121: /* VSX Scalar Round to Double-Precision Integer
5447 Using Round toward -Infinity */
5448 case 105: /* VSX Scalar Round to Double-Precision Integer
5449 Using Round toward +Infinity */
5450 case 89: /* VSX Scalar Round to Double-Precision Integer
5451 Using Round toward Zero */
5452 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5453 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5454 case 281: /* VSX Scalar Round to Single-Precision */
5455 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5457 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5459 case 75: /* VSX Scalar Square Root Double-Precision */
5460 case 11: /* VSX Scalar Square Root Single-Precision */
5461 case 393: /* VSX Vector round Double-Precision to
5462 Single-Precision and Convert to
5463 Single-Precision format */
5464 case 472: /* VSX Vector truncate Double-Precision to
5465 Integer and Convert to Signed Integer
5466 Doubleword format with Saturate */
5467 case 216: /* VSX Vector truncate Double-Precision to
5468 Integer and Convert to Signed Integer Word
5469 Format with Saturate */
5470 case 456: /* VSX Vector truncate Double-Precision to
5471 Integer and Convert to Unsigned Integer
5472 Doubleword format with Saturate */
5473 case 200: /* VSX Vector truncate Double-Precision to
5474 Integer and Convert to Unsigned Integer Word
5475 Format with Saturate */
5476 case 457: /* VSX Vector Convert Single-Precision to
5477 Double-Precision format */
5478 case 408: /* VSX Vector truncate Single-Precision to
5479 Integer and Convert to Signed Integer
5480 Doubleword format with Saturate */
5481 case 152: /* VSX Vector truncate Single-Precision to
5482 Integer and Convert to Signed Integer Word
5483 Format with Saturate */
5484 case 392: /* VSX Vector truncate Single-Precision to
5485 Integer and Convert to Unsigned Integer
5486 Doubleword format with Saturate */
5487 case 136: /* VSX Vector truncate Single-Precision to
5488 Integer and Convert to Unsigned Integer Word
5489 Format with Saturate */
5490 case 504: /* VSX Vector Convert and round Signed Integer
5491 Doubleword to Double-Precision format */
5492 case 440: /* VSX Vector Convert and round Signed Integer
5493 Doubleword to Single-Precision format */
5494 case 248: /* VSX Vector Convert Signed Integer Word to
5495 Double-Precision format */
5496 case 184: /* VSX Vector Convert and round Signed Integer
5497 Word to Single-Precision format */
5498 case 488: /* VSX Vector Convert and round Unsigned
5499 Integer Doubleword to Double-Precision format */
5500 case 424: /* VSX Vector Convert and round Unsigned
5501 Integer Doubleword to Single-Precision format */
5502 case 232: /* VSX Vector Convert and round Unsigned
5503 Integer Word to Double-Precision format */
5504 case 168: /* VSX Vector Convert and round Unsigned
5505 Integer Word to Single-Precision format */
5506 case 201: /* VSX Vector Round to Double-Precision
5507 Integer using round to Nearest Away */
5508 case 235: /* VSX Vector Round to Double-Precision
5509 Integer Exact using Current rounding mode */
5510 case 249: /* VSX Vector Round to Double-Precision
5511 Integer using round toward -Infinity */
5512 case 233: /* VSX Vector Round to Double-Precision
5513 Integer using round toward +Infinity */
5514 case 217: /* VSX Vector Round to Double-Precision
5515 Integer using round toward Zero */
5516 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5517 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5518 case 137: /* VSX Vector Round to Single-Precision Integer
5519 Using Round to Nearest Away */
5520 case 171: /* VSX Vector Round to Single-Precision Integer
5521 Exact Using Current rounding mode */
5522 case 185: /* VSX Vector Round to Single-Precision Integer
5523 Using Round toward -Infinity */
5524 case 169: /* VSX Vector Round to Single-Precision Integer
5525 Using Round toward +Infinity */
5526 case 153: /* VSX Vector Round to Single-Precision Integer
5527 Using round toward Zero */
5528 case 202: /* VSX Vector Reciprocal Square Root Estimate
5530 case 138: /* VSX Vector Reciprocal Square Root Estimate
5532 case 203: /* VSX Vector Square Root Double-Precision */
5533 case 139: /* VSX Vector Square Root Single-Precision */
5534 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5536 case 345: /* VSX Scalar Absolute Value Double-Precision */
5537 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5538 Vector Single-Precision format Non-signalling */
5539 case 331: /* VSX Scalar Convert Single-Precision to
5540 Double-Precision format Non-signalling */
5541 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5542 case 377: /* VSX Scalar Negate Double-Precision */
5543 case 473: /* VSX Vector Absolute Value Double-Precision */
5544 case 409: /* VSX Vector Absolute Value Single-Precision */
5545 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5546 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5547 case 505: /* VSX Vector Negate Double-Precision */
5548 case 441: /* VSX Vector Negate Single-Precision */
5549 case 164: /* VSX Splat Word */
5550 case 165: /* VSX Vector Extract Unsigned Word */
5551 case 181: /* VSX Vector Insert Word */
5552 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5555 case 298: /* VSX Scalar Test Data Class Single-Precision */
5556 case 362: /* VSX Scalar Test Data Class Double-Precision */
5557 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5559 case 106: /* VSX Scalar Test for software Square Root
5561 case 234: /* VSX Vector Test for software Square Root
5563 case 170: /* VSX Vector Test for software Square Root
5565 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5569 switch (PPC_FIELD (insn
, 11, 5))
5571 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5572 case 1: /* VSX Scalar Extract Significand Double-Precision */
5573 record_full_arch_list_add_reg (regcache
,
5574 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5576 case 16: /* VSX Scalar Convert Half-Precision format to
5577 Double-Precision format */
5578 case 17: /* VSX Scalar round & Convert Double-Precision format
5579 to Half-Precision format */
5580 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5581 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5587 switch (PPC_FIELD (insn
, 11, 5))
5589 case 24: /* VSX Vector Convert Half-Precision format to
5590 Single-Precision format */
5591 case 25: /* VSX Vector round and Convert Single-Precision format
5592 to Half-Precision format */
5593 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5595 case 0: /* VSX Vector Extract Exponent Double-Precision */
5596 case 1: /* VSX Vector Extract Significand Double-Precision */
5597 case 7: /* VSX Vector Byte-Reverse Halfword */
5598 case 8: /* VSX Vector Extract Exponent Single-Precision */
5599 case 9: /* VSX Vector Extract Significand Single-Precision */
5600 case 15: /* VSX Vector Byte-Reverse Word */
5601 case 23: /* VSX Vector Byte-Reverse Doubleword */
5602 case 31: /* VSX Vector Byte-Reverse Quadword */
5603 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5611 case 360: /* VSX Vector Splat Immediate Byte */
5612 if (PPC_FIELD (insn
, 11, 2) == 0)
5614 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5618 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5619 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5623 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5625 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5629 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5630 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5634 /* Parse and record instructions of primary opcode-61 at ADDR.
5635 Return 0 if successful. */
5638 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5639 CORE_ADDR addr
, uint32_t insn
)
5641 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5647 case 0: /* Store Floating-Point Double Pair */
5648 case 2: /* Store VSX Scalar Doubleword */
5649 case 3: /* Store VSX Scalar Single */
5650 if (PPC_RA (insn
) != 0)
5651 regcache_raw_read_unsigned (regcache
,
5652 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5654 ea
+= PPC_DS (insn
) << 2;
5657 case 0: /* Store Floating-Point Double Pair */
5660 case 2: /* Store VSX Scalar Doubleword */
5663 case 3: /* Store VSX Scalar Single */
5669 record_full_arch_list_add_mem (ea
, size
);
5675 case 1: /* Load VSX Vector */
5676 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5678 case 5: /* Store VSX Vector */
5679 if (PPC_RA (insn
) != 0)
5680 regcache_raw_read_unsigned (regcache
,
5681 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5683 ea
+= PPC_DQ (insn
) << 4;
5684 record_full_arch_list_add_mem (ea
, 16);
5688 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5689 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5693 /* Parse and record instructions of primary opcode-63 at ADDR.
5694 Return 0 if successful. */
5697 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5698 CORE_ADDR addr
, uint32_t insn
)
5700 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5701 int ext
= PPC_EXTOP (insn
);
5706 case 18: /* Floating Divide */
5707 case 20: /* Floating Subtract */
5708 case 21: /* Floating Add */
5709 case 22: /* Floating Square Root */
5710 case 24: /* Floating Reciprocal Estimate */
5711 case 25: /* Floating Multiply */
5712 case 26: /* Floating Reciprocal Square Root Estimate */
5713 case 28: /* Floating Multiply-Subtract */
5714 case 29: /* Floating Multiply-Add */
5715 case 30: /* Floating Negative Multiply-Subtract */
5716 case 31: /* Floating Negative Multiply-Add */
5717 record_full_arch_list_add_reg (regcache
,
5718 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5720 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5721 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5724 case 23: /* Floating Select */
5725 record_full_arch_list_add_reg (regcache
,
5726 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5728 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5734 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5735 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5737 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5738 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5744 case 2: /* DFP Add Quad */
5745 case 3: /* DFP Quantize Quad */
5746 case 34: /* DFP Multiply Quad */
5747 case 35: /* DFP Reround Quad */
5748 case 67: /* DFP Quantize Immediate Quad */
5749 case 99: /* DFP Round To FP Integer With Inexact Quad */
5750 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5751 case 258: /* DFP Convert To DFP Extended Quad */
5752 case 514: /* DFP Subtract Quad */
5753 case 546: /* DFP Divide Quad */
5754 case 770: /* DFP Round To DFP Long Quad */
5755 case 802: /* DFP Convert From Fixed Quad */
5756 case 834: /* DFP Encode BCD To DPD Quad */
5758 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5759 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5760 record_full_arch_list_add_reg (regcache
, tmp
);
5761 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5762 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5765 case 130: /* DFP Compare Ordered Quad */
5766 case 162: /* DFP Test Exponent Quad */
5767 case 194: /* DFP Test Data Class Quad */
5768 case 226: /* DFP Test Data Group Quad */
5769 case 642: /* DFP Compare Unordered Quad */
5770 case 674: /* DFP Test Significance Quad */
5771 case 675: /* DFP Test Significance Immediate Quad */
5772 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5773 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5776 case 66: /* DFP Shift Significand Left Immediate Quad */
5777 case 98: /* DFP Shift Significand Right Immediate Quad */
5778 case 322: /* DFP Decode DPD To BCD Quad */
5779 case 866: /* DFP Insert Biased Exponent Quad */
5780 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5781 record_full_arch_list_add_reg (regcache
, tmp
);
5782 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5784 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5787 case 290: /* DFP Convert To Fixed Quad */
5788 record_full_arch_list_add_reg (regcache
,
5789 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5791 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5792 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5795 case 354: /* DFP Extract Biased Exponent Quad */
5796 record_full_arch_list_add_reg (regcache
,
5797 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5799 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5802 case 12: /* Floating Round to Single-Precision */
5803 case 14: /* Floating Convert To Integer Word */
5804 case 15: /* Floating Convert To Integer Word
5805 with round toward Zero */
5806 case 142: /* Floating Convert To Integer Word Unsigned */
5807 case 143: /* Floating Convert To Integer Word Unsigned
5808 with round toward Zero */
5809 case 392: /* Floating Round to Integer Nearest */
5810 case 424: /* Floating Round to Integer Toward Zero */
5811 case 456: /* Floating Round to Integer Plus */
5812 case 488: /* Floating Round to Integer Minus */
5813 case 814: /* Floating Convert To Integer Doubleword */
5814 case 815: /* Floating Convert To Integer Doubleword
5815 with round toward Zero */
5816 case 846: /* Floating Convert From Integer Doubleword */
5817 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5818 case 943: /* Floating Convert To Integer Doubleword Unsigned
5819 with round toward Zero */
5820 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5821 record_full_arch_list_add_reg (regcache
,
5822 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5824 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5825 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5829 switch (PPC_FIELD (insn
, 11, 5))
5831 case 1: /* Move From FPSCR & Clear Enables */
5832 case 20: /* Move From FPSCR Control & set DRN */
5833 case 21: /* Move From FPSCR Control & set DRN Immediate */
5834 case 22: /* Move From FPSCR Control & set RN */
5835 case 23: /* Move From FPSCR Control & set RN Immediate */
5836 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5838 case 0: /* Move From FPSCR */
5839 case 24: /* Move From FPSCR Lightweight */
5840 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5841 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5842 record_full_arch_list_add_reg (regcache
,
5843 tdep
->ppc_fp0_regnum
5849 case 8: /* Floating Copy Sign */
5850 case 40: /* Floating Negate */
5851 case 72: /* Floating Move Register */
5852 case 136: /* Floating Negative Absolute Value */
5853 case 264: /* Floating Absolute Value */
5854 record_full_arch_list_add_reg (regcache
,
5855 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5857 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5860 case 838: /* Floating Merge Odd Word */
5861 case 966: /* Floating Merge Even Word */
5862 record_full_arch_list_add_reg (regcache
,
5863 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5866 case 38: /* Move To FPSCR Bit 1 */
5867 case 70: /* Move To FPSCR Bit 0 */
5868 case 134: /* Move To FPSCR Field Immediate */
5869 case 711: /* Move To FPSCR Fields */
5871 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5872 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5875 case 0: /* Floating Compare Unordered */
5876 case 32: /* Floating Compare Ordered */
5877 case 64: /* Move to Condition Register from FPSCR */
5878 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5879 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5880 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5881 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5882 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5884 case 128: /* Floating Test for software Divide */
5885 case 160: /* Floating Test for software Square Root */
5886 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5889 case 4: /* VSX Scalar Add Quad-Precision */
5890 case 36: /* VSX Scalar Multiply Quad-Precision */
5891 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5892 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5893 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5894 case 484: /* VSX Scalar Negative Multiply-Subtract
5896 case 516: /* VSX Scalar Subtract Quad-Precision */
5897 case 548: /* VSX Scalar Divide Quad-Precision */
5898 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5900 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5901 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5902 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5906 switch (PPC_FIELD (insn
, 11, 5))
5908 case 27: /* VSX Scalar Square Root Quad-Precision */
5909 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5911 case 0: /* VSX Scalar Absolute Quad-Precision */
5912 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5913 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5914 case 16: /* VSX Scalar Negate Quad-Precision */
5915 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5916 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5922 switch (PPC_FIELD (insn
, 11, 5))
5924 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5925 to Unsigned Word format */
5926 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5927 Quad-Precision format */
5928 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5929 to Signed Word format */
5930 case 10: /* VSX Scalar Convert Signed Doubleword format to
5931 Quad-Precision format */
5932 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5933 to Unsigned Doubleword format */
5934 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5935 Double-Precision format */
5936 case 22: /* VSX Scalar Convert Double-Precision format to
5937 Quad-Precision format */
5938 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5939 to Signed Doubleword format */
5940 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5941 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5946 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5947 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5951 /* Parse the current instruction and record the values of the registers and
5952 memory that will be changed in current instruction to "record_arch_list".
5953 Return -1 if something wrong. */
5956 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5959 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5960 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5964 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5965 op6
= PPC_OP6 (insn
);
5969 case 2: /* Trap Doubleword Immediate */
5970 case 3: /* Trap Word Immediate */
5975 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5979 case 17: /* System call */
5980 if (PPC_LEV (insn
) != 0)
5983 if (tdep
->ppc_syscall_record
!= NULL
)
5985 if (tdep
->ppc_syscall_record (regcache
) != 0)
5990 printf_unfiltered (_("no syscall record support\n"));
5995 case 7: /* Multiply Low Immediate */
5996 record_full_arch_list_add_reg (regcache
,
5997 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6000 case 8: /* Subtract From Immediate Carrying */
6001 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
6002 record_full_arch_list_add_reg (regcache
,
6003 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6006 case 10: /* Compare Logical Immediate */
6007 case 11: /* Compare Immediate */
6008 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6011 case 13: /* Add Immediate Carrying and Record */
6012 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6014 case 12: /* Add Immediate Carrying */
6015 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
6017 case 14: /* Add Immediate */
6018 case 15: /* Add Immediate Shifted */
6019 record_full_arch_list_add_reg (regcache
,
6020 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6023 case 16: /* Branch Conditional */
6024 if ((PPC_BO (insn
) & 0x4) == 0)
6025 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
6027 case 18: /* Branch */
6029 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
6033 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
6037 case 20: /* Rotate Left Word Immediate then Mask Insert */
6038 case 21: /* Rotate Left Word Immediate then AND with Mask */
6039 case 23: /* Rotate Left Word then AND with Mask */
6040 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
6041 /* Rotate Left Doubleword Immediate then Clear Right */
6042 /* Rotate Left Doubleword Immediate then Clear */
6043 /* Rotate Left Doubleword then Clear Left */
6044 /* Rotate Left Doubleword then Clear Right */
6045 /* Rotate Left Doubleword Immediate then Mask Insert */
6047 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6048 record_full_arch_list_add_reg (regcache
,
6049 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6052 case 28: /* AND Immediate */
6053 case 29: /* AND Immediate Shifted */
6054 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6056 case 24: /* OR Immediate */
6057 case 25: /* OR Immediate Shifted */
6058 case 26: /* XOR Immediate */
6059 case 27: /* XOR Immediate Shifted */
6060 record_full_arch_list_add_reg (regcache
,
6061 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6065 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
6069 case 33: /* Load Word and Zero with Update */
6070 case 35: /* Load Byte and Zero with Update */
6071 case 41: /* Load Halfword and Zero with Update */
6072 case 43: /* Load Halfword Algebraic with Update */
6073 record_full_arch_list_add_reg (regcache
,
6074 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6076 case 32: /* Load Word and Zero */
6077 case 34: /* Load Byte and Zero */
6078 case 40: /* Load Halfword and Zero */
6079 case 42: /* Load Halfword Algebraic */
6080 record_full_arch_list_add_reg (regcache
,
6081 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6084 case 46: /* Load Multiple Word */
6085 for (i
= PPC_RT (insn
); i
< 32; i
++)
6086 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
6089 case 56: /* Load Quadword */
6090 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
6091 record_full_arch_list_add_reg (regcache
, tmp
);
6092 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6095 case 49: /* Load Floating-Point Single with Update */
6096 case 51: /* Load Floating-Point Double with Update */
6097 record_full_arch_list_add_reg (regcache
,
6098 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6100 case 48: /* Load Floating-Point Single */
6101 case 50: /* Load Floating-Point Double */
6102 record_full_arch_list_add_reg (regcache
,
6103 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6106 case 47: /* Store Multiple Word */
6110 if (PPC_RA (insn
) != 0)
6111 regcache_raw_read_unsigned (regcache
,
6112 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6115 iaddr
+= PPC_D (insn
);
6116 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
6120 case 37: /* Store Word with Update */
6121 case 39: /* Store Byte with Update */
6122 case 45: /* Store Halfword with Update */
6123 case 53: /* Store Floating-Point Single with Update */
6124 case 55: /* Store Floating-Point Double with Update */
6125 record_full_arch_list_add_reg (regcache
,
6126 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6128 case 36: /* Store Word */
6129 case 38: /* Store Byte */
6130 case 44: /* Store Halfword */
6131 case 52: /* Store Floating-Point Single */
6132 case 54: /* Store Floating-Point Double */
6137 if (PPC_RA (insn
) != 0)
6138 regcache_raw_read_unsigned (regcache
,
6139 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6141 iaddr
+= PPC_D (insn
);
6143 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
6145 else if (op6
== 54 || op6
== 55)
6147 else if (op6
== 44 || op6
== 45)
6149 else if (op6
== 38 || op6
== 39)
6154 record_full_arch_list_add_mem (iaddr
, size
);
6161 case 0: /* Load Floating-Point Double Pair */
6162 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6163 record_full_arch_list_add_reg (regcache
, tmp
);
6164 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6166 case 2: /* Load VSX Scalar Doubleword */
6167 case 3: /* Load VSX Scalar Single */
6168 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6175 case 58: /* Load Doubleword */
6176 /* Load Doubleword with Update */
6177 /* Load Word Algebraic */
6178 if (PPC_FIELD (insn
, 30, 2) > 2)
6181 record_full_arch_list_add_reg (regcache
,
6182 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6183 if (PPC_BIT (insn
, 31))
6184 record_full_arch_list_add_reg (regcache
,
6185 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6189 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6194 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6199 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6203 case 62: /* Store Doubleword */
6204 /* Store Doubleword with Update */
6205 /* Store Quadword with Update */
6209 int sub2
= PPC_FIELD (insn
, 30, 2);
6214 if (PPC_RA (insn
) != 0)
6215 regcache_raw_read_unsigned (regcache
,
6216 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6219 size
= (sub2
== 2) ? 16 : 8;
6221 iaddr
+= PPC_DS (insn
) << 2;
6222 record_full_arch_list_add_mem (iaddr
, size
);
6224 if (op6
== 62 && sub2
== 1)
6225 record_full_arch_list_add_reg (regcache
,
6226 tdep
->ppc_gp0_regnum
+
6233 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6239 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6240 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6244 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6246 if (record_full_arch_list_add_end ())
6251 /* Initialize the current architecture based on INFO. If possible, re-use an
6252 architecture from ARCHES, which is a list of architectures already created
6253 during this debugging session.
6255 Called e.g. at program startup, when reading a core file, and when reading
6258 static struct gdbarch
*
6259 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6261 struct gdbarch
*gdbarch
;
6262 struct gdbarch_tdep
*tdep
;
6263 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6264 enum bfd_architecture arch
;
6267 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6269 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6270 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6271 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6272 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6273 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6274 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6275 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6276 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6277 int have_htm_tar
= 0;
6278 int tdesc_wordsize
= -1;
6279 const struct target_desc
*tdesc
= info
.target_desc
;
6280 tdesc_arch_data_up tdesc_data
;
6281 int num_pseudoregs
= 0;
6284 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6285 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6287 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6288 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6290 /* Check word size. If INFO is from a binary file, infer it from
6291 that, else choose a likely default. */
6292 if (from_xcoff_exec
)
6294 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6299 else if (from_elf_exec
)
6301 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6306 else if (tdesc_has_registers (tdesc
))
6310 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6311 wordsize
= (info
.bfd_arch_info
->bits_per_word
6312 / info
.bfd_arch_info
->bits_per_byte
);
6317 /* Get the architecture and machine from the BFD. */
6318 arch
= info
.bfd_arch_info
->arch
;
6319 mach
= info
.bfd_arch_info
->mach
;
6321 /* For e500 executables, the apuinfo section is of help here. Such
6322 section contains the identifier and revision number of each
6323 Application-specific Processing Unit that is present on the
6324 chip. The content of the section is determined by the assembler
6325 which looks at each instruction and determines which unit (and
6326 which version of it) can execute it. Grovel through the section
6327 looking for relevant e500 APUs. */
6329 if (bfd_uses_spe_extensions (info
.abfd
))
6331 arch
= info
.bfd_arch_info
->arch
;
6332 mach
= bfd_mach_ppc_e500
;
6333 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6334 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6337 /* Find a default target description which describes our register
6338 layout, if we do not already have one. */
6339 if (! tdesc_has_registers (tdesc
))
6341 const struct ppc_variant
*v
;
6343 /* Choose variant. */
6344 v
= find_variant_by_arch (arch
, mach
);
6351 gdb_assert (tdesc_has_registers (tdesc
));
6353 /* Check any target description for validity. */
6354 if (tdesc_has_registers (tdesc
))
6356 static const char *const gprs
[] = {
6357 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6358 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6359 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6360 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6362 const struct tdesc_feature
*feature
;
6364 static const char *const msr_names
[] = { "msr", "ps" };
6365 static const char *const cr_names
[] = { "cr", "cnd" };
6366 static const char *const ctr_names
[] = { "ctr", "cnt" };
6368 feature
= tdesc_find_feature (tdesc
,
6369 "org.gnu.gdb.power.core");
6370 if (feature
== NULL
)
6373 tdesc_data
= tdesc_data_alloc ();
6376 for (i
= 0; i
< ppc_num_gprs
; i
++)
6377 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6379 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6380 PPC_PC_REGNUM
, "pc");
6381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6382 PPC_LR_REGNUM
, "lr");
6383 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6384 PPC_XER_REGNUM
, "xer");
6386 /* Allow alternate names for these registers, to accomodate GDB's
6388 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6389 PPC_MSR_REGNUM
, msr_names
);
6390 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6391 PPC_CR_REGNUM
, cr_names
);
6392 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6393 PPC_CTR_REGNUM
, ctr_names
);
6398 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6399 PPC_MQ_REGNUM
, "mq");
6401 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6403 wordsize
= tdesc_wordsize
;
6405 feature
= tdesc_find_feature (tdesc
,
6406 "org.gnu.gdb.power.fpu");
6407 if (feature
!= NULL
)
6409 static const char *const fprs
[] = {
6410 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6411 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6412 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6413 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6416 for (i
= 0; i
< ppc_num_fprs
; i
++)
6417 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6418 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6419 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6420 PPC_FPSCR_REGNUM
, "fpscr");
6426 /* The fpscr register was expanded in isa 2.05 to 64 bits
6427 along with the addition of the decimal floating point
6429 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6435 feature
= tdesc_find_feature (tdesc
,
6436 "org.gnu.gdb.power.altivec");
6437 if (feature
!= NULL
)
6439 static const char *const vector_regs
[] = {
6440 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6441 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6442 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6443 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6447 for (i
= 0; i
< ppc_num_gprs
; i
++)
6448 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6451 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6452 PPC_VSCR_REGNUM
, "vscr");
6453 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6454 PPC_VRSAVE_REGNUM
, "vrsave");
6456 if (have_spe
|| !valid_p
)
6463 /* Check for POWER7 VSX registers support. */
6464 feature
= tdesc_find_feature (tdesc
,
6465 "org.gnu.gdb.power.vsx");
6467 if (feature
!= NULL
)
6469 static const char *const vsx_regs
[] = {
6470 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6471 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6472 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6473 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6474 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6480 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6481 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6482 PPC_VSR0_UPPER_REGNUM
+ i
,
6485 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6493 /* On machines supporting the SPE APU, the general-purpose registers
6494 are 64 bits long. There are SIMD vector instructions to treat them
6495 as pairs of floats, but the rest of the instruction set treats them
6496 as 32-bit registers, and only operates on their lower halves.
6498 In the GDB regcache, we treat their high and low halves as separate
6499 registers. The low halves we present as the general-purpose
6500 registers, and then we have pseudo-registers that stitch together
6501 the upper and lower halves and present them as pseudo-registers.
6503 Thus, the target description is expected to supply the upper
6504 halves separately. */
6506 feature
= tdesc_find_feature (tdesc
,
6507 "org.gnu.gdb.power.spe");
6508 if (feature
!= NULL
)
6510 static const char *const upper_spe
[] = {
6511 "ev0h", "ev1h", "ev2h", "ev3h",
6512 "ev4h", "ev5h", "ev6h", "ev7h",
6513 "ev8h", "ev9h", "ev10h", "ev11h",
6514 "ev12h", "ev13h", "ev14h", "ev15h",
6515 "ev16h", "ev17h", "ev18h", "ev19h",
6516 "ev20h", "ev21h", "ev22h", "ev23h",
6517 "ev24h", "ev25h", "ev26h", "ev27h",
6518 "ev28h", "ev29h", "ev30h", "ev31h"
6522 for (i
= 0; i
< ppc_num_gprs
; i
++)
6523 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6524 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6526 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6527 PPC_SPE_ACC_REGNUM
, "acc");
6528 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6529 PPC_SPE_FSCR_REGNUM
, "spefscr");
6531 if (have_mq
|| have_fpu
|| !valid_p
)
6538 /* Program Priority Register. */
6539 feature
= tdesc_find_feature (tdesc
,
6540 "org.gnu.gdb.power.ppr");
6541 if (feature
!= NULL
)
6544 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6545 PPC_PPR_REGNUM
, "ppr");
6554 /* Data Stream Control Register. */
6555 feature
= tdesc_find_feature (tdesc
,
6556 "org.gnu.gdb.power.dscr");
6557 if (feature
!= NULL
)
6560 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6561 PPC_DSCR_REGNUM
, "dscr");
6570 /* Target Address Register. */
6571 feature
= tdesc_find_feature (tdesc
,
6572 "org.gnu.gdb.power.tar");
6573 if (feature
!= NULL
)
6576 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6577 PPC_TAR_REGNUM
, "tar");
6586 /* Event-based Branching Registers. */
6587 feature
= tdesc_find_feature (tdesc
,
6588 "org.gnu.gdb.power.ebb");
6589 if (feature
!= NULL
)
6591 static const char *const ebb_regs
[] = {
6592 "bescr", "ebbhr", "ebbrr"
6596 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6597 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6598 PPC_BESCR_REGNUM
+ i
,
6607 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6609 feature
= tdesc_find_feature (tdesc
,
6610 "org.gnu.gdb.power.linux.pmu");
6611 if (feature
!= NULL
)
6615 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6618 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6621 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6624 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6627 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6638 /* Hardware Transactional Memory Registers. */
6639 feature
= tdesc_find_feature (tdesc
,
6640 "org.gnu.gdb.power.htm.spr");
6641 if (feature
!= NULL
)
6643 static const char *const tm_spr_regs
[] = {
6644 "tfhar", "texasr", "tfiar"
6648 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6649 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6650 PPC_TFHAR_REGNUM
+ i
,
6660 feature
= tdesc_find_feature (tdesc
,
6661 "org.gnu.gdb.power.htm.core");
6662 if (feature
!= NULL
)
6664 static const char *const cgprs
[] = {
6665 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6666 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6667 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6668 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6669 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6674 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6675 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6686 feature
= tdesc_find_feature (tdesc
,
6687 "org.gnu.gdb.power.htm.fpu");
6688 if (feature
!= NULL
)
6692 static const char *const cfprs
[] = {
6693 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6694 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6695 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6696 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6697 "cf30", "cf31", "cfpscr"
6700 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6701 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6712 feature
= tdesc_find_feature (tdesc
,
6713 "org.gnu.gdb.power.htm.altivec");
6714 if (feature
!= NULL
)
6718 static const char *const cvmx
[] = {
6719 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6720 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6721 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6722 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6723 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6727 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6728 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6729 PPC_CVR0_REGNUM
+ i
,
6734 have_htm_altivec
= 1;
6737 have_htm_altivec
= 0;
6739 feature
= tdesc_find_feature (tdesc
,
6740 "org.gnu.gdb.power.htm.vsx");
6741 if (feature
!= NULL
)
6745 static const char *const cvsx
[] = {
6746 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6747 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6748 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6749 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6750 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6754 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6755 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6756 (PPC_CVSR0_UPPER_REGNUM
6760 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6767 feature
= tdesc_find_feature (tdesc
,
6768 "org.gnu.gdb.power.htm.ppr");
6769 if (feature
!= NULL
)
6771 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6772 PPC_CPPR_REGNUM
, "cppr");
6781 feature
= tdesc_find_feature (tdesc
,
6782 "org.gnu.gdb.power.htm.dscr");
6783 if (feature
!= NULL
)
6785 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6786 PPC_CDSCR_REGNUM
, "cdscr");
6795 feature
= tdesc_find_feature (tdesc
,
6796 "org.gnu.gdb.power.htm.tar");
6797 if (feature
!= NULL
)
6799 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6800 PPC_CTAR_REGNUM
, "ctar");
6810 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6811 complain for a 32-bit binary on a 64-bit target; we do not yet
6812 support that. For instance, the 32-bit ABI routines expect
6815 As long as there isn't an explicit target description, we'll
6816 choose one based on the BFD architecture and get a word size
6817 matching the binary (probably powerpc:common or
6818 powerpc:common64). So there is only trouble if a 64-bit target
6819 supplies a 64-bit description while debugging a 32-bit
6821 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6827 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6830 elf_abi
= POWERPC_ELF_V1
;
6833 elf_abi
= POWERPC_ELF_V2
;
6840 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6842 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6843 Tag_GNU_Power_ABI_FP
) & 3)
6846 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6849 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6856 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6858 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6859 Tag_GNU_Power_ABI_FP
) >> 2)
6862 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6865 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6872 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6874 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6875 Tag_GNU_Power_ABI_Vector
))
6878 vector_abi
= POWERPC_VEC_GENERIC
;
6881 vector_abi
= POWERPC_VEC_ALTIVEC
;
6884 vector_abi
= POWERPC_VEC_SPE
;
6892 /* At this point, the only supported ELF-based 64-bit little-endian
6893 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6894 default. All other supported ELF-based operating systems use the
6895 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6896 e.g. because we run a legacy binary, or have attached to a process
6897 and have not found any associated binary file, set the default
6898 according to this heuristic. */
6899 if (elf_abi
== POWERPC_ELF_AUTO
)
6901 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6902 elf_abi
= POWERPC_ELF_V2
;
6904 elf_abi
= POWERPC_ELF_V1
;
6907 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6909 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6912 soft_float
= !have_fpu
;
6914 /* If we have a hard float binary or setting but no floating point
6915 registers, downgrade to soft float anyway. We're still somewhat
6916 useful in this scenario. */
6917 if (!soft_float
&& !have_fpu
)
6920 /* Similarly for vector registers. */
6921 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6922 vector_abi
= POWERPC_VEC_GENERIC
;
6924 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6925 vector_abi
= POWERPC_VEC_GENERIC
;
6927 if (vector_abi
== POWERPC_VEC_AUTO
)
6930 vector_abi
= POWERPC_VEC_ALTIVEC
;
6932 vector_abi
= POWERPC_VEC_SPE
;
6934 vector_abi
= POWERPC_VEC_GENERIC
;
6937 /* Do not limit the vector ABI based on available hardware, since we
6938 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6940 /* Find a candidate among extant architectures. */
6941 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6943 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6945 /* Word size in the various PowerPC bfd_arch_info structs isn't
6946 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6947 separate word size check. */
6948 tdep
= gdbarch_tdep (arches
->gdbarch
);
6949 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6951 if (tdep
&& tdep
->soft_float
!= soft_float
)
6953 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6955 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6957 if (tdep
&& tdep
->wordsize
== wordsize
)
6958 return arches
->gdbarch
;
6961 /* None found, create a new architecture from INFO, whose bfd_arch_info
6962 validity depends on the source:
6963 - executable useless
6964 - rs6000_host_arch() good
6966 - "set arch" trust blindly
6967 - GDB startup useless but harmless */
6969 tdep
= XCNEW (struct gdbarch_tdep
);
6970 tdep
->wordsize
= wordsize
;
6971 tdep
->elf_abi
= elf_abi
;
6972 tdep
->soft_float
= soft_float
;
6973 tdep
->long_double_abi
= long_double_abi
;
6974 tdep
->vector_abi
= vector_abi
;
6976 gdbarch
= gdbarch_alloc (&info
, tdep
);
6978 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6979 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6980 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6981 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6982 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6983 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6984 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6985 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6987 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6988 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6989 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6990 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6991 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6992 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6993 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6994 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6995 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6996 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6997 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
6998 tdep
->have_ebb
= have_ebb
;
7000 /* If additional pmu registers are added, care must be taken when
7001 setting new fields in the tdep below, to maintain compatibility
7002 with features that only provide some of the registers. Currently
7003 gdb access to the pmu registers is only supported in linux, and
7004 linux only provides a subset of the pmu registers defined in the
7007 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
7008 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
7009 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
7010 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
7011 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
7013 tdep
->have_htm_spr
= have_htm_spr
;
7014 tdep
->have_htm_core
= have_htm_core
;
7015 tdep
->have_htm_fpu
= have_htm_fpu
;
7016 tdep
->have_htm_altivec
= have_htm_altivec
;
7017 tdep
->have_htm_vsx
= have_htm_vsx
;
7018 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
7019 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
7020 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
7022 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
7023 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
7024 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
7025 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
7027 /* The XML specification for PowerPC sensibly calls the MSR "msr".
7028 GDB traditionally called it "ps", though, so let GDB add an
7030 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
7033 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
7035 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
7037 /* Set lr_frame_offset. */
7039 tdep
->lr_frame_offset
= 16;
7041 tdep
->lr_frame_offset
= 4;
7043 if (have_spe
|| have_dfp
|| have_altivec
7044 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
7046 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
7047 set_gdbarch_pseudo_register_write (gdbarch
,
7048 rs6000_pseudo_register_write
);
7049 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
7050 rs6000_ax_pseudo_register_collect
);
7053 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
7055 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
7057 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
7060 num_pseudoregs
+= 32;
7062 num_pseudoregs
+= 16;
7064 num_pseudoregs
+= 32;
7066 /* Include both VSX and Extended FP registers. */
7067 num_pseudoregs
+= 96;
7069 num_pseudoregs
+= 16;
7070 /* Include both checkpointed VSX and EFP registers. */
7072 num_pseudoregs
+= 64 + 32;
7074 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
7076 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7077 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
7078 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7079 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7080 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7081 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7082 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7083 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
7084 set_gdbarch_char_signed (gdbarch
, 0);
7086 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
7089 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
7091 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
7092 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
7093 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
7095 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
7096 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
7099 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
7100 else if (wordsize
== 8)
7101 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
7103 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
7104 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
7105 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
7107 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7109 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
7110 rs6000_breakpoint::kind_from_pc
);
7111 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
7112 rs6000_breakpoint::bp_from_kind
);
7114 /* The value of symbols of type N_SO and N_FUN maybe null when
7116 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
7118 /* Handles single stepping of atomic sequences. */
7119 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
7121 /* Not sure on this. FIXMEmgo */
7122 set_gdbarch_frame_args_skip (gdbarch
, 8);
7124 /* Helpers for function argument information. */
7125 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
7128 set_gdbarch_in_solib_return_trampoline
7129 (gdbarch
, rs6000_in_solib_return_trampoline
);
7130 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
7132 /* Hook in the DWARF CFI frame unwinder. */
7133 dwarf2_append_unwinders (gdbarch
);
7134 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
7136 /* Frame handling. */
7137 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
7139 /* Setup displaced stepping. */
7140 set_gdbarch_displaced_step_copy_insn (gdbarch
,
7141 ppc_displaced_step_copy_insn
);
7142 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
7143 ppc_displaced_step_hw_singlestep
);
7144 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
7145 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
7146 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
7147 set_gdbarch_displaced_step_restore_all_in_ptid
7148 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
7150 set_gdbarch_max_insn_length (gdbarch
, 2 * PPC_INSN_SIZE
);
7152 /* Hook in ABI-specific overrides, if they have been registered. */
7153 info
.target_desc
= tdesc
;
7154 info
.tdesc_data
= tdesc_data
.get ();
7155 gdbarch_init_osabi (info
, gdbarch
);
7159 case GDB_OSABI_LINUX
:
7160 case GDB_OSABI_NETBSD
:
7161 case GDB_OSABI_UNKNOWN
:
7162 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7163 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7164 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7167 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7169 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7170 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7171 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7174 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7175 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7176 rs6000_pseudo_register_reggroup_p
);
7177 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
7179 /* Override the normal target description method to make the SPE upper
7180 halves anonymous. */
7181 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7183 /* Choose register numbers for all supported pseudo-registers. */
7184 tdep
->ppc_ev0_regnum
= -1;
7185 tdep
->ppc_dl0_regnum
= -1;
7186 tdep
->ppc_v0_alias_regnum
= -1;
7187 tdep
->ppc_vsr0_regnum
= -1;
7188 tdep
->ppc_efpr0_regnum
= -1;
7189 tdep
->ppc_cdl0_regnum
= -1;
7190 tdep
->ppc_cvsr0_regnum
= -1;
7191 tdep
->ppc_cefpr0_regnum
= -1;
7193 cur_reg
= gdbarch_num_regs (gdbarch
);
7197 tdep
->ppc_ev0_regnum
= cur_reg
;
7202 tdep
->ppc_dl0_regnum
= cur_reg
;
7207 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7212 tdep
->ppc_vsr0_regnum
= cur_reg
;
7214 tdep
->ppc_efpr0_regnum
= cur_reg
;
7219 tdep
->ppc_cdl0_regnum
= cur_reg
;
7224 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7226 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7230 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7232 /* Register the ravenscar_arch_ops. */
7233 if (mach
== bfd_mach_ppc_e500
)
7234 register_e500_ravenscar_ops (gdbarch
);
7236 register_ppc_ravenscar_ops (gdbarch
);
7238 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7239 set_gdbarch_valid_disassembler_options (gdbarch
,
7240 disassembler_options_powerpc ());
7246 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7253 /* FIXME: Dump gdbarch_tdep. */
7257 powerpc_set_soft_float (const char *args
, int from_tty
,
7258 struct cmd_list_element
*c
)
7260 struct gdbarch_info info
;
7262 /* Update the architecture. */
7263 gdbarch_info_init (&info
);
7264 if (!gdbarch_update_p (info
))
7265 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7269 powerpc_set_vector_abi (const char *args
, int from_tty
,
7270 struct cmd_list_element
*c
)
7272 struct gdbarch_info info
;
7275 for (vector_abi
= POWERPC_VEC_AUTO
;
7276 vector_abi
!= POWERPC_VEC_LAST
;
7278 if (strcmp (powerpc_vector_abi_string
,
7279 powerpc_vector_strings
[vector_abi
]) == 0)
7281 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7285 if (vector_abi
== POWERPC_VEC_LAST
)
7286 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7287 powerpc_vector_abi_string
);
7289 /* Update the architecture. */
7290 gdbarch_info_init (&info
);
7291 if (!gdbarch_update_p (info
))
7292 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7295 /* Show the current setting of the exact watchpoints flag. */
7298 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7299 struct cmd_list_element
*c
,
7302 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7305 /* Read a PPC instruction from memory. */
7308 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7310 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7311 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7313 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7316 /* Return non-zero if the instructions at PC match the series
7317 described in PATTERN, or zero otherwise. PATTERN is an array of
7318 'struct ppc_insn_pattern' objects, terminated by an entry whose
7321 When the match is successful, fill INSNS[i] with what PATTERN[i]
7322 matched. If PATTERN[i] is optional, and the instruction wasn't
7323 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7324 INSNS should have as many elements as PATTERN, minus the terminator.
7325 Note that, if PATTERN contains optional instructions which aren't
7326 present in memory, then INSNS will have holes, so INSNS[i] isn't
7327 necessarily the i'th instruction in memory. */
7330 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7331 const struct ppc_insn_pattern
*pattern
,
7332 unsigned int *insns
)
7337 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7340 insn
= read_insn (frame
, pc
);
7342 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7348 else if (!pattern
[i
].optional
)
7355 /* Return the 'd' field of the d-form instruction INSN, properly
7359 ppc_insn_d_field (unsigned int insn
)
7361 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7364 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7365 zero bits concatenated at the right, and properly
7369 ppc_insn_ds_field (unsigned int insn
)
7371 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7375 ppc_insn_prefix_dform (unsigned int insn1
, unsigned int insn2
)
7377 /* result is 34-bits */
7378 return (CORE_ADDR
) ((((insn1
& 0x3ffff) ^ 0x20000) - 0x20000) << 16)
7379 | (CORE_ADDR
)(insn2
& 0xffff);
7382 /* Initialization code. */
7384 void _initialize_rs6000_tdep ();
7386 _initialize_rs6000_tdep ()
7388 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7389 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7391 /* Initialize the standard target descriptions. */
7392 initialize_tdesc_powerpc_32 ();
7393 initialize_tdesc_powerpc_altivec32 ();
7394 initialize_tdesc_powerpc_vsx32 ();
7395 initialize_tdesc_powerpc_403 ();
7396 initialize_tdesc_powerpc_403gc ();
7397 initialize_tdesc_powerpc_405 ();
7398 initialize_tdesc_powerpc_505 ();
7399 initialize_tdesc_powerpc_601 ();
7400 initialize_tdesc_powerpc_602 ();
7401 initialize_tdesc_powerpc_603 ();
7402 initialize_tdesc_powerpc_604 ();
7403 initialize_tdesc_powerpc_64 ();
7404 initialize_tdesc_powerpc_altivec64 ();
7405 initialize_tdesc_powerpc_vsx64 ();
7406 initialize_tdesc_powerpc_7400 ();
7407 initialize_tdesc_powerpc_750 ();
7408 initialize_tdesc_powerpc_860 ();
7409 initialize_tdesc_powerpc_e500 ();
7410 initialize_tdesc_rs6000 ();
7412 /* Add root prefix command for all "set powerpc"/"show powerpc"
7414 add_basic_prefix_cmd ("powerpc", no_class
,
7415 _("Various PowerPC-specific commands."),
7416 &setpowerpccmdlist
, 0, &setlist
);
7418 add_show_prefix_cmd ("powerpc", no_class
,
7419 _("Various PowerPC-specific commands."),
7420 &showpowerpccmdlist
, 0, &showlist
);
7422 /* Add a command to allow the user to force the ABI. */
7423 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7424 &powerpc_soft_float_global
,
7425 _("Set whether to use a soft-float ABI."),
7426 _("Show whether to use a soft-float ABI."),
7428 powerpc_set_soft_float
, NULL
,
7429 &setpowerpccmdlist
, &showpowerpccmdlist
);
7431 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7432 &powerpc_vector_abi_string
,
7433 _("Set the vector ABI."),
7434 _("Show the vector ABI."),
7435 NULL
, powerpc_set_vector_abi
, NULL
,
7436 &setpowerpccmdlist
, &showpowerpccmdlist
);
7438 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7439 &target_exact_watchpoints
,
7441 Set whether to use just one debug register for watchpoints on scalars."),
7443 Show whether to use just one debug register for watchpoints on scalars."),
7445 If true, GDB will use only one debug register when watching a variable of\n\
7446 scalar type, thus assuming that the variable is accessed through the address\n\
7447 of its first byte."),
7448 NULL
, show_powerpc_exact_watchpoints
,
7449 &setpowerpccmdlist
, &showpowerpccmdlist
);