1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 static const registry
<inferior
>::key
<ppc_inferior_data
> ppc_inferior_data_key
;
160 /* Get the per-inferior PowerPC data for INF. */
163 get_ppc_per_inferior (inferior
*inf
)
165 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
167 if (per_inf
== nullptr)
168 per_inf
= ppc_inferior_data_key
.emplace (inf
);
173 /* To be used by skip_prologue. */
175 struct rs6000_framedata
177 int offset
; /* total size of frame --- the distance
178 by which we decrement sp to allocate
180 int saved_gpr
; /* smallest # of saved gpr */
181 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
182 int saved_fpr
; /* smallest # of saved fpr */
183 int saved_vr
; /* smallest # of saved vr */
184 int saved_ev
; /* smallest # of saved ev */
185 int alloca_reg
; /* alloca register number (frame ptr) */
186 char frameless
; /* true if frameless functions. */
187 char nosavedpc
; /* true if pc not saved. */
188 char used_bl
; /* true if link register clobbered */
189 int gpr_offset
; /* offset of saved gprs from prev sp */
190 int fpr_offset
; /* offset of saved fprs from prev sp */
191 int vr_offset
; /* offset of saved vrs from prev sp */
192 int ev_offset
; /* offset of saved evs from prev sp */
193 int lr_offset
; /* offset of saved lr */
194 int lr_register
; /* register of saved lr, if trustworthy */
195 int cr_offset
; /* offset of saved cr */
196 int vrsave_offset
; /* offset of saved vrsave register */
200 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
202 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
204 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
205 if (tdep
->ppc_vsr0_regnum
< 0)
208 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
209 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
212 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
214 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
216 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
217 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
220 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
224 /* Return true if REGNO is an SPE register, false otherwise. */
226 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
228 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
230 /* Is it a reference to EV0 -- EV31, and do we have those? */
231 if (IS_SPE_PSEUDOREG (tdep
, regno
))
234 /* Is it a reference to one of the raw upper GPR halves? */
235 if (tdep
->ppc_ev0_upper_regnum
>= 0
236 && tdep
->ppc_ev0_upper_regnum
<= regno
237 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
240 /* Is it a reference to the 64-bit accumulator, and do we have that? */
241 if (tdep
->ppc_acc_regnum
>= 0
242 && tdep
->ppc_acc_regnum
== regno
)
245 /* Is it a reference to the SPE floating-point status and control register,
246 and do we have that? */
247 if (tdep
->ppc_spefscr_regnum
>= 0
248 && tdep
->ppc_spefscr_regnum
== regno
)
255 /* Return non-zero if the architecture described by GDBARCH has
256 floating-point registers (f0 --- f31 and fpscr). */
258 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
260 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
262 return (tdep
->ppc_fp0_regnum
>= 0
263 && tdep
->ppc_fpscr_regnum
>= 0);
266 /* Return non-zero if the architecture described by GDBARCH has
267 Altivec registers (vr0 --- vr31, vrsave and vscr). */
269 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
271 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
273 return (tdep
->ppc_vr0_regnum
>= 0
274 && tdep
->ppc_vrsave_regnum
>= 0);
277 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
280 This is a helper function for init_sim_regno_table, constructing
281 the table mapping GDB register numbers to sim register numbers; we
282 initialize every element in that table to -1 before we start
285 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
287 /* Make sure we don't try to assign any given GDB register a sim
288 register number more than once. */
289 gdb_assert (table
[gdb_regno
] == -1);
290 table
[gdb_regno
] = sim_regno
;
294 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
295 numbers to simulator register numbers, based on the values placed
296 in the ARCH->tdep->ppc_foo_regnum members. */
298 init_sim_regno_table (struct gdbarch
*arch
)
300 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (arch
);
301 int total_regs
= gdbarch_num_regs (arch
);
302 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
304 static const char *const segment_regs
[] = {
305 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
306 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
309 /* Presume that all registers not explicitly mentioned below are
310 unavailable from the sim. */
311 for (i
= 0; i
< total_regs
; i
++)
314 /* General-purpose registers. */
315 for (i
= 0; i
< ppc_num_gprs
; i
++)
316 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
318 /* Floating-point registers. */
319 if (tdep
->ppc_fp0_regnum
>= 0)
320 for (i
= 0; i
< ppc_num_fprs
; i
++)
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_fp0_regnum
+ i
,
323 sim_ppc_f0_regnum
+ i
);
324 if (tdep
->ppc_fpscr_regnum
>= 0)
325 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
327 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
328 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
329 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
331 /* Segment registers. */
332 for (i
= 0; i
< ppc_num_srs
; i
++)
336 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
338 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
341 /* Altivec registers. */
342 if (tdep
->ppc_vr0_regnum
>= 0)
344 for (i
= 0; i
< ppc_num_vrs
; i
++)
345 set_sim_regno (sim_regno
,
346 tdep
->ppc_vr0_regnum
+ i
,
347 sim_ppc_vr0_regnum
+ i
);
349 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
350 we can treat this more like the other cases. */
351 set_sim_regno (sim_regno
,
352 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
353 sim_ppc_vscr_regnum
);
355 /* vsave is a special-purpose register, so the code below handles it. */
357 /* SPE APU (E500) registers. */
358 if (tdep
->ppc_ev0_upper_regnum
>= 0)
359 for (i
= 0; i
< ppc_num_gprs
; i
++)
360 set_sim_regno (sim_regno
,
361 tdep
->ppc_ev0_upper_regnum
+ i
,
362 sim_ppc_rh0_regnum
+ i
);
363 if (tdep
->ppc_acc_regnum
>= 0)
364 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
365 /* spefscr is a special-purpose register, so the code below handles it. */
368 /* Now handle all special-purpose registers. Verify that they
369 haven't mistakenly been assigned numbers by any of the above
371 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
373 const char *spr_name
= sim_spr_register_name (i
);
376 if (spr_name
!= NULL
)
377 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
380 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
384 /* Drop the initialized array into place. */
385 tdep
->sim_regno
= sim_regno
;
389 /* Given a GDB register number REG, return the corresponding SIM
392 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
394 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
397 if (tdep
->sim_regno
== NULL
)
398 init_sim_regno_table (gdbarch
);
400 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
401 sim_regno
= tdep
->sim_regno
[reg
];
406 return LEGACY_SIM_REGNO_IGNORE
;
411 /* Register set support functions. */
413 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
414 Write the register to REGCACHE. */
417 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
418 const gdb_byte
*regs
, size_t offset
, int regsize
)
420 if (regnum
!= -1 && offset
!= -1)
424 struct gdbarch
*gdbarch
= regcache
->arch ();
425 int gdb_regsize
= register_size (gdbarch
, regnum
);
426 if (gdb_regsize
< regsize
427 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
428 offset
+= regsize
- gdb_regsize
;
430 regcache
->raw_supply (regnum
, regs
+ offset
);
434 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
435 in a field REGSIZE wide. Zero pad as necessary. */
438 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
439 gdb_byte
*regs
, size_t offset
, int regsize
)
441 if (regnum
!= -1 && offset
!= -1)
445 struct gdbarch
*gdbarch
= regcache
->arch ();
446 int gdb_regsize
= register_size (gdbarch
, regnum
);
447 if (gdb_regsize
< regsize
)
449 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
451 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
452 offset
+= regsize
- gdb_regsize
;
455 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
456 regsize
- gdb_regsize
);
459 regcache
->raw_collect (regnum
, regs
+ offset
);
464 ppc_greg_offset (struct gdbarch
*gdbarch
,
465 ppc_gdbarch_tdep
*tdep
,
466 const struct ppc_reg_offsets
*offsets
,
470 *regsize
= offsets
->gpr_size
;
471 if (regnum
>= tdep
->ppc_gp0_regnum
472 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
473 return (offsets
->r0_offset
474 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
476 if (regnum
== gdbarch_pc_regnum (gdbarch
))
477 return offsets
->pc_offset
;
479 if (regnum
== tdep
->ppc_ps_regnum
)
480 return offsets
->ps_offset
;
482 if (regnum
== tdep
->ppc_lr_regnum
)
483 return offsets
->lr_offset
;
485 if (regnum
== tdep
->ppc_ctr_regnum
)
486 return offsets
->ctr_offset
;
488 *regsize
= offsets
->xr_size
;
489 if (regnum
== tdep
->ppc_cr_regnum
)
490 return offsets
->cr_offset
;
492 if (regnum
== tdep
->ppc_xer_regnum
)
493 return offsets
->xer_offset
;
495 if (regnum
== tdep
->ppc_mq_regnum
)
496 return offsets
->mq_offset
;
502 ppc_fpreg_offset (ppc_gdbarch_tdep
*tdep
,
503 const struct ppc_reg_offsets
*offsets
,
506 if (regnum
>= tdep
->ppc_fp0_regnum
507 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
508 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
510 if (regnum
== tdep
->ppc_fpscr_regnum
)
511 return offsets
->fpscr_offset
;
516 /* Supply register REGNUM in the general-purpose register set REGSET
517 from the buffer specified by GREGS and LEN to register cache
518 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
521 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
522 int regnum
, const void *gregs
, size_t len
)
524 struct gdbarch
*gdbarch
= regcache
->arch ();
525 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
526 const struct ppc_reg_offsets
*offsets
527 = (const struct ppc_reg_offsets
*) regset
->regmap
;
534 int gpr_size
= offsets
->gpr_size
;
536 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
537 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
538 i
++, offset
+= gpr_size
)
539 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
542 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
543 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
544 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
545 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
546 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
548 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
549 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
550 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
551 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
553 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
554 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
556 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
562 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
563 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
566 /* Supply register REGNUM in the floating-point register set REGSET
567 from the buffer specified by FPREGS and LEN to register cache
568 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
571 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
572 int regnum
, const void *fpregs
, size_t len
)
574 struct gdbarch
*gdbarch
= regcache
->arch ();
575 const struct ppc_reg_offsets
*offsets
;
578 if (!ppc_floating_point_unit_p (gdbarch
))
581 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
582 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
587 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
588 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
590 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
592 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
593 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
594 offsets
->fpscr_size
);
598 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
599 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
600 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
603 /* Collect register REGNUM in the general-purpose register set
604 REGSET from register cache REGCACHE into the buffer specified by
605 GREGS and LEN. If REGNUM is -1, do this for all registers in
609 ppc_collect_gregset (const struct regset
*regset
,
610 const struct regcache
*regcache
,
611 int regnum
, void *gregs
, size_t len
)
613 struct gdbarch
*gdbarch
= regcache
->arch ();
614 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
615 const struct ppc_reg_offsets
*offsets
616 = (const struct ppc_reg_offsets
*) regset
->regmap
;
623 int gpr_size
= offsets
->gpr_size
;
625 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
626 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
627 i
++, offset
+= gpr_size
)
628 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
630 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
631 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
632 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
633 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
634 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
635 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
636 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
637 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
638 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
639 (gdb_byte
*) gregs
, offsets
->cr_offset
,
641 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
642 (gdb_byte
*) gregs
, offsets
->xer_offset
,
644 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
645 (gdb_byte
*) gregs
, offsets
->mq_offset
,
650 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
651 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
654 /* Collect register REGNUM in the floating-point register set
655 REGSET from register cache REGCACHE into the buffer specified by
656 FPREGS and LEN. If REGNUM is -1, do this for all registers in
660 ppc_collect_fpregset (const struct regset
*regset
,
661 const struct regcache
*regcache
,
662 int regnum
, void *fpregs
, size_t len
)
664 struct gdbarch
*gdbarch
= regcache
->arch ();
665 const struct ppc_reg_offsets
*offsets
;
668 if (!ppc_floating_point_unit_p (gdbarch
))
671 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
672 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
677 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
678 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
680 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
682 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
683 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
684 offsets
->fpscr_size
);
688 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
689 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
690 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
694 insn_changes_sp_or_jumps (unsigned long insn
)
696 int opcode
= (insn
>> 26) & 0x03f;
697 int sd
= (insn
>> 21) & 0x01f;
698 int a
= (insn
>> 16) & 0x01f;
699 int subcode
= (insn
>> 1) & 0x3ff;
701 /* Changes the stack pointer. */
703 /* NOTE: There are many ways to change the value of a given register.
704 The ways below are those used when the register is R1, the SP,
705 in a funtion's epilogue. */
707 if (opcode
== 31 && subcode
== 444 && a
== 1)
708 return 1; /* mr R1,Rn */
709 if (opcode
== 14 && sd
== 1)
710 return 1; /* addi R1,Rn,simm */
711 if (opcode
== 58 && sd
== 1)
712 return 1; /* ld R1,ds(Rn) */
714 /* Transfers control. */
720 if (opcode
== 19 && subcode
== 16)
722 if (opcode
== 19 && subcode
== 528)
723 return 1; /* bcctr */
728 /* Return true if we are in the function's epilogue, i.e. after the
729 instruction that destroyed the function's stack frame.
731 1) scan forward from the point of execution:
732 a) If you find an instruction that modifies the stack pointer
733 or transfers control (except a return), execution is not in
735 b) Stop scanning if you find a return instruction or reach the
736 end of the function or reach the hard limit for the size of
738 2) scan backward from the point of execution:
739 a) If you find an instruction that modifies the stack pointer,
740 execution *is* in an epilogue, return.
741 b) Stop scanning if you reach an instruction that transfers
742 control or the beginning of the function or reach the hard
743 limit for the size of an epilogue. */
746 rs6000_in_function_epilogue_frame_p (frame_info_ptr curfrm
,
747 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
749 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
750 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
751 bfd_byte insn_buf
[PPC_INSN_SIZE
];
752 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
755 /* Find the search limits based on function boundaries and hard limit. */
757 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
760 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
761 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
763 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
764 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
766 /* Scan forward until next 'blr'. */
768 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
770 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
771 {insn_buf
, PPC_INSN_SIZE
}))
773 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
774 if (insn
== 0x4e800020)
776 /* Assume a bctr is a tail call unless it points strictly within
778 if (insn
== 0x4e800420)
780 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
781 tdep
->ppc_ctr_regnum
);
782 if (ctr
> func_start
&& ctr
< func_end
)
787 if (insn_changes_sp_or_jumps (insn
))
791 /* Scan backward until adjustment to stack pointer (R1). */
793 for (scan_pc
= pc
- PPC_INSN_SIZE
;
794 scan_pc
>= epilogue_start
;
795 scan_pc
-= PPC_INSN_SIZE
)
797 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
798 {insn_buf
, PPC_INSN_SIZE
}))
800 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
801 if (insn_changes_sp_or_jumps (insn
))
808 /* Implement the stack_frame_destroyed_p gdbarch method. */
811 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
813 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
817 /* Get the ith function argument for the current function. */
819 rs6000_fetch_pointer_argument (frame_info_ptr frame
, int argi
,
822 return get_frame_register_unsigned (frame
, 3 + argi
);
825 /* Sequence of bytes for breakpoint instruction. */
827 constexpr gdb_byte big_breakpoint
[] = { 0x7f, 0xe0, 0x00, 0x08 };
828 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x00, 0xe0, 0x7f };
830 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
833 /* Instruction masks for displaced stepping. */
834 #define OP_MASK 0xfc000000
835 #define BP_MASK 0xFC0007FE
836 #define B_INSN 0x48000000
837 #define BC_INSN 0x40000000
838 #define BXL_INSN 0x4c000000
839 #define BP_INSN 0x7C000008
841 /* Instruction masks used during single-stepping of atomic
843 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
844 #define LWARX_INSTRUCTION 0x7c000028
845 #define LDARX_INSTRUCTION 0x7c0000A8
846 #define LBARX_INSTRUCTION 0x7c000068
847 #define LHARX_INSTRUCTION 0x7c0000e8
848 #define LQARX_INSTRUCTION 0x7c000228
849 #define STORE_CONDITIONAL_MASK 0xfc0007ff
850 #define STWCX_INSTRUCTION 0x7c00012d
851 #define STDCX_INSTRUCTION 0x7c0001ad
852 #define STBCX_INSTRUCTION 0x7c00056d
853 #define STHCX_INSTRUCTION 0x7c0005ad
854 #define STQCX_INSTRUCTION 0x7c00016d
856 /* Instruction masks for single-stepping of addpcis/lnia. */
857 #define ADDPCIS_INSN 0x4c000004
858 #define ADDPCIS_INSN_MASK 0xfc00003e
859 #define ADDPCIS_TARGET_REGISTER 0x03F00000
860 #define ADDPCIS_INSN_REGSHIFT 21
862 #define PNOP_MASK 0xfff3ffff
863 #define PNOP_INSN 0x07000000
864 #define R_MASK 0x00100000
865 #define R_ZERO 0x00000000
867 /* Check if insn is one of the Load And Reserve instructions used for atomic
869 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
870 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
871 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
872 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
873 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
874 /* Check if insn is one of the Store Conditional instructions used for atomic
876 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
877 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
878 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
879 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
880 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
882 typedef buf_displaced_step_copy_insn_closure
883 ppc_displaced_step_copy_insn_closure
;
885 /* We can't displaced step atomic sequences. */
887 static displaced_step_copy_insn_closure_up
888 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
889 CORE_ADDR from
, CORE_ADDR to
,
890 struct regcache
*regs
)
892 size_t len
= gdbarch_max_insn_length (gdbarch
);
893 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
894 (new ppc_displaced_step_copy_insn_closure (len
));
895 gdb_byte
*buf
= closure
->buf
.data ();
896 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 len
= target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY
, NULL
,
901 if ((ssize_t
) len
< PPC_INSN_SIZE
)
902 memory_error (TARGET_XFER_E_IO
, from
);
904 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
906 /* Check for PNOP and for prefixed instructions with R=0. Those
907 instructions are safe to displace. Prefixed instructions with R=1
908 will read/write data to/from locations relative to the current PC.
909 We would not be able to fixup after an instruction has written data
910 into a displaced location, so decline to displace those instructions. */
911 if ((insn
& OP_MASK
) == 1 << 26)
913 if (((insn
& PNOP_MASK
) != PNOP_INSN
)
914 && ((insn
& R_MASK
) != R_ZERO
))
916 displaced_debug_printf ("Not displacing prefixed instruction %08x at %s",
917 insn
, paddress (gdbarch
, from
));
922 /* Non-prefixed instructions.. */
924 /* Set the instruction length to 4 to match the actual instruction
929 /* Assume all atomic sequences start with a Load and Reserve instruction. */
930 if (IS_LOAD_AND_RESERVE_INSN (insn
))
932 displaced_debug_printf ("can't displaced step atomic sequence at %s",
933 paddress (gdbarch
, from
));
938 write_memory (to
, buf
, len
);
940 displaced_debug_printf ("copy %s->%s: %s",
941 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
942 displaced_step_dump_bytes (buf
, len
).c_str ());
944 /* This is a work around for a problem with g++ 4.8. */
945 return displaced_step_copy_insn_closure_up (closure
.release ());
948 /* Fix up the state of registers and memory after having single-stepped
949 a displaced instruction. */
951 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
952 struct displaced_step_copy_insn_closure
*closure_
,
953 CORE_ADDR from
, CORE_ADDR to
,
954 struct regcache
*regs
)
956 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
957 /* Our closure is a copy of the instruction. */
958 ppc_displaced_step_copy_insn_closure
*closure
959 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
960 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
961 PPC_INSN_SIZE
, byte_order
);
963 /* Offset for non PC-relative instructions. */
966 opcode
= insn
& OP_MASK
;
968 /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
969 if ((opcode
) == 1 << 26)
970 offset
= 2 * PPC_INSN_SIZE
;
972 offset
= PPC_INSN_SIZE
;
974 displaced_debug_printf ("(ppc) fixup (%s, %s)",
975 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
977 /* Handle the addpcis/lnia instruction. */
978 if ((insn
& ADDPCIS_INSN_MASK
) == ADDPCIS_INSN
)
980 LONGEST displaced_offset
;
981 ULONGEST current_val
;
982 /* Measure the displacement. */
983 displaced_offset
= from
- to
;
984 /* Identify the target register that was updated by the instruction. */
985 int regnum
= (insn
& ADDPCIS_TARGET_REGISTER
) >> ADDPCIS_INSN_REGSHIFT
;
986 /* Read and update the target value. */
987 regcache_cooked_read_unsigned (regs
, regnum
, ¤t_val
);
988 displaced_debug_printf ("addpcis target regnum %d was %s now %s",
989 regnum
, paddress (gdbarch
, current_val
),
990 paddress (gdbarch
, current_val
991 + displaced_offset
));
992 regcache_cooked_write_unsigned (regs
, regnum
,
993 current_val
+ displaced_offset
);
994 /* point the PC back at the non-displaced instruction. */
995 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
998 /* Handle PC-relative branch instructions. */
999 else if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1001 ULONGEST current_pc
;
1003 /* Read the current PC value after the instruction has been executed
1004 in a displaced location. Calculate the offset to be applied to the
1005 original PC value before the displaced stepping. */
1006 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1008 offset
= current_pc
- to
;
1010 if (opcode
!= BXL_INSN
)
1012 /* Check for AA bit indicating whether this is an absolute
1013 addressing or PC-relative (1: absolute, 0: relative). */
1016 /* PC-relative addressing is being used in the branch. */
1017 displaced_debug_printf ("(ppc) branch instruction: %s",
1018 paddress (gdbarch
, insn
));
1019 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
1020 paddress (gdbarch
, current_pc
),
1021 paddress (gdbarch
, from
+ offset
));
1023 regcache_cooked_write_unsigned (regs
,
1024 gdbarch_pc_regnum (gdbarch
),
1030 /* If we're here, it means we have a branch to LR or CTR. If the
1031 branch was taken, the offset is probably greater than 4 (the next
1032 instruction), so it's safe to assume that an offset of 4 means we
1033 did not take the branch. */
1034 if (offset
== PPC_INSN_SIZE
)
1035 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1036 from
+ PPC_INSN_SIZE
);
1039 /* Check for LK bit indicating whether we should set the link
1040 register to point to the next instruction
1041 (1: Set, 0: Don't set). */
1044 /* Link register needs to be set to the next instruction's PC. */
1045 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
1046 regcache_cooked_write_unsigned (regs
,
1047 tdep
->ppc_lr_regnum
,
1048 from
+ PPC_INSN_SIZE
);
1049 displaced_debug_printf ("(ppc) adjusted LR to %s",
1050 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1054 /* Check for breakpoints in the inferior. If we've found one, place the PC
1055 right at the breakpoint instruction. */
1056 else if ((insn
& BP_MASK
) == BP_INSN
)
1057 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1060 /* Handle any other instructions that do not fit in the categories
1062 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1067 /* Implementation of gdbarch_displaced_step_prepare. */
1069 static displaced_step_prepare_status
1070 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1071 CORE_ADDR
&displaced_pc
)
1073 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1075 if (!per_inferior
->disp_step_buf
.has_value ())
1077 /* Figure out where the displaced step buffer is. */
1078 CORE_ADDR disp_step_buf_addr
1079 = displaced_step_at_entry_point (thread
->inf
->gdbarch
);
1081 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1084 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1087 /* Implementation of gdbarch_displaced_step_finish. */
1089 static displaced_step_finish_status
1090 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1093 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1095 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1097 return per_inferior
->disp_step_buf
->finish (arch
, thread
, sig
);
1100 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1103 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1105 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1107 if (per_inferior
== nullptr
1108 || !per_inferior
->disp_step_buf
.has_value ())
1111 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1114 /* Always use hardware single-stepping to execute the
1115 displaced instruction. */
1117 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1122 /* Checks for an atomic sequence of instructions beginning with a
1123 Load And Reserve instruction and ending with a Store Conditional
1124 instruction. If such a sequence is found, attempt to step through it.
1125 A breakpoint is placed at the end of the sequence. */
1126 std::vector
<CORE_ADDR
>
1127 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1129 struct gdbarch
*gdbarch
= regcache
->arch ();
1130 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1131 CORE_ADDR pc
= regcache_read_pc (regcache
);
1132 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1134 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1135 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1138 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1139 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1140 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1142 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1143 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1146 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1148 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1150 if ((insn
& OP_MASK
) == 1 << 26)
1151 loc
+= 2 * PPC_INSN_SIZE
;
1153 loc
+= PPC_INSN_SIZE
;
1154 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1156 /* Assume that there is at most one conditional branch in the atomic
1157 sequence. If a conditional branch is found, put a breakpoint in
1158 its destination address. */
1159 if ((insn
& OP_MASK
) == BC_INSN
)
1161 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1162 int absolute
= insn
& 2;
1164 if (bc_insn_count
>= 1)
1165 return {}; /* More than one conditional branch found, fallback
1166 to the standard single-step code. */
1169 breaks
[1] = immediate
;
1171 breaks
[1] = loc
+ immediate
;
1177 if (IS_STORE_CONDITIONAL_INSN (insn
))
1181 /* Assume that the atomic sequence ends with a Store Conditional
1183 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1187 loc
+= PPC_INSN_SIZE
;
1189 /* Insert a breakpoint right after the end of the atomic sequence. */
1192 /* Check for duplicated breakpoints. Check also for a breakpoint
1193 placed (branch instruction's destination) anywhere in sequence. */
1195 && (breaks
[1] == breaks
[0]
1196 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1197 last_breakpoint
= 0;
1199 std::vector
<CORE_ADDR
> next_pcs
;
1201 for (index
= 0; index
<= last_breakpoint
; index
++)
1202 next_pcs
.push_back (breaks
[index
]);
1208 #define SIGNED_SHORT(x) \
1209 ((sizeof (short) == 2) \
1210 ? ((int)(short)(x)) \
1211 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1213 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1215 /* Limit the number of skipped non-prologue instructions, as the examining
1216 of the prologue is expensive. */
1217 static int max_skip_non_prologue_insns
= 10;
1219 /* Return nonzero if the given instruction OP can be part of the prologue
1220 of a function and saves a parameter on the stack. FRAMEP should be
1221 set if one of the previous instructions in the function has set the
1225 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1227 /* Move parameters from argument registers to temporary register. */
1228 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1230 /* Rx must be scratch register r0. */
1231 const int rx_regno
= (op
>> 16) & 31;
1232 /* Ry: Only r3 - r10 are used for parameter passing. */
1233 const int ry_regno
= GET_SRC_REG (op
);
1235 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1237 *r0_contains_arg
= 1;
1244 /* Save a General Purpose Register on stack. */
1246 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1247 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1249 /* Rx: Only r3 - r10 are used for parameter passing. */
1250 const int rx_regno
= GET_SRC_REG (op
);
1252 return (rx_regno
>= 3 && rx_regno
<= 10);
1255 /* Save a General Purpose Register on stack via the Frame Pointer. */
1258 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1259 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1260 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1262 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1263 However, the compiler sometimes uses r0 to hold an argument. */
1264 const int rx_regno
= GET_SRC_REG (op
);
1266 return ((rx_regno
>= 3 && rx_regno
<= 10)
1267 || (rx_regno
== 0 && *r0_contains_arg
));
1270 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1272 /* Only f2 - f8 are used for parameter passing. */
1273 const int src_regno
= GET_SRC_REG (op
);
1275 return (src_regno
>= 2 && src_regno
<= 8);
1278 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1280 /* Only f2 - f8 are used for parameter passing. */
1281 const int src_regno
= GET_SRC_REG (op
);
1283 return (src_regno
>= 2 && src_regno
<= 8);
1286 /* Not an insn that saves a parameter on stack. */
1290 /* Assuming that INSN is a "bl" instruction located at PC, return
1291 nonzero if the destination of the branch is a "blrl" instruction.
1293 This sequence is sometimes found in certain function prologues.
1294 It allows the function to load the LR register with a value that
1295 they can use to access PIC data using PC-relative offsets. */
1298 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1305 absolute
= (int) ((insn
>> 1) & 1);
1306 immediate
= ((insn
& ~3) << 6) >> 6;
1310 dest
= pc
+ immediate
;
1312 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1313 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1319 /* Return true if OP is a stw or std instruction with
1320 register operands RS and RA and any immediate offset.
1322 If WITH_UPDATE is true, also return true if OP is
1323 a stwu or stdu instruction with the same operands.
1325 Return false otherwise.
1328 store_insn_p (unsigned long op
, unsigned long rs
,
1329 unsigned long ra
, bool with_update
)
1334 if (/* std RS, SIMM(RA) */
1335 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1336 /* stw RS, SIMM(RA) */
1337 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1342 if (/* stdu RS, SIMM(RA) */
1343 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1344 /* stwu RS, SIMM(RA) */
1345 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1352 /* Masks for decoding a branch-and-link (bl) instruction.
1354 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1355 The former is anded with the opcode in question; if the result of
1356 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1357 question is a ``bl'' instruction.
1359 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1360 the branch displacement. */
1362 #define BL_MASK 0xfc000001
1363 #define BL_INSTRUCTION 0x48000001
1364 #define BL_DISPLACEMENT_MASK 0x03fffffc
1366 static unsigned long
1367 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1369 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1373 /* Fetch the instruction and convert it to an integer. */
1374 if (target_read_memory (pc
, buf
, 4))
1376 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1381 /* GCC generates several well-known sequences of instructions at the begining
1382 of each function prologue when compiling with -fstack-check. If one of
1383 such sequences starts at START_PC, then return the address of the
1384 instruction immediately past this sequence. Otherwise, return START_PC. */
1387 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1389 CORE_ADDR pc
= start_pc
;
1390 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1392 /* First possible sequence: A small number of probes.
1393 stw 0, -<some immediate>(1)
1394 [repeat this instruction any (small) number of times]. */
1396 if ((op
& 0xffff0000) == 0x90010000)
1398 while ((op
& 0xffff0000) == 0x90010000)
1401 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1406 /* Second sequence: A probing loop.
1407 addi 12,1,-<some immediate>
1408 lis 0,-<some immediate>
1409 [possibly ori 0,0,<some immediate>]
1413 addi 12,12,-<some immediate>
1416 [possibly one last probe: stw 0,<some immediate>(12)]. */
1420 /* addi 12,1,-<some immediate> */
1421 if ((op
& 0xffff0000) != 0x39810000)
1424 /* lis 0,-<some immediate> */
1426 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1427 if ((op
& 0xffff0000) != 0x3c000000)
1431 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1432 /* [possibly ori 0,0,<some immediate>] */
1433 if ((op
& 0xffff0000) == 0x60000000)
1436 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1439 if (op
!= 0x7c0c0214)
1444 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1445 if (op
!= 0x7c0c0000)
1450 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1451 if ((op
& 0xff9f0001) != 0x41820000)
1454 /* addi 12,12,-<some immediate> */
1456 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1457 if ((op
& 0xffff0000) != 0x398c0000)
1462 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1463 if (op
!= 0x900c0000)
1468 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1469 if ((op
& 0xfc000001) != 0x48000000)
1472 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1474 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1475 if ((op
& 0xffff0000) == 0x900c0000)
1478 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1481 /* We found a valid stack-check sequence, return the new PC. */
1485 /* Third sequence: No probe; instead, a comparison between the stack size
1486 limit (saved in a run-time global variable) and the current stack
1489 addi 0,1,-<some immediate>
1490 lis 12,__gnat_stack_limit@ha
1491 lwz 12,__gnat_stack_limit@l(12)
1494 or, with a small variant in the case of a bigger stack frame:
1495 addis 0,1,<some immediate>
1496 addic 0,0,-<some immediate>
1497 lis 12,__gnat_stack_limit@ha
1498 lwz 12,__gnat_stack_limit@l(12)
1503 /* addi 0,1,-<some immediate> */
1504 if ((op
& 0xffff0000) != 0x38010000)
1506 /* small stack frame variant not recognized; try the
1507 big stack frame variant: */
1509 /* addis 0,1,<some immediate> */
1510 if ((op
& 0xffff0000) != 0x3c010000)
1513 /* addic 0,0,-<some immediate> */
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xffff0000) != 0x30000000)
1520 /* lis 12,<some immediate> */
1522 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1523 if ((op
& 0xffff0000) != 0x3d800000)
1526 /* lwz 12,<some immediate>(12) */
1528 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1529 if ((op
& 0xffff0000) != 0x818c0000)
1534 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1535 if ((op
& 0xfffffffe) != 0x7c406008)
1538 /* We found a valid stack-check sequence, return the new PC. */
1542 /* No stack check code in our prologue, return the start_pc. */
1546 /* return pc value after skipping a function prologue and also return
1547 information about a function frame.
1549 in struct rs6000_framedata fdata:
1550 - frameless is TRUE, if function does not have a frame.
1551 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1552 - offset is the initial size of this stack frame --- the amount by
1553 which we decrement the sp to allocate the frame.
1554 - saved_gpr is the number of the first saved gpr.
1555 - saved_fpr is the number of the first saved fpr.
1556 - saved_vr is the number of the first saved vr.
1557 - saved_ev is the number of the first saved ev.
1558 - alloca_reg is the number of the register used for alloca() handling.
1560 - gpr_offset is the offset of the first saved gpr from the previous frame.
1561 - fpr_offset is the offset of the first saved fpr from the previous frame.
1562 - vr_offset is the offset of the first saved vr from the previous frame.
1563 - ev_offset is the offset of the first saved ev from the previous frame.
1564 - lr_offset is the offset of the saved lr
1565 - cr_offset is the offset of the saved cr
1566 - vrsave_offset is the offset of the saved vrsave register. */
1569 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1570 struct rs6000_framedata
*fdata
)
1572 CORE_ADDR orig_pc
= pc
;
1573 CORE_ADDR last_prologue_pc
= pc
;
1574 CORE_ADDR li_found_pc
= 0;
1578 long alloca_reg_offset
= 0;
1579 long vr_saved_offset
= 0;
1585 int vrsave_reg
= -1;
1588 int minimal_toc_loaded
= 0;
1589 int prev_insn_was_prologue_insn
= 1;
1590 int num_skip_non_prologue_insns
= 0;
1591 int r0_contains_arg
= 0;
1592 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1593 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
1594 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1596 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1597 fdata
->saved_gpr
= -1;
1598 fdata
->saved_fpr
= -1;
1599 fdata
->saved_vr
= -1;
1600 fdata
->saved_ev
= -1;
1601 fdata
->alloca_reg
= -1;
1602 fdata
->frameless
= 1;
1603 fdata
->nosavedpc
= 1;
1604 fdata
->lr_register
= -1;
1606 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1612 /* Sometimes it isn't clear if an instruction is a prologue
1613 instruction or not. When we encounter one of these ambiguous
1614 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1615 Otherwise, we'll assume that it really is a prologue instruction. */
1616 if (prev_insn_was_prologue_insn
)
1617 last_prologue_pc
= pc
;
1619 /* Stop scanning if we've hit the limit. */
1623 prev_insn_was_prologue_insn
= 1;
1625 /* Fetch the instruction and convert it to an integer. */
1626 if (target_read_memory (pc
, buf
, 4))
1628 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1630 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1632 /* Since shared library / PIC code, which needs to get its
1633 address at runtime, can appear to save more than one link
1647 remember just the first one, but skip over additional
1650 lr_reg
= (op
& 0x03e00000) >> 21;
1652 r0_contains_arg
= 0;
1655 else if ((op
& 0xfc1fffff) == 0x7c000026)
1657 cr_reg
= (op
& 0x03e00000) >> 21;
1659 r0_contains_arg
= 0;
1663 else if ((op
& 0xfc1f0000) == 0xd8010000)
1664 { /* stfd Rx,NUM(r1) */
1665 reg
= GET_SRC_REG (op
);
1666 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1668 fdata
->saved_fpr
= reg
;
1669 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1674 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1675 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1676 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1677 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1680 reg
= GET_SRC_REG (op
);
1681 if ((op
& 0xfc1f0000) == 0xbc010000)
1682 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1684 fdata
->gpr_mask
|= 1U << reg
;
1685 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1687 fdata
->saved_gpr
= reg
;
1688 if ((op
& 0xfc1f0003) == 0xf8010000)
1690 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1695 else if ((op
& 0xffff0000) == 0x3c4c0000
1696 || (op
& 0xffff0000) == 0x3c400000
1697 || (op
& 0xffff0000) == 0x38420000)
1699 /* . 0: addis 2,12,.TOC.-0b@ha
1700 . addi 2,2,.TOC.-0b@l
1704 used by ELFv2 global entry points to set up r2. */
1707 else if (op
== 0x60000000)
1710 /* Allow nops in the prologue, but do not consider them to
1711 be part of the prologue unless followed by other prologue
1713 prev_insn_was_prologue_insn
= 0;
1717 else if ((op
& 0xffff0000) == 0x3c000000)
1718 { /* addis 0,0,NUM, used for >= 32k frames */
1719 fdata
->offset
= (op
& 0x0000ffff) << 16;
1720 fdata
->frameless
= 0;
1721 r0_contains_arg
= 0;
1725 else if ((op
& 0xffff0000) == 0x60000000)
1726 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1727 fdata
->offset
|= (op
& 0x0000ffff);
1728 fdata
->frameless
= 0;
1729 r0_contains_arg
= 0;
1733 else if (lr_reg
>= 0 &&
1734 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1736 (store_insn_p (op
, lr_reg
,
1737 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1740 if (store_insn_p (op
, lr_reg
, 1, true))
1741 fdata
->lr_offset
= offset
;
1742 else /* LR save through frame pointer. */
1743 fdata
->lr_offset
= alloca_reg_offset
;
1745 fdata
->nosavedpc
= 0;
1746 /* Invalidate lr_reg, but don't set it to -1.
1747 That would mean that it had never been set. */
1749 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1750 (op
& 0xfc000000) == 0x90000000) /* stw */
1752 /* Does not update r1, so add displacement to lr_offset. */
1753 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1758 else if (cr_reg
>= 0 &&
1759 (store_insn_p (op
, cr_reg
, 1, true)))
1761 fdata
->cr_offset
= offset
;
1762 /* Invalidate cr_reg, but don't set it to -1.
1763 That would mean that it had never been set. */
1765 if ((op
& 0xfc000003) == 0xf8000000 ||
1766 (op
& 0xfc000000) == 0x90000000)
1768 /* Does not update r1, so add displacement to cr_offset. */
1769 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1774 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1776 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1777 prediction bits. If the LR has already been saved, we can
1781 else if (op
== 0x48000005)
1788 else if (op
== 0x48000004)
1793 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1794 in V.4 -mminimal-toc */
1795 (op
& 0xffff0000) == 0x3bde0000)
1796 { /* addi 30,30,foo@l */
1800 else if ((op
& 0xfc000001) == 0x48000001)
1804 fdata
->frameless
= 0;
1806 /* If the return address has already been saved, we can skip
1807 calls to blrl (for PIC). */
1808 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1814 /* Don't skip over the subroutine call if it is not within
1815 the first three instructions of the prologue and either
1816 we have no line table information or the line info tells
1817 us that the subroutine call is not part of the line
1818 associated with the prologue. */
1819 if ((pc
- orig_pc
) > 8)
1821 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1822 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1824 if ((prologue_sal
.line
== 0)
1825 || (prologue_sal
.line
!= this_sal
.line
))
1829 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1831 /* At this point, make sure this is not a trampoline
1832 function (a function that simply calls another functions,
1833 and nothing else). If the next is not a nop, this branch
1834 was part of the function prologue. */
1836 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1837 break; /* Don't skip over
1843 /* update stack pointer */
1844 else if ((op
& 0xfc1f0000) == 0x94010000)
1845 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1846 fdata
->frameless
= 0;
1847 fdata
->offset
= SIGNED_SHORT (op
);
1848 offset
= fdata
->offset
;
1851 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1852 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1853 /* No way to figure out what r1 is going to be. */
1854 fdata
->frameless
= 0;
1855 offset
= fdata
->offset
;
1858 else if ((op
& 0xfc1f0003) == 0xf8010001)
1859 { /* stdu rX,NUM(r1) */
1860 fdata
->frameless
= 0;
1861 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1862 offset
= fdata
->offset
;
1865 else if ((op
& 0xffff0000) == 0x38210000)
1866 { /* addi r1,r1,SIMM */
1867 fdata
->frameless
= 0;
1868 fdata
->offset
+= SIGNED_SHORT (op
);
1869 offset
= fdata
->offset
;
1872 /* Load up minimal toc pointer. Do not treat an epilogue restore
1873 of r31 as a minimal TOC load. */
1874 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1875 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1877 && !minimal_toc_loaded
)
1879 minimal_toc_loaded
= 1;
1882 /* move parameters from argument registers to local variable
1885 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1886 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1887 (((op
>> 21) & 31) <= 10) &&
1888 ((long) ((op
>> 16) & 31)
1889 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1893 /* store parameters in stack */
1895 /* Move parameters from argument registers to temporary register. */
1896 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1900 /* Set up frame pointer */
1902 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1904 fdata
->frameless
= 0;
1906 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1907 alloca_reg_offset
= offset
;
1910 /* Another way to set up the frame pointer. */
1912 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1913 || op
== 0x7c3f0b78)
1915 fdata
->frameless
= 0;
1917 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1918 alloca_reg_offset
= offset
;
1921 /* Another way to set up the frame pointer. */
1923 else if ((op
& 0xfc1fffff) == 0x38010000)
1924 { /* addi rX, r1, 0x0 */
1925 fdata
->frameless
= 0;
1927 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1928 + ((op
& ~0x38010000) >> 21));
1929 alloca_reg_offset
= offset
;
1932 /* AltiVec related instructions. */
1933 /* Store the vrsave register (spr 256) in another register for
1934 later manipulation, or load a register into the vrsave
1935 register. 2 instructions are used: mfvrsave and
1936 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1937 and mtspr SPR256, Rn. */
1938 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1939 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1940 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1942 vrsave_reg
= GET_SRC_REG (op
);
1945 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1949 /* Store the register where vrsave was saved to onto the stack:
1950 rS is the register where vrsave was stored in a previous
1952 /* 100100 sssss 00001 dddddddd dddddddd */
1953 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1955 if (vrsave_reg
== GET_SRC_REG (op
))
1957 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1962 /* Compute the new value of vrsave, by modifying the register
1963 where vrsave was saved to. */
1964 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1965 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1969 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1970 in a pair of insns to save the vector registers on the
1972 /* 001110 00000 00000 iiii iiii iiii iiii */
1973 /* 001110 01110 00000 iiii iiii iiii iiii */
1974 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1975 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1977 if ((op
& 0xffff0000) == 0x38000000)
1978 r0_contains_arg
= 0;
1980 vr_saved_offset
= SIGNED_SHORT (op
);
1982 /* This insn by itself is not part of the prologue, unless
1983 if part of the pair of insns mentioned above. So do not
1984 record this insn as part of the prologue yet. */
1985 prev_insn_was_prologue_insn
= 0;
1987 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1988 /* 011111 sssss 11111 00000 00111001110 */
1989 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1991 if (pc
== (li_found_pc
+ 4))
1993 vr_reg
= GET_SRC_REG (op
);
1994 /* If this is the first vector reg to be saved, or if
1995 it has a lower number than others previously seen,
1996 reupdate the frame info. */
1997 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1999 fdata
->saved_vr
= vr_reg
;
2000 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2002 vr_saved_offset
= -1;
2007 /* End AltiVec related instructions. */
2009 /* Start BookE related instructions. */
2010 /* Store gen register S at (r31+uimm).
2011 Any register less than r13 is volatile, so we don't care. */
2012 /* 000100 sssss 11111 iiiii 01100100001 */
2013 else if (arch_info
->mach
== bfd_mach_ppc_e500
2014 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2016 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2019 ev_reg
= GET_SRC_REG (op
);
2020 imm
= (op
>> 11) & 0x1f;
2021 ev_offset
= imm
* 8;
2022 /* If this is the first vector reg to be saved, or if
2023 it has a lower number than others previously seen,
2024 reupdate the frame info. */
2025 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2027 fdata
->saved_ev
= ev_reg
;
2028 fdata
->ev_offset
= ev_offset
+ offset
;
2033 /* Store gen register rS at (r1+rB). */
2034 /* 000100 sssss 00001 bbbbb 01100100000 */
2035 else if (arch_info
->mach
== bfd_mach_ppc_e500
2036 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2038 if (pc
== (li_found_pc
+ 4))
2040 ev_reg
= GET_SRC_REG (op
);
2041 /* If this is the first vector reg to be saved, or if
2042 it has a lower number than others previously seen,
2043 reupdate the frame info. */
2044 /* We know the contents of rB from the previous instruction. */
2045 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2047 fdata
->saved_ev
= ev_reg
;
2048 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2050 vr_saved_offset
= -1;
2056 /* Store gen register r31 at (rA+uimm). */
2057 /* 000100 11111 aaaaa iiiii 01100100001 */
2058 else if (arch_info
->mach
== bfd_mach_ppc_e500
2059 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2061 /* Wwe know that the source register is 31 already, but
2062 it can't hurt to compute it. */
2063 ev_reg
= GET_SRC_REG (op
);
2064 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2065 /* If this is the first vector reg to be saved, or if
2066 it has a lower number than others previously seen,
2067 reupdate the frame info. */
2068 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2070 fdata
->saved_ev
= ev_reg
;
2071 fdata
->ev_offset
= ev_offset
+ offset
;
2076 /* Store gen register S at (r31+r0).
2077 Store param on stack when offset from SP bigger than 4 bytes. */
2078 /* 000100 sssss 11111 00000 01100100000 */
2079 else if (arch_info
->mach
== bfd_mach_ppc_e500
2080 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2082 if (pc
== (li_found_pc
+ 4))
2084 if ((op
& 0x03e00000) >= 0x01a00000)
2086 ev_reg
= GET_SRC_REG (op
);
2087 /* If this is the first vector reg to be saved, or if
2088 it has a lower number than others previously seen,
2089 reupdate the frame info. */
2090 /* We know the contents of r0 from the previous
2092 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2094 fdata
->saved_ev
= ev_reg
;
2095 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2099 vr_saved_offset
= -1;
2104 /* End BookE related instructions. */
2108 /* Not a recognized prologue instruction.
2109 Handle optimizer code motions into the prologue by continuing
2110 the search if we have no valid frame yet or if the return
2111 address is not yet saved in the frame. Also skip instructions
2112 if some of the GPRs expected to be saved are not yet saved. */
2113 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2114 && fdata
->saved_gpr
!= -1)
2116 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2118 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2122 if (op
== 0x4e800020 /* blr */
2123 || op
== 0x4e800420) /* bctr */
2124 /* Do not scan past epilogue in frameless functions or
2127 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2128 /* Never skip branches. */
2131 /* Test based on opcode and mask values of
2132 powerpc_opcodes[svc..svcla] in opcodes/ppc-opc.c. */
2133 if ((op
& 0xffff0000) == 0x44000000)
2134 /* Never skip system calls. */
2137 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2138 /* Do not scan too many insns, scanning insns is expensive with
2142 /* Continue scanning. */
2143 prev_insn_was_prologue_insn
= 0;
2149 /* I have problems with skipping over __main() that I need to address
2150 * sometime. Previously, I used to use misc_function_vector which
2151 * didn't work as well as I wanted to be. -MGO */
2153 /* If the first thing after skipping a prolog is a branch to a function,
2154 this might be a call to an initializer in main(), introduced by gcc2.
2155 We'd like to skip over it as well. Fortunately, xlc does some extra
2156 work before calling a function right after a prologue, thus we can
2157 single out such gcc2 behaviour. */
2160 if ((op
& 0xfc000001) == 0x48000001)
2161 { /* bl foo, an initializer function? */
2162 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2164 if (op
== 0x4def7b82)
2165 { /* cror 0xf, 0xf, 0xf (nop) */
2167 /* Check and see if we are in main. If so, skip over this
2168 initializer function as well. */
2170 tmp
= find_pc_misc_function (pc
);
2172 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2178 if (pc
== lim_pc
&& lr_reg
>= 0)
2179 fdata
->lr_register
= lr_reg
;
2181 fdata
->offset
= -fdata
->offset
;
2182 return last_prologue_pc
;
2186 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2188 struct rs6000_framedata frame
;
2189 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2191 /* See if we can determine the end of the prologue via the symbol table.
2192 If so, then return either PC, or the PC after the prologue, whichever
2194 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2196 CORE_ADDR post_prologue_pc
2197 = skip_prologue_using_sal (gdbarch
, func_addr
);
2198 if (post_prologue_pc
!= 0)
2199 return std::max (pc
, post_prologue_pc
);
2202 /* Can't determine prologue from the symbol table, need to examine
2205 /* Find an upper limit on the function prologue using the debug
2206 information. If the debug information could not be used to provide
2207 that bound, then use an arbitrary large number as the upper bound. */
2208 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2210 limit_pc
= pc
+ 100; /* Magic. */
2212 /* Do not allow limit_pc to be past the function end, if we know
2213 where that end is... */
2214 if (func_end_addr
&& limit_pc
> func_end_addr
)
2215 limit_pc
= func_end_addr
;
2217 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2221 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2222 in the prologue of main().
2224 The function below examines the code pointed at by PC and checks to
2225 see if it corresponds to a call to __eabi. If so, it returns the
2226 address of the instruction following that call. Otherwise, it simply
2230 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2236 if (target_read_memory (pc
, buf
, 4))
2238 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2240 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2242 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2243 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2244 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2246 /* We check for ___eabi (three leading underscores) in addition
2247 to __eabi in case the GCC option "-fleading-underscore" was
2248 used to compile the program. */
2249 if (s
.minsym
!= NULL
2250 && s
.minsym
->linkage_name () != NULL
2251 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2252 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2258 /* All the ABI's require 16 byte alignment. */
2260 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2262 return (addr
& -16);
2265 /* Return whether handle_inferior_event() should proceed through code
2266 starting at PC in function NAME when stepping.
2268 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2269 handle memory references that are too distant to fit in instructions
2270 generated by the compiler. For example, if 'foo' in the following
2275 is greater than 32767, the linker might replace the lwz with a branch to
2276 somewhere in @FIX1 that does the load in 2 instructions and then branches
2277 back to where execution should continue.
2279 GDB should silently step over @FIX code, just like AIX dbx does.
2280 Unfortunately, the linker uses the "b" instruction for the
2281 branches, meaning that the link register doesn't get set.
2282 Therefore, GDB's usual step_over_function () mechanism won't work.
2284 Instead, use the gdbarch_skip_trampoline_code and
2285 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2289 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2290 CORE_ADDR pc
, const char *name
)
2292 return name
&& startswith (name
, "@FIX");
2295 /* Skip code that the user doesn't want to see when stepping:
2297 1. Indirect function calls use a piece of trampoline code to do context
2298 switching, i.e. to set the new TOC table. Skip such code if we are on
2299 its first instruction (as when we have single-stepped to here).
2301 2. Skip shared library trampoline code (which is different from
2302 indirect function call trampolines).
2304 3. Skip bigtoc fixup code.
2306 Result is desired PC to step until, or NULL if we are not in
2307 code that should be skipped. */
2310 rs6000_skip_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
2312 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2313 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2314 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2315 unsigned int ii
, op
;
2317 CORE_ADDR solib_target_pc
;
2318 struct bound_minimal_symbol msymbol
;
2320 static unsigned trampoline_code
[] =
2322 0x800b0000, /* l r0,0x0(r11) */
2323 0x90410014, /* st r2,0x14(r1) */
2324 0x7c0903a6, /* mtctr r0 */
2325 0x804b0004, /* l r2,0x4(r11) */
2326 0x816b0008, /* l r11,0x8(r11) */
2327 0x4e800420, /* bctr */
2328 0x4e800020, /* br */
2332 /* Check for bigtoc fixup code. */
2333 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2335 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2336 msymbol
.minsym
->linkage_name ()))
2338 /* Double-check that the third instruction from PC is relative "b". */
2339 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2340 if ((op
& 0xfc000003) == 0x48000000)
2342 /* Extract bits 6-29 as a signed 24-bit relative word address and
2343 add it to the containing PC. */
2344 rel
= ((int)(op
<< 6) >> 6);
2345 return pc
+ 8 + rel
;
2349 /* If pc is in a shared library trampoline, return its target. */
2350 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2351 if (solib_target_pc
)
2352 return solib_target_pc
;
2354 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2356 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2357 if (op
!= trampoline_code
[ii
])
2360 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2362 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2366 /* ISA-specific vector types. */
2368 static struct type
*
2369 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2371 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2373 if (!tdep
->ppc_builtin_type_vec64
)
2375 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2377 /* The type we're building is this: */
2379 union __gdb_builtin_type_vec64
2383 int32_t v2_int32
[2];
2384 int16_t v4_int16
[4];
2391 t
= arch_composite_type (gdbarch
,
2392 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2393 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2394 append_composite_type_field (t
, "v2_float",
2395 init_vector_type (bt
->builtin_float
, 2));
2396 append_composite_type_field (t
, "v2_int32",
2397 init_vector_type (bt
->builtin_int32
, 2));
2398 append_composite_type_field (t
, "v4_int16",
2399 init_vector_type (bt
->builtin_int16
, 4));
2400 append_composite_type_field (t
, "v8_int8",
2401 init_vector_type (bt
->builtin_int8
, 8));
2403 t
->set_is_vector (true);
2404 t
->set_name ("ppc_builtin_type_vec64");
2405 tdep
->ppc_builtin_type_vec64
= t
;
2408 return tdep
->ppc_builtin_type_vec64
;
2411 /* Vector 128 type. */
2413 static struct type
*
2414 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2416 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2418 if (!tdep
->ppc_builtin_type_vec128
)
2420 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2422 /* The type we're building is this
2424 type = union __ppc_builtin_type_vec128 {
2425 float128_t float128;
2427 double v2_double[2];
2429 int32_t v4_int32[4];
2430 int16_t v8_int16[8];
2431 int8_t v16_int8[16];
2435 /* PPC specific type for IEEE 128-bit float field */
2436 struct type
*t_float128
2437 = arch_float_type (gdbarch
, 128, "float128_t", floatformats_ieee_quad
);
2441 t
= arch_composite_type (gdbarch
,
2442 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2443 append_composite_type_field (t
, "float128", t_float128
);
2444 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2445 append_composite_type_field (t
, "v2_double",
2446 init_vector_type (bt
->builtin_double
, 2));
2447 append_composite_type_field (t
, "v4_float",
2448 init_vector_type (bt
->builtin_float
, 4));
2449 append_composite_type_field (t
, "v4_int32",
2450 init_vector_type (bt
->builtin_int32
, 4));
2451 append_composite_type_field (t
, "v8_int16",
2452 init_vector_type (bt
->builtin_int16
, 8));
2453 append_composite_type_field (t
, "v16_int8",
2454 init_vector_type (bt
->builtin_int8
, 16));
2456 t
->set_is_vector (true);
2457 t
->set_name ("ppc_builtin_type_vec128");
2458 tdep
->ppc_builtin_type_vec128
= t
;
2461 return tdep
->ppc_builtin_type_vec128
;
2464 /* Return the name of register number REGNO, or the empty string if it
2465 is an anonymous register. */
2468 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2470 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2472 /* The upper half "registers" have names in the XML description,
2473 but we present only the low GPRs and the full 64-bit registers
2475 if (tdep
->ppc_ev0_upper_regnum
>= 0
2476 && tdep
->ppc_ev0_upper_regnum
<= regno
2477 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2480 /* Hide the upper halves of the vs0~vs31 registers. */
2481 if (tdep
->ppc_vsr0_regnum
>= 0
2482 && tdep
->ppc_vsr0_upper_regnum
<= regno
2483 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2486 /* Hide the upper halves of the cvs0~cvs31 registers. */
2487 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2488 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2491 /* Check if the SPE pseudo registers are available. */
2492 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2494 static const char *const spe_regnames
[] = {
2495 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2496 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2497 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2498 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2500 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2503 /* Check if the decimal128 pseudo-registers are available. */
2504 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2506 static const char *const dfp128_regnames
[] = {
2507 "dl0", "dl1", "dl2", "dl3",
2508 "dl4", "dl5", "dl6", "dl7",
2509 "dl8", "dl9", "dl10", "dl11",
2510 "dl12", "dl13", "dl14", "dl15"
2512 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2515 /* Check if this is a vX alias for a raw vrX vector register. */
2516 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2518 static const char *const vector_alias_regnames
[] = {
2519 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2520 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2521 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2522 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2524 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2527 /* Check if this is a VSX pseudo-register. */
2528 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2530 static const char *const vsx_regnames
[] = {
2531 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2532 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2533 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2534 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2535 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2536 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2537 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2538 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2539 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2541 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2544 /* Check if the this is a Extended FP pseudo-register. */
2545 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2547 static const char *const efpr_regnames
[] = {
2548 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2549 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2550 "f46", "f47", "f48", "f49", "f50", "f51",
2551 "f52", "f53", "f54", "f55", "f56", "f57",
2552 "f58", "f59", "f60", "f61", "f62", "f63"
2554 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2557 /* Check if this is a Checkpointed DFP pseudo-register. */
2558 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2560 static const char *const cdfp128_regnames
[] = {
2561 "cdl0", "cdl1", "cdl2", "cdl3",
2562 "cdl4", "cdl5", "cdl6", "cdl7",
2563 "cdl8", "cdl9", "cdl10", "cdl11",
2564 "cdl12", "cdl13", "cdl14", "cdl15"
2566 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2569 /* Check if this is a Checkpointed VSX pseudo-register. */
2570 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2572 static const char *const cvsx_regnames
[] = {
2573 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2574 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2575 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2576 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2577 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2578 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2579 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2580 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2581 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2583 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2586 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2587 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2589 static const char *const cefpr_regnames
[] = {
2590 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2591 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2592 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2593 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2594 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2596 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2599 return tdesc_register_name (gdbarch
, regno
);
2602 /* Return the GDB type object for the "standard" data type of data in
2605 static struct type
*
2606 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2608 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2610 /* These are the e500 pseudo-registers. */
2611 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2612 return rs6000_builtin_type_vec64 (gdbarch
);
2613 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2614 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2615 /* PPC decimal128 pseudo-registers. */
2616 return builtin_type (gdbarch
)->builtin_declong
;
2617 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2618 return gdbarch_register_type (gdbarch
,
2619 tdep
->ppc_vr0_regnum
2621 - tdep
->ppc_v0_alias_regnum
));
2622 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2623 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2624 /* POWER7 VSX pseudo-registers. */
2625 return rs6000_builtin_type_vec128 (gdbarch
);
2626 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2627 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2628 /* POWER7 Extended FP pseudo-registers. */
2629 return builtin_type (gdbarch
)->builtin_double
;
2631 internal_error (__FILE__
, __LINE__
,
2632 _("rs6000_pseudo_register_type: "
2633 "called on unexpected register '%s' (%d)"),
2634 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2637 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2638 the vX aliases for the vector registers by always returning false
2639 to avoid duplicated information in "info register vector/all",
2640 since the raw vrX registers will already show in these cases. For
2641 other pseudo-registers we use the default membership function. */
2644 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2645 const struct reggroup
*group
)
2647 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2649 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2652 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2655 /* The register format for RS/6000 floating point registers is always
2656 double, we need a conversion if the memory format is float. */
2659 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2662 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2664 return (tdep
->ppc_fp0_regnum
>= 0
2665 && regnum
>= tdep
->ppc_fp0_regnum
2666 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2667 && type
->code () == TYPE_CODE_FLT
2669 != builtin_type (gdbarch
)->builtin_double
->length ()));
2673 rs6000_register_to_value (frame_info_ptr frame
,
2677 int *optimizedp
, int *unavailablep
)
2679 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2680 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2682 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2684 if (!get_frame_register_bytes (frame
, regnum
, 0,
2685 gdb::make_array_view (from
,
2686 register_size (gdbarch
,
2688 optimizedp
, unavailablep
))
2691 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2693 *optimizedp
= *unavailablep
= 0;
2698 rs6000_value_to_register (frame_info_ptr frame
,
2701 const gdb_byte
*from
)
2703 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2704 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2706 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2708 target_float_convert (from
, type
,
2709 to
, builtin_type (gdbarch
)->builtin_double
);
2710 put_frame_register (frame
, regnum
, to
);
2713 /* The type of a function that moves the value of REG between CACHE
2714 or BUF --- in either direction. */
2715 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2718 /* Move SPE vector register values between a 64-bit buffer and the two
2719 32-bit raw register halves in a regcache. This function handles
2720 both splitting a 64-bit value into two 32-bit halves, and joining
2721 two halves into a whole 64-bit value, depending on the function
2722 passed as the MOVE argument.
2724 EV_REG must be the number of an SPE evN vector register --- a
2725 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2728 Call MOVE once for each 32-bit half of that register, passing
2729 REGCACHE, the number of the raw register corresponding to that
2730 half, and the address of the appropriate half of BUFFER.
2732 For example, passing 'regcache_raw_read' as the MOVE function will
2733 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2734 'regcache_raw_supply' will supply the contents of BUFFER to the
2735 appropriate pair of raw registers in REGCACHE.
2737 You may need to cast away some 'const' qualifiers when passing
2738 MOVE, since this function can't tell at compile-time which of
2739 REGCACHE or BUFFER is acting as the source of the data. If C had
2740 co-variant type qualifiers, ... */
2742 static enum register_status
2743 e500_move_ev_register (move_ev_register_func move
,
2744 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2746 struct gdbarch
*arch
= regcache
->arch ();
2747 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (arch
);
2749 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2750 enum register_status status
;
2752 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2754 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2756 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2758 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2760 if (status
== REG_VALID
)
2761 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2766 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2767 if (status
== REG_VALID
)
2768 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2775 static enum register_status
2776 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2778 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2783 static enum register_status
2784 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2785 int ev_reg
, gdb_byte
*buffer
)
2787 struct gdbarch
*arch
= regcache
->arch ();
2788 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2790 enum register_status status
;
2792 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2794 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2796 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2798 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2800 if (status
== REG_VALID
)
2801 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2806 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2807 if (status
== REG_VALID
)
2808 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2817 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2818 int reg_nr
, const gdb_byte
*buffer
)
2820 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2821 reg_nr
, (void *) buffer
);
2824 /* Read method for DFP pseudo-registers. */
2825 static enum register_status
2826 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2827 int reg_nr
, gdb_byte
*buffer
)
2829 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2831 enum register_status status
;
2833 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2835 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2836 fp0
= PPC_F0_REGNUM
;
2840 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2842 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2843 fp0
= PPC_CF0_REGNUM
;
2846 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2848 /* Read two FP registers to form a whole dl register. */
2849 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2850 if (status
== REG_VALID
)
2851 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2856 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2857 if (status
== REG_VALID
)
2858 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2864 /* Write method for DFP pseudo-registers. */
2866 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2867 int reg_nr
, const gdb_byte
*buffer
)
2869 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2872 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2874 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2875 fp0
= PPC_F0_REGNUM
;
2879 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2881 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2882 fp0
= PPC_CF0_REGNUM
;
2885 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2887 /* Write each half of the dl register into a separate
2889 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2890 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2894 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2895 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2899 /* Read method for the vX aliases for the raw vrX registers. */
2901 static enum register_status
2902 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2903 readable_regcache
*regcache
, int reg_nr
,
2906 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2907 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2909 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2910 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2914 /* Write method for the vX aliases for the raw vrX registers. */
2917 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2918 struct regcache
*regcache
,
2919 int reg_nr
, const gdb_byte
*buffer
)
2921 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2922 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2924 regcache
->raw_write (tdep
->ppc_vr0_regnum
2925 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2928 /* Read method for POWER7 VSX pseudo-registers. */
2929 static enum register_status
2930 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2931 int reg_nr
, gdb_byte
*buffer
)
2933 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2934 int reg_index
, vr0
, fp0
, vsr0_upper
;
2935 enum register_status status
;
2937 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2939 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2940 vr0
= PPC_VR0_REGNUM
;
2941 fp0
= PPC_F0_REGNUM
;
2942 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2946 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2948 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2949 vr0
= PPC_CVR0_REGNUM
;
2950 fp0
= PPC_CF0_REGNUM
;
2951 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2954 /* Read the portion that overlaps the VMX registers. */
2956 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2958 /* Read the portion that overlaps the FPR registers. */
2959 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2961 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2962 if (status
== REG_VALID
)
2963 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2968 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2969 if (status
== REG_VALID
)
2970 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2976 /* Write method for POWER7 VSX pseudo-registers. */
2978 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2979 int reg_nr
, const gdb_byte
*buffer
)
2981 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2982 int reg_index
, vr0
, fp0
, vsr0_upper
;
2984 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2986 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2987 vr0
= PPC_VR0_REGNUM
;
2988 fp0
= PPC_F0_REGNUM
;
2989 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2993 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2995 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2996 vr0
= PPC_CVR0_REGNUM
;
2997 fp0
= PPC_CF0_REGNUM
;
2998 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3001 /* Write the portion that overlaps the VMX registers. */
3003 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
3005 /* Write the portion that overlaps the FPR registers. */
3006 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3008 regcache
->raw_write (fp0
+ reg_index
, buffer
);
3009 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
3013 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
3014 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
3018 /* Read method for POWER7 Extended FP pseudo-registers. */
3019 static enum register_status
3020 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
3021 int reg_nr
, gdb_byte
*buffer
)
3023 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3026 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3028 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3029 vr0
= PPC_VR0_REGNUM
;
3033 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3035 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3036 vr0
= PPC_CVR0_REGNUM
;
3039 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3041 /* Read the portion that overlaps the VMX register. */
3042 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
3043 register_size (gdbarch
, reg_nr
),
3047 /* Write method for POWER7 Extended FP pseudo-registers. */
3049 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3050 int reg_nr
, const gdb_byte
*buffer
)
3052 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3054 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3056 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3058 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3059 vr0
= PPC_VR0_REGNUM
;
3063 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3065 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3066 vr0
= PPC_CVR0_REGNUM
;
3068 /* The call to raw_write_part fails silently if the initial read
3069 of the read-update-write sequence returns an invalid status,
3070 so we check this manually and throw an error if needed. */
3071 regcache
->raw_update (vr0
+ reg_index
);
3072 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
3073 error (_("Cannot write to the checkpointed EFP register, "
3074 "the corresponding vector register is unavailable."));
3077 /* Write the portion that overlaps the VMX register. */
3078 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3079 register_size (gdbarch
, reg_nr
), buffer
);
3082 static enum register_status
3083 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3084 readable_regcache
*regcache
,
3085 int reg_nr
, gdb_byte
*buffer
)
3087 struct gdbarch
*regcache_arch
= regcache
->arch ();
3088 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3090 gdb_assert (regcache_arch
== gdbarch
);
3092 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3093 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3094 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3095 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3096 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3097 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3098 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3100 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3101 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3102 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3103 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3104 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3105 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3107 internal_error (__FILE__
, __LINE__
,
3108 _("rs6000_pseudo_register_read: "
3109 "called on unexpected register '%s' (%d)"),
3110 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3114 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3115 struct regcache
*regcache
,
3116 int reg_nr
, const gdb_byte
*buffer
)
3118 struct gdbarch
*regcache_arch
= regcache
->arch ();
3119 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3121 gdb_assert (regcache_arch
== gdbarch
);
3123 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3124 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3125 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3126 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3127 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3128 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3129 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3130 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3131 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3132 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3133 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3134 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3135 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3137 internal_error (__FILE__
, __LINE__
,
3138 _("rs6000_pseudo_register_write: "
3139 "called on unexpected register '%s' (%d)"),
3140 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3143 /* Set the register mask in AX with the registers that form the DFP or
3144 checkpointed DFP pseudo-register REG_NR. */
3147 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3148 struct agent_expr
*ax
, int reg_nr
)
3150 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3153 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3155 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3156 fp0
= PPC_F0_REGNUM
;
3160 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3162 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3163 fp0
= PPC_CF0_REGNUM
;
3166 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3167 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3170 /* Set the register mask in AX with the raw vector register that
3171 corresponds to its REG_NR alias. */
3174 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3175 struct agent_expr
*ax
, int reg_nr
)
3177 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3178 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3180 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3181 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3184 /* Set the register mask in AX with the registers that form the VSX or
3185 checkpointed VSX pseudo-register REG_NR. */
3188 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3189 struct agent_expr
*ax
, int reg_nr
)
3191 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3192 int reg_index
, vr0
, fp0
, vsr0_upper
;
3194 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3196 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3197 vr0
= PPC_VR0_REGNUM
;
3198 fp0
= PPC_F0_REGNUM
;
3199 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3203 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3205 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3206 vr0
= PPC_CVR0_REGNUM
;
3207 fp0
= PPC_CF0_REGNUM
;
3208 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3213 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3217 ax_reg_mask (ax
, fp0
+ reg_index
);
3218 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3222 /* Set the register mask in AX with the register that corresponds to
3223 the EFP or checkpointed EFP pseudo-register REG_NR. */
3226 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3227 struct agent_expr
*ax
, int reg_nr
)
3229 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3232 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3234 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3235 vr0
= PPC_VR0_REGNUM
;
3239 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3241 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3242 vr0
= PPC_CVR0_REGNUM
;
3245 ax_reg_mask (ax
, vr0
+ reg_index
);
3249 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3250 struct agent_expr
*ax
, int reg_nr
)
3252 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3253 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3255 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3256 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3257 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3259 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3260 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3262 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3264 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3266 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3268 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3269 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3271 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3273 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3274 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3276 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3279 internal_error (__FILE__
, __LINE__
,
3280 _("rs6000_pseudo_register_collect: "
3281 "called on unexpected register '%s' (%d)"),
3282 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3288 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3289 struct agent_expr
*ax
, struct axs_value
*value
,
3292 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3293 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3294 value
->kind
= axs_lvalue_register
;
3295 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3299 /* Convert a DBX STABS register number to a GDB register number. */
3301 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3303 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3305 if (0 <= num
&& num
<= 31)
3306 return tdep
->ppc_gp0_regnum
+ num
;
3307 else if (32 <= num
&& num
<= 63)
3308 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3309 specifies registers the architecture doesn't have? Our
3310 callers don't check the value we return. */
3311 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3312 else if (77 <= num
&& num
<= 108)
3313 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3314 else if (1200 <= num
&& num
< 1200 + 32)
3315 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3320 return tdep
->ppc_mq_regnum
;
3322 return tdep
->ppc_lr_regnum
;
3324 return tdep
->ppc_ctr_regnum
;
3326 return tdep
->ppc_xer_regnum
;
3328 return tdep
->ppc_vrsave_regnum
;
3330 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3332 return tdep
->ppc_acc_regnum
;
3334 return tdep
->ppc_spefscr_regnum
;
3341 /* Convert a Dwarf 2 register number to a GDB register number. */
3343 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3345 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3347 if (0 <= num
&& num
<= 31)
3348 return tdep
->ppc_gp0_regnum
+ num
;
3349 else if (32 <= num
&& num
<= 63)
3350 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3351 specifies registers the architecture doesn't have? Our
3352 callers don't check the value we return. */
3353 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3354 else if (1124 <= num
&& num
< 1124 + 32)
3355 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3356 else if (1200 <= num
&& num
< 1200 + 32)
3357 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3362 return tdep
->ppc_cr_regnum
;
3364 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3366 return tdep
->ppc_acc_regnum
;
3368 return tdep
->ppc_mq_regnum
;
3370 return tdep
->ppc_xer_regnum
;
3372 return tdep
->ppc_lr_regnum
;
3374 return tdep
->ppc_ctr_regnum
;
3376 return tdep
->ppc_vrsave_regnum
;
3378 return tdep
->ppc_spefscr_regnum
;
3381 /* Unknown DWARF register number. */
3385 /* Translate a .eh_frame register to DWARF register, or adjust a
3386 .debug_frame register. */
3389 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3391 /* GCC releases before 3.4 use GCC internal register numbering in
3392 .debug_frame (and .debug_info, et cetera). The numbering is
3393 different from the standard SysV numbering for everything except
3394 for GPRs and FPRs. We can not detect this problem in most cases
3395 - to get accurate debug info for variables living in lr, ctr, v0,
3396 et cetera, use a newer version of GCC. But we must detect
3397 one important case - lr is in column 65 in .debug_frame output,
3400 GCC 3.4, and the "hammer" branch, have a related problem. They
3401 record lr register saves in .debug_frame as 108, but still record
3402 the return column as 65. We fix that up too.
3404 We can do this because 65 is assigned to fpsr, and GCC never
3405 generates debug info referring to it. To add support for
3406 handwritten debug info that restores fpsr, we would need to add a
3407 producer version check to this. */
3416 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3417 internal register numbering; translate that to the standard DWARF2
3418 register numbering. */
3419 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3421 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3422 return num
- 68 + 86;
3423 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3424 return num
- 77 + 1124;
3436 case 109: /* vrsave */
3438 case 110: /* vscr */
3440 case 111: /* spe_acc */
3442 case 112: /* spefscr */
3450 /* Handling the various POWER/PowerPC variants. */
3452 /* Information about a particular processor variant. */
3456 /* Name of this variant. */
3459 /* English description of the variant. */
3460 const char *description
;
3462 /* bfd_arch_info.arch corresponding to variant. */
3463 enum bfd_architecture arch
;
3465 /* bfd_arch_info.mach corresponding to variant. */
3468 /* Target description for this variant. */
3469 const struct target_desc
**tdesc
;
3472 static struct ppc_variant variants
[] =
3474 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3475 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3476 {"power", "POWER user-level", bfd_arch_rs6000
,
3477 bfd_mach_rs6k
, &tdesc_rs6000
},
3478 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3479 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3480 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3481 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3482 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3483 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3484 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3485 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3486 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3487 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3488 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3489 604, &tdesc_powerpc_604
},
3490 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3491 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3492 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3493 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3494 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3495 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3496 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3497 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3498 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3499 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3500 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3501 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3504 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3505 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3506 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3507 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3508 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3509 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3510 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3511 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3512 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3513 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3514 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3515 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3517 /* FIXME: I haven't checked the register sets of the following. */
3518 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3519 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3520 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3521 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3522 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3523 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3525 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3528 /* Return the variant corresponding to architecture ARCH and machine number
3529 MACH. If no such variant exists, return null. */
3531 static const struct ppc_variant
*
3532 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3534 const struct ppc_variant
*v
;
3536 for (v
= variants
; v
->name
; v
++)
3537 if (arch
== v
->arch
&& mach
== v
->mach
)
3545 struct rs6000_frame_cache
3548 CORE_ADDR initial_sp
;
3549 trad_frame_saved_reg
*saved_regs
;
3551 /* Set BASE_P to true if this frame cache is properly initialized.
3552 Otherwise set to false because some registers or memory cannot
3555 /* Cache PC for building unavailable frame. */
3559 static struct rs6000_frame_cache
*
3560 rs6000_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3562 struct rs6000_frame_cache
*cache
;
3563 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3564 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3565 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3566 struct rs6000_framedata fdata
;
3567 int wordsize
= tdep
->wordsize
;
3568 CORE_ADDR func
= 0, pc
= 0;
3570 if ((*this_cache
) != NULL
)
3571 return (struct rs6000_frame_cache
*) (*this_cache
);
3572 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3573 (*this_cache
) = cache
;
3575 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3579 func
= get_frame_func (this_frame
);
3581 pc
= get_frame_pc (this_frame
);
3582 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3584 /* Figure out the parent's stack pointer. */
3586 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3587 address of the current frame. Things might be easier if the
3588 ->frame pointed to the outer-most address of the frame. In
3589 the mean time, the address of the prev frame is used as the
3590 base address of this frame. */
3591 cache
->base
= get_frame_register_unsigned
3592 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3594 catch (const gdb_exception_error
&ex
)
3596 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3598 return (struct rs6000_frame_cache
*) (*this_cache
);
3601 /* If the function appears to be frameless, check a couple of likely
3602 indicators that we have simply failed to find the frame setup.
3603 Two common cases of this are missing symbols (i.e.
3604 get_frame_func returns the wrong address or 0), and assembly
3605 stubs which have a fast exit path but set up a frame on the slow
3608 If the LR appears to return to this function, then presume that
3609 we have an ABI compliant frame that we failed to find. */
3610 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3615 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3616 if (func
== 0 && saved_lr
== pc
)
3620 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3621 if (func
== saved_func
)
3627 fdata
.frameless
= 0;
3628 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3632 if (!fdata
.frameless
)
3634 /* Frameless really means stackless. */
3637 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3638 byte_order
, &backchain
))
3639 cache
->base
= (CORE_ADDR
) backchain
;
3642 cache
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->base
);
3644 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3645 All fpr's from saved_fpr to fp31 are saved. */
3647 if (fdata
.saved_fpr
>= 0)
3650 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3652 /* If skip_prologue says floating-point registers were saved,
3653 but the current architecture has no floating-point registers,
3654 then that's strange. But we have no indices to even record
3655 the addresses under, so we just ignore it. */
3656 if (ppc_floating_point_unit_p (gdbarch
))
3657 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3659 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3664 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3665 All gpr's from saved_gpr to gpr31 are saved (except during the
3668 if (fdata
.saved_gpr
>= 0)
3671 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3672 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3674 if (fdata
.gpr_mask
& (1U << i
))
3675 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3676 gpr_addr
+= wordsize
;
3680 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3681 All vr's from saved_vr to vr31 are saved. */
3682 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3684 if (fdata
.saved_vr
>= 0)
3687 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3688 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3690 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3691 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3696 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3697 All vr's from saved_ev to ev31 are saved. ????? */
3698 if (tdep
->ppc_ev0_regnum
!= -1)
3700 if (fdata
.saved_ev
>= 0)
3703 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3704 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3706 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3708 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3709 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3711 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3716 /* If != 0, fdata.cr_offset is the offset from the frame that
3718 if (fdata
.cr_offset
!= 0)
3719 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3722 /* If != 0, fdata.lr_offset is the offset from the frame that
3724 if (fdata
.lr_offset
!= 0)
3725 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3727 else if (fdata
.lr_register
!= -1)
3728 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3729 /* The PC is found in the link register. */
3730 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3731 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3733 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3734 holds the VRSAVE. */
3735 if (fdata
.vrsave_offset
!= 0)
3736 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3737 + fdata
.vrsave_offset
);
3739 if (fdata
.alloca_reg
< 0)
3740 /* If no alloca register used, then fi->frame is the value of the
3741 %sp for this frame, and it is good enough. */
3743 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3746 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3753 rs6000_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3754 struct frame_id
*this_id
)
3756 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3761 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3765 /* This marks the outermost frame. */
3766 if (info
->base
== 0)
3769 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3772 static struct value
*
3773 rs6000_frame_prev_register (frame_info_ptr this_frame
,
3774 void **this_cache
, int regnum
)
3776 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3778 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3781 static const struct frame_unwind rs6000_frame_unwind
=
3785 default_frame_unwind_stop_reason
,
3786 rs6000_frame_this_id
,
3787 rs6000_frame_prev_register
,
3789 default_frame_sniffer
3792 /* Allocate and initialize a frame cache for an epilogue frame.
3793 SP is restored and prev-PC is stored in LR. */
3795 static struct rs6000_frame_cache
*
3796 rs6000_epilogue_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3798 struct rs6000_frame_cache
*cache
;
3799 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3800 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3803 return (struct rs6000_frame_cache
*) *this_cache
;
3805 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3806 (*this_cache
) = cache
;
3807 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3811 /* At this point the stack looks as if we just entered the
3812 function, and the return address is stored in LR. */
3815 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3816 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3819 cache
->initial_sp
= sp
;
3821 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)].set_value (lr
);
3823 catch (const gdb_exception_error
&ex
)
3825 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3832 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3833 Return the frame ID of an epilogue frame. */
3836 rs6000_epilogue_frame_this_id (frame_info_ptr this_frame
,
3837 void **this_cache
, struct frame_id
*this_id
)
3840 struct rs6000_frame_cache
*info
=
3841 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3843 pc
= get_frame_func (this_frame
);
3844 if (info
->base
== 0)
3845 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3847 (*this_id
) = frame_id_build (info
->base
, pc
);
3850 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3851 Return the register value of REGNUM in previous frame. */
3853 static struct value
*
3854 rs6000_epilogue_frame_prev_register (frame_info_ptr this_frame
,
3855 void **this_cache
, int regnum
)
3857 struct rs6000_frame_cache
*info
=
3858 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3859 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3862 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3863 Check whether this an epilogue frame. */
3866 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3867 frame_info_ptr this_frame
,
3868 void **this_prologue_cache
)
3870 if (frame_relative_level (this_frame
) == 0)
3871 return rs6000_in_function_epilogue_frame_p (this_frame
,
3872 get_frame_arch (this_frame
),
3873 get_frame_pc (this_frame
));
3878 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3879 a function without debug information. */
3881 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3885 default_frame_unwind_stop_reason
,
3886 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3888 rs6000_epilogue_frame_sniffer
3893 rs6000_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
3895 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3897 return info
->initial_sp
;
3900 static const struct frame_base rs6000_frame_base
= {
3901 &rs6000_frame_unwind
,
3902 rs6000_frame_base_address
,
3903 rs6000_frame_base_address
,
3904 rs6000_frame_base_address
3907 static const struct frame_base
*
3908 rs6000_frame_base_sniffer (frame_info_ptr this_frame
)
3910 return &rs6000_frame_base
;
3913 /* DWARF-2 frame support. Used to handle the detection of
3914 clobbered registers during function calls. */
3917 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3918 struct dwarf2_frame_state_reg
*reg
,
3919 frame_info_ptr this_frame
)
3921 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3923 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3924 non-volatile registers. We will use the same code for both. */
3926 /* Call-saved GP registers. */
3927 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3928 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3929 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3930 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3932 /* Call-clobbered GP registers. */
3933 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3934 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3935 || (regnum
== tdep
->ppc_gp0_regnum
))
3936 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3938 /* Deal with FP registers, if supported. */
3939 if (tdep
->ppc_fp0_regnum
>= 0)
3941 /* Call-saved FP registers. */
3942 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3943 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3944 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3946 /* Call-clobbered FP registers. */
3947 if ((regnum
>= tdep
->ppc_fp0_regnum
3948 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3949 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3952 /* Deal with ALTIVEC registers, if supported. */
3953 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3955 /* Call-saved Altivec registers. */
3956 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3957 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3958 || regnum
== tdep
->ppc_vrsave_regnum
)
3959 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3961 /* Call-clobbered Altivec registers. */
3962 if ((regnum
>= tdep
->ppc_vr0_regnum
3963 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3964 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3967 /* Handle PC register and Stack Pointer correctly. */
3968 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3969 reg
->how
= DWARF2_FRAME_REG_RA
;
3970 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3971 reg
->how
= DWARF2_FRAME_REG_CFA
;
3975 /* Return true if a .gnu_attributes section exists in BFD and it
3976 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3977 section exists in BFD and it indicates that SPE extensions are in
3978 use. Check the .gnu.attributes section first, as the binary might be
3979 compiled for SPE, but not actually using SPE instructions. */
3982 bfd_uses_spe_extensions (bfd
*abfd
)
3985 gdb_byte
*contents
= NULL
;
3994 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3995 could be using the SPE vector abi without actually using any spe
3996 bits whatsoever. But it's close enough for now. */
3997 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3998 Tag_GNU_Power_ABI_Vector
);
3999 if (vector_abi
== 3)
4003 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
4007 size
= bfd_section_size (sect
);
4008 contents
= (gdb_byte
*) xmalloc (size
);
4009 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
4015 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
4021 char name[name_len rounded up to 4-byte alignment];
4022 char data[data_len];
4025 Technically, there's only supposed to be one such structure in a
4026 given apuinfo section, but the linker is not always vigilant about
4027 merging apuinfo sections from input files. Just go ahead and parse
4028 them all, exiting early when we discover the binary uses SPE
4031 It's not specified in what endianness the information in this
4032 section is stored. Assume that it's the endianness of the BFD. */
4036 unsigned int name_len
;
4037 unsigned int data_len
;
4040 /* If we can't read the first three fields, we're done. */
4044 name_len
= bfd_get_32 (abfd
, ptr
);
4045 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
4046 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
4047 type
= bfd_get_32 (abfd
, ptr
+ 8);
4050 /* The name must be "APUinfo\0". */
4052 && strcmp ((const char *) ptr
, "APUinfo") != 0)
4056 /* The type must be 2. */
4060 /* The data is stored as a series of uint32. The upper half of
4061 each uint32 indicates the particular APU used and the lower
4062 half indicates the revision of that APU. We just care about
4065 /* Not 4-byte quantities. */
4071 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
4072 unsigned int apu
= apuinfo
>> 16;
4076 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4078 if (apu
== 0x100 || apu
== 0x101)
4093 /* These are macros for parsing instruction fields (I.1.6.28) */
4095 #define PPC_FIELD(value, from, len) \
4096 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4097 #define PPC_SEXT(v, bs) \
4098 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4099 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4100 - ((CORE_ADDR) 1 << ((bs) - 1)))
4101 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4102 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4103 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4104 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4105 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4106 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4107 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4108 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4109 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4110 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4111 | (PPC_FIELD (insn, 16, 5) << 5))
4112 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4113 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4114 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4115 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4116 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4117 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4118 #define PPC_OE(insn) PPC_BIT (insn, 21)
4119 #define PPC_RC(insn) PPC_BIT (insn, 31)
4120 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4121 #define PPC_LK(insn) PPC_BIT (insn, 31)
4122 #define PPC_TX(insn) PPC_BIT (insn, 31)
4123 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4125 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4126 #define PPC_XTp(insn) ((PPC_BIT (insn, 10) << 5) \
4127 | PPC_FIELD (insn, 6, 4) << 1)
4128 #define PPC_XSp(insn) ((PPC_BIT (insn, 10) << 5) \
4129 | PPC_FIELD (insn, 6, 4) << 1)
4130 #define PPC_XER_NB(xer) (xer & 0x7f)
4132 /* The following macros are for the prefixed instructions. */
4133 #define P_PPC_D(insn_prefix, insn_suffix) \
4134 PPC_SEXT (PPC_FIELD (insn_prefix, 14, 18) << 16 \
4135 | PPC_FIELD (insn_suffix, 16, 16), 34)
4136 #define P_PPC_TX5(insn_sufix) PPC_BIT (insn_suffix, 5)
4137 #define P_PPC_TX15(insn_suffix) PPC_BIT (insn_suffix, 15)
4138 #define P_PPC_XT(insn_suffix) ((PPC_TX (insn_suffix) << 5) \
4139 | PPC_T (insn_suffix))
4140 #define P_PPC_XT5(insn_suffix) ((P_PPC_TX5 (insn_suffix) << 5) \
4141 | PPC_T (insn_suffix))
4142 #define P_PPC_XT15(insn_suffix) \
4143 ((P_PPC_TX15 (insn_suffix) << 5) | PPC_T (insn_suffix))
4145 /* Record Vector-Scalar Registers.
4146 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4147 Otherwise, it's just a VR register. Record them accordingly. */
4150 ppc_record_vsr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
, int vsr
)
4152 if (vsr
< 0 || vsr
>= 64)
4157 if (tdep
->ppc_vr0_regnum
>= 0)
4158 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4162 if (tdep
->ppc_fp0_regnum
>= 0)
4163 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4164 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4165 record_full_arch_list_add_reg (regcache
,
4166 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4172 /* The ppc_record_ACC_fpscr() records the changes to the VSR registers
4173 modified by a floating point instruction. The ENTRY argument selects which
4174 of the eight AT entries needs to be recorded. The boolean SAVE_FPSCR
4175 argument is set to TRUE to indicate the FPSCR also needs to be recorded.
4176 The function returns 0 on success. */
4179 ppc_record_ACC_fpscr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
,
4180 int entry
, bool save_fpscr
)
4183 if (entry
< 0 || entry
>= 8)
4186 /* The ACC register file consists of 8 register entries, each register
4187 entry consist of four 128-bit rows.
4189 The ACC rows map to specific VSR registers.
4195 ACC[7][0] -> VSR[28]
4196 ACC[7][1] -> VSR[29]
4197 ACC[7][2] -> VSR[30]
4198 ACC[7][3] -> VSR[31]
4201 In ISA 3.1 the ACC is mapped on top of VSR[0] thru VSR[31].
4203 In the future, the ACC may be implemented as an independent register file
4204 rather than mapping on top of the VSRs. This will then require the ACC to
4205 be assigned its own register number and the ptrace interface to be able
4206 access the ACC. Note the ptrace interface for the ACC will also need to
4209 /* ACC maps over the same VSR space as the fp registers. */
4210 for (i
= 0; i
< 4; i
++)
4212 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
4214 record_full_arch_list_add_reg (regcache
,
4215 tdep
->ppc_vsr0_upper_regnum
4220 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4225 /* Parse and record instructions primary opcode-4 at ADDR.
4226 Return 0 if successful. */
4229 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4230 CORE_ADDR addr
, uint32_t insn
)
4232 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4233 int ext
= PPC_FIELD (insn
, 21, 11);
4234 int vra
= PPC_FIELD (insn
, 11, 5);
4238 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4239 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4240 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4241 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4242 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4244 case 20: /* Move To VSR Byte Mask Immediate opcode, b2 = 0,
4246 case 21: /* Move To VSR Byte Mask Immediate opcode, b2 = 1,
4248 case 23: /* Vector Multiply-Sum & write Carry-out Unsigned
4250 case 24: /* Vector Extract Double Unsigned Byte to VSR
4251 using GPR-specified Left-Index */
4252 case 25: /* Vector Extract Double Unsigned Byte to VSR
4253 using GPR-specified Right-Index */
4254 case 26: /* Vector Extract Double Unsigned Halfword to VSR
4255 using GPR-specified Left-Index */
4256 case 27: /* Vector Extract Double Unsigned Halfword to VSR
4257 using GPR-specified Right-Index */
4258 case 28: /* Vector Extract Double Unsigned Word to VSR
4259 using GPR-specified Left-Index */
4260 case 29: /* Vector Extract Double Unsigned Word to VSR
4261 using GPR-specified Right-Index */
4262 case 30: /* Vector Extract Double Unsigned Doubleword to VSR
4263 using GPR-specified Left-Index */
4264 case 31: /* Vector Extract Double Unsigned Doubleword to VSR
4265 using GPR-specified Right-Index */
4266 case 42: /* Vector Select */
4267 case 43: /* Vector Permute */
4268 case 59: /* Vector Permute Right-indexed */
4269 case 22: /* Vector Shift
4270 Left Double by Bit Immediate if insn[21] = 0
4271 Right Double by Bit Immediate if insn[21] = 1 */
4272 case 44: /* Vector Shift Left Double by Octet Immediate */
4273 case 45: /* Vector Permute and Exclusive-OR */
4274 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4275 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4276 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4277 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4278 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4279 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4280 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4281 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4282 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4283 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4284 case 46: /* Vector Multiply-Add Single-Precision */
4285 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4286 record_full_arch_list_add_reg (regcache
,
4287 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4290 case 48: /* Multiply-Add High Doubleword */
4291 case 49: /* Multiply-Add High Doubleword Unsigned */
4292 case 51: /* Multiply-Add Low Doubleword */
4293 record_full_arch_list_add_reg (regcache
,
4294 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4298 switch ((ext
& 0x1ff))
4301 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4302 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4303 && vra
!= 4 /* Decimal Convert To Zoned */
4304 && vra
!= 5 /* Decimal Convert To National */
4305 && vra
!= 6 /* Decimal Convert From Zoned */
4306 && vra
!= 7 /* Decimal Convert From National */
4307 && vra
!= 31) /* Decimal Set Sign */
4310 /* 5.16 Decimal Integer Arithmetic Instructions */
4311 case 1: /* Decimal Add Modulo */
4312 case 65: /* Decimal Subtract Modulo */
4314 case 193: /* Decimal Shift */
4315 case 129: /* Decimal Unsigned Shift */
4316 case 449: /* Decimal Shift and Round */
4318 case 257: /* Decimal Truncate */
4319 case 321: /* Decimal Unsigned Truncate */
4321 /* Bit-21 should be set. */
4322 if (!PPC_BIT (insn
, 21))
4325 record_full_arch_list_add_reg (regcache
,
4326 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4327 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4331 /* Bit-21 is used for RC */
4332 switch (ext
& 0x3ff)
4334 case 5: /* Vector Rotate Left Quadword */
4335 case 69: /* Vector Rotate Left Quadword then Mask Insert */
4336 case 325: /* Vector Rotate Left Quadword then AND with Mask */
4337 case 6: /* Vector Compare Equal To Unsigned Byte */
4338 case 70: /* Vector Compare Equal To Unsigned Halfword */
4339 case 134: /* Vector Compare Equal To Unsigned Word */
4340 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4341 case 774: /* Vector Compare Greater Than Signed Byte */
4342 case 838: /* Vector Compare Greater Than Signed Halfword */
4343 case 902: /* Vector Compare Greater Than Signed Word */
4344 case 967: /* Vector Compare Greater Than Signed Doubleword */
4345 case 903: /* Vector Compare Greater Than Signed Quadword */
4346 case 518: /* Vector Compare Greater Than Unsigned Byte */
4347 case 646: /* Vector Compare Greater Than Unsigned Word */
4348 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4349 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4350 case 647: /* Vector Compare Greater Than Unsigned Quadword */
4351 case 966: /* Vector Compare Bounds Single-Precision */
4352 case 198: /* Vector Compare Equal To Single-Precision */
4353 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4354 case 455: /* Vector Compare Equal Quadword */
4355 case 710: /* Vector Compare Greater Than Single-Precision */
4356 case 7: /* Vector Compare Not Equal Byte */
4357 case 71: /* Vector Compare Not Equal Halfword */
4358 case 135: /* Vector Compare Not Equal Word */
4359 case 263: /* Vector Compare Not Equal or Zero Byte */
4360 case 327: /* Vector Compare Not Equal or Zero Halfword */
4361 case 391: /* Vector Compare Not Equal or Zero Word */
4363 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4364 record_full_arch_list_add_reg (regcache
,
4365 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4369 switch (vra
) /* Bit-21 is used for RC */
4371 case 0: /* Vector String Isolate Byte Left-justified */
4372 case 1: /* Vector String Isolate Byte Right-justified */
4373 case 2: /* Vector String Isolate Halfword Left-justified */
4374 case 3: /* Vector String Isolate Halfword Right-justified */
4376 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4377 record_full_arch_list_add_reg (regcache
,
4378 tdep
->ppc_vr0_regnum
4388 case 0: /* Vector Count Leading Zero Least-Significant Bits
4390 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4392 record_full_arch_list_add_reg (regcache
,
4393 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4396 case 6: /* Vector Negate Word */
4397 case 7: /* Vector Negate Doubleword */
4398 case 8: /* Vector Parity Byte Word */
4399 case 9: /* Vector Parity Byte Doubleword */
4400 case 10: /* Vector Parity Byte Quadword */
4401 case 16: /* Vector Extend Sign Byte To Word */
4402 case 17: /* Vector Extend Sign Halfword To Word */
4403 case 24: /* Vector Extend Sign Byte To Doubleword */
4404 case 25: /* Vector Extend Sign Halfword To Doubleword */
4405 case 26: /* Vector Extend Sign Word To Doubleword */
4406 case 27: /* Vector Extend Sign Doubleword To Quadword */
4407 case 28: /* Vector Count Trailing Zeros Byte */
4408 case 29: /* Vector Count Trailing Zeros Halfword */
4409 case 30: /* Vector Count Trailing Zeros Word */
4410 case 31: /* Vector Count Trailing Zeros Doubleword */
4411 record_full_arch_list_add_reg (regcache
,
4412 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4421 case 0: /* Vector Expand Byte Mask */
4422 case 1: /* Vector Expand Halfword Mask */
4423 case 2: /* Vector Expand Word Mask */
4424 case 3: /* Vector Expand Doubleword Mask */
4425 case 4: /* Vector Expand Quadword Mask */
4426 case 16: /* Move to VSR Byte Mask */
4427 case 17: /* Move to VSR Halfword Mask */
4428 case 18: /* Move to VSR Word Mask */
4429 case 19: /* Move to VSR Doubleword Mask */
4430 case 20: /* Move to VSR Quadword Mask */
4431 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
4434 case 8: /* Vector Extract Byte Mask */
4435 case 9: /* Vector Extract Halfword Mask */
4436 case 10: /* Vector Extract Word Mask */
4437 case 11: /* Vector Extract Doubleword Mask */
4438 case 12: /* Vector Extract Quadword Mask */
4440 /* Ignore the MP bit in the LSB position of the vra value. */
4441 case 24: /* Vector Count Mask Bits Byte, MP = 0 */
4442 case 25: /* Vector Count Mask Bits Byte, MP = 1 */
4443 case 26: /* Vector Count Mask Bits Halfword, MP = 0 */
4444 case 27: /* Vector Count Mask Bits Halfword, MP = 1 */
4445 case 28: /* Vector Count Mask Bits Word, MP = 0 */
4446 case 29: /* Vector Count Mask Bits Word, MP = 1 */
4447 case 30: /* Vector Count Mask Bits Doubleword, MP = 0 */
4448 case 31: /* Vector Count Mask Bits Doubleword, MP = 1 */
4449 record_full_arch_list_add_reg (regcache
,
4450 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4451 record_full_arch_list_add_reg (regcache
,
4452 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4460 case 257: /* Vector Compare Unsigned Quadword */
4461 case 321: /* Vector Compare Signed Quadword */
4462 /* Comparison tests that always set CR field BF */
4463 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4464 record_full_arch_list_add_reg (regcache
,
4465 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4468 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4469 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4470 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4471 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4472 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4473 case 462: /* Vector Pack Signed Word Signed Saturate */
4474 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4475 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4476 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4477 case 512: /* Vector Add Unsigned Byte Saturate */
4478 case 576: /* Vector Add Unsigned Halfword Saturate */
4479 case 640: /* Vector Add Unsigned Word Saturate */
4480 case 768: /* Vector Add Signed Byte Saturate */
4481 case 832: /* Vector Add Signed Halfword Saturate */
4482 case 896: /* Vector Add Signed Word Saturate */
4483 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4484 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4485 case 1664: /* Vector Subtract Unsigned Word Saturate */
4486 case 1792: /* Vector Subtract Signed Byte Saturate */
4487 case 1856: /* Vector Subtract Signed Halfword Saturate */
4488 case 1920: /* Vector Subtract Signed Word Saturate */
4490 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4491 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4492 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4493 case 1672: /* Vector Sum across Half Signed Word Saturate */
4494 case 1928: /* Vector Sum across Signed Word Saturate */
4495 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4496 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4497 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4499 case 12: /* Vector Merge High Byte */
4500 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4501 case 76: /* Vector Merge High Halfword */
4502 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4503 case 140: /* Vector Merge High Word */
4504 case 268: /* Vector Merge Low Byte */
4505 case 332: /* Vector Merge Low Halfword */
4506 case 396: /* Vector Merge Low Word */
4507 case 397: /* Vector Clear Leftmost Bytes */
4508 case 461: /* Vector Clear Rightmost Bytes */
4509 case 526: /* Vector Unpack High Signed Byte */
4510 case 590: /* Vector Unpack High Signed Halfword */
4511 case 654: /* Vector Unpack Low Signed Byte */
4512 case 718: /* Vector Unpack Low Signed Halfword */
4513 case 782: /* Vector Pack Pixel */
4514 case 846: /* Vector Unpack High Pixel */
4515 case 974: /* Vector Unpack Low Pixel */
4516 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4517 case 1614: /* Vector Unpack High Signed Word */
4518 case 1676: /* Vector Merge Odd Word */
4519 case 1742: /* Vector Unpack Low Signed Word */
4520 case 1932: /* Vector Merge Even Word */
4521 case 524: /* Vector Splat Byte */
4522 case 588: /* Vector Splat Halfword */
4523 case 652: /* Vector Splat Word */
4524 case 780: /* Vector Splat Immediate Signed Byte */
4525 case 844: /* Vector Splat Immediate Signed Halfword */
4526 case 908: /* Vector Splat Immediate Signed Word */
4527 case 261: /* Vector Shift Left Quadword */
4528 case 452: /* Vector Shift Left */
4529 case 517: /* Vector Shift Right Quadword */
4530 case 708: /* Vector Shift Right */
4531 case 773: /* Vector Shift Right Algebraic Quadword */
4532 case 1036: /* Vector Shift Left by Octet */
4533 case 1100: /* Vector Shift Right by Octet */
4534 case 0: /* Vector Add Unsigned Byte Modulo */
4535 case 64: /* Vector Add Unsigned Halfword Modulo */
4536 case 128: /* Vector Add Unsigned Word Modulo */
4537 case 192: /* Vector Add Unsigned Doubleword Modulo */
4538 case 256: /* Vector Add Unsigned Quadword Modulo */
4539 case 320: /* Vector Add & write Carry Unsigned Quadword */
4540 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4541 case 8: /* Vector Multiply Odd Unsigned Byte */
4542 case 72: /* Vector Multiply Odd Unsigned Halfword */
4543 case 136: /* Vector Multiply Odd Unsigned Word */
4544 case 200: /* Vector Multiply Odd Unsigned Doubleword */
4545 case 264: /* Vector Multiply Odd Signed Byte */
4546 case 328: /* Vector Multiply Odd Signed Halfword */
4547 case 392: /* Vector Multiply Odd Signed Word */
4548 case 456: /* Vector Multiply Odd Signed Doubleword */
4549 case 520: /* Vector Multiply Even Unsigned Byte */
4550 case 584: /* Vector Multiply Even Unsigned Halfword */
4551 case 648: /* Vector Multiply Even Unsigned Word */
4552 case 712: /* Vector Multiply Even Unsigned Doubleword */
4553 case 776: /* Vector Multiply Even Signed Byte */
4554 case 840: /* Vector Multiply Even Signed Halfword */
4555 case 904: /* Vector Multiply Even Signed Word */
4556 case 968: /* Vector Multiply Even Signed Doubleword */
4557 case 457: /* Vector Multiply Low Doubleword */
4558 case 649: /* Vector Multiply High Unsigned Word */
4559 case 713: /* Vector Multiply High Unsigned Doubleword */
4560 case 905: /* Vector Multiply High Signed Word */
4561 case 969: /* Vector Multiply High Signed Doubleword */
4562 case 11: /* Vector Divide Unsigned Quadword */
4563 case 203: /* Vector Divide Unsigned Doubleword */
4564 case 139: /* Vector Divide Unsigned Word */
4565 case 267: /* Vector Divide Signed Quadword */
4566 case 459: /* Vector Divide Signed Doubleword */
4567 case 395: /* Vector Divide Signed Word */
4568 case 523: /* Vector Divide Extended Unsigned Quadword */
4569 case 715: /* Vector Divide Extended Unsigned Doubleword */
4570 case 651: /* Vector Divide Extended Unsigned Word */
4571 case 779: /* Vector Divide Extended Signed Quadword */
4572 case 971: /* Vector Divide Extended Signed Doubleword */
4573 case 907: /* Vector Divide Extended Unsigned Word */
4574 case 1547: /* Vector Modulo Unsigned Quadword */
4575 case 1675: /* Vector Modulo Unsigned Word */
4576 case 1739: /* Vector Modulo Unsigned Doubleword */
4577 case 1803: /* Vector Modulo Signed Quadword */
4578 case 1931: /* Vector Modulo Signed Word */
4579 case 1995: /* Vector Modulo Signed Doubleword */
4581 case 137: /* Vector Multiply Unsigned Word Modulo */
4582 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4583 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4584 case 1152: /* Vector Subtract Unsigned Word Modulo */
4585 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4586 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4587 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4588 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4589 case 1282: /* Vector Average Signed Byte */
4590 case 1346: /* Vector Average Signed Halfword */
4591 case 1410: /* Vector Average Signed Word */
4592 case 1026: /* Vector Average Unsigned Byte */
4593 case 1090: /* Vector Average Unsigned Halfword */
4594 case 1154: /* Vector Average Unsigned Word */
4595 case 258: /* Vector Maximum Signed Byte */
4596 case 322: /* Vector Maximum Signed Halfword */
4597 case 386: /* Vector Maximum Signed Word */
4598 case 450: /* Vector Maximum Signed Doubleword */
4599 case 2: /* Vector Maximum Unsigned Byte */
4600 case 66: /* Vector Maximum Unsigned Halfword */
4601 case 130: /* Vector Maximum Unsigned Word */
4602 case 194: /* Vector Maximum Unsigned Doubleword */
4603 case 770: /* Vector Minimum Signed Byte */
4604 case 834: /* Vector Minimum Signed Halfword */
4605 case 898: /* Vector Minimum Signed Word */
4606 case 962: /* Vector Minimum Signed Doubleword */
4607 case 514: /* Vector Minimum Unsigned Byte */
4608 case 578: /* Vector Minimum Unsigned Halfword */
4609 case 642: /* Vector Minimum Unsigned Word */
4610 case 706: /* Vector Minimum Unsigned Doubleword */
4611 case 1028: /* Vector Logical AND */
4612 case 1668: /* Vector Logical Equivalent */
4613 case 1092: /* Vector Logical AND with Complement */
4614 case 1412: /* Vector Logical NAND */
4615 case 1348: /* Vector Logical OR with Complement */
4616 case 1156: /* Vector Logical OR */
4617 case 1284: /* Vector Logical NOR */
4618 case 1220: /* Vector Logical XOR */
4619 case 4: /* Vector Rotate Left Byte */
4620 case 132: /* Vector Rotate Left Word VX-form */
4621 case 68: /* Vector Rotate Left Halfword */
4622 case 196: /* Vector Rotate Left Doubleword */
4623 case 260: /* Vector Shift Left Byte */
4624 case 388: /* Vector Shift Left Word */
4625 case 324: /* Vector Shift Left Halfword */
4626 case 1476: /* Vector Shift Left Doubleword */
4627 case 516: /* Vector Shift Right Byte */
4628 case 644: /* Vector Shift Right Word */
4629 case 580: /* Vector Shift Right Halfword */
4630 case 1732: /* Vector Shift Right Doubleword */
4631 case 772: /* Vector Shift Right Algebraic Byte */
4632 case 900: /* Vector Shift Right Algebraic Word */
4633 case 836: /* Vector Shift Right Algebraic Halfword */
4634 case 964: /* Vector Shift Right Algebraic Doubleword */
4635 case 10: /* Vector Add Single-Precision */
4636 case 74: /* Vector Subtract Single-Precision */
4637 case 1034: /* Vector Maximum Single-Precision */
4638 case 1098: /* Vector Minimum Single-Precision */
4639 case 842: /* Vector Convert From Signed Fixed-Point Word */
4640 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4641 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4642 case 522: /* Vector Round to Single-Precision Integer Nearest */
4643 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4644 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4645 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4646 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4647 case 266: /* Vector Reciprocal Estimate Single-Precision */
4648 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4649 case 1288: /* Vector AES Cipher */
4650 case 1289: /* Vector AES Cipher Last */
4651 case 1352: /* Vector AES Inverse Cipher */
4652 case 1353: /* Vector AES Inverse Cipher Last */
4653 case 1480: /* Vector AES SubBytes */
4654 case 1730: /* Vector SHA-512 Sigma Doubleword */
4655 case 1666: /* Vector SHA-256 Sigma Word */
4656 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4657 case 1160: /* Vector Polynomial Multiply-Sum Word */
4658 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4659 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4660 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4661 case 1794: /* Vector Count Leading Zeros Byte */
4662 case 1858: /* Vector Count Leading Zeros Halfword */
4663 case 1922: /* Vector Count Leading Zeros Word */
4664 case 1924: /* Vector Count Leading Zeros Doubleword under
4666 case 1986: /* Vector Count Leading Zeros Doubleword */
4667 case 1988: /* Vector Count Trailing Zeros Doubleword under bit
4669 case 1795: /* Vector Population Count Byte */
4670 case 1859: /* Vector Population Count Halfword */
4671 case 1923: /* Vector Population Count Word */
4672 case 1987: /* Vector Population Count Doubleword */
4673 case 1356: /* Vector Bit Permute Quadword */
4674 case 1484: /* Vector Bit Permute Doubleword */
4675 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4676 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4678 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4679 case 65: /* Vector Multiply-by-10 Extended & write Carry
4680 Unsigned Quadword */
4681 case 1027: /* Vector Absolute Difference Unsigned Byte */
4682 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4683 case 1155: /* Vector Absolute Difference Unsigned Word */
4684 case 1796: /* Vector Shift Right Variable */
4685 case 1860: /* Vector Shift Left Variable */
4686 case 133: /* Vector Rotate Left Word then Mask Insert */
4687 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4688 case 389: /* Vector Rotate Left Word then AND with Mask */
4689 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4690 case 525: /* Vector Extract Unsigned Byte */
4691 case 589: /* Vector Extract Unsigned Halfword */
4692 case 653: /* Vector Extract Unsigned Word */
4693 case 717: /* Vector Extract Doubleword */
4694 case 15: /* Vector Insert Byte from VSR using GPR-specified
4696 case 79: /* Vector Insert Halfword from VSR using GPR-specified
4698 case 143: /* Vector Insert Word from VSR using GPR-specified
4700 case 207: /* Vector Insert Word from GPR using
4701 immediate-specified index */
4702 case 463: /* Vector Insert Doubleword from GPR using
4703 immediate-specified index */
4704 case 271: /* Vector Insert Byte from VSR using GPR-specified
4706 case 335: /* Vector Insert Halfword from VSR using GPR-specified
4708 case 399: /* Vector Insert Word from VSR using GPR-specified
4710 case 527: /* Vector Insert Byte from GPR using GPR-specified
4712 case 591: /* Vector Insert Halfword from GPR using GPR-specified
4714 case 655: /* Vector Insert Word from GPR using GPR-specified
4716 case 719: /* Vector Insert Doubleword from GPR using
4717 GPR-specified Left-Index */
4718 case 783: /* Vector Insert Byte from GPR using GPR-specified
4720 case 847: /* Vector Insert Halfword from GPR using GPR-specified
4722 case 911: /* Vector Insert Word from GPR using GPR-specified
4724 case 975: /* Vector Insert Doubleword from GPR using
4725 GPR-specified Right-Index */
4726 case 781: /* Vector Insert Byte */
4727 case 845: /* Vector Insert Halfword */
4728 case 909: /* Vector Insert Word */
4729 case 973: /* Vector Insert Doubleword */
4730 case 1357: /* Vector Centrifuge Doubleword */
4731 case 1421: /* Vector Parallel Bits Extract Doubleword */
4732 case 1485: /* Vector Parallel Bits Deposit Doubleword */
4733 record_full_arch_list_add_reg (regcache
,
4734 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4737 case 1228: /* Vector Gather every Nth Bit */
4738 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4739 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4740 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4741 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4742 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4743 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4744 record_full_arch_list_add_reg (regcache
,
4745 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4748 case 1604: /* Move To Vector Status and Control Register */
4749 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4751 case 1540: /* Move From Vector Status and Control Register */
4752 record_full_arch_list_add_reg (regcache
,
4753 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4755 case 833: /* Decimal Copy Sign */
4756 record_full_arch_list_add_reg (regcache
,
4757 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4758 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4762 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
4763 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4767 /* Parse and record instructions of primary opcode 6 at ADDR.
4768 Return 0 if successful. */
4771 ppc_process_record_op6 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4772 CORE_ADDR addr
, uint32_t insn
)
4774 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4775 int subtype
= PPC_FIELD (insn
, 28, 4);
4780 case 0: /* Load VSX Vector Paired */
4781 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
));
4782 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
) + 1);
4784 case 1: /* Store VSX Vector Paired */
4785 if (PPC_RA (insn
) != 0)
4786 regcache_raw_read_unsigned (regcache
,
4787 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ea
);
4788 ea
+= PPC_DQ (insn
) << 4;
4789 record_full_arch_list_add_mem (ea
, 32);
4795 /* Parse and record instructions of primary opcode-19 at ADDR.
4796 Return 0 if successful. */
4799 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4800 CORE_ADDR addr
, uint32_t insn
)
4802 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4803 int ext
= PPC_EXTOP (insn
);
4805 switch (ext
& 0x01f)
4807 case 2: /* Add PC Immediate Shifted */
4808 record_full_arch_list_add_reg (regcache
,
4809 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4815 case 0: /* Move Condition Register Field */
4816 case 33: /* Condition Register NOR */
4817 case 129: /* Condition Register AND with Complement */
4818 case 193: /* Condition Register XOR */
4819 case 225: /* Condition Register NAND */
4820 case 257: /* Condition Register AND */
4821 case 289: /* Condition Register Equivalent */
4822 case 417: /* Condition Register OR with Complement */
4823 case 449: /* Condition Register OR */
4824 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4827 case 16: /* Branch Conditional */
4828 case 560: /* Branch Conditional to Branch Target Address Register */
4829 if ((PPC_BO (insn
) & 0x4) == 0)
4830 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4832 case 528: /* Branch Conditional to Count Register */
4834 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4837 case 150: /* Instruction Synchronize */
4842 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
4843 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4847 /* Parse and record instructions of primary opcode-31 with the extended opcode
4848 177. The argument is the word instruction (insn). Return 0 if successful.
4852 ppc_process_record_op31_177 (struct gdbarch
*gdbarch
,
4853 struct regcache
*regcache
,
4856 int RA_opcode
= PPC_RA(insn
);
4857 int as
= PPC_FIELD (insn
, 6, 3);
4858 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4862 case 0: /* VSX Move From Accumulator, xxmfacc */
4863 case 1: /* VSX Move To Accumulator, xxmtacc */
4864 case 3: /* VSX Set Accumulator to Zero, xxsetaccz */
4865 ppc_record_ACC_fpscr (regcache
, tdep
, as
, false);
4871 /* Parse and record instructions of primary opcode-31 at ADDR.
4872 Return 0 if successful. */
4875 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4876 CORE_ADDR addr
, uint32_t insn
)
4878 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4879 int ext
= PPC_EXTOP (insn
);
4880 int tmp
, nr
, nb
= 0, i
;
4881 CORE_ADDR at_dcsz
, ea
= 0;
4882 ULONGEST rb
, ra
, xer
;
4885 /* These instructions have OE bit. */
4886 switch (ext
& 0x1ff)
4888 /* These write RT and XER. Update CR if RC is set. */
4889 case 8: /* Subtract from carrying */
4890 case 10: /* Add carrying */
4891 case 136: /* Subtract from extended */
4892 case 138: /* Add extended */
4893 case 200: /* Subtract from zero extended */
4894 case 202: /* Add to zero extended */
4895 case 232: /* Subtract from minus one extended */
4896 case 234: /* Add to minus one extended */
4897 /* CA is always altered, but SO/OV are only altered when OE=1.
4898 In any case, XER is always altered. */
4899 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4901 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4902 record_full_arch_list_add_reg (regcache
,
4903 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4906 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4907 case 40: /* Subtract from */
4908 case 104: /* Negate */
4909 case 233: /* Multiply low doubleword */
4910 case 235: /* Multiply low word */
4912 case 393: /* Divide Doubleword Extended Unsigned */
4913 case 395: /* Divide Word Extended Unsigned */
4914 case 425: /* Divide Doubleword Extended */
4915 case 427: /* Divide Word Extended */
4916 case 457: /* Divide Doubleword Unsigned */
4917 case 459: /* Divide Word Unsigned */
4918 case 489: /* Divide Doubleword */
4919 case 491: /* Divide Word */
4921 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4923 case 9: /* Multiply High Doubleword Unsigned */
4924 case 11: /* Multiply High Word Unsigned */
4925 case 73: /* Multiply High Doubleword */
4926 case 75: /* Multiply High Word */
4928 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4929 record_full_arch_list_add_reg (regcache
,
4930 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4934 if ((ext
& 0x1f) == 15)
4936 /* Integer Select. bit[16:20] is used for BC. */
4937 record_full_arch_list_add_reg (regcache
,
4938 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4942 if ((ext
& 0xff) == 170)
4944 /* Add Extended using alternate carry bits */
4945 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4946 record_full_arch_list_add_reg (regcache
,
4947 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4953 case 78: /* Determine Leftmost Zero Byte */
4955 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4956 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4957 record_full_arch_list_add_reg (regcache
,
4958 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4961 /* These only write RT. */
4962 case 19: /* Move from condition register */
4963 /* Move From One Condition Register Field */
4964 case 74: /* Add and Generate Sixes */
4965 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4966 case 302: /* Move From Branch History Rolling Buffer */
4967 case 339: /* Move From Special Purpose Register */
4968 case 371: /* Move From Time Base [Phased-Out] */
4969 case 309: /* Load Doubleword Monitored Indexed */
4970 case 128: /* Set Boolean */
4971 case 384: /* Set Boolean Condition */
4972 case 416: /* Set Boolean Condition Reverse */
4973 case 448: /* Set Negative Boolean Condition */
4974 case 480: /* Set Negative Boolean Condition Reverse */
4975 case 755: /* Deliver A Random Number */
4976 record_full_arch_list_add_reg (regcache
,
4977 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4980 /* These only write to RA. */
4981 case 51: /* Move From VSR Doubleword */
4982 case 59: /* Count Leading Zeros Doubleword under bit Mask */
4983 case 115: /* Move From VSR Word and Zero */
4984 case 122: /* Population count bytes */
4985 case 155: /* Byte-Reverse Word */
4986 case 156: /* Parallel Bits Deposit Doubleword */
4987 case 187: /* Byte-Reverse Doubleword */
4988 case 188: /* Parallel Bits Extract Doubleword */
4989 case 219: /* Byte-Reverse Halfword */
4990 case 220: /* Centrifuge Doubleword */
4991 case 378: /* Population count words */
4992 case 506: /* Population count doublewords */
4993 case 154: /* Parity Word */
4994 case 186: /* Parity Doubleword */
4995 case 252: /* Bit Permute Doubleword */
4996 case 282: /* Convert Declets To Binary Coded Decimal */
4997 case 314: /* Convert Binary Coded Decimal To Declets */
4998 case 508: /* Compare bytes */
4999 case 307: /* Move From VSR Lower Doubleword */
5000 case 571: /* Count Trailing Zeros Doubleword under bit Mask */
5001 record_full_arch_list_add_reg (regcache
,
5002 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5005 /* These write CR and optional RA. */
5006 case 792: /* Shift Right Algebraic Word */
5007 case 794: /* Shift Right Algebraic Doubleword */
5008 case 824: /* Shift Right Algebraic Word Immediate */
5009 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
5010 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
5011 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5012 record_full_arch_list_add_reg (regcache
,
5013 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5015 case 0: /* Compare */
5016 case 32: /* Compare logical */
5017 case 144: /* Move To Condition Register Fields */
5018 /* Move To One Condition Register Field */
5019 case 192: /* Compare Ranged Byte */
5020 case 224: /* Compare Equal Byte */
5021 case 576: /* Move XER to CR Extended */
5022 case 902: /* Paste (should always fail due to single-stepping and
5023 the memory location might not be accessible, so
5025 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5028 /* These write to RT. Update RA if 'update indexed.' */
5029 case 53: /* Load Doubleword with Update Indexed */
5030 case 119: /* Load Byte and Zero with Update Indexed */
5031 case 311: /* Load Halfword and Zero with Update Indexed */
5032 case 55: /* Load Word and Zero with Update Indexed */
5033 case 375: /* Load Halfword Algebraic with Update Indexed */
5034 case 373: /* Load Word Algebraic with Update Indexed */
5035 record_full_arch_list_add_reg (regcache
,
5036 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5038 case 21: /* Load Doubleword Indexed */
5039 case 52: /* Load Byte And Reserve Indexed */
5040 case 116: /* Load Halfword And Reserve Indexed */
5041 case 20: /* Load Word And Reserve Indexed */
5042 case 84: /* Load Doubleword And Reserve Indexed */
5043 case 87: /* Load Byte and Zero Indexed */
5044 case 279: /* Load Halfword and Zero Indexed */
5045 case 23: /* Load Word and Zero Indexed */
5046 case 343: /* Load Halfword Algebraic Indexed */
5047 case 341: /* Load Word Algebraic Indexed */
5048 case 790: /* Load Halfword Byte-Reverse Indexed */
5049 case 534: /* Load Word Byte-Reverse Indexed */
5050 case 532: /* Load Doubleword Byte-Reverse Indexed */
5051 case 582: /* Load Word Atomic */
5052 case 614: /* Load Doubleword Atomic */
5053 case 265: /* Modulo Unsigned Doubleword */
5054 case 777: /* Modulo Signed Doubleword */
5055 case 267: /* Modulo Unsigned Word */
5056 case 779: /* Modulo Signed Word */
5057 record_full_arch_list_add_reg (regcache
,
5058 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5061 case 597: /* Load String Word Immediate */
5062 case 533: /* Load String Word Indexed */
5071 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5072 nr
= PPC_XER_NB (xer
);
5077 /* If n=0, the contents of register RT are undefined. */
5081 for (i
= 0; i
< nr
; i
++)
5082 record_full_arch_list_add_reg (regcache
,
5083 tdep
->ppc_gp0_regnum
5084 + ((PPC_RT (insn
) + i
) & 0x1f));
5087 case 276: /* Load Quadword And Reserve Indexed */
5088 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5089 record_full_arch_list_add_reg (regcache
, tmp
);
5090 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5093 /* These write VRT. */
5094 case 6: /* Load Vector for Shift Left Indexed */
5095 case 38: /* Load Vector for Shift Right Indexed */
5096 case 7: /* Load Vector Element Byte Indexed */
5097 case 39: /* Load Vector Element Halfword Indexed */
5098 case 71: /* Load Vector Element Word Indexed */
5099 case 103: /* Load Vector Indexed */
5100 case 359: /* Load Vector Indexed LRU */
5101 record_full_arch_list_add_reg (regcache
,
5102 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
5105 /* These write FRT. Update RA if 'update indexed.' */
5106 case 567: /* Load Floating-Point Single with Update Indexed */
5107 case 631: /* Load Floating-Point Double with Update Indexed */
5108 record_full_arch_list_add_reg (regcache
,
5109 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5111 case 535: /* Load Floating-Point Single Indexed */
5112 case 599: /* Load Floating-Point Double Indexed */
5113 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
5114 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
5115 record_full_arch_list_add_reg (regcache
,
5116 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5119 case 791: /* Load Floating-Point Double Pair Indexed */
5120 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5121 record_full_arch_list_add_reg (regcache
, tmp
);
5122 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5125 /* These write to destination register PPC_XT. */
5126 case 179: /* Move To VSR Doubleword */
5127 case 211: /* Move To VSR Word Algebraic */
5128 case 243: /* Move To VSR Word and Zero */
5129 case 588: /* Load VSX Scalar Doubleword Indexed */
5130 case 524: /* Load VSX Scalar Single-Precision Indexed */
5131 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
5132 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
5133 case 13: /* Load VSX Vector Rightmost Byte Indexed */
5134 case 45: /* Load VSX Vector Rightmost Halfword Indexed */
5135 case 77: /* Load VSX Vector Rightmost Word Indexed */
5136 case 109: /* Load VSX Vector Rightmost Doubleword Indexed */
5137 case 844: /* Load VSX Vector Doubleword*2 Indexed */
5138 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
5139 case 780: /* Load VSX Vector Word*4 Indexed */
5140 case 268: /* Load VSX Vector Indexed */
5141 case 364: /* Load VSX Vector Word & Splat Indexed */
5142 case 812: /* Load VSX Vector Halfword*8 Indexed */
5143 case 876: /* Load VSX Vector Byte*16 Indexed */
5144 case 269: /* Load VSX Vector with Length */
5145 case 301: /* Load VSX Vector Left-justified with Length */
5146 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
5147 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
5148 case 403: /* Move To VSR Word & Splat */
5149 case 435: /* Move To VSR Double Doubleword */
5150 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5153 case 333: /* Load VSX Vector Paired Indexed */
5154 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
));
5155 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
) + 1);
5158 /* These write RA. Update CR if RC is set. */
5159 case 24: /* Shift Left Word */
5160 case 26: /* Count Leading Zeros Word */
5161 case 27: /* Shift Left Doubleword */
5163 case 58: /* Count Leading Zeros Doubleword */
5164 case 60: /* AND with Complement */
5166 case 284: /* Equivalent */
5168 case 476: /* NAND */
5169 case 412: /* OR with Complement */
5171 case 536: /* Shift Right Word */
5172 case 539: /* Shift Right Doubleword */
5173 case 922: /* Extend Sign Halfword */
5174 case 954: /* Extend Sign Byte */
5175 case 986: /* Extend Sign Word */
5176 case 538: /* Count Trailing Zeros Word */
5177 case 570: /* Count Trailing Zeros Doubleword */
5178 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
5179 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
5181 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
5182 && (PPC_RS (insn
) == PPC_RA (insn
))
5183 && (PPC_RA (insn
) == PPC_RB (insn
))
5186 /* or Rx,Rx,Rx alters PRI in PPR. */
5187 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5192 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5193 record_full_arch_list_add_reg (regcache
,
5194 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5198 case 181: /* Store Doubleword with Update Indexed */
5199 case 183: /* Store Word with Update Indexed */
5200 case 247: /* Store Byte with Update Indexed */
5201 case 439: /* Store Half Word with Update Indexed */
5202 case 695: /* Store Floating-Point Single with Update Indexed */
5203 case 759: /* Store Floating-Point Double with Update Indexed */
5204 record_full_arch_list_add_reg (regcache
,
5205 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5207 case 135: /* Store Vector Element Byte Indexed */
5208 case 167: /* Store Vector Element Halfword Indexed */
5209 case 199: /* Store Vector Element Word Indexed */
5210 case 231: /* Store Vector Indexed */
5211 case 487: /* Store Vector Indexed LRU */
5212 case 716: /* Store VSX Scalar Doubleword Indexed */
5213 case 140: /* Store VSX Scalar as Integer Word Indexed */
5214 case 652: /* Store VSX Scalar Single-Precision Indexed */
5215 case 972: /* Store VSX Vector Doubleword*2 Indexed */
5216 case 908: /* Store VSX Vector Word*4 Indexed */
5217 case 149: /* Store Doubleword Indexed */
5218 case 151: /* Store Word Indexed */
5219 case 215: /* Store Byte Indexed */
5220 case 407: /* Store Half Word Indexed */
5221 case 694: /* Store Byte Conditional Indexed */
5222 case 726: /* Store Halfword Conditional Indexed */
5223 case 150: /* Store Word Conditional Indexed */
5224 case 214: /* Store Doubleword Conditional Indexed */
5225 case 182: /* Store Quadword Conditional Indexed */
5226 case 662: /* Store Word Byte-Reverse Indexed */
5227 case 918: /* Store Halfword Byte-Reverse Indexed */
5228 case 660: /* Store Doubleword Byte-Reverse Indexed */
5229 case 663: /* Store Floating-Point Single Indexed */
5230 case 727: /* Store Floating-Point Double Indexed */
5231 case 919: /* Store Floating-Point Double Pair Indexed */
5232 case 983: /* Store Floating-Point as Integer Word Indexed */
5233 case 396: /* Store VSX Vector Indexed */
5234 case 940: /* Store VSX Vector Halfword*8 Indexed */
5235 case 1004: /* Store VSX Vector Byte*16 Indexed */
5236 case 909: /* Store VSX Scalar as Integer Byte Indexed */
5237 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
5238 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
5239 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5242 if (PPC_RA (insn
) != 0)
5243 regcache_raw_read_unsigned (regcache
,
5244 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5245 regcache_raw_read_unsigned (regcache
,
5246 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5251 case 183: /* Store Word with Update Indexed */
5252 case 199: /* Store Vector Element Word Indexed */
5253 case 140: /* Store VSX Scalar as Integer Word Indexed */
5254 case 652: /* Store VSX Scalar Single-Precision Indexed */
5255 case 151: /* Store Word Indexed */
5256 case 150: /* Store Word Conditional Indexed */
5257 case 662: /* Store Word Byte-Reverse Indexed */
5258 case 663: /* Store Floating-Point Single Indexed */
5259 case 695: /* Store Floating-Point Single with Update Indexed */
5260 case 983: /* Store Floating-Point as Integer Word Indexed */
5263 case 247: /* Store Byte with Update Indexed */
5264 case 135: /* Store Vector Element Byte Indexed */
5265 case 215: /* Store Byte Indexed */
5266 case 694: /* Store Byte Conditional Indexed */
5267 case 909: /* Store VSX Scalar as Integer Byte Indexed */
5270 case 439: /* Store Halfword with Update Indexed */
5271 case 167: /* Store Vector Element Halfword Indexed */
5272 case 407: /* Store Halfword Indexed */
5273 case 726: /* Store Halfword Conditional Indexed */
5274 case 918: /* Store Halfword Byte-Reverse Indexed */
5275 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
5278 case 181: /* Store Doubleword with Update Indexed */
5279 case 716: /* Store VSX Scalar Doubleword Indexed */
5280 case 149: /* Store Doubleword Indexed */
5281 case 214: /* Store Doubleword Conditional Indexed */
5282 case 660: /* Store Doubleword Byte-Reverse Indexed */
5283 case 727: /* Store Floating-Point Double Indexed */
5284 case 759: /* Store Floating-Point Double with Update Indexed */
5287 case 972: /* Store VSX Vector Doubleword*2 Indexed */
5288 case 908: /* Store VSX Vector Word*4 Indexed */
5289 case 182: /* Store Quadword Conditional Indexed */
5290 case 231: /* Store Vector Indexed */
5291 case 487: /* Store Vector Indexed LRU */
5292 case 919: /* Store Floating-Point Double Pair Indexed */
5293 case 396: /* Store VSX Vector Indexed */
5294 case 940: /* Store VSX Vector Halfword*8 Indexed */
5295 case 1004: /* Store VSX Vector Byte*16 Indexed */
5302 /* Align address for Store Vector instructions. */
5305 case 167: /* Store Vector Element Halfword Indexed */
5309 case 199: /* Store Vector Element Word Indexed */
5313 case 231: /* Store Vector Indexed */
5314 case 487: /* Store Vector Indexed LRU */
5319 record_full_arch_list_add_mem (ea
, size
);
5322 case 141: /* Store VSX Vector Rightmost Byte Indexed */
5323 case 173: /* Store VSX Vector Rightmost Halfword Indexed */
5324 case 205: /* Store VSX Vector Rightmost Word Indexed */
5325 case 237: /* Store VSX Vector Rightmost Doubleword Indexed */
5338 if (PPC_RA (insn
) != 0)
5339 regcache_raw_read_unsigned (regcache
,
5340 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5341 regcache_raw_read_unsigned (regcache
,
5342 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5344 record_full_arch_list_add_mem (ea
, nb
);
5347 case 397: /* Store VSX Vector with Length */
5348 case 429: /* Store VSX Vector Left-justified with Length */
5350 if (PPC_RA (insn
) != 0)
5351 regcache_raw_read_unsigned (regcache
,
5352 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5354 regcache_raw_read_unsigned (regcache
,
5355 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5356 /* Store up to 16 bytes. */
5357 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
5359 record_full_arch_list_add_mem (ea
, nb
);
5362 case 461: /* Store VSX Vector Paired Indexed */
5364 if (PPC_RA (insn
) != 0)
5365 regcache_raw_read_unsigned (regcache
,
5366 tdep
->ppc_gp0_regnum
5367 + PPC_RA (insn
), &ea
);
5368 regcache_raw_read_unsigned (regcache
,
5369 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5371 record_full_arch_list_add_mem (ea
, 32);
5375 case 710: /* Store Word Atomic */
5376 case 742: /* Store Doubleword Atomic */
5378 if (PPC_RA (insn
) != 0)
5379 regcache_raw_read_unsigned (regcache
,
5380 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5384 case 710: /* Store Word Atomic */
5387 case 742: /* Store Doubleword Atomic */
5393 record_full_arch_list_add_mem (ea
, size
);
5396 case 725: /* Store String Word Immediate */
5398 if (PPC_RA (insn
) != 0)
5399 regcache_raw_read_unsigned (regcache
,
5400 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5407 record_full_arch_list_add_mem (ea
, nb
);
5411 case 661: /* Store String Word Indexed */
5413 if (PPC_RA (insn
) != 0)
5414 regcache_raw_read_unsigned (regcache
,
5415 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5418 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5419 nb
= PPC_XER_NB (xer
);
5423 regcache_raw_read_unsigned (regcache
,
5424 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
5427 record_full_arch_list_add_mem (ea
, nb
);
5432 case 467: /* Move To Special Purpose Register */
5433 switch (PPC_SPR (insn
))
5436 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5439 if (tdep
->ppc_dscr_regnum
>= 0)
5440 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5443 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5446 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5448 case 256: /* VRSAVE */
5449 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5452 if (tdep
->ppc_tar_regnum
>= 0)
5453 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5457 if (tdep
->ppc_ppr_regnum
>= 0)
5458 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5464 case 147: /* Move To Split Little Endian */
5465 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5468 case 512: /* Move to Condition Register from XER */
5469 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5470 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5473 case 4: /* Trap Word */
5474 case 68: /* Trap Doubleword */
5475 case 430: /* Clear BHRB */
5476 case 598: /* Synchronize */
5477 case 62: /* Wait for Interrupt */
5479 case 22: /* Instruction Cache Block Touch */
5480 case 854: /* Enforce In-order Execution of I/O */
5481 case 246: /* Data Cache Block Touch for Store */
5482 case 54: /* Data Cache Block Store */
5483 case 86: /* Data Cache Block Flush */
5484 case 278: /* Data Cache Block Touch */
5485 case 758: /* Data Cache Block Allocate */
5486 case 982: /* Instruction Cache Block Invalidate */
5487 case 774: /* Copy */
5488 case 838: /* CP_Abort */
5491 case 654: /* Transaction Begin */
5492 case 686: /* Transaction End */
5493 case 750: /* Transaction Suspend or Resume */
5494 case 782: /* Transaction Abort Word Conditional */
5495 case 814: /* Transaction Abort Doubleword Conditional */
5496 case 846: /* Transaction Abort Word Conditional Immediate */
5497 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5498 case 910: /* Transaction Abort */
5499 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5501 case 718: /* Transaction Check */
5502 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5505 case 1014: /* Data Cache Block set to Zero */
5506 if (target_auxv_search (current_inferior ()->top_target (),
5507 AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5509 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5512 if (PPC_RA (insn
) != 0)
5513 regcache_raw_read_unsigned (regcache
,
5514 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5515 regcache_raw_read_unsigned (regcache
,
5516 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5517 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5518 record_full_arch_list_add_mem (ea
, at_dcsz
);
5522 if (ppc_process_record_op31_177 (gdbarch
, regcache
, insn
) == 0)
5527 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
5528 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5532 /* Parse and record instructions of primary opcode-59 at ADDR.
5533 Return 0 if successful. */
5536 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5537 CORE_ADDR addr
, uint32_t insn
)
5539 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5540 int ext
= PPC_EXTOP (insn
);
5541 int at
= PPC_FIELD (insn
, 6, 3);
5545 case 18: /* Floating Divide */
5546 case 20: /* Floating Subtract */
5547 case 21: /* Floating Add */
5548 case 22: /* Floating Square Root */
5549 case 24: /* Floating Reciprocal Estimate */
5550 case 25: /* Floating Multiply */
5551 case 26: /* Floating Reciprocal Square Root Estimate */
5552 case 28: /* Floating Multiply-Subtract */
5553 case 29: /* Floating Multiply-Add */
5554 case 30: /* Floating Negative Multiply-Subtract */
5555 case 31: /* Floating Negative Multiply-Add */
5556 record_full_arch_list_add_reg (regcache
,
5557 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5559 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5560 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5565 /* MMA instructions, keep looking. */
5566 switch (ext
>> 2) /* Additional opcode field is upper 8-bits of ext */
5568 case 3: /* VSX Vector 8-bit Signed/Unsigned Integer GER, xvi8ger4 */
5569 case 2: /* VSX Vector 8-bit Signed/Unsigned Integer GER Positive
5570 multiply, Positive accumulate, xvi8ger4pp */
5572 case 99: /* VSX Vector 8-bit Signed/Unsigned Integer GER with
5573 Saturate Positive multiply, Positive accumulate,
5576 case 35: /* VSX Vector 4-bit Signed Integer GER, xvi4ger8 */
5577 case 34: /* VSX Vector 4-bit Signed Integer GER Positive multiply,
5578 Positive accumulate, xvi4ger8pp */
5580 case 75: /* VSX Vector 16-bit Signed Integer GER, xvi16ger2 */
5581 case 107: /* VSX Vector 16-bit Signed Integer GER Positive multiply,
5582 Positive accumulate, xvi16ger2pp */
5584 case 43: /* VSX Vector 16-bit Signed Integer GER with Saturation,
5586 case 42: /* VSX Vector 16-bit Signed Integer GER with Saturation
5587 Positive multiply, Positive accumulate, xvi16ger2spp */
5588 ppc_record_ACC_fpscr (regcache
, tdep
, at
, false);
5591 case 19: /* VSX Vector 16-bit Floating-Point GER, xvf16ger2 */
5592 case 18: /* VSX Vector 16-bit Floating-Point GER Positive multiply,
5593 Positive accumulate, xvf16ger2pp */
5594 case 146: /* VSX Vector 16-bit Floating-Point GER Positive multiply,
5595 Negative accumulate, xvf16ger2pn */
5596 case 82: /* VSX Vector 16-bit Floating-Point GER Negative multiply,
5597 Positive accumulate, xvf16ger2np */
5598 case 210: /* VSX Vector 16-bit Floating-Point GER Negative multiply,
5599 Negative accumulate, xvf16ger2nn */
5601 case 27: /* VSX Vector 32-bit Floating-Point GER, xvf32ger */
5602 case 26: /* VSX Vector 32-bit Floating-Point GER Positive multiply,
5603 Positive accumulate, xvf32gerpp */
5604 case 154: /* VSX Vector 32-bit Floating-Point GER Positive multiply,
5605 Negative accumulate, xvf32gerpn */
5606 case 90: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
5607 Positive accumulate, xvf32gernp */
5608 case 218: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
5609 Negative accumulate, xvf32gernn */
5611 case 59: /* VSX Vector 64-bit Floating-Point GER, pmxvf64ger */
5612 case 58: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
5613 Positive accumulate, xvf64gerpp */
5614 case 186: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
5615 Negative accumulate, xvf64gerpn */
5616 case 122: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
5617 Positive accumulate, xvf64gernp */
5618 case 250: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
5619 Negative accumulate, pmxvf64gernn */
5621 case 51: /* VSX Vector bfloat16 GER, xvbf16ger2 */
5622 case 50: /* VSX Vector bfloat16 GER Positive multiply,
5623 Positive accumulate, xvbf16ger2pp */
5624 case 178: /* VSX Vector bfloat16 GER Positive multiply,
5625 Negative accumulate, xvbf16ger2pn */
5626 case 114: /* VSX Vector bfloat16 GER Negative multiply,
5627 Positive accumulate, xvbf16ger2np */
5628 case 242: /* VSX Vector bfloat16 GER Negative multiply,
5629 Negative accumulate, xvbf16ger2nn */
5630 ppc_record_ACC_fpscr (regcache
, tdep
, at
, true);
5636 case 2: /* DFP Add */
5637 case 3: /* DFP Quantize */
5638 case 34: /* DFP Multiply */
5639 case 35: /* DFP Reround */
5640 case 67: /* DFP Quantize Immediate */
5641 case 99: /* DFP Round To FP Integer With Inexact */
5642 case 227: /* DFP Round To FP Integer Without Inexact */
5643 case 258: /* DFP Convert To DFP Long! */
5644 case 290: /* DFP Convert To Fixed */
5645 case 514: /* DFP Subtract */
5646 case 546: /* DFP Divide */
5647 case 770: /* DFP Round To DFP Short! */
5648 case 802: /* DFP Convert From Fixed */
5649 case 834: /* DFP Encode BCD To DPD */
5651 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5652 record_full_arch_list_add_reg (regcache
,
5653 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5654 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5657 case 130: /* DFP Compare Ordered */
5658 case 162: /* DFP Test Exponent */
5659 case 194: /* DFP Test Data Class */
5660 case 226: /* DFP Test Data Group */
5661 case 642: /* DFP Compare Unordered */
5662 case 674: /* DFP Test Significance */
5663 case 675: /* DFP Test Significance Immediate */
5664 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5668 case 66: /* DFP Shift Significand Left Immediate */
5669 case 98: /* DFP Shift Significand Right Immediate */
5670 case 322: /* DFP Decode DPD To BCD */
5671 case 354: /* DFP Extract Biased Exponent */
5672 case 866: /* DFP Insert Biased Exponent */
5673 record_full_arch_list_add_reg (regcache
,
5674 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5676 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5679 case 846: /* Floating Convert From Integer Doubleword Single */
5680 case 974: /* Floating Convert From Integer Doubleword Unsigned
5682 record_full_arch_list_add_reg (regcache
,
5683 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5685 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5686 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5691 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
5692 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5696 /* Parse and record an XX2-Form instruction with opcode 60 at ADDR. The
5697 word instruction is an argument insn. Return 0 if successful. */
5700 ppc_process_record_op60_XX2 (struct gdbarch
*gdbarch
,
5701 struct regcache
*regcache
,
5702 CORE_ADDR addr
, uint32_t insn
)
5704 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5705 int RA_opcode
= PPC_RA(insn
);
5709 case 2: /* VSX Vector Test Least-Significant Bit by Byte */
5710 case 25: /* VSX Vector round and Convert Single-Precision format
5711 to Half-Precision format. Only changes the CR
5713 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5715 case 17: /* VSX Vector Convert with round Single-Precision
5716 to bfloat16 format */
5717 case 24: /* VSX Vector Convert Half-Precision format to
5718 Single-Precision format */
5719 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5721 case 0: /* VSX Vector Extract Exponent Double-Precision */
5722 case 1: /* VSX Vector Extract Significand Double-Precision */
5723 case 7: /* VSX Vector Byte-Reverse Halfword */
5724 case 8: /* VSX Vector Extract Exponent Single-Precision */
5725 case 9: /* VSX Vector Extract Significand Single-Precision */
5726 case 15: /* VSX Vector Byte-Reverse Word */
5727 case 16: /* VSX Vector Convert bfloat16 to Single-Precision
5728 format Non-signaling */
5729 case 23: /* VSX Vector Byte-Reverse Doubleword */
5730 case 31: /* VSX Vector Byte-Reverse Quadword */
5731 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5738 /* Parse and record instructions of primary opcode-60 at ADDR.
5739 Return 0 if successful. */
5742 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5743 CORE_ADDR addr
, uint32_t insn
)
5745 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5746 int ext
= PPC_EXTOP (insn
);
5750 case 0: /* VSX Scalar Add Single-Precision */
5751 case 32: /* VSX Scalar Add Double-Precision */
5752 case 24: /* VSX Scalar Divide Single-Precision */
5753 case 56: /* VSX Scalar Divide Double-Precision */
5754 case 176: /* VSX Scalar Copy Sign Double-Precision */
5755 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5756 case 41: /* ditto */
5757 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5759 case 160: /* VSX Scalar Maximum Double-Precision */
5760 case 168: /* VSX Scalar Minimum Double-Precision */
5761 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5762 case 57: /* ditto */
5763 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5764 case 25: /* ditto */
5765 case 48: /* VSX Scalar Multiply Double-Precision */
5766 case 16: /* VSX Scalar Multiply Single-Precision */
5767 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5768 case 169: /* ditto */
5769 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5770 case 137: /* ditto */
5771 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5772 case 185: /* ditto */
5773 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5774 case 153: /* ditto */
5775 case 40: /* VSX Scalar Subtract Double-Precision */
5776 case 8: /* VSX Scalar Subtract Single-Precision */
5777 case 96: /* VSX Vector Add Double-Precision */
5778 case 64: /* VSX Vector Add Single-Precision */
5779 case 120: /* VSX Vector Divide Double-Precision */
5780 case 88: /* VSX Vector Divide Single-Precision */
5781 case 97: /* VSX Vector Multiply-Add Double-Precision */
5782 case 105: /* ditto */
5783 case 65: /* VSX Vector Multiply-Add Single-Precision */
5784 case 73: /* ditto */
5785 case 224: /* VSX Vector Maximum Double-Precision */
5786 case 192: /* VSX Vector Maximum Single-Precision */
5787 case 232: /* VSX Vector Minimum Double-Precision */
5788 case 200: /* VSX Vector Minimum Single-Precision */
5789 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5790 case 121: /* ditto */
5791 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5792 case 89: /* ditto */
5793 case 112: /* VSX Vector Multiply Double-Precision */
5794 case 80: /* VSX Vector Multiply Single-Precision */
5795 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5796 case 233: /* ditto */
5797 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5798 case 201: /* ditto */
5799 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5800 case 249: /* ditto */
5801 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5802 case 217: /* ditto */
5803 case 104: /* VSX Vector Subtract Double-Precision */
5804 case 72: /* VSX Vector Subtract Single-Precision */
5805 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5806 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5807 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5808 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5809 case 3: /* VSX Scalar Compare Equal Double-Precision */
5810 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5811 case 19: /* VSX Scalar Compare Greater Than or Equal
5813 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5815 case 240: /* VSX Vector Copy Sign Double-Precision */
5816 case 208: /* VSX Vector Copy Sign Single-Precision */
5817 case 130: /* VSX Logical AND */
5818 case 138: /* VSX Logical AND with Complement */
5819 case 186: /* VSX Logical Equivalence */
5820 case 178: /* VSX Logical NAND */
5821 case 170: /* VSX Logical OR with Complement */
5822 case 162: /* VSX Logical NOR */
5823 case 146: /* VSX Logical OR */
5824 case 154: /* VSX Logical XOR */
5825 case 18: /* VSX Merge High Word */
5826 case 50: /* VSX Merge Low Word */
5827 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5828 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5829 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5830 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5831 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5832 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5833 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5834 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5835 case 216: /* VSX Vector Insert Exponent Single-Precision */
5836 case 248: /* VSX Vector Insert Exponent Double-Precision */
5837 case 26: /* VSX Vector Permute */
5838 case 58: /* VSX Vector Permute Right-indexed */
5839 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5840 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5841 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5842 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5843 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5846 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5847 case 125: /* VSX Vector Test for software Divide Double-Precision */
5848 case 93: /* VSX Vector Test for software Divide Single-Precision */
5849 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5852 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5853 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5854 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5855 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5856 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5860 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5862 case 99: /* VSX Vector Compare Equal To Double-Precision */
5863 case 67: /* VSX Vector Compare Equal To Single-Precision */
5864 case 115: /* VSX Vector Compare Greater Than or
5865 Equal To Double-Precision */
5866 case 83: /* VSX Vector Compare Greater Than or
5867 Equal To Single-Precision */
5868 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5869 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5871 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5872 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5873 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5879 case 265: /* VSX Scalar round Double-Precision to
5880 Single-Precision and Convert to
5881 Single-Precision format */
5882 case 344: /* VSX Scalar truncate Double-Precision to
5883 Integer and Convert to Signed Integer
5884 Doubleword format with Saturate */
5885 case 88: /* VSX Scalar truncate Double-Precision to
5886 Integer and Convert to Signed Integer Word
5887 Format with Saturate */
5888 case 328: /* VSX Scalar truncate Double-Precision integer
5889 and Convert to Unsigned Integer Doubleword
5890 Format with Saturate */
5891 case 72: /* VSX Scalar truncate Double-Precision to
5892 Integer and Convert to Unsigned Integer Word
5893 Format with Saturate */
5894 case 329: /* VSX Scalar Convert Single-Precision to
5895 Double-Precision format */
5896 case 376: /* VSX Scalar Convert Signed Integer
5897 Doubleword to floating-point format and
5898 Round to Double-Precision format */
5899 case 312: /* VSX Scalar Convert Signed Integer
5900 Doubleword to floating-point format and
5901 round to Single-Precision */
5902 case 360: /* VSX Scalar Convert Unsigned Integer
5903 Doubleword to floating-point format and
5904 Round to Double-Precision format */
5905 case 296: /* VSX Scalar Convert Unsigned Integer
5906 Doubleword to floating-point format and
5907 Round to Single-Precision */
5908 case 73: /* VSX Scalar Round to Double-Precision Integer
5909 Using Round to Nearest Away */
5910 case 107: /* VSX Scalar Round to Double-Precision Integer
5911 Exact using Current rounding mode */
5912 case 121: /* VSX Scalar Round to Double-Precision Integer
5913 Using Round toward -Infinity */
5914 case 105: /* VSX Scalar Round to Double-Precision Integer
5915 Using Round toward +Infinity */
5916 case 89: /* VSX Scalar Round to Double-Precision Integer
5917 Using Round toward Zero */
5918 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5919 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5920 case 281: /* VSX Scalar Round to Single-Precision */
5921 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5923 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5925 case 75: /* VSX Scalar Square Root Double-Precision */
5926 case 11: /* VSX Scalar Square Root Single-Precision */
5927 case 393: /* VSX Vector round Double-Precision to
5928 Single-Precision and Convert to
5929 Single-Precision format */
5930 case 472: /* VSX Vector truncate Double-Precision to
5931 Integer and Convert to Signed Integer
5932 Doubleword format with Saturate */
5933 case 216: /* VSX Vector truncate Double-Precision to
5934 Integer and Convert to Signed Integer Word
5935 Format with Saturate */
5936 case 456: /* VSX Vector truncate Double-Precision to
5937 Integer and Convert to Unsigned Integer
5938 Doubleword format with Saturate */
5939 case 200: /* VSX Vector truncate Double-Precision to
5940 Integer and Convert to Unsigned Integer Word
5941 Format with Saturate */
5942 case 457: /* VSX Vector Convert Single-Precision to
5943 Double-Precision format */
5944 case 408: /* VSX Vector truncate Single-Precision to
5945 Integer and Convert to Signed Integer
5946 Doubleword format with Saturate */
5947 case 152: /* VSX Vector truncate Single-Precision to
5948 Integer and Convert to Signed Integer Word
5949 Format with Saturate */
5950 case 392: /* VSX Vector truncate Single-Precision to
5951 Integer and Convert to Unsigned Integer
5952 Doubleword format with Saturate */
5953 case 136: /* VSX Vector truncate Single-Precision to
5954 Integer and Convert to Unsigned Integer Word
5955 Format with Saturate */
5956 case 504: /* VSX Vector Convert and round Signed Integer
5957 Doubleword to Double-Precision format */
5958 case 440: /* VSX Vector Convert and round Signed Integer
5959 Doubleword to Single-Precision format */
5960 case 248: /* VSX Vector Convert Signed Integer Word to
5961 Double-Precision format */
5962 case 184: /* VSX Vector Convert and round Signed Integer
5963 Word to Single-Precision format */
5964 case 488: /* VSX Vector Convert and round Unsigned
5965 Integer Doubleword to Double-Precision format */
5966 case 424: /* VSX Vector Convert and round Unsigned
5967 Integer Doubleword to Single-Precision format */
5968 case 232: /* VSX Vector Convert and round Unsigned
5969 Integer Word to Double-Precision format */
5970 case 168: /* VSX Vector Convert and round Unsigned
5971 Integer Word to Single-Precision format */
5972 case 201: /* VSX Vector Round to Double-Precision
5973 Integer using round to Nearest Away */
5974 case 235: /* VSX Vector Round to Double-Precision
5975 Integer Exact using Current rounding mode */
5976 case 249: /* VSX Vector Round to Double-Precision
5977 Integer using round toward -Infinity */
5978 case 233: /* VSX Vector Round to Double-Precision
5979 Integer using round toward +Infinity */
5980 case 217: /* VSX Vector Round to Double-Precision
5981 Integer using round toward Zero */
5982 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5983 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5984 case 137: /* VSX Vector Round to Single-Precision Integer
5985 Using Round to Nearest Away */
5986 case 171: /* VSX Vector Round to Single-Precision Integer
5987 Exact Using Current rounding mode */
5988 case 185: /* VSX Vector Round to Single-Precision Integer
5989 Using Round toward -Infinity */
5990 case 169: /* VSX Vector Round to Single-Precision Integer
5991 Using Round toward +Infinity */
5992 case 153: /* VSX Vector Round to Single-Precision Integer
5993 Using round toward Zero */
5994 case 202: /* VSX Vector Reciprocal Square Root Estimate
5996 case 138: /* VSX Vector Reciprocal Square Root Estimate
5998 case 203: /* VSX Vector Square Root Double-Precision */
5999 case 139: /* VSX Vector Square Root Single-Precision */
6000 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6002 case 345: /* VSX Scalar Absolute Value Double-Precision */
6003 case 267: /* VSX Scalar Convert Scalar Single-Precision to
6004 Vector Single-Precision format Non-signalling */
6005 case 331: /* VSX Scalar Convert Single-Precision to
6006 Double-Precision format Non-signalling */
6007 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
6008 case 377: /* VSX Scalar Negate Double-Precision */
6009 case 473: /* VSX Vector Absolute Value Double-Precision */
6010 case 409: /* VSX Vector Absolute Value Single-Precision */
6011 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
6012 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
6013 case 505: /* VSX Vector Negate Double-Precision */
6014 case 441: /* VSX Vector Negate Single-Precision */
6015 case 164: /* VSX Splat Word */
6016 case 165: /* VSX Vector Extract Unsigned Word */
6017 case 181: /* VSX Vector Insert Word */
6018 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6021 case 298: /* VSX Scalar Test Data Class Single-Precision */
6022 case 362: /* VSX Scalar Test Data Class Double-Precision */
6023 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6025 case 106: /* VSX Scalar Test for software Square Root
6027 case 234: /* VSX Vector Test for software Square Root
6029 case 170: /* VSX Vector Test for software Square Root
6031 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6035 switch (PPC_FIELD (insn
, 11, 5))
6037 case 0: /* VSX Scalar Extract Exponent Double-Precision */
6038 case 1: /* VSX Scalar Extract Significand Double-Precision */
6039 record_full_arch_list_add_reg (regcache
,
6040 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6042 case 16: /* VSX Scalar Convert Half-Precision format to
6043 Double-Precision format */
6044 case 17: /* VSX Scalar round & Convert Double-Precision format
6045 to Half-Precision format */
6046 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6047 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6053 if (ppc_process_record_op60_XX2 (gdbarch
, regcache
, addr
, insn
) != 0)
6061 if (PPC_FIELD (insn
, 11, 2) == 0) /* VSX Vector Splat Immediate Byte */
6063 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6066 if (PPC_FIELD (insn
, 11, 5) == 31) /* Load VSX Vector Special Value
6069 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6073 case 916: /* VSX Vector Generate PCV from Byte Mask */
6074 case 917: /* VSX Vector Generate PCV from Halfword Mask */
6075 case 948: /* VSX Vector Generate PCV from Word Mask */
6076 case 949: /* VSX Vector Generate PCV from Doubleword Mask */
6077 case 918: /* VSX Scalar Insert Exponent Double-Precision */
6078 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6082 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
6084 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6088 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6089 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
6093 /* Parse and record instructions of primary opcode-61 at ADDR.
6094 Return 0 if successful. */
6097 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6098 CORE_ADDR addr
, uint32_t insn
)
6100 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6106 case 0: /* Store Floating-Point Double Pair */
6107 case 2: /* Store VSX Scalar Doubleword */
6108 case 3: /* Store VSX Scalar Single */
6109 if (PPC_RA (insn
) != 0)
6110 regcache_raw_read_unsigned (regcache
,
6111 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6113 ea
+= PPC_DS (insn
) << 2;
6116 case 0: /* Store Floating-Point Double Pair */
6119 case 2: /* Store VSX Scalar Doubleword */
6122 case 3: /* Store VSX Scalar Single */
6128 record_full_arch_list_add_mem (ea
, size
);
6134 case 1: /* Load VSX Vector */
6135 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6137 case 5: /* Store VSX Vector */
6138 if (PPC_RA (insn
) != 0)
6139 regcache_raw_read_unsigned (regcache
,
6140 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6142 ea
+= PPC_DQ (insn
) << 4;
6143 record_full_arch_list_add_mem (ea
, 16);
6147 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6148 "at %s.\n", insn
, paddress (gdbarch
, addr
));
6152 /* Parse and record instructions of primary opcode-63 at ADDR.
6153 Return 0 if successful. */
6156 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6157 CORE_ADDR addr
, uint32_t insn
)
6159 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6160 int ext
= PPC_EXTOP (insn
);
6165 case 18: /* Floating Divide */
6166 case 20: /* Floating Subtract */
6167 case 21: /* Floating Add */
6168 case 22: /* Floating Square Root */
6169 case 24: /* Floating Reciprocal Estimate */
6170 case 25: /* Floating Multiply */
6171 case 26: /* Floating Reciprocal Square Root Estimate */
6172 case 28: /* Floating Multiply-Subtract */
6173 case 29: /* Floating Multiply-Add */
6174 case 30: /* Floating Negative Multiply-Subtract */
6175 case 31: /* Floating Negative Multiply-Add */
6176 record_full_arch_list_add_reg (regcache
,
6177 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6179 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6180 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6183 case 23: /* Floating Select */
6184 record_full_arch_list_add_reg (regcache
,
6185 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6187 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6193 case 5: /* VSX Scalar Round to Quad-Precision Integer */
6194 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
6196 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6197 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6203 case 2: /* DFP Add Quad */
6204 case 3: /* DFP Quantize Quad */
6205 case 34: /* DFP Multiply Quad */
6206 case 35: /* DFP Reround Quad */
6207 case 67: /* DFP Quantize Immediate Quad */
6208 case 99: /* DFP Round To FP Integer With Inexact Quad */
6209 case 227: /* DFP Round To FP Integer Without Inexact Quad */
6210 case 258: /* DFP Convert To DFP Extended Quad */
6211 case 514: /* DFP Subtract Quad */
6212 case 546: /* DFP Divide Quad */
6213 case 770: /* DFP Round To DFP Long Quad */
6214 case 802: /* DFP Convert From Fixed Quad */
6215 case 834: /* DFP Encode BCD To DPD Quad */
6217 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6218 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
6219 record_full_arch_list_add_reg (regcache
, tmp
);
6220 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6221 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6224 case 130: /* DFP Compare Ordered Quad */
6225 case 162: /* DFP Test Exponent Quad */
6226 case 194: /* DFP Test Data Class Quad */
6227 case 226: /* DFP Test Data Group Quad */
6228 case 642: /* DFP Compare Unordered Quad */
6229 case 674: /* DFP Test Significance Quad */
6230 case 675: /* DFP Test Significance Immediate Quad */
6231 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6232 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6235 case 66: /* DFP Shift Significand Left Immediate Quad */
6236 case 98: /* DFP Shift Significand Right Immediate Quad */
6237 case 322: /* DFP Decode DPD To BCD Quad */
6238 case 866: /* DFP Insert Biased Exponent Quad */
6239 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
6240 record_full_arch_list_add_reg (regcache
, tmp
);
6241 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6243 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6246 case 290: /* DFP Convert To Fixed Quad */
6247 record_full_arch_list_add_reg (regcache
,
6248 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6250 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6251 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6254 case 354: /* DFP Extract Biased Exponent Quad */
6255 record_full_arch_list_add_reg (regcache
,
6256 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6258 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6261 case 12: /* Floating Round to Single-Precision */
6262 case 14: /* Floating Convert To Integer Word */
6263 case 15: /* Floating Convert To Integer Word
6264 with round toward Zero */
6265 case 142: /* Floating Convert To Integer Word Unsigned */
6266 case 143: /* Floating Convert To Integer Word Unsigned
6267 with round toward Zero */
6268 case 392: /* Floating Round to Integer Nearest */
6269 case 424: /* Floating Round to Integer Toward Zero */
6270 case 456: /* Floating Round to Integer Plus */
6271 case 488: /* Floating Round to Integer Minus */
6272 case 814: /* Floating Convert To Integer Doubleword */
6273 case 815: /* Floating Convert To Integer Doubleword
6274 with round toward Zero */
6275 case 846: /* Floating Convert From Integer Doubleword */
6276 case 942: /* Floating Convert To Integer Doubleword Unsigned */
6277 case 943: /* Floating Convert To Integer Doubleword Unsigned
6278 with round toward Zero */
6279 case 974: /* Floating Convert From Integer Doubleword Unsigned */
6280 record_full_arch_list_add_reg (regcache
,
6281 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6283 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6284 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6288 switch (PPC_FIELD (insn
, 11, 5))
6290 case 1: /* Move From FPSCR & Clear Enables */
6291 case 20: /* Move From FPSCR Control & set DRN */
6292 case 21: /* Move From FPSCR Control & set DRN Immediate */
6293 case 22: /* Move From FPSCR Control & set RN */
6294 case 23: /* Move From FPSCR Control & set RN Immediate */
6295 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6297 case 0: /* Move From FPSCR */
6298 case 24: /* Move From FPSCR Lightweight */
6299 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
6300 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6301 record_full_arch_list_add_reg (regcache
,
6302 tdep
->ppc_fp0_regnum
6308 case 8: /* Floating Copy Sign */
6309 case 40: /* Floating Negate */
6310 case 72: /* Floating Move Register */
6311 case 136: /* Floating Negative Absolute Value */
6312 case 264: /* Floating Absolute Value */
6313 record_full_arch_list_add_reg (regcache
,
6314 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6316 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6319 case 838: /* Floating Merge Odd Word */
6320 case 966: /* Floating Merge Even Word */
6321 record_full_arch_list_add_reg (regcache
,
6322 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6325 case 38: /* Move To FPSCR Bit 1 */
6326 case 70: /* Move To FPSCR Bit 0 */
6327 case 134: /* Move To FPSCR Field Immediate */
6328 case 711: /* Move To FPSCR Fields */
6330 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6331 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6334 case 0: /* Floating Compare Unordered */
6335 case 32: /* Floating Compare Ordered */
6336 case 64: /* Move to Condition Register from FPSCR */
6337 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
6338 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
6339 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
6340 case 708: /* VSX Scalar Test Data Class Quad-Precision */
6341 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6343 case 128: /* Floating Test for software Divide */
6344 case 160: /* Floating Test for software Square Root */
6345 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6348 case 4: /* VSX Scalar Add Quad-Precision */
6349 case 36: /* VSX Scalar Multiply Quad-Precision */
6350 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
6351 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
6352 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
6353 case 484: /* VSX Scalar Negative Multiply-Subtract
6355 case 516: /* VSX Scalar Subtract Quad-Precision */
6356 case 548: /* VSX Scalar Divide Quad-Precision */
6359 switch (PPC_FIELD (insn
, 11, 5))
6361 case 0: /* DFP Convert From Fixed Quadword Quad */
6362 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6364 record_full_arch_list_add_reg (regcache
,
6365 tdep
->ppc_fp0_regnum
6367 record_full_arch_list_add_reg (regcache
,
6368 tdep
->ppc_fp0_regnum
6369 + PPC_FRT (insn
) + 1);
6371 case 1: /* DFP Convert To Fixed Quadword Quad */
6372 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6373 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6378 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6380 case 68: /* VSX Scalar Compare Equal Quad-Precision */
6381 case 196: /* VSX Scalar Compare Greater Than or Equal
6383 case 228: /* VSX Scalar Compare Greater Than Quad-Precision */
6384 case 676: /* VSX Scalar Maximum Type-C Quad-Precision */
6385 case 740: /* VSX Scalar Minimum Type-C Quad-Precision */
6386 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6388 case 100: /* VSX Scalar Copy Sign Quad-Precision */
6389 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
6390 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6394 switch (PPC_FIELD (insn
, 11, 5))
6396 case 27: /* VSX Scalar Square Root Quad-Precision */
6397 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6399 case 0: /* VSX Scalar Absolute Quad-Precision */
6400 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
6401 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
6402 case 16: /* VSX Scalar Negate Quad-Precision */
6403 case 18: /* VSX Scalar Extract Significand Quad-Precision */
6404 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6410 switch (PPC_FIELD (insn
, 11, 5))
6412 case 0: /* VSX Scalar Convert with round to zero
6413 Quad-Precision to Unsigned Quadword */
6414 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
6415 to Unsigned Word format */
6416 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
6417 Quad-Precision format */
6418 case 3: /* VSX Scalar Convert with round
6419 Unsigned Quadword to Quad-Precision */
6420 case 8: /* VSX Scalar Convert with round to zero
6421 Quad-Precision to Signed Quadword */
6422 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
6423 to Signed Word format */
6424 case 10: /* VSX Scalar Convert Signed Doubleword format to
6425 Quad-Precision format */
6426 case 11: /* VSX Scalar Convert with round
6427 Signed Quadword to Quad-Precision */
6428 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
6429 to Unsigned Doubleword format */
6430 case 20: /* VSX Scalar round & Convert Quad-Precision format to
6431 Double-Precision format */
6432 case 22: /* VSX Scalar Convert Double-Precision format to
6433 Quad-Precision format */
6434 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
6435 to Signed Doubleword format */
6436 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6437 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6442 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6443 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
6447 /* Record the prefixed instructions with primary opcode 32. The arguments are
6448 the first 32-bits of the instruction (insn_prefix), and the second 32-bits
6449 of the instruction (insn_suffix). Return 0 on success. */
6452 ppc_process_record_prefix_op42 (struct gdbarch
*gdbarch
,
6453 struct regcache
*regcache
,
6454 uint32_t insn_prefix
, uint32_t insn_suffix
)
6456 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6457 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6458 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6465 case 0: /* Prefixed Load VSX Scalar Doubleword, plxsd */
6466 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn_suffix
) + 32);
6468 case 2: /* Prefixed Load Halfword Algebraic, plha */
6469 record_full_arch_list_add_reg (regcache
,
6470 tdep
->ppc_gp0_regnum
6471 + PPC_RT (insn_suffix
));
6479 /* Record the prefixed XX3-Form instructions with primary opcode 59. The
6480 arguments are the first 32-bits of the instruction (insn_prefix), and the
6481 second 32-bits of the instruction (insn_suffix). Return 0 on success. */
6484 ppc_process_record_prefix_op59_XX3 (struct gdbarch
*gdbarch
,
6485 struct regcache
*regcache
,
6486 uint32_t insn_prefix
, uint32_t insn_suffix
)
6488 int opcode
= PPC_FIELD (insn_suffix
, 21, 8);
6489 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6490 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6491 int at
= PPC_FIELD (insn_suffix
, 6, 3);
6492 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6499 case 35: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
6500 MMIRR, pmxvi4ger8 */
6501 case 34: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
6502 MMIRR, pmxvi4ger8pp */
6504 case 99: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6505 Integer GER with Saturate Positive multiply,
6506 Positive accumulate, xvi8ger4spp */
6508 case 3: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6509 Integer GER MMIRR, pmxvi8ger4 */
6510 case 2: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6511 Integer GER Positive multiply, Positive accumulate
6512 MMIRR, pmxvi8ger4pp */
6514 case 75: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6515 GER MMIRR, pmxvi16ger2 */
6516 case 107: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6517 GER Positive multiply, Positive accumulate,
6520 case 43: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6521 GER with Saturation MMIRR, pmxvi16ger2s */
6522 case 42: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6523 GER with Saturation Positive multiply, Positive
6524 accumulate MMIRR, pmxvi16ger2spp */
6525 ppc_record_ACC_fpscr (regcache
, tdep
, at
, false);
6528 case 19: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6529 GER MMIRR, pmxvf16ger2 */
6530 case 18: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6531 GER Positive multiply, Positive accumulate MMIRR,
6533 case 146: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6534 GER Positive multiply, Negative accumulate MMIRR,
6536 case 82: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6537 GER Negative multiply, Positive accumulate MMIRR,
6539 case 210: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6540 GER Negative multiply, Negative accumulate MMIRR,
6543 case 27: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6544 GER MMIRR, pmxvf32ger */
6545 case 26: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6546 GER Positive multiply, Positive accumulate MMIRR,
6548 case 154: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6549 GER Positive multiply, Negative accumulate MMIRR,
6551 case 90: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6552 GER Negative multiply, Positive accumulate MMIRR,
6554 case 218: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6555 GER Negative multiply, Negative accumulate MMIRR,
6558 case 59: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6559 GER MMIRR, pmxvf64ger */
6560 case 58: /* Floating-Point GER Positive multiply, Positive
6561 accumulate MMIRR, pmxvf64gerpp */
6562 case 186: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6563 GER Positive multiply, Negative accumulate MMIRR,
6565 case 122: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6566 GER Negative multiply, Positive accumulate MMIRR,
6568 case 250: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6569 GER Negative multiply, Negative accumulate MMIRR,
6572 case 51: /* Prefixed Masked VSX Vector bfloat16 GER MMIRR,
6574 case 50: /* Prefixed Masked VSX Vector bfloat16 GER Positive
6575 multiply, Positive accumulate MMIRR,
6577 case 178: /* Prefixed Masked VSX Vector bfloat16 GER Positive
6578 multiply, Negative accumulate MMIRR,
6580 case 114: /* Prefixed Masked VSX Vector bfloat16 GER Negative
6581 multiply, Positive accumulate MMIRR,
6583 case 242: /* Prefixed Masked VSX Vector bfloat16 GER Negative
6584 multiply, Negative accumulate MMIRR,
6586 ppc_record_ACC_fpscr (regcache
, tdep
, at
, true);
6596 /* Record the prefixed store instructions. The arguments are the instruction
6597 address, the first 32-bits of the instruction(insn_prefix) and the following
6598 32-bits of the instruction (insn_suffix). Return 0 on success. */
6601 ppc_process_record_prefix_store (struct gdbarch
*gdbarch
,
6602 struct regcache
*regcache
,
6603 CORE_ADDR addr
, uint32_t insn_prefix
,
6604 uint32_t insn_suffix
)
6606 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6609 int R
= PPC_BIT (insn_prefix
, 11);
6610 int op6
= PPC_OP6 (insn_suffix
);
6614 if (PPC_RA (insn_suffix
) != 0)
6615 regcache_raw_read_unsigned (regcache
, tdep
->ppc_gp0_regnum
6616 + PPC_RA (insn_suffix
), &iaddr
);
6620 iaddr
= addr
; /* PC relative */
6626 size
= 1; /* store byte, pstb */
6629 size
= 2; /* store halfword, psth */
6633 size
= 4; /* store word, pstw, pstfs */
6637 size
= 8; /* store double word, pstd, pstfd */
6640 size
= 16; /* store quadword, pstq */
6645 iaddr
+= P_PPC_D (insn_prefix
, insn_suffix
);
6646 record_full_arch_list_add_mem (iaddr
, size
);
6650 /* Record the prefixed instructions with primary op code 32. The arguments
6651 are the first 32-bits of the instruction (insn_prefix) and the following
6652 32-bits of the instruction (insn_suffix). Return 0 on success. */
6655 ppc_process_record_prefix_op32 (struct gdbarch
*gdbarch
,
6656 struct regcache
*regcache
,
6657 uint32_t insn_prefix
, uint32_t insn_suffix
)
6659 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6660 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6661 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6662 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6668 switch (PPC_FIELD (insn_suffix
, 11, 3))
6670 case 0: /* VSX Vector Splat Immediate Word 8RR, xxsplti32dx */
6671 ppc_record_vsr (regcache
, tdep
, P_PPC_XT15 (insn_suffix
));
6675 switch (PPC_FIELD (insn_suffix
, 11, 4))
6677 case 2: /* VSX Vector Splat Immediate Double-Precision
6679 case 3: /* VSX Vector Splat Immediate Word 8RR, xxspltiw */
6680 ppc_record_vsr (regcache
, tdep
, P_PPC_XT15 (insn_suffix
));
6692 if (ST1
== 0) /* Prefixed Load Word and Zero, plwz */
6693 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
6694 + PPC_RT (insn_suffix
));
6705 /* Record the prefixed instructions with primary op code 33. The arguments
6706 are the first 32-bits of the instruction(insn_prefix) and the following
6707 32-bits of the instruction (insn_suffix). Return 0 on success. */
6710 ppc_process_record_prefix_op33 (struct gdbarch
*gdbarch
,
6711 struct regcache
*regcache
,
6712 uint32_t insn_prefix
, uint32_t insn_suffix
)
6714 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6715 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6716 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6721 switch (PPC_FIELD (insn_suffix
, 26, 2))
6723 case 0: /* VSX Vector Blend Variable Byte 8RR, xxblendvb */
6724 case 1: /* VSX Vector Blend Variable Halfword, xxblendvh */
6725 case 2: /* VSX Vector Blend Variable Word, xxblendvw */
6726 case 3: /* VSX Vector Blend Variable Doubleword, xxblendvd */
6727 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn_suffix
));
6742 /* Record the prefixed instructions with primary op code 34. The arguments
6743 are the first 32-bits of the instruction(insn_prefix) and the following
6744 32-bits of the instruction (insn_suffix). Return 0 on success. */
6747 ppc_process_record_prefix_op34 (struct gdbarch
*gdbarch
,
6748 struct regcache
*regcache
,
6749 uint32_t insn_prefix
, uint32_t insn_suffix
)
6751 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6752 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6753 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6754 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6759 switch (PPC_FIELD (insn_suffix
, 26, 2))
6761 case 0: /* VSX Vector Permute Extended 8RR, xxpermx */
6762 case 1: /* VSX Vector Evaluate 8RR, xxeval */
6763 ppc_record_vsr (regcache
, tdep
, P_PPC_XT (insn_suffix
));
6774 if (ST1
== 0) /* Prefixed Load Word and Zero, plbz */
6775 record_full_arch_list_add_reg (regcache
,
6776 tdep
->ppc_gp0_regnum
6777 + PPC_RT (insn_suffix
));
6788 /* Record the prefixed VSX store, form DS, instructions. The arguments are the
6789 instruction address (addr), the first 32-bits of the instruction
6790 (insn_prefix) followed by the 32-bit instruction suffix (insn_suffix).
6791 Return 0 on success. */
6794 ppc_process_record_prefix_store_vsx_ds_form (struct gdbarch
*gdbarch
,
6795 struct regcache
*regcache
,
6797 uint32_t insn_prefix
,
6798 uint32_t insn_suffix
)
6800 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6803 int R
= PPC_BIT (insn_prefix
, 11);
6804 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6805 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6807 if ((type
== 0) && (ST1
== 0))
6811 if (PPC_RA (insn_suffix
) != 0)
6812 regcache_raw_read_unsigned (regcache
,
6813 tdep
->ppc_gp0_regnum
6814 + PPC_RA (insn_suffix
),
6819 ea
= addr
; /* PC relative */
6822 ea
+= P_PPC_D (insn_prefix
, insn_suffix
);
6823 switch (PPC_FIELD (insn_suffix
, 0, 6))
6825 case 46: /* Prefixed Store VSX Scalar Doubleword, pstxsd */
6828 case 47: /* Prefixed,Store VSX Scalar Single-Precision, pstxssp */
6834 record_full_arch_list_add_mem (ea
, size
);
6841 /* Record the prefixed VSX, form D, instructions. The arguments are the
6842 instruction address for PC-relative addresss (addr), the first 32-bits of
6843 the instruction (insn_prefix) and the following 32-bits of the instruction
6844 (insn_suffix). Return 0 on success. */
6847 ppc_process_record_prefix_vsx_d_form (struct gdbarch
*gdbarch
,
6848 struct regcache
*regcache
,
6850 uint32_t insn_prefix
,
6851 uint32_t insn_suffix
)
6853 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6856 int R
= PPC_BIT (insn_prefix
, 11);
6857 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6858 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6860 if ((type
== 0) && (ST1
== 0))
6862 switch (PPC_FIELD (insn_suffix
, 0, 5))
6864 case 25: /* Prefixed Load VSX Vector, plxv */
6865 ppc_record_vsr (regcache
, tdep
, P_PPC_XT5 (insn_prefix
));
6867 case 27: /* Prefixed Store VSX Vector 8LS, pstxv */
6872 if (PPC_RA (insn_suffix
) != 0)
6873 regcache_raw_read_unsigned (regcache
,
6874 tdep
->ppc_gp0_regnum
6875 + PPC_RA (insn_suffix
),
6880 ea
= addr
; /* PC relative */
6883 ea
+= P_PPC_D (insn_prefix
, insn_suffix
);
6884 record_full_arch_list_add_mem (ea
, size
);
6894 /* Parse the current instruction and record the values of the registers and
6895 memory that will be changed in current instruction to "record_arch_list".
6896 Return -1 if something wrong. */
6898 /* This handles the recording of the various prefix instructions. It takes
6899 the instruction address, the first 32-bits of the instruction (insn_prefix)
6900 and the following 32-bits of the instruction (insn_suffix). Return 0 on
6904 ppc_process_prefix_instruction (int insn_prefix
, int insn_suffix
,
6905 CORE_ADDR addr
, struct gdbarch
*gdbarch
,
6906 struct regcache
*regcache
)
6908 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6909 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6910 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6913 /* D-form has uses a 5-bit opcode in the instruction suffix */
6914 if (ppc_process_record_prefix_vsx_d_form ( gdbarch
, regcache
, addr
,
6915 insn_prefix
, insn_suffix
) == 0)
6918 op6
= PPC_OP6 (insn_suffix
); /* 6-bit opcode in the instruction suffix */
6922 case 14: /* Prefixed Add Immediate, paddi */
6923 if ((type
== 2) && (ST1
== 0))
6924 record_full_arch_list_add_reg (regcache
,
6925 tdep
->ppc_gp0_regnum
6926 + PPC_RT (insn_suffix
));
6928 goto UNKNOWN_PREFIX_OP
;
6932 if (ppc_process_record_prefix_op32 (gdbarch
, regcache
,
6933 insn_prefix
, insn_suffix
) != 0)
6934 goto UNKNOWN_PREFIX_OP
;
6938 if (ppc_process_record_prefix_op33 (gdbarch
, regcache
,
6939 insn_prefix
, insn_suffix
) != 0)
6940 goto UNKNOWN_PREFIX_OP
;
6943 case 34: /* Prefixed Load Byte and Zero, plbz */
6944 if (ppc_process_record_prefix_op34 (gdbarch
, regcache
,
6945 insn_prefix
, insn_suffix
) != 0)
6946 goto UNKNOWN_PREFIX_OP
;
6948 case 40: /* Prefixed Load Halfword and Zero, plhz */
6949 if ((type
== 2) && (ST1
== 0))
6950 record_full_arch_list_add_reg (regcache
,
6951 tdep
->ppc_gp0_regnum
6952 + PPC_RT (insn_suffix
));
6954 goto UNKNOWN_PREFIX_OP
;
6959 case 36: /* Prefixed Store Word, pstw */
6960 case 38: /* Prefixed Store Byte, pstb */
6961 case 44: /* Prefixed Store Halfword, psth */
6962 case 52: /* Prefixed Store Floating-Point Single, pstfs */
6963 case 54: /* Prefixed Store Floating-Point Double, pstfd */
6964 case 60: /* Prefixed Store Quadword, pstq */
6965 case 61: /* Prefixed Store Doubleword, pstd */
6966 if (ppc_process_record_prefix_store (gdbarch
, regcache
, addr
,
6967 insn_prefix
, insn_suffix
) != 0)
6968 goto UNKNOWN_PREFIX_OP
;
6972 if (ppc_process_record_prefix_op42 (gdbarch
, regcache
,
6973 insn_prefix
, insn_suffix
) != 0)
6974 goto UNKNOWN_PREFIX_OP
;
6977 case 43: /* Prefixed Load VSX Scalar Single-Precision, plxssp */
6978 if ((type
== 0) && (ST1
== 0))
6979 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn_suffix
) + 32);
6981 goto UNKNOWN_PREFIX_OP
;
6986 if (ppc_process_record_prefix_store_vsx_ds_form (gdbarch
, regcache
, addr
,
6987 insn_prefix
, insn_suffix
) != 0)
6988 goto UNKNOWN_PREFIX_OP
;
6991 case 56: /* Prefixed Load Quadword, plq */
6993 if ((type
== 0) && (ST1
== 0))
6996 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn_suffix
) & ~1);
6997 record_full_arch_list_add_reg (regcache
, tmp
);
6998 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7001 goto UNKNOWN_PREFIX_OP
;
7005 case 41: /* Prefixed Load Word Algebraic, plwa */
7006 case 57: /* Prefixed Load Doubleword, pld */
7007 if ((type
== 0) && (ST1
== 0))
7008 record_full_arch_list_add_reg (regcache
,
7009 tdep
->ppc_gp0_regnum
7010 + PPC_RT (insn_suffix
));
7012 goto UNKNOWN_PREFIX_OP
;
7015 case 48: /* Prefixed Load Floating-Point Single, plfs */
7016 case 50: /* Prefixed Load Floating-Point Double, plfd */
7017 if ((type
== 2) && (ST1
== 0))
7018 record_full_arch_list_add_reg (regcache
,
7019 tdep
->ppc_fp0_regnum
7020 + PPC_FRT (insn_suffix
));
7022 goto UNKNOWN_PREFIX_OP
;
7025 case 58: /* Prefixed Load VSX Vector Paired, plxvp */
7026 if ((type
== 0) && (ST1
== 0))
7028 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn_suffix
));
7029 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn_suffix
) + 1);
7032 goto UNKNOWN_PREFIX_OP
;
7036 if (ppc_process_record_prefix_op59_XX3 (gdbarch
, regcache
, insn_prefix
,
7038 goto UNKNOWN_PREFIX_OP
;
7041 case 62: /* Prefixed Store VSX Vector Paired 8LS, pstxvp */
7042 if ((type
== 0) && (ST1
== 0))
7044 int R
= PPC_BIT (insn_prefix
, 11);
7049 if (PPC_RA (insn_suffix
) != 0)
7050 regcache_raw_read_unsigned (regcache
,
7051 tdep
->ppc_gp0_regnum
7052 + PPC_RA (insn_suffix
), &ea
);
7056 ea
= addr
; /* PC relative */
7059 ea
+= P_PPC_D (insn_prefix
, insn_suffix
) << 4;
7060 record_full_arch_list_add_mem (ea
, 32);
7063 goto UNKNOWN_PREFIX_OP
;
7068 gdb_printf (gdb_stdlog
,
7069 "Warning: Don't know how to record prefix instruction "
7070 "%08x %08x at %s, %d.\n",
7071 insn_prefix
, insn_suffix
, paddress (gdbarch
, addr
),
7077 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
7080 if (record_full_arch_list_add_end ())
7086 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7089 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
7090 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7091 uint32_t insn
, insn_suffix
;
7094 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
7095 op6
= PPC_OP6 (insn
);
7099 case 1: /* prefixed instruction */
7101 /* Get the lower 32-bits of the prefixed instruction. */
7102 insn_suffix
= read_memory_unsigned_integer (addr
+4, 4, byte_order
);
7103 return ppc_process_prefix_instruction (insn
, insn_suffix
, addr
,
7106 case 2: /* Trap Doubleword Immediate */
7107 case 3: /* Trap Word Immediate */
7111 case 4: /* Vector Integer, Compare, Logical, Shift, etc. */
7112 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
7116 case 6: /* Vector Load and Store */
7117 if (ppc_process_record_op6 (gdbarch
, regcache
, addr
, insn
) != 0)
7121 case 17: /* System call */
7122 if (PPC_LEV (insn
) != 0)
7125 if (tdep
->ppc_syscall_record
!= NULL
)
7127 if (tdep
->ppc_syscall_record (regcache
) != 0)
7132 gdb_printf (gdb_stderr
, _("no syscall record support\n"));
7137 case 7: /* Multiply Low Immediate */
7138 record_full_arch_list_add_reg (regcache
,
7139 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7142 case 8: /* Subtract From Immediate Carrying */
7143 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
7144 record_full_arch_list_add_reg (regcache
,
7145 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7148 case 10: /* Compare Logical Immediate */
7149 case 11: /* Compare Immediate */
7150 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7153 case 13: /* Add Immediate Carrying and Record */
7154 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7156 case 12: /* Add Immediate Carrying */
7157 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
7159 case 14: /* Add Immediate */
7160 case 15: /* Add Immediate Shifted */
7161 record_full_arch_list_add_reg (regcache
,
7162 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7165 case 16: /* Branch Conditional */
7166 if ((PPC_BO (insn
) & 0x4) == 0)
7167 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
7169 case 18: /* Branch */
7171 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
7175 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
7179 case 20: /* Rotate Left Word Immediate then Mask Insert */
7180 case 21: /* Rotate Left Word Immediate then AND with Mask */
7181 case 23: /* Rotate Left Word then AND with Mask */
7182 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
7183 /* Rotate Left Doubleword Immediate then Clear Right */
7184 /* Rotate Left Doubleword Immediate then Clear */
7185 /* Rotate Left Doubleword then Clear Left */
7186 /* Rotate Left Doubleword then Clear Right */
7187 /* Rotate Left Doubleword Immediate then Mask Insert */
7189 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7190 record_full_arch_list_add_reg (regcache
,
7191 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7194 case 28: /* AND Immediate */
7195 case 29: /* AND Immediate Shifted */
7196 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7198 case 24: /* OR Immediate */
7199 case 25: /* OR Immediate Shifted */
7200 case 26: /* XOR Immediate */
7201 case 27: /* XOR Immediate Shifted */
7202 record_full_arch_list_add_reg (regcache
,
7203 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7207 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
7211 case 33: /* Load Word and Zero with Update */
7212 case 35: /* Load Byte and Zero with Update */
7213 case 41: /* Load Halfword and Zero with Update */
7214 case 43: /* Load Halfword Algebraic with Update */
7215 record_full_arch_list_add_reg (regcache
,
7216 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7218 case 32: /* Load Word and Zero */
7219 case 34: /* Load Byte and Zero */
7220 case 40: /* Load Halfword and Zero */
7221 case 42: /* Load Halfword Algebraic */
7222 record_full_arch_list_add_reg (regcache
,
7223 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7226 case 46: /* Load Multiple Word */
7227 for (i
= PPC_RT (insn
); i
< 32; i
++)
7228 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
7231 case 56: /* Load Quadword */
7232 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
7233 record_full_arch_list_add_reg (regcache
, tmp
);
7234 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7237 case 49: /* Load Floating-Point Single with Update */
7238 case 51: /* Load Floating-Point Double with Update */
7239 record_full_arch_list_add_reg (regcache
,
7240 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7242 case 48: /* Load Floating-Point Single */
7243 case 50: /* Load Floating-Point Double */
7244 record_full_arch_list_add_reg (regcache
,
7245 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
7248 case 47: /* Store Multiple Word */
7252 if (PPC_RA (insn
) != 0)
7253 regcache_raw_read_unsigned (regcache
,
7254 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7257 iaddr
+= PPC_D (insn
);
7258 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
7262 case 37: /* Store Word with Update */
7263 case 39: /* Store Byte with Update */
7264 case 45: /* Store Halfword with Update */
7265 case 53: /* Store Floating-Point Single with Update */
7266 case 55: /* Store Floating-Point Double with Update */
7267 record_full_arch_list_add_reg (regcache
,
7268 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7270 case 36: /* Store Word */
7271 case 38: /* Store Byte */
7272 case 44: /* Store Halfword */
7273 case 52: /* Store Floating-Point Single */
7274 case 54: /* Store Floating-Point Double */
7279 if (PPC_RA (insn
) != 0)
7280 regcache_raw_read_unsigned (regcache
,
7281 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7283 iaddr
+= PPC_D (insn
);
7285 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
7287 else if (op6
== 54 || op6
== 55)
7289 else if (op6
== 44 || op6
== 45)
7291 else if (op6
== 38 || op6
== 39)
7296 record_full_arch_list_add_mem (iaddr
, size
);
7303 case 0: /* Load Floating-Point Double Pair */
7304 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
7305 record_full_arch_list_add_reg (regcache
, tmp
);
7306 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7308 case 2: /* Load VSX Scalar Doubleword */
7309 case 3: /* Load VSX Scalar Single */
7310 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
7317 case 58: /* Load Doubleword */
7318 /* Load Doubleword with Update */
7319 /* Load Word Algebraic */
7320 if (PPC_FIELD (insn
, 30, 2) > 2)
7323 record_full_arch_list_add_reg (regcache
,
7324 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7325 if (PPC_BIT (insn
, 31))
7326 record_full_arch_list_add_reg (regcache
,
7327 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7331 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
7336 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
7341 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
7345 case 62: /* Store Doubleword */
7346 /* Store Doubleword with Update */
7347 /* Store Quadword with Update */
7351 int sub2
= PPC_FIELD (insn
, 30, 2);
7356 if (PPC_RA (insn
) != 0)
7357 regcache_raw_read_unsigned (regcache
,
7358 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7361 size
= (sub2
== 2) ? 16 : 8;
7363 iaddr
+= PPC_DS (insn
) << 2;
7364 record_full_arch_list_add_mem (iaddr
, size
);
7366 if (op6
== 62 && sub2
== 1)
7367 record_full_arch_list_add_reg (regcache
,
7368 tdep
->ppc_gp0_regnum
+
7375 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
7381 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
7382 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
7386 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
7388 if (record_full_arch_list_add_end ())
7393 /* Used for matching tw, twi, td and tdi instructions for POWER. */
7395 static constexpr uint32_t TX_INSN_MASK
= 0xFC0007FF;
7396 static constexpr uint32_t TW_INSN
= 0x7C000008;
7397 static constexpr uint32_t TD_INSN
= 0x7C000088;
7399 static constexpr uint32_t TXI_INSN_MASK
= 0xFC000000;
7400 static constexpr uint32_t TWI_INSN
= 0x0C000000;
7401 static constexpr uint32_t TDI_INSN
= 0x08000000;
7404 is_tw_insn (uint32_t insn
)
7406 return (insn
& TX_INSN_MASK
) == TW_INSN
;
7410 is_twi_insn (uint32_t insn
)
7412 return (insn
& TXI_INSN_MASK
) == TWI_INSN
;
7416 is_td_insn (uint32_t insn
)
7418 return (insn
& TX_INSN_MASK
) == TD_INSN
;
7422 is_tdi_insn (uint32_t insn
)
7424 return (insn
& TXI_INSN_MASK
) == TDI_INSN
;
7427 /* Implementation of gdbarch_program_breakpoint_here_p for POWER. */
7430 rs6000_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
7432 gdb_byte target_mem
[PPC_INSN_SIZE
];
7434 /* Enable the automatic memory restoration from breakpoints while
7435 we read the memory. Otherwise we may find temporary breakpoints, ones
7436 inserted by GDB, and flag them as permanent breakpoints. */
7437 scoped_restore restore_memory
7438 = make_scoped_restore_show_memory_breakpoints (0);
7440 if (target_read_memory (address
, target_mem
, PPC_INSN_SIZE
) == 0)
7442 uint32_t insn
= (uint32_t) extract_unsigned_integer
7443 (target_mem
, PPC_INSN_SIZE
, gdbarch_byte_order_for_code (gdbarch
));
7445 /* Check if INSN is a TW, TWI, TD or TDI instruction. There
7446 are multiple choices of such instructions with different registers
7447 and / or immediate values but they all cause a break. */
7448 if (is_tw_insn (insn
) || is_twi_insn (insn
) || is_td_insn (insn
)
7449 || is_tdi_insn (insn
))
7456 /* Initialize the current architecture based on INFO. If possible, re-use an
7457 architecture from ARCHES, which is a list of architectures already created
7458 during this debugging session.
7460 Called e.g. at program startup, when reading a core file, and when reading
7463 static struct gdbarch
*
7464 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7466 struct gdbarch
*gdbarch
;
7467 int wordsize
, from_xcoff_exec
, from_elf_exec
;
7468 enum bfd_architecture arch
;
7471 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
7473 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
7474 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
7475 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
7476 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
7477 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
7478 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
7479 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
7480 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
7481 int have_htm_tar
= 0;
7482 int tdesc_wordsize
= -1;
7483 const struct target_desc
*tdesc
= info
.target_desc
;
7484 tdesc_arch_data_up tdesc_data
;
7485 int num_pseudoregs
= 0;
7488 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
7489 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
7491 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
7492 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
7494 /* Check word size. If INFO is from a binary file, infer it from
7495 that, else choose a likely default. */
7496 if (from_xcoff_exec
)
7498 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
7503 else if (from_elf_exec
)
7505 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
7510 else if (tdesc_has_registers (tdesc
))
7514 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
7515 wordsize
= (info
.bfd_arch_info
->bits_per_word
7516 / info
.bfd_arch_info
->bits_per_byte
);
7521 /* Get the architecture and machine from the BFD. */
7522 arch
= info
.bfd_arch_info
->arch
;
7523 mach
= info
.bfd_arch_info
->mach
;
7525 /* For e500 executables, the apuinfo section is of help here. Such
7526 section contains the identifier and revision number of each
7527 Application-specific Processing Unit that is present on the
7528 chip. The content of the section is determined by the assembler
7529 which looks at each instruction and determines which unit (and
7530 which version of it) can execute it. Grovel through the section
7531 looking for relevant e500 APUs. */
7533 if (bfd_uses_spe_extensions (info
.abfd
))
7535 arch
= info
.bfd_arch_info
->arch
;
7536 mach
= bfd_mach_ppc_e500
;
7537 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
7538 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
7541 /* Find a default target description which describes our register
7542 layout, if we do not already have one. */
7543 if (! tdesc_has_registers (tdesc
))
7545 const struct ppc_variant
*v
;
7547 /* Choose variant. */
7548 v
= find_variant_by_arch (arch
, mach
);
7555 gdb_assert (tdesc_has_registers (tdesc
));
7557 /* Check any target description for validity. */
7558 if (tdesc_has_registers (tdesc
))
7560 static const char *const gprs
[] = {
7561 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7562 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7563 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7564 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7566 const struct tdesc_feature
*feature
;
7568 static const char *const msr_names
[] = { "msr", "ps" };
7569 static const char *const cr_names
[] = { "cr", "cnd" };
7570 static const char *const ctr_names
[] = { "ctr", "cnt" };
7572 feature
= tdesc_find_feature (tdesc
,
7573 "org.gnu.gdb.power.core");
7574 if (feature
== NULL
)
7577 tdesc_data
= tdesc_data_alloc ();
7580 for (i
= 0; i
< ppc_num_gprs
; i
++)
7581 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7583 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7584 PPC_PC_REGNUM
, "pc");
7585 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7586 PPC_LR_REGNUM
, "lr");
7587 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7588 PPC_XER_REGNUM
, "xer");
7590 /* Allow alternate names for these registers, to accomodate GDB's
7592 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7593 PPC_MSR_REGNUM
, msr_names
);
7594 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7595 PPC_CR_REGNUM
, cr_names
);
7596 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7597 PPC_CTR_REGNUM
, ctr_names
);
7602 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7603 PPC_MQ_REGNUM
, "mq");
7605 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
7607 wordsize
= tdesc_wordsize
;
7609 feature
= tdesc_find_feature (tdesc
,
7610 "org.gnu.gdb.power.fpu");
7611 if (feature
!= NULL
)
7613 static const char *const fprs
[] = {
7614 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7615 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7616 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7617 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
7620 for (i
= 0; i
< ppc_num_fprs
; i
++)
7621 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7622 PPC_F0_REGNUM
+ i
, fprs
[i
]);
7623 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7624 PPC_FPSCR_REGNUM
, "fpscr");
7630 /* The fpscr register was expanded in isa 2.05 to 64 bits
7631 along with the addition of the decimal floating point
7633 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
7639 feature
= tdesc_find_feature (tdesc
,
7640 "org.gnu.gdb.power.altivec");
7641 if (feature
!= NULL
)
7643 static const char *const vector_regs
[] = {
7644 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
7645 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
7646 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
7647 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
7651 for (i
= 0; i
< ppc_num_gprs
; i
++)
7652 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7655 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7656 PPC_VSCR_REGNUM
, "vscr");
7657 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7658 PPC_VRSAVE_REGNUM
, "vrsave");
7660 if (have_spe
|| !valid_p
)
7667 /* Check for POWER7 VSX registers support. */
7668 feature
= tdesc_find_feature (tdesc
,
7669 "org.gnu.gdb.power.vsx");
7671 if (feature
!= NULL
)
7673 static const char *const vsx_regs
[] = {
7674 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
7675 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
7676 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
7677 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
7678 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
7684 for (i
= 0; i
< ppc_num_vshrs
; i
++)
7685 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7686 PPC_VSR0_UPPER_REGNUM
+ i
,
7689 if (!valid_p
|| !have_fpu
|| !have_altivec
)
7697 /* On machines supporting the SPE APU, the general-purpose registers
7698 are 64 bits long. There are SIMD vector instructions to treat them
7699 as pairs of floats, but the rest of the instruction set treats them
7700 as 32-bit registers, and only operates on their lower halves.
7702 In the GDB regcache, we treat their high and low halves as separate
7703 registers. The low halves we present as the general-purpose
7704 registers, and then we have pseudo-registers that stitch together
7705 the upper and lower halves and present them as pseudo-registers.
7707 Thus, the target description is expected to supply the upper
7708 halves separately. */
7710 feature
= tdesc_find_feature (tdesc
,
7711 "org.gnu.gdb.power.spe");
7712 if (feature
!= NULL
)
7714 static const char *const upper_spe
[] = {
7715 "ev0h", "ev1h", "ev2h", "ev3h",
7716 "ev4h", "ev5h", "ev6h", "ev7h",
7717 "ev8h", "ev9h", "ev10h", "ev11h",
7718 "ev12h", "ev13h", "ev14h", "ev15h",
7719 "ev16h", "ev17h", "ev18h", "ev19h",
7720 "ev20h", "ev21h", "ev22h", "ev23h",
7721 "ev24h", "ev25h", "ev26h", "ev27h",
7722 "ev28h", "ev29h", "ev30h", "ev31h"
7726 for (i
= 0; i
< ppc_num_gprs
; i
++)
7727 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7728 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
7730 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7731 PPC_SPE_ACC_REGNUM
, "acc");
7732 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7733 PPC_SPE_FSCR_REGNUM
, "spefscr");
7735 if (have_mq
|| have_fpu
|| !valid_p
)
7742 /* Program Priority Register. */
7743 feature
= tdesc_find_feature (tdesc
,
7744 "org.gnu.gdb.power.ppr");
7745 if (feature
!= NULL
)
7748 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7749 PPC_PPR_REGNUM
, "ppr");
7758 /* Data Stream Control Register. */
7759 feature
= tdesc_find_feature (tdesc
,
7760 "org.gnu.gdb.power.dscr");
7761 if (feature
!= NULL
)
7764 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7765 PPC_DSCR_REGNUM
, "dscr");
7774 /* Target Address Register. */
7775 feature
= tdesc_find_feature (tdesc
,
7776 "org.gnu.gdb.power.tar");
7777 if (feature
!= NULL
)
7780 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7781 PPC_TAR_REGNUM
, "tar");
7790 /* Event-based Branching Registers. */
7791 feature
= tdesc_find_feature (tdesc
,
7792 "org.gnu.gdb.power.ebb");
7793 if (feature
!= NULL
)
7795 static const char *const ebb_regs
[] = {
7796 "bescr", "ebbhr", "ebbrr"
7800 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
7801 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7802 PPC_BESCR_REGNUM
+ i
,
7811 /* Subset of the ISA 2.07 Performance Monitor Registers provided
7813 feature
= tdesc_find_feature (tdesc
,
7814 "org.gnu.gdb.power.linux.pmu");
7815 if (feature
!= NULL
)
7819 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7822 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7825 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7828 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7831 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7842 /* Hardware Transactional Memory Registers. */
7843 feature
= tdesc_find_feature (tdesc
,
7844 "org.gnu.gdb.power.htm.spr");
7845 if (feature
!= NULL
)
7847 static const char *const tm_spr_regs
[] = {
7848 "tfhar", "texasr", "tfiar"
7852 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
7853 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7854 PPC_TFHAR_REGNUM
+ i
,
7864 feature
= tdesc_find_feature (tdesc
,
7865 "org.gnu.gdb.power.htm.core");
7866 if (feature
!= NULL
)
7868 static const char *const cgprs
[] = {
7869 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
7870 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
7871 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
7872 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
7873 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
7878 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
7879 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7890 feature
= tdesc_find_feature (tdesc
,
7891 "org.gnu.gdb.power.htm.fpu");
7892 if (feature
!= NULL
)
7896 static const char *const cfprs
[] = {
7897 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
7898 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
7899 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
7900 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
7901 "cf30", "cf31", "cfpscr"
7904 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
7905 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7916 feature
= tdesc_find_feature (tdesc
,
7917 "org.gnu.gdb.power.htm.altivec");
7918 if (feature
!= NULL
)
7922 static const char *const cvmx
[] = {
7923 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
7924 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
7925 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
7926 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
7927 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
7931 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
7932 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7933 PPC_CVR0_REGNUM
+ i
,
7938 have_htm_altivec
= 1;
7941 have_htm_altivec
= 0;
7943 feature
= tdesc_find_feature (tdesc
,
7944 "org.gnu.gdb.power.htm.vsx");
7945 if (feature
!= NULL
)
7949 static const char *const cvsx
[] = {
7950 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
7951 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
7952 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
7953 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
7954 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
7958 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
7959 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7960 (PPC_CVSR0_UPPER_REGNUM
7964 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
7971 feature
= tdesc_find_feature (tdesc
,
7972 "org.gnu.gdb.power.htm.ppr");
7973 if (feature
!= NULL
)
7975 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7976 PPC_CPPR_REGNUM
, "cppr");
7985 feature
= tdesc_find_feature (tdesc
,
7986 "org.gnu.gdb.power.htm.dscr");
7987 if (feature
!= NULL
)
7989 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7990 PPC_CDSCR_REGNUM
, "cdscr");
7999 feature
= tdesc_find_feature (tdesc
,
8000 "org.gnu.gdb.power.htm.tar");
8001 if (feature
!= NULL
)
8003 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
8004 PPC_CTAR_REGNUM
, "ctar");
8014 /* If we have a 64-bit binary on a 32-bit target, complain. Also
8015 complain for a 32-bit binary on a 64-bit target; we do not yet
8016 support that. For instance, the 32-bit ABI routines expect
8019 As long as there isn't an explicit target description, we'll
8020 choose one based on the BFD architecture and get a word size
8021 matching the binary (probably powerpc:common or
8022 powerpc:common64). So there is only trouble if a 64-bit target
8023 supplies a 64-bit description while debugging a 32-bit
8025 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
8031 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
8034 elf_abi
= POWERPC_ELF_V1
;
8037 elf_abi
= POWERPC_ELF_V2
;
8044 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
8046 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8047 Tag_GNU_Power_ABI_FP
) & 3)
8050 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
8053 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
8060 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
8062 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8063 Tag_GNU_Power_ABI_FP
) >> 2)
8066 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
8069 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
8076 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
8078 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8079 Tag_GNU_Power_ABI_Vector
))
8082 vector_abi
= POWERPC_VEC_GENERIC
;
8085 vector_abi
= POWERPC_VEC_ALTIVEC
;
8088 vector_abi
= POWERPC_VEC_SPE
;
8096 /* At this point, the only supported ELF-based 64-bit little-endian
8097 operating system is GNU/Linux, and this uses the ELFv2 ABI by
8098 default. All other supported ELF-based operating systems use the
8099 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
8100 e.g. because we run a legacy binary, or have attached to a process
8101 and have not found any associated binary file, set the default
8102 according to this heuristic. */
8103 if (elf_abi
== POWERPC_ELF_AUTO
)
8105 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
8106 elf_abi
= POWERPC_ELF_V2
;
8108 elf_abi
= POWERPC_ELF_V1
;
8111 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
8113 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
8116 soft_float
= !have_fpu
;
8118 /* If we have a hard float binary or setting but no floating point
8119 registers, downgrade to soft float anyway. We're still somewhat
8120 useful in this scenario. */
8121 if (!soft_float
&& !have_fpu
)
8124 /* Similarly for vector registers. */
8125 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
8126 vector_abi
= POWERPC_VEC_GENERIC
;
8128 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
8129 vector_abi
= POWERPC_VEC_GENERIC
;
8131 if (vector_abi
== POWERPC_VEC_AUTO
)
8134 vector_abi
= POWERPC_VEC_ALTIVEC
;
8136 vector_abi
= POWERPC_VEC_SPE
;
8138 vector_abi
= POWERPC_VEC_GENERIC
;
8141 /* Do not limit the vector ABI based on available hardware, since we
8142 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
8144 /* Find a candidate among extant architectures. */
8145 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8147 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8149 /* Word size in the various PowerPC bfd_arch_info structs isn't
8150 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
8151 separate word size check. */
8152 ppc_gdbarch_tdep
*tdep
8153 = gdbarch_tdep
<ppc_gdbarch_tdep
> (arches
->gdbarch
);
8154 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
8156 if (tdep
&& tdep
->soft_float
!= soft_float
)
8158 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
8160 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
8162 if (tdep
&& tdep
->wordsize
== wordsize
)
8163 return arches
->gdbarch
;
8166 /* None found, create a new architecture from INFO, whose bfd_arch_info
8167 validity depends on the source:
8168 - executable useless
8169 - rs6000_host_arch() good
8171 - "set arch" trust blindly
8172 - GDB startup useless but harmless */
8174 ppc_gdbarch_tdep
*tdep
= new ppc_gdbarch_tdep
;
8175 tdep
->wordsize
= wordsize
;
8176 tdep
->elf_abi
= elf_abi
;
8177 tdep
->soft_float
= soft_float
;
8178 tdep
->long_double_abi
= long_double_abi
;
8179 tdep
->vector_abi
= vector_abi
;
8181 gdbarch
= gdbarch_alloc (&info
, tdep
);
8183 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
8184 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
8185 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
8186 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
8187 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
8188 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
8189 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
8190 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
8192 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
8193 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
8194 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
8195 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
8196 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
8197 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
8198 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
8199 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
8200 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
8201 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
8202 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
8203 tdep
->have_ebb
= have_ebb
;
8205 /* If additional pmu registers are added, care must be taken when
8206 setting new fields in the tdep below, to maintain compatibility
8207 with features that only provide some of the registers. Currently
8208 gdb access to the pmu registers is only supported in linux, and
8209 linux only provides a subset of the pmu registers defined in the
8212 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
8213 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
8214 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
8215 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
8216 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
8218 tdep
->have_htm_spr
= have_htm_spr
;
8219 tdep
->have_htm_core
= have_htm_core
;
8220 tdep
->have_htm_fpu
= have_htm_fpu
;
8221 tdep
->have_htm_altivec
= have_htm_altivec
;
8222 tdep
->have_htm_vsx
= have_htm_vsx
;
8223 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
8224 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
8225 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
8227 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
8228 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
8229 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
8230 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
8232 /* The XML specification for PowerPC sensibly calls the MSR "msr".
8233 GDB traditionally called it "ps", though, so let GDB add an
8235 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
8238 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
8240 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
8242 /* Set lr_frame_offset. */
8244 tdep
->lr_frame_offset
= 16;
8246 tdep
->lr_frame_offset
= 4;
8248 if (have_spe
|| have_dfp
|| have_altivec
8249 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
8251 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
8252 set_gdbarch_pseudo_register_write (gdbarch
,
8253 rs6000_pseudo_register_write
);
8254 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8255 rs6000_ax_pseudo_register_collect
);
8258 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
8260 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8262 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
8265 num_pseudoregs
+= 32;
8267 num_pseudoregs
+= 16;
8269 num_pseudoregs
+= 32;
8271 /* Include both VSX and Extended FP registers. */
8272 num_pseudoregs
+= 96;
8274 num_pseudoregs
+= 16;
8275 /* Include both checkpointed VSX and EFP registers. */
8277 num_pseudoregs
+= 64 + 32;
8279 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
8281 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
8282 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
8283 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
8284 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
8285 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
8286 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
8287 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
8288 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
8289 set_gdbarch_char_signed (gdbarch
, 0);
8291 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
8294 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
8296 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
8297 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
8298 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
8300 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
8301 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
8304 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
8305 else if (wordsize
== 8)
8306 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
8308 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
8309 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
8310 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
8312 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8314 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
8315 rs6000_breakpoint::kind_from_pc
);
8316 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
8317 rs6000_breakpoint::bp_from_kind
);
8318 set_gdbarch_program_breakpoint_here_p (gdbarch
,
8319 rs6000_program_breakpoint_here_p
);
8321 /* The value of symbols of type N_SO and N_FUN maybe null when
8323 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
8325 /* Handles single stepping of atomic sequences. */
8326 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
8328 /* Not sure on this. FIXMEmgo */
8329 set_gdbarch_frame_args_skip (gdbarch
, 8);
8331 /* Helpers for function argument information. */
8332 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
8335 set_gdbarch_in_solib_return_trampoline
8336 (gdbarch
, rs6000_in_solib_return_trampoline
);
8337 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
8339 /* Hook in the DWARF CFI frame unwinder. */
8340 dwarf2_append_unwinders (gdbarch
);
8341 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
8343 /* Frame handling. */
8344 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
8346 /* Setup displaced stepping. */
8347 set_gdbarch_displaced_step_copy_insn (gdbarch
,
8348 ppc_displaced_step_copy_insn
);
8349 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
8350 ppc_displaced_step_hw_singlestep
);
8351 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
8352 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
8353 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
8354 set_gdbarch_displaced_step_restore_all_in_ptid
8355 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
8357 set_gdbarch_max_insn_length (gdbarch
, 2 * PPC_INSN_SIZE
);
8359 /* Hook in ABI-specific overrides, if they have been registered. */
8360 info
.target_desc
= tdesc
;
8361 info
.tdesc_data
= tdesc_data
.get ();
8362 gdbarch_init_osabi (info
, gdbarch
);
8366 case GDB_OSABI_LINUX
:
8367 case GDB_OSABI_NETBSD
:
8368 case GDB_OSABI_UNKNOWN
:
8369 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
8370 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
8371 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
8374 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
8376 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
8377 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
8378 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
8381 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
8382 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
8383 rs6000_pseudo_register_reggroup_p
);
8384 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8386 /* Override the normal target description method to make the SPE upper
8387 halves anonymous. */
8388 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
8390 /* Choose register numbers for all supported pseudo-registers. */
8391 tdep
->ppc_ev0_regnum
= -1;
8392 tdep
->ppc_dl0_regnum
= -1;
8393 tdep
->ppc_v0_alias_regnum
= -1;
8394 tdep
->ppc_vsr0_regnum
= -1;
8395 tdep
->ppc_efpr0_regnum
= -1;
8396 tdep
->ppc_cdl0_regnum
= -1;
8397 tdep
->ppc_cvsr0_regnum
= -1;
8398 tdep
->ppc_cefpr0_regnum
= -1;
8400 cur_reg
= gdbarch_num_regs (gdbarch
);
8404 tdep
->ppc_ev0_regnum
= cur_reg
;
8409 tdep
->ppc_dl0_regnum
= cur_reg
;
8414 tdep
->ppc_v0_alias_regnum
= cur_reg
;
8419 tdep
->ppc_vsr0_regnum
= cur_reg
;
8421 tdep
->ppc_efpr0_regnum
= cur_reg
;
8426 tdep
->ppc_cdl0_regnum
= cur_reg
;
8431 tdep
->ppc_cvsr0_regnum
= cur_reg
;
8433 tdep
->ppc_cefpr0_regnum
= cur_reg
;
8437 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
8439 /* Register the ravenscar_arch_ops. */
8440 if (mach
== bfd_mach_ppc_e500
)
8441 register_e500_ravenscar_ops (gdbarch
);
8443 register_ppc_ravenscar_ops (gdbarch
);
8445 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
8446 set_gdbarch_valid_disassembler_options (gdbarch
,
8447 disassembler_options_powerpc ());
8453 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8455 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
8460 /* FIXME: Dump gdbarch_tdep. */
8464 powerpc_set_soft_float (const char *args
, int from_tty
,
8465 struct cmd_list_element
*c
)
8467 struct gdbarch_info info
;
8469 /* Update the architecture. */
8470 if (!gdbarch_update_p (info
))
8471 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8475 powerpc_set_vector_abi (const char *args
, int from_tty
,
8476 struct cmd_list_element
*c
)
8480 for (vector_abi
= POWERPC_VEC_AUTO
;
8481 vector_abi
!= POWERPC_VEC_LAST
;
8483 if (strcmp (powerpc_vector_abi_string
,
8484 powerpc_vector_strings
[vector_abi
]) == 0)
8486 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
8490 if (vector_abi
== POWERPC_VEC_LAST
)
8491 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
8492 powerpc_vector_abi_string
);
8494 /* Update the architecture. */
8496 if (!gdbarch_update_p (info
))
8497 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8500 /* Show the current setting of the exact watchpoints flag. */
8503 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
8504 struct cmd_list_element
*c
,
8507 gdb_printf (file
, _("Use of exact watchpoints is %s.\n"), value
);
8510 /* Read a PPC instruction from memory. */
8513 read_insn (frame_info_ptr frame
, CORE_ADDR pc
)
8515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8516 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8518 return read_memory_unsigned_integer (pc
, 4, byte_order
);
8521 /* Return non-zero if the instructions at PC match the series
8522 described in PATTERN, or zero otherwise. PATTERN is an array of
8523 'struct ppc_insn_pattern' objects, terminated by an entry whose
8526 When the match is successful, fill INSNS[i] with what PATTERN[i]
8527 matched. If PATTERN[i] is optional, and the instruction wasn't
8528 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
8529 INSNS should have as many elements as PATTERN, minus the terminator.
8530 Note that, if PATTERN contains optional instructions which aren't
8531 present in memory, then INSNS will have holes, so INSNS[i] isn't
8532 necessarily the i'th instruction in memory. */
8535 ppc_insns_match_pattern (frame_info_ptr frame
, CORE_ADDR pc
,
8536 const struct ppc_insn_pattern
*pattern
,
8537 unsigned int *insns
)
8542 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
8545 insn
= read_insn (frame
, pc
);
8547 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
8553 else if (!pattern
[i
].optional
)
8560 /* Return the 'd' field of the d-form instruction INSN, properly
8564 ppc_insn_d_field (unsigned int insn
)
8566 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
8569 /* Return the 'ds' field of the ds-form instruction INSN, with the two
8570 zero bits concatenated at the right, and properly
8574 ppc_insn_ds_field (unsigned int insn
)
8576 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
8580 ppc_insn_prefix_dform (unsigned int insn1
, unsigned int insn2
)
8582 /* result is 34-bits */
8583 return (CORE_ADDR
) ((((insn1
& 0x3ffff) ^ 0x20000) - 0x20000) << 16)
8584 | (CORE_ADDR
)(insn2
& 0xffff);
8587 /* Initialization code. */
8589 void _initialize_rs6000_tdep ();
8591 _initialize_rs6000_tdep ()
8593 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
8594 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
8596 /* Initialize the standard target descriptions. */
8597 initialize_tdesc_powerpc_32 ();
8598 initialize_tdesc_powerpc_altivec32 ();
8599 initialize_tdesc_powerpc_vsx32 ();
8600 initialize_tdesc_powerpc_403 ();
8601 initialize_tdesc_powerpc_403gc ();
8602 initialize_tdesc_powerpc_405 ();
8603 initialize_tdesc_powerpc_505 ();
8604 initialize_tdesc_powerpc_601 ();
8605 initialize_tdesc_powerpc_602 ();
8606 initialize_tdesc_powerpc_603 ();
8607 initialize_tdesc_powerpc_604 ();
8608 initialize_tdesc_powerpc_64 ();
8609 initialize_tdesc_powerpc_altivec64 ();
8610 initialize_tdesc_powerpc_vsx64 ();
8611 initialize_tdesc_powerpc_7400 ();
8612 initialize_tdesc_powerpc_750 ();
8613 initialize_tdesc_powerpc_860 ();
8614 initialize_tdesc_powerpc_e500 ();
8615 initialize_tdesc_rs6000 ();
8617 /* Add root prefix command for all "set powerpc"/"show powerpc"
8619 add_setshow_prefix_cmd ("powerpc", no_class
,
8620 _("Various PowerPC-specific commands."),
8621 _("Various PowerPC-specific commands."),
8622 &setpowerpccmdlist
, &showpowerpccmdlist
,
8623 &setlist
, &showlist
);
8625 /* Add a command to allow the user to force the ABI. */
8626 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
8627 &powerpc_soft_float_global
,
8628 _("Set whether to use a soft-float ABI."),
8629 _("Show whether to use a soft-float ABI."),
8631 powerpc_set_soft_float
, NULL
,
8632 &setpowerpccmdlist
, &showpowerpccmdlist
);
8634 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
8635 &powerpc_vector_abi_string
,
8636 _("Set the vector ABI."),
8637 _("Show the vector ABI."),
8638 NULL
, powerpc_set_vector_abi
, NULL
,
8639 &setpowerpccmdlist
, &showpowerpccmdlist
);
8641 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
8642 &target_exact_watchpoints
,
8644 Set whether to use just one debug register for watchpoints on scalars."),
8646 Show whether to use just one debug register for watchpoints on scalars."),
8648 If true, GDB will use only one debug register when watching a variable of\n\
8649 scalar type, thus assuming that the variable is accessed through the address\n\
8650 of its first byte."),
8651 NULL
, show_powerpc_exact_watchpoints
,
8652 &setpowerpccmdlist
, &showpowerpccmdlist
);