1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2/frame.h"
35 #include "arch-utils.h"
37 #include "target-float.h"
39 #include "reggroups.h"
46 #include "solib-svr4.h"
51 /* registers numbers shared with the simulator. */
52 #include "gdb/sim-sh.h"
55 /* List of "set sh ..." and "show sh ..." commands. */
56 static struct cmd_list_element
*setshcmdlist
= NULL
;
57 static struct cmd_list_element
*showshcmdlist
= NULL
;
59 static const char sh_cc_gcc
[] = "gcc";
60 static const char sh_cc_renesas
[] = "renesas";
61 static const char *const sh_cc_enum
[] = {
67 static const char *sh_active_calling_convention
= sh_cc_gcc
;
69 #define SH_NUM_REGS 67
78 /* Flag showing that a frame has been created in the prologue code. */
81 /* Saved registers. */
82 CORE_ADDR saved_regs
[SH_NUM_REGS
];
87 sh_is_renesas_calling_convention (struct type
*func_type
)
93 func_type
= check_typedef (func_type
);
95 if (func_type
->code () == TYPE_CODE_PTR
)
96 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
98 if (func_type
->code () == TYPE_CODE_FUNC
99 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
103 if (sh_active_calling_convention
== sh_cc_renesas
)
110 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
112 static const char *register_names
[] = {
113 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
114 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
115 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
117 "", "", "", "", "", "", "", "",
118 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
126 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
128 return register_names
[reg_nr
];
132 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
134 static const char *register_names
[] = {
135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
137 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
139 "", "", "", "", "", "", "", "",
140 "", "", "", "", "", "", "", "",
142 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
143 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
144 "", "", "", "", "", "", "", "",
148 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
150 return register_names
[reg_nr
];
154 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
156 static const char *register_names
[] = {
157 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
158 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
159 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
161 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
162 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
164 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
165 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
166 "", "", "", "", "", "", "", "",
170 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
172 return register_names
[reg_nr
];
176 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
178 static const char *register_names
[] = {
179 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
180 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
181 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
183 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
184 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
192 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
194 return register_names
[reg_nr
];
198 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
200 static const char *register_names
[] = {
201 /* general registers 0-15 */
202 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
203 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
205 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
208 /* floating point registers 25 - 40 */
209 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
210 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
213 /* 43 - 62. Banked registers. The bank number used is determined by
214 the bank register (63). */
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
216 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
217 "machb", "ivnb", "prb", "gbrb", "maclb",
218 /* 63: register bank number, not a real register but used to
219 communicate the register bank currently get/set. This register
220 is hidden to the user, who manipulates it using the pseudo
221 register called "bank" (67). See below. */
224 "ibcr", "ibnr", "tbr",
225 /* 67: register bank number, the user visible pseudo register. */
227 /* double precision (pseudo) 68 - 75 */
228 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
232 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
234 return register_names
[reg_nr
];
238 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
240 static const char *register_names
[] = {
241 /* general registers 0-15 */
242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
245 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
248 /* floating point registers 25 - 40 */
249 "", "", "", "", "", "", "", "",
250 "", "", "", "", "", "", "", "",
253 /* 43 - 62. Banked registers. The bank number used is determined by
254 the bank register (63). */
255 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
256 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
257 "machb", "ivnb", "prb", "gbrb", "maclb",
258 /* 63: register bank number, not a real register but used to
259 communicate the register bank currently get/set. This register
260 is hidden to the user, who manipulates it using the pseudo
261 register called "bank" (67). See below. */
264 "ibcr", "ibnr", "tbr",
265 /* 67: register bank number, the user visible pseudo register. */
267 /* double precision (pseudo) 68 - 75 */
268 "", "", "", "", "", "", "", "",
272 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
274 return register_names
[reg_nr
];
278 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
280 static const char *register_names
[] = {
281 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
282 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
283 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
285 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
286 "y0", "y1", "", "", "", "", "", "mod",
288 "rs", "re", "", "", "", "", "", "",
289 "", "", "", "", "", "", "", "",
290 "", "", "", "", "", "", "", "",
294 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
296 return register_names
[reg_nr
];
300 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
302 static const char *register_names
[] = {
303 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
304 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
305 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
307 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
308 "y0", "y1", "", "", "", "", "", "mod",
310 "rs", "re", "", "", "", "", "", "",
311 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
312 "", "", "", "", "", "", "", "",
313 "", "", "", "", "", "", "", "",
317 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
319 return register_names
[reg_nr
];
323 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
325 static const char *register_names
[] = {
326 /* general registers 0-15 */
327 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
328 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
330 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
333 /* floating point registers 25 - 40 */
334 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
335 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
339 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
341 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
343 "", "", "", "", "", "", "", "",
344 /* pseudo bank register. */
346 /* double precision (pseudo) 68 - 75 */
347 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
348 /* vectors (pseudo) 76 - 79 */
349 "fv0", "fv4", "fv8", "fv12",
350 /* FIXME: missing XF */
351 /* FIXME: missing XD */
355 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
357 return register_names
[reg_nr
];
361 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
363 static const char *register_names
[] = {
364 /* general registers 0-15 */
365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
368 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
371 /* floating point registers 25 - 40 -- not for nofpu target */
372 "", "", "", "", "", "", "", "",
373 "", "", "", "", "", "", "", "",
377 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
379 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
381 "", "", "", "", "", "", "", "",
382 /* pseudo bank register. */
384 /* double precision (pseudo) 68 - 75 -- not for nofpu target */
385 "", "", "", "", "", "", "", "",
386 /* vectors (pseudo) 76 - 79 -- not for nofpu target */
391 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
393 return register_names
[reg_nr
];
397 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
399 static const char *register_names
[] = {
400 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
401 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
402 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
404 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
405 "y0", "y1", "", "", "", "", "", "mod",
407 "rs", "re", "", "", "", "", "", "",
408 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
409 "", "", "", "", "", "", "", "",
410 "", "", "", "", "", "", "", "",
414 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
416 return register_names
[reg_nr
];
419 /* Implement the breakpoint_kind_from_pc gdbarch method. */
422 sh_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
427 /* Implement the sw_breakpoint_from_kind gdbarch method. */
429 static const gdb_byte
*
430 sh_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
434 /* For remote stub targets, trapa #20 is used. */
435 if (strcmp (target_shortname
, "remote") == 0)
437 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
438 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
440 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
441 return big_remote_breakpoint
;
443 return little_remote_breakpoint
;
447 /* 0xc3c3 is trapa #c3, and it works in big and little endian
449 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
455 /* Prologue looks like
459 sub <room_for_loca_vars>,r15
462 Actually it can be more complicated than this but that's it, basically. */
464 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
465 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
467 /* JSR @Rm 0100mmmm00001011 */
468 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
470 /* STS.L PR,@-r15 0100111100100010
471 r15-4-->r15, PR-->(r15) */
472 #define IS_STS(x) ((x) == 0x4f22)
474 /* STS.L MACL,@-r15 0100111100010010
475 r15-4-->r15, MACL-->(r15) */
476 #define IS_MACL_STS(x) ((x) == 0x4f12)
478 /* MOV.L Rm,@-r15 00101111mmmm0110
479 r15-4-->r15, Rm-->(R15) */
480 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
482 /* MOV r15,r14 0110111011110011
484 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
486 /* ADD #imm,r15 01111111iiiiiiii
488 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
490 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
491 #define IS_SHLL_R3(x) ((x) == 0x4300)
493 /* ADD r3,r15 0011111100111100
495 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
497 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
498 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
499 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
500 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
501 make this entirely clear. */
502 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
503 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
505 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
506 #define IS_MOV_ARG_TO_REG(x) \
507 (((x) & 0xf00f) == 0x6003 && \
508 ((x) & 0x00f0) >= 0x0040 && \
509 ((x) & 0x00f0) <= 0x0070)
510 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
511 #define IS_MOV_ARG_TO_IND_R14(x) \
512 (((x) & 0xff0f) == 0x2e02 && \
513 ((x) & 0x00f0) >= 0x0040 && \
514 ((x) & 0x00f0) <= 0x0070)
515 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
516 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
517 (((x) & 0xff00) == 0x1e00 && \
518 ((x) & 0x00f0) >= 0x0040 && \
519 ((x) & 0x00f0) <= 0x0070)
521 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
522 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
523 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
524 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
525 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
526 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
527 /* SUB Rn,R15 00111111nnnn1000 */
528 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
530 #define FPSCR_SZ (1 << 20)
532 /* The following instructions are used for epilogue testing. */
533 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
534 #define IS_RTS(x) ((x) == 0x000b)
535 #define IS_LDS(x) ((x) == 0x4f26)
536 #define IS_MACL_LDS(x) ((x) == 0x4f16)
537 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
538 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
539 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
542 sh_analyze_prologue (struct gdbarch
*gdbarch
,
543 CORE_ADDR pc
, CORE_ADDR limit_pc
,
544 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
546 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
551 int reg
, sav_reg
= -1;
554 for (; pc
< limit_pc
; pc
+= 2)
556 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
557 /* See where the registers will be saved to. */
560 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
561 cache
->sp_offset
+= 4;
563 else if (IS_STS (inst
))
565 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
566 cache
->sp_offset
+= 4;
568 else if (IS_MACL_STS (inst
))
570 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
571 cache
->sp_offset
+= 4;
573 else if (IS_MOV_R3 (inst
))
575 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
577 else if (IS_SHLL_R3 (inst
))
581 else if (IS_ADD_R3SP (inst
))
583 cache
->sp_offset
+= -r3_val
;
585 else if (IS_ADD_IMM_SP (inst
))
587 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
588 cache
->sp_offset
-= offset
;
590 else if (IS_MOVW_PCREL_TO_REG (inst
))
594 reg
= GET_TARGET_REG (inst
);
598 offset
= (inst
& 0xff) << 1;
600 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
604 else if (IS_MOVL_PCREL_TO_REG (inst
))
608 reg
= GET_TARGET_REG (inst
);
612 offset
= (inst
& 0xff) << 2;
614 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
619 else if (IS_MOVI20 (inst
)
620 && (pc
+ 2 < limit_pc
))
624 reg
= GET_TARGET_REG (inst
);
628 sav_offset
= GET_SOURCE_REG (inst
) << 16;
629 /* MOVI20 is a 32 bit instruction! */
632 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
633 /* Now sav_offset contains an unsigned 20 bit value.
634 It must still get sign extended. */
635 if (sav_offset
& 0x00080000)
636 sav_offset
|= 0xfff00000;
640 else if (IS_SUB_REG_FROM_SP (inst
))
642 reg
= GET_SOURCE_REG (inst
);
643 if (sav_reg
> 0 && reg
== sav_reg
)
647 cache
->sp_offset
+= sav_offset
;
649 else if (IS_FPUSH (inst
))
651 if (fpscr
& FPSCR_SZ
)
653 cache
->sp_offset
+= 8;
657 cache
->sp_offset
+= 4;
660 else if (IS_MOV_SP_FP (inst
))
663 /* Don't go any further than six more instructions. */
664 limit_pc
= std::min (limit_pc
, pc
+ (2 * 6));
667 /* At this point, only allow argument register moves to other
668 registers or argument register moves to @(X,fp) which are
669 moving the register arguments onto the stack area allocated
670 by a former add somenumber to SP call. Don't allow moving
671 to an fp indirect address above fp + cache->sp_offset. */
672 for (; pc
< limit_pc
; pc
+= 2)
674 inst
= read_memory_integer (pc
, 2, byte_order
);
675 if (IS_MOV_ARG_TO_IND_R14 (inst
))
677 reg
= GET_SOURCE_REG (inst
);
678 if (cache
->sp_offset
> 0)
679 cache
->saved_regs
[reg
] = cache
->sp_offset
;
681 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
683 reg
= GET_SOURCE_REG (inst
);
684 offset
= (inst
& 0xf) * 4;
685 if (cache
->sp_offset
> offset
)
686 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
688 else if (IS_MOV_ARG_TO_REG (inst
))
695 else if (IS_JSR (inst
))
697 /* We have found a jsr that has been scheduled into the prologue.
698 If we continue the scan and return a pc someplace after this,
699 then setting a breakpoint on this function will cause it to
700 appear to be called after the function it is calling via the
701 jsr, which will be very confusing. Most likely the next
702 instruction is going to be IS_MOV_SP_FP in the delay slot. If
703 so, note that before returning the current pc. */
704 if (pc
+ 2 < limit_pc
)
706 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
707 if (IS_MOV_SP_FP (inst
))
712 #if 0 /* This used to just stop when it found an instruction
713 that was not considered part of the prologue. Now,
714 we just keep going looking for likely
724 /* Skip any prologue before the guts of a function. */
726 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
728 CORE_ADDR post_prologue_pc
, func_addr
, func_end_addr
, limit_pc
;
729 struct sh_frame_cache cache
;
731 /* See if we can determine the end of the prologue via the symbol table.
732 If so, then return either PC, or the PC after the prologue, whichever
734 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
736 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
737 if (post_prologue_pc
!= 0)
738 return std::max (pc
, post_prologue_pc
);
741 /* Can't determine prologue from the symbol table, need to examine
744 /* Find an upper limit on the function prologue using the debug
745 information. If the debug information could not be used to provide
746 that bound, then use an arbitrary large number as the upper bound. */
747 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
749 /* Don't go any further than 28 instructions. */
750 limit_pc
= pc
+ (2 * 28);
752 /* Do not allow limit_pc to be past the function end, if we know
753 where that end is... */
754 if (func_end_addr
!= 0)
755 limit_pc
= std::min (limit_pc
, func_end_addr
);
757 cache
.sp_offset
= -4;
758 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, limit_pc
, &cache
, 0);
760 pc
= post_prologue_pc
;
767 Aggregate types not bigger than 8 bytes that have the same size and
768 alignment as one of the integer scalar types are returned in the
769 same registers as the integer type they match.
771 For example, a 2-byte aligned structure with size 2 bytes has the
772 same size and alignment as a short int, and will be returned in R0.
773 A 4-byte aligned structure with size 8 bytes has the same size and
774 alignment as a long long int, and will be returned in R0 and R1.
776 When an aggregate type is returned in R0 and R1, R0 contains the
777 first four bytes of the aggregate, and R1 contains the
778 remainder. If the size of the aggregate type is not a multiple of 4
779 bytes, the aggregate is tail-padded up to a multiple of 4
780 bytes. The value of the padding is undefined. For little-endian
781 targets the padding will appear at the most significant end of the
782 last element, for big-endian targets the padding appears at the
783 least significant end of the last element.
785 All other aggregate types are returned by address. The caller
786 function passes the address of an area large enough to hold the
787 aggregate value in R2. The called function stores the result in
790 To reiterate, structs smaller than 8 bytes could also be returned
791 in memory, if they don't pass the "same size and alignment as an
796 struct s { char c[3]; } wibble;
797 struct s foo(void) { return wibble; }
799 the return value from foo() will be in memory, not
800 in R0, because there is no 3-byte integer type.
804 struct s { char c[2]; } wibble;
805 struct s foo(void) { return wibble; }
807 because a struct containing two chars has alignment 1, that matches
808 type char, but size 2, that matches type short. There's no integer
809 type that has alignment 1 and size 2, so the struct is returned in
813 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
815 int len
= TYPE_LENGTH (type
);
816 int nelem
= type
->num_fields ();
818 /* The Renesas ABI returns aggregate types always on stack. */
819 if (renesas_abi
&& (type
->code () == TYPE_CODE_STRUCT
820 || type
->code () == TYPE_CODE_UNION
))
823 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
824 fit in two registers anyway) use struct convention. */
825 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
828 /* Scalar types and aggregate types with exactly one field are aligned
829 by definition. They are returned in registers. */
833 /* If the first field in the aggregate has the same length as the entire
834 aggregate type, the type is returned in registers. */
835 if (TYPE_LENGTH (type
->field (0).type ()) == len
)
838 /* If the size of the aggregate is 8 bytes and the first field is
839 of size 4 bytes its alignment is equal to long long's alignment,
840 so it's returned in registers. */
841 if (len
== 8 && TYPE_LENGTH (type
->field (0).type ()) == 4)
844 /* Otherwise use struct convention. */
849 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
851 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
852 if (renesas_abi
&& type
->num_fields () == 0 && TYPE_LENGTH (type
) >= 8)
854 return sh_use_struct_convention (renesas_abi
, type
);
858 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
863 /* Function: push_dummy_call (formerly push_arguments)
864 Setup the function arguments for calling a function in the inferior.
866 On the Renesas SH architecture, there are four registers (R4 to R7)
867 which are dedicated for passing function arguments. Up to the first
868 four arguments (depending on size) may go into these registers.
869 The rest go on the stack.
871 MVS: Except on SH variants that have floating point registers.
872 In that case, float and double arguments are passed in the same
873 manner, but using FP registers instead of GP registers.
875 Arguments that are smaller than 4 bytes will still take up a whole
876 register or a whole 32-bit word on the stack, and will be
877 right-justified in the register or the stack word. This includes
878 chars, shorts, and small aggregate types.
880 Arguments that are larger than 4 bytes may be split between two or
881 more registers. If there are not enough registers free, an argument
882 may be passed partly in a register (or registers), and partly on the
883 stack. This includes doubles, long longs, and larger aggregates.
884 As far as I know, there is no upper limit to the size of aggregates
885 that will be passed in this way; in other words, the convention of
886 passing a pointer to a large aggregate instead of a copy is not used.
888 MVS: The above appears to be true for the SH variants that do not
889 have an FPU, however those that have an FPU appear to copy the
890 aggregate argument onto the stack (and not place it in registers)
891 if it is larger than 16 bytes (four GP registers).
893 An exceptional case exists for struct arguments (and possibly other
894 aggregates such as arrays) if the size is larger than 4 bytes but
895 not a multiple of 4 bytes. In this case the argument is never split
896 between the registers and the stack, but instead is copied in its
897 entirety onto the stack, AND also copied into as many registers as
898 there is room for. In other words, space in registers permitting,
899 two copies of the same argument are passed in. As far as I can tell,
900 only the one on the stack is used, although that may be a function
901 of the level of compiler optimization. I suspect this is a compiler
902 bug. Arguments of these odd sizes are left-justified within the
903 word (as opposed to arguments smaller than 4 bytes, which are
906 If the function is to return an aggregate type such as a struct, it
907 is either returned in the normal return value register R0 (if its
908 size is no greater than one byte), or else the caller must allocate
909 space into which the callee will copy the return value (if the size
910 is greater than one byte). In this case, a pointer to the return
911 value location is passed into the callee in register R2, which does
912 not displace any of the other arguments passed in via registers R4
915 /* Helper function to justify value in register according to endianness. */
916 static const gdb_byte
*
917 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
919 static gdb_byte valbuf
[4];
921 memset (valbuf
, 0, sizeof (valbuf
));
924 /* value gets right-justified in the register or stack word. */
925 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
926 memcpy (valbuf
+ (4 - len
), value_contents (val
), len
);
928 memcpy (valbuf
, value_contents (val
), len
);
931 return value_contents (val
);
934 /* Helper function to eval number of bytes to allocate on stack. */
936 sh_stack_allocsize (int nargs
, struct value
**args
)
940 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
944 /* Helper functions for getting the float arguments right. Registers usage
945 depends on the ABI and the endianness. The comments should enlighten how
946 it's intended to work. */
948 /* This array stores which of the float arg registers are already in use. */
949 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
951 /* This function just resets the above array to "no reg used so far". */
953 sh_init_flt_argreg (void)
955 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
958 /* This function returns the next register to use for float arg passing.
959 It returns either a valid value between FLOAT_ARG0_REGNUM and
960 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
961 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
963 Note that register number 0 in flt_argreg_array corresponds with the
964 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
965 29) the parity of the register number is preserved, which is important
966 for the double register passing test (see the "argreg & 1" test below). */
968 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
972 /* First search for the next free register. */
973 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
975 if (!flt_argreg_array
[argreg
])
978 /* No register left? */
979 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
980 return FLOAT_ARGLAST_REGNUM
+ 1;
984 /* Doubles are always starting in a even register number. */
987 /* In gcc ABI, the skipped register is lost for further argument
988 passing now. Not so in Renesas ABI. */
989 if (!sh_is_renesas_calling_convention (func_type
))
990 flt_argreg_array
[argreg
] = 1;
994 /* No register left? */
995 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
996 return FLOAT_ARGLAST_REGNUM
+ 1;
998 /* Also mark the next register as used. */
999 flt_argreg_array
[argreg
+ 1] = 1;
1001 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1002 && !sh_is_renesas_calling_convention (func_type
))
1004 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
1005 if (!flt_argreg_array
[argreg
+ 1])
1008 flt_argreg_array
[argreg
] = 1;
1009 return FLOAT_ARG0_REGNUM
+ argreg
;
1012 /* Helper function which figures out, if a type is treated like a float type.
1014 The FPU ABIs have a special way how to treat types as float types.
1015 Structures with exactly one member, which is of type float or double, are
1016 treated exactly as the base types float or double:
1026 are handled the same way as just
1032 As a result, arguments of these struct types are pushed into floating point
1033 registers exactly as floats or doubles, using the same decision algorithm.
1035 The same is valid if these types are used as function return types. The
1036 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1037 or even using struct convention as it is for other structs. */
1040 sh_treat_as_flt_p (struct type
*type
)
1042 /* Ordinary float types are obviously treated as float. */
1043 if (type
->code () == TYPE_CODE_FLT
)
1045 /* Otherwise non-struct types are not treated as float. */
1046 if (type
->code () != TYPE_CODE_STRUCT
)
1048 /* Otherwise structs with more than one member are not treated as float. */
1049 if (type
->num_fields () != 1)
1051 /* Otherwise if the type of that member is float, the whole type is
1052 treated as float. */
1053 if (type
->field (0).type ()->code () == TYPE_CODE_FLT
)
1055 /* Otherwise it's not treated as float. */
1060 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1061 struct value
*function
,
1062 struct regcache
*regcache
,
1063 CORE_ADDR bp_addr
, int nargs
,
1064 struct value
**args
,
1065 CORE_ADDR sp
, function_call_return_method return_method
,
1066 CORE_ADDR struct_addr
)
1068 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1069 int stack_offset
= 0;
1070 int argreg
= ARG0_REGNUM
;
1073 struct type
*func_type
= value_type (function
);
1076 const gdb_byte
*val
;
1077 int len
, reg_size
= 0;
1078 int pass_on_stack
= 0;
1080 int last_reg_arg
= INT_MAX
;
1082 /* The Renesas ABI expects all varargs arguments, plus the last
1083 non-vararg argument to be on the stack, no matter how many
1084 registers have been used so far. */
1085 if (sh_is_renesas_calling_convention (func_type
)
1086 && func_type
->has_varargs ())
1087 last_reg_arg
= func_type
->num_fields () - 2;
1089 /* First force sp to a 4-byte alignment. */
1090 sp
= sh_frame_align (gdbarch
, sp
);
1092 /* Make room on stack for args. */
1093 sp
-= sh_stack_allocsize (nargs
, args
);
1095 /* Initialize float argument mechanism. */
1096 sh_init_flt_argreg ();
1098 /* Now load as many as possible of the first arguments into
1099 registers, and push the rest onto the stack. There are 16 bytes
1100 in four registers available. Loop thru args from first to last. */
1101 for (argnum
= 0; argnum
< nargs
; argnum
++)
1103 type
= value_type (args
[argnum
]);
1104 len
= TYPE_LENGTH (type
);
1105 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1107 /* Some decisions have to be made how various types are handled.
1108 This also differs in different ABIs. */
1111 /* Find out the next register to use for a floating point value. */
1112 treat_as_flt
= sh_treat_as_flt_p (type
);
1114 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1115 /* In Renesas ABI, long longs and aggregate types are always passed
1117 else if (sh_is_renesas_calling_convention (func_type
)
1118 && ((type
->code () == TYPE_CODE_INT
&& len
== 8)
1119 || type
->code () == TYPE_CODE_STRUCT
1120 || type
->code () == TYPE_CODE_UNION
))
1122 /* In contrast to non-FPU CPUs, arguments are never split between
1123 registers and stack. If an argument doesn't fit in the remaining
1124 registers it's always pushed entirely on the stack. */
1125 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1130 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1131 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1133 || argnum
> last_reg_arg
)
1135 /* The data goes entirely on the stack, 4-byte aligned. */
1136 reg_size
= (len
+ 3) & ~3;
1137 write_memory (sp
+ stack_offset
, val
, reg_size
);
1138 stack_offset
+= reg_size
;
1140 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1142 /* Argument goes in a float argument register. */
1143 reg_size
= register_size (gdbarch
, flt_argreg
);
1144 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1145 /* In little endian mode, float types taking two registers
1146 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1147 be stored swapped in the argument registers. The below
1148 code first writes the first 32 bits in the next but one
1149 register, increments the val and len values accordingly
1150 and then proceeds as normal by writing the second 32 bits
1151 into the next register. */
1152 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1153 && TYPE_LENGTH (type
) == 2 * reg_size
)
1155 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1159 regval
= extract_unsigned_integer (val
, reg_size
,
1162 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1164 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1166 /* there's room in a register */
1167 reg_size
= register_size (gdbarch
, argreg
);
1168 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1169 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1171 /* Store the value one register at a time or in one step on
1178 if (return_method
== return_method_struct
)
1180 if (sh_is_renesas_calling_convention (func_type
))
1181 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1182 the stack and store the struct return address there. */
1183 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1185 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1186 its own dedicated register. */
1187 regcache_cooked_write_unsigned (regcache
,
1188 STRUCT_RETURN_REGNUM
, struct_addr
);
1191 /* Store return address. */
1192 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1194 /* Update stack pointer. */
1195 regcache_cooked_write_unsigned (regcache
,
1196 gdbarch_sp_regnum (gdbarch
), sp
);
1202 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1203 struct value
*function
,
1204 struct regcache
*regcache
,
1206 int nargs
, struct value
**args
,
1208 function_call_return_method return_method
,
1209 CORE_ADDR struct_addr
)
1211 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1212 int stack_offset
= 0;
1213 int argreg
= ARG0_REGNUM
;
1215 struct type
*func_type
= value_type (function
);
1218 const gdb_byte
*val
;
1219 int len
, reg_size
= 0;
1220 int pass_on_stack
= 0;
1221 int last_reg_arg
= INT_MAX
;
1223 /* The Renesas ABI expects all varargs arguments, plus the last
1224 non-vararg argument to be on the stack, no matter how many
1225 registers have been used so far. */
1226 if (sh_is_renesas_calling_convention (func_type
)
1227 && func_type
->has_varargs ())
1228 last_reg_arg
= func_type
->num_fields () - 2;
1230 /* First force sp to a 4-byte alignment. */
1231 sp
= sh_frame_align (gdbarch
, sp
);
1233 /* Make room on stack for args. */
1234 sp
-= sh_stack_allocsize (nargs
, args
);
1236 /* Now load as many as possible of the first arguments into
1237 registers, and push the rest onto the stack. There are 16 bytes
1238 in four registers available. Loop thru args from first to last. */
1239 for (argnum
= 0; argnum
< nargs
; argnum
++)
1241 type
= value_type (args
[argnum
]);
1242 len
= TYPE_LENGTH (type
);
1243 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1245 /* Some decisions have to be made how various types are handled.
1246 This also differs in different ABIs. */
1248 /* Renesas ABI pushes doubles and long longs entirely on stack.
1249 Same goes for aggregate types. */
1250 if (sh_is_renesas_calling_convention (func_type
)
1251 && ((type
->code () == TYPE_CODE_INT
&& len
>= 8)
1252 || (type
->code () == TYPE_CODE_FLT
&& len
>= 8)
1253 || type
->code () == TYPE_CODE_STRUCT
1254 || type
->code () == TYPE_CODE_UNION
))
1258 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1259 || argnum
> last_reg_arg
)
1261 /* The remainder of the data goes entirely on the stack,
1263 reg_size
= (len
+ 3) & ~3;
1264 write_memory (sp
+ stack_offset
, val
, reg_size
);
1265 stack_offset
+= reg_size
;
1267 else if (argreg
<= ARGLAST_REGNUM
)
1269 /* There's room in a register. */
1270 reg_size
= register_size (gdbarch
, argreg
);
1271 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1272 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1274 /* Store the value reg_size bytes at a time. This means that things
1275 larger than reg_size bytes may go partly in registers and partly
1282 if (return_method
== return_method_struct
)
1284 if (sh_is_renesas_calling_convention (func_type
))
1285 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1286 the stack and store the struct return address there. */
1287 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1289 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1290 its own dedicated register. */
1291 regcache_cooked_write_unsigned (regcache
,
1292 STRUCT_RETURN_REGNUM
, struct_addr
);
1295 /* Store return address. */
1296 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1298 /* Update stack pointer. */
1299 regcache_cooked_write_unsigned (regcache
,
1300 gdbarch_sp_regnum (gdbarch
), sp
);
1305 /* Find a function's return value in the appropriate registers (in
1306 regbuf), and copy it into valbuf. Extract from an array REGBUF
1307 containing the (raw) register state a function return value of type
1308 TYPE, and copy that, in virtual format, into VALBUF. */
1310 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1313 struct gdbarch
*gdbarch
= regcache
->arch ();
1314 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1315 int len
= TYPE_LENGTH (type
);
1321 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1322 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1326 int i
, regnum
= R0_REGNUM
;
1327 for (i
= 0; i
< len
; i
+= 4)
1328 regcache
->raw_read (regnum
++, valbuf
+ i
);
1331 error (_("bad size for return value"));
1335 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1338 struct gdbarch
*gdbarch
= regcache
->arch ();
1339 if (sh_treat_as_flt_p (type
))
1341 int len
= TYPE_LENGTH (type
);
1342 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1343 for (i
= 0; i
< len
; i
+= 4)
1344 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1345 regcache
->raw_read (regnum
++,
1346 valbuf
+ len
- 4 - i
);
1348 regcache
->raw_read (regnum
++, valbuf
+ i
);
1351 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1354 /* Write into appropriate registers a function return value
1355 of type TYPE, given in virtual format.
1356 If the architecture is sh4 or sh3e, store a function's return value
1357 in the R0 general register or in the FP0 floating point register,
1358 depending on the type of the return value. In all the other cases
1359 the result is stored in r0, left-justified. */
1361 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1362 const gdb_byte
*valbuf
)
1364 struct gdbarch
*gdbarch
= regcache
->arch ();
1365 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1367 int len
= TYPE_LENGTH (type
);
1371 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1372 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1376 int i
, regnum
= R0_REGNUM
;
1377 for (i
= 0; i
< len
; i
+= 4)
1378 regcache
->raw_write (regnum
++, valbuf
+ i
);
1383 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1384 const gdb_byte
*valbuf
)
1386 struct gdbarch
*gdbarch
= regcache
->arch ();
1387 if (sh_treat_as_flt_p (type
))
1389 int len
= TYPE_LENGTH (type
);
1390 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1391 for (i
= 0; i
< len
; i
+= 4)
1392 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1393 regcache
->raw_write (regnum
++,
1394 valbuf
+ len
- 4 - i
);
1396 regcache
->raw_write (regnum
++, valbuf
+ i
);
1399 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1402 static enum return_value_convention
1403 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct value
*function
,
1404 struct type
*type
, struct regcache
*regcache
,
1405 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1407 struct type
*func_type
= function
? value_type (function
) : NULL
;
1409 if (sh_use_struct_convention_nofpu (
1410 sh_is_renesas_calling_convention (func_type
), type
))
1411 return RETURN_VALUE_STRUCT_CONVENTION
;
1413 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1415 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1416 return RETURN_VALUE_REGISTER_CONVENTION
;
1419 static enum return_value_convention
1420 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct value
*function
,
1421 struct type
*type
, struct regcache
*regcache
,
1422 struct value
*value
,
1423 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1425 struct type
*func_type
= function
? value_type (function
) : NULL
;
1427 if (sh_use_struct_convention (
1428 sh_is_renesas_calling_convention (func_type
), type
))
1429 return RETURN_VALUE_STRUCT_CONVENTION
;
1431 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1433 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1434 return RETURN_VALUE_REGISTER_CONVENTION
;
1437 static struct type
*
1438 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1440 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1441 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1442 return builtin_type (gdbarch
)->builtin_float
;
1443 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1444 return builtin_type (gdbarch
)->builtin_double
;
1446 return builtin_type (gdbarch
)->builtin_int
;
1449 /* Return the GDB type object for the "standard" data type
1450 of data in register N. */
1451 static struct type
*
1452 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1454 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1455 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1456 return builtin_type (gdbarch
)->builtin_float
;
1458 return builtin_type (gdbarch
)->builtin_int
;
1461 static struct type
*
1462 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1464 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1468 static struct type
*
1469 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1471 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1472 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1473 return builtin_type (gdbarch
)->builtin_float
;
1474 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1475 return builtin_type (gdbarch
)->builtin_double
;
1476 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1477 return sh_sh4_build_float_register_type (gdbarch
, 3);
1479 return builtin_type (gdbarch
)->builtin_int
;
1482 static struct type
*
1483 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1485 return builtin_type (gdbarch
)->builtin_int
;
1488 /* Is a register in a reggroup?
1489 The default code in reggroup.c doesn't identify system registers, some
1490 float registers or any of the vector registers.
1491 TODO: sh2a and dsp registers. */
1493 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1494 struct reggroup
*reggroup
)
1496 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1497 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
1500 if (reggroup
== float_reggroup
1501 && (regnum
== FPUL_REGNUM
1502 || regnum
== FPSCR_REGNUM
))
1505 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1507 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
1509 if (reggroup
== general_reggroup
)
1513 if (regnum
== VBR_REGNUM
1514 || regnum
== SR_REGNUM
1515 || regnum
== FPSCR_REGNUM
1516 || regnum
== SSR_REGNUM
1517 || regnum
== SPC_REGNUM
)
1519 if (reggroup
== system_reggroup
)
1521 if (reggroup
== general_reggroup
)
1525 /* The default code can cope with any other registers. */
1526 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1529 /* On the sh4, the DRi pseudo registers are problematic if the target
1530 is little endian. When the user writes one of those registers, for
1531 instance with 'set var $dr0=1', we want the double to be stored
1533 fr0 = 0x00 0x00 0xf0 0x3f
1534 fr1 = 0x00 0x00 0x00 0x00
1536 This corresponds to little endian byte order & big endian word
1537 order. However if we let gdb write the register w/o conversion, it
1538 will write fr0 and fr1 this way:
1539 fr0 = 0x00 0x00 0x00 0x00
1540 fr1 = 0x00 0x00 0xf0 0x3f
1541 because it will consider fr0 and fr1 as a single LE stretch of memory.
1543 To achieve what we want we must force gdb to store things in
1544 floatformat_ieee_double_littlebyte_bigword (which is defined in
1545 include/floatformat.h and libiberty/floatformat.c.
1547 In case the target is big endian, there is no problem, the
1548 raw bytes will look like:
1549 fr0 = 0x3f 0xf0 0x00 0x00
1550 fr1 = 0x00 0x00 0x00 0x00
1552 The other pseudo registers (the FVs) also don't pose a problem
1553 because they are stored as 4 individual FP elements. */
1555 static struct type
*
1556 sh_littlebyte_bigword_type (struct gdbarch
*gdbarch
)
1558 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1560 if (tdep
->sh_littlebyte_bigword_type
== NULL
)
1561 tdep
->sh_littlebyte_bigword_type
1562 = arch_float_type (gdbarch
, -1, "builtin_type_sh_littlebyte_bigword",
1563 floatformats_ieee_double_littlebyte_bigword
);
1565 return tdep
->sh_littlebyte_bigword_type
;
1569 sh_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1570 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1572 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1574 /* It is a no-op. */
1575 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1579 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1580 target_float_convert (from
, sh_littlebyte_bigword_type (gdbarch
),
1584 ("sh_register_convert_to_virtual called with non DR register number");
1588 sh_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1589 int regnum
, const gdb_byte
*from
, gdb_byte
*to
)
1591 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1593 /* It is a no-op. */
1594 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1598 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1599 target_float_convert (from
, type
,
1600 to
, sh_littlebyte_bigword_type (gdbarch
));
1602 error (_("sh_register_convert_to_raw called with non DR register number"));
1605 /* For vectors of 4 floating point registers. */
1607 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
1611 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1612 + (fv_regnum
- FV0_REGNUM
) * 4;
1616 /* For double precision floating point registers, i.e 2 fp regs. */
1618 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
1622 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1623 + (dr_regnum
- DR0_REGNUM
) * 2;
1627 /* Concatenate PORTIONS contiguous raw registers starting at
1628 BASE_REGNUM into BUFFER. */
1630 static enum register_status
1631 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1632 readable_regcache
*regcache
,
1634 int base_regnum
, gdb_byte
*buffer
)
1638 for (portion
= 0; portion
< portions
; portion
++)
1640 enum register_status status
;
1643 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1644 status
= regcache
->raw_read (base_regnum
+ portion
, b
);
1645 if (status
!= REG_VALID
)
1652 static enum register_status
1653 sh_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
1654 int reg_nr
, gdb_byte
*buffer
)
1657 enum register_status status
;
1659 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1660 return regcache
->raw_read (BANK_REGNUM
, buffer
);
1661 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1663 /* Enough space for two float registers. */
1664 gdb_byte temp_buffer
[4 * 2];
1665 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1667 /* Build the value in the provided buffer. */
1668 /* Read the real regs for which this one is an alias. */
1669 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1670 2, base_regnum
, temp_buffer
);
1671 if (status
== REG_VALID
)
1673 /* We must pay attention to the endianness. */
1674 sh_register_convert_to_virtual (gdbarch
, reg_nr
,
1675 register_type (gdbarch
, reg_nr
),
1676 temp_buffer
, buffer
);
1680 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1682 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1684 /* Read the real regs for which this one is an alias. */
1685 return pseudo_register_read_portions (gdbarch
, regcache
,
1686 4, base_regnum
, buffer
);
1689 gdb_assert_not_reached ("invalid pseudo register number");
1693 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1694 int reg_nr
, const gdb_byte
*buffer
)
1696 int base_regnum
, portion
;
1698 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1700 /* When the bank register is written to, the whole register bank
1701 is switched and all values in the bank registers must be read
1702 from the target/sim again. We're just invalidating the regcache
1703 so that a re-read happens next time it's necessary. */
1706 regcache
->raw_write (BANK_REGNUM
, buffer
);
1707 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
1708 regcache
->invalidate (bregnum
);
1710 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1712 /* Enough space for two float registers. */
1713 gdb_byte temp_buffer
[4 * 2];
1714 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1716 /* We must pay attention to the endianness. */
1717 sh_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1718 reg_nr
, buffer
, temp_buffer
);
1720 /* Write the real regs for which this one is an alias. */
1721 for (portion
= 0; portion
< 2; portion
++)
1722 regcache
->raw_write (base_regnum
+ portion
,
1724 + register_size (gdbarch
,
1725 base_regnum
) * portion
));
1727 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1729 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1731 /* Write the real regs for which this one is an alias. */
1732 for (portion
= 0; portion
< 4; portion
++)
1733 regcache
->raw_write (base_regnum
+ portion
,
1735 + register_size (gdbarch
,
1736 base_regnum
) * portion
));
1741 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1743 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
1744 return legacy_register_sim_regno (gdbarch
, nr
);
1745 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1746 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1747 if (nr
== MOD_REGNUM
)
1748 return SIM_SH_MOD_REGNUM
;
1749 if (nr
== RS_REGNUM
)
1750 return SIM_SH_RS_REGNUM
;
1751 if (nr
== RE_REGNUM
)
1752 return SIM_SH_RE_REGNUM
;
1753 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
1754 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1759 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1764 return SIM_SH_TBR_REGNUM
;
1766 return SIM_SH_IBNR_REGNUM
;
1768 return SIM_SH_IBCR_REGNUM
;
1770 return SIM_SH_BANK_REGNUM
;
1772 return SIM_SH_BANK_MACL_REGNUM
;
1774 return SIM_SH_BANK_GBR_REGNUM
;
1776 return SIM_SH_BANK_PR_REGNUM
;
1778 return SIM_SH_BANK_IVN_REGNUM
;
1780 return SIM_SH_BANK_MACH_REGNUM
;
1784 return legacy_register_sim_regno (gdbarch
, nr
);
1787 /* Set up the register unwinding such that call-clobbered registers are
1788 not displayed in frames >0 because the true value is not certain.
1789 The 'undefined' registers will show up as 'not available' unless the
1792 This function is currently set up for SH4 and compatible only. */
1795 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1796 struct dwarf2_frame_state_reg
*reg
,
1797 struct frame_info
*this_frame
)
1799 /* Mark the PC as the destination for the return address. */
1800 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1801 reg
->how
= DWARF2_FRAME_REG_RA
;
1803 /* Mark the stack pointer as the call frame address. */
1804 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1805 reg
->how
= DWARF2_FRAME_REG_CFA
;
1807 /* The above was taken from the default init_reg in dwarf2-frame.c
1808 while the below is SH specific. */
1810 /* Caller save registers. */
1811 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
1812 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
1813 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
1814 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
1815 || (regnum
== MACH_REGNUM
)
1816 || (regnum
== MACL_REGNUM
)
1817 || (regnum
== FPUL_REGNUM
)
1818 || (regnum
== SR_REGNUM
))
1819 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1821 /* Callee save registers. */
1822 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
1823 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
1824 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
1825 || (regnum
== FV0_REGNUM
+3))
1826 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1828 /* Other registers. These are not in the ABI and may or may not
1829 mean anything in frames >0 so don't show them. */
1830 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
1831 || (regnum
== GBR_REGNUM
)
1832 || (regnum
== VBR_REGNUM
)
1833 || (regnum
== FPSCR_REGNUM
)
1834 || (regnum
== SSR_REGNUM
)
1835 || (regnum
== SPC_REGNUM
))
1836 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1839 static struct sh_frame_cache
*
1840 sh_alloc_frame_cache (void)
1842 struct sh_frame_cache
*cache
;
1845 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1849 cache
->saved_sp
= 0;
1850 cache
->sp_offset
= 0;
1853 /* Frameless until proven otherwise. */
1856 /* Saved registers. We initialize these to -1 since zero is a valid
1857 offset (that's where fp is supposed to be stored). */
1858 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1860 cache
->saved_regs
[i
] = -1;
1866 static struct sh_frame_cache
*
1867 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1869 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1870 struct sh_frame_cache
*cache
;
1871 CORE_ADDR current_pc
;
1875 return (struct sh_frame_cache
*) *this_cache
;
1877 cache
= sh_alloc_frame_cache ();
1878 *this_cache
= cache
;
1880 /* In principle, for normal frames, fp holds the frame pointer,
1881 which holds the base address for the current stack frame.
1882 However, for functions that don't need it, the frame pointer is
1883 optional. For these "frameless" functions the frame pointer is
1884 actually the frame pointer of the calling frame. */
1885 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
1886 if (cache
->base
== 0)
1889 cache
->pc
= get_frame_func (this_frame
);
1890 current_pc
= get_frame_pc (this_frame
);
1895 /* Check for the existence of the FPSCR register. If it exists,
1896 fetch its value for use in prologue analysis. Passing a zero
1897 value is the best choice for architecture variants upon which
1898 there's no FPSCR register. */
1899 if (gdbarch_register_reggroup_p (gdbarch
, FPSCR_REGNUM
, all_reggroup
))
1900 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
1904 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
1907 if (!cache
->uses_fp
)
1909 /* We didn't find a valid frame, which means that CACHE->base
1910 currently holds the frame pointer for our calling frame. If
1911 we're at the start of a function, or somewhere half-way its
1912 prologue, the function's frame probably hasn't been fully
1913 setup yet. Try to reconstruct the base address for the stack
1914 frame by looking at the stack pointer. For truly "frameless"
1915 functions this might work too. */
1916 cache
->base
= get_frame_register_unsigned
1917 (this_frame
, gdbarch_sp_regnum (gdbarch
));
1920 /* Now that we have the base address for the stack frame we can
1921 calculate the value of sp in the calling frame. */
1922 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1924 /* Adjust all the saved registers such that they contain addresses
1925 instead of offsets. */
1926 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1927 if (cache
->saved_regs
[i
] != -1)
1928 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1933 static struct value
*
1934 sh_frame_prev_register (struct frame_info
*this_frame
,
1935 void **this_cache
, int regnum
)
1937 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1938 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1940 gdb_assert (regnum
>= 0);
1942 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1943 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1945 /* The PC of the previous frame is stored in the PR register of
1946 the current frame. Frob regnum so that we pull the value from
1947 the correct place. */
1948 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1951 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1952 return frame_unwind_got_memory (this_frame
, regnum
,
1953 cache
->saved_regs
[regnum
]);
1955 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1959 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1960 struct frame_id
*this_id
)
1962 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1964 /* This marks the outermost frame. */
1965 if (cache
->base
== 0)
1968 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1971 static const struct frame_unwind sh_frame_unwind
= {
1973 default_frame_unwind_stop_reason
,
1975 sh_frame_prev_register
,
1977 default_frame_sniffer
1981 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1983 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1988 static const struct frame_base sh_frame_base
= {
1990 sh_frame_base_address
,
1991 sh_frame_base_address
,
1992 sh_frame_base_address
1995 static struct sh_frame_cache
*
1996 sh_make_stub_cache (struct frame_info
*this_frame
)
1998 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1999 struct sh_frame_cache
*cache
;
2001 cache
= sh_alloc_frame_cache ();
2004 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2010 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2011 struct frame_id
*this_id
)
2013 struct sh_frame_cache
*cache
;
2015 if (*this_cache
== NULL
)
2016 *this_cache
= sh_make_stub_cache (this_frame
);
2017 cache
= (struct sh_frame_cache
*) *this_cache
;
2019 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2023 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2024 struct frame_info
*this_frame
,
2025 void **this_prologue_cache
)
2027 CORE_ADDR addr_in_block
;
2029 addr_in_block
= get_frame_address_in_block (this_frame
);
2030 if (in_plt_section (addr_in_block
))
2036 static const struct frame_unwind sh_stub_unwind
=
2039 default_frame_unwind_stop_reason
,
2041 sh_frame_prev_register
,
2043 sh_stub_unwind_sniffer
2046 /* Implement the stack_frame_destroyed_p gdbarch method.
2048 The epilogue is defined here as the area at the end of a function,
2049 either on the `ret' instruction itself or after an instruction which
2050 destroys the function's stack frame. */
2053 sh_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2055 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2056 CORE_ADDR func_addr
= 0, func_end
= 0;
2058 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2061 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2062 for a nop and some fixed data (e.g. big offsets) which are
2063 unfortunately also treated as part of the function (which
2064 means, they are below func_end. */
2065 CORE_ADDR addr
= func_end
- 28;
2066 if (addr
< func_addr
+ 4)
2067 addr
= func_addr
+ 4;
2071 /* First search forward until hitting an rts. */
2072 while (addr
< func_end
2073 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2075 if (addr
>= func_end
)
2078 /* At this point we should find a mov.l @r15+,r14 instruction,
2079 either before or after the rts. If not, then the function has
2080 probably no "normal" epilogue and we bail out here. */
2081 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2082 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2085 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2089 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2091 /* Step over possible lds.l @r15+,macl. */
2092 if (IS_MACL_LDS (inst
))
2095 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2098 /* Step over possible lds.l @r15+,pr. */
2102 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2105 /* Step over possible mov r14,r15. */
2106 if (IS_MOV_FP_SP (inst
))
2109 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2112 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2114 while (addr
> func_addr
+ 4
2115 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2118 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2121 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2122 That's allowed for the epilogue. */
2123 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2124 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2125 && addr
> func_addr
+ 6
2126 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2137 /* Supply register REGNUM from the buffer specified by REGS and LEN
2138 in the register set REGSET to register cache REGCACHE.
2139 REGTABLE specifies where each register can be found in REGS.
2140 If REGNUM is -1, do this for all registers in REGSET. */
2143 sh_corefile_supply_regset (const struct regset
*regset
,
2144 struct regcache
*regcache
,
2145 int regnum
, const void *regs
, size_t len
)
2147 struct gdbarch
*gdbarch
= regcache
->arch ();
2148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2149 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2150 ? tdep
->core_gregmap
2151 : tdep
->core_fpregmap
);
2154 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2156 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2157 && regmap
[i
].offset
+ 4 <= len
)
2158 regcache
->raw_supply
2159 (regmap
[i
].regnum
, (char *) regs
+ regmap
[i
].offset
);
2163 /* Collect register REGNUM in the register set REGSET from register cache
2164 REGCACHE into the buffer specified by REGS and LEN.
2165 REGTABLE specifies where each register can be found in REGS.
2166 If REGNUM is -1, do this for all registers in REGSET. */
2169 sh_corefile_collect_regset (const struct regset
*regset
,
2170 const struct regcache
*regcache
,
2171 int regnum
, void *regs
, size_t len
)
2173 struct gdbarch
*gdbarch
= regcache
->arch ();
2174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2175 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2176 ? tdep
->core_gregmap
2177 : tdep
->core_fpregmap
);
2180 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2182 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2183 && regmap
[i
].offset
+ 4 <= len
)
2184 regcache
->raw_collect (regmap
[i
].regnum
,
2185 (char *)regs
+ regmap
[i
].offset
);
2189 /* The following two regsets have the same contents, so it is tempting to
2190 unify them, but they are distiguished by their address, so don't. */
2192 const struct regset sh_corefile_gregset
=
2195 sh_corefile_supply_regset
,
2196 sh_corefile_collect_regset
2199 static const struct regset sh_corefile_fpregset
=
2202 sh_corefile_supply_regset
,
2203 sh_corefile_collect_regset
2207 sh_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
2208 iterate_over_regset_sections_cb
*cb
,
2210 const struct regcache
*regcache
)
2212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2214 if (tdep
->core_gregmap
!= NULL
)
2215 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
,
2216 &sh_corefile_gregset
, NULL
, cb_data
);
2218 if (tdep
->core_fpregmap
!= NULL
)
2219 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
,
2220 &sh_corefile_fpregset
, NULL
, cb_data
);
2223 /* This is the implementation of gdbarch method
2224 return_in_first_hidden_param_p. */
2227 sh_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
2235 static struct gdbarch
*
2236 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2238 struct gdbarch
*gdbarch
;
2239 struct gdbarch_tdep
*tdep
;
2241 /* If there is already a candidate, use it. */
2242 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2244 return arches
->gdbarch
;
2246 /* None found, create a new architecture from the information
2248 tdep
= XCNEW (struct gdbarch_tdep
);
2249 gdbarch
= gdbarch_alloc (&info
, tdep
);
2251 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2252 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2253 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2254 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2256 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2257 set_gdbarch_wchar_signed (gdbarch
, 0);
2259 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2260 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2261 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2262 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2264 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2265 set_gdbarch_sp_regnum (gdbarch
, 15);
2266 set_gdbarch_pc_regnum (gdbarch
, 16);
2267 set_gdbarch_fp0_regnum (gdbarch
, -1);
2268 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2270 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2271 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2273 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, sh_breakpoint_kind_from_pc
);
2274 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, sh_sw_breakpoint_from_kind
);
2276 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2278 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2280 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2281 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2283 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2284 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
2285 sh_return_in_first_hidden_param_p
);
2287 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2289 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2290 frame_base_set_default (gdbarch
, &sh_frame_base
);
2292 set_gdbarch_stack_frame_destroyed_p (gdbarch
, sh_stack_frame_destroyed_p
);
2294 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2296 set_gdbarch_iterate_over_regset_sections
2297 (gdbarch
, sh_iterate_over_regset_sections
);
2299 switch (info
.bfd_arch_info
->mach
)
2302 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2306 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2310 /* doubles on sh2e and sh3e are actually 4 byte. */
2311 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2312 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2314 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2315 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2316 set_gdbarch_fp0_regnum (gdbarch
, 25);
2317 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2318 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2322 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2323 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2324 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2326 set_gdbarch_fp0_regnum (gdbarch
, 25);
2327 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2328 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2329 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2330 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2331 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2334 case bfd_mach_sh2a_nofpu
:
2335 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2336 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2338 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2339 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2340 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2343 case bfd_mach_sh_dsp
:
2344 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2345 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2349 case bfd_mach_sh3_nommu
:
2350 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2351 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2355 case bfd_mach_sh2a_or_sh3e
:
2356 /* doubles on sh2e and sh3e are actually 4 byte. */
2357 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2358 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2360 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2361 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2362 set_gdbarch_fp0_regnum (gdbarch
, 25);
2363 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2364 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2367 case bfd_mach_sh3_dsp
:
2368 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2369 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2374 case bfd_mach_sh2a_or_sh4
:
2375 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2376 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2377 set_gdbarch_fp0_regnum (gdbarch
, 25);
2378 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2379 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2380 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2381 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2382 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2385 case bfd_mach_sh4_nofpu
:
2386 case bfd_mach_sh4a_nofpu
:
2387 case bfd_mach_sh4_nommu_nofpu
:
2388 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2389 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2392 case bfd_mach_sh4al_dsp
:
2393 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2394 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2398 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2402 /* Hook in ABI-specific overrides, if they have been registered. */
2403 gdbarch_init_osabi (info
, gdbarch
);
2405 dwarf2_append_unwinders (gdbarch
);
2406 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
2407 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2412 void _initialize_sh_tdep ();
2414 _initialize_sh_tdep ()
2416 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2418 add_basic_prefix_cmd ("sh", no_class
, "SH specific commands.",
2419 &setshcmdlist
, "set sh ", 0, &setlist
);
2420 add_show_prefix_cmd ("sh", no_class
, "SH specific commands.",
2421 &showshcmdlist
, "show sh ", 0, &showlist
);
2423 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2424 &sh_active_calling_convention
,
2425 _("Set calling convention used when calling target "
2426 "functions from GDB."),
2427 _("Show calling convention used when calling target "
2428 "functions from GDB."),
2429 _("gcc - Use GCC calling convention (default).\n"
2430 "renesas - Enforce Renesas calling convention."),
2432 &setshcmdlist
, &showshcmdlist
);