]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - gdb/sh-tdep.c
projects / thirdparty / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
2007-06-18 Markus Deuling <deuling@de.ibm.com>
[thirdparty/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 /*
24 Contributed by Steve Chamberlain
25 sac@cygnus.com
26 */
27
28 #include "defs.h"
29 #include "frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
32 #include "dwarf2-frame.h"
33 #include "symtab.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "regcache.h"
45 #include "doublest.h"
46 #include "osabi.h"
47 #include "reggroups.h"
48
49 #include "sh-tdep.h"
50
51 #include "elf-bfd.h"
52 #include "solib-svr4.h"
53
54 /* sh flags */
55 #include "elf/sh.h"
56 /* registers numbers shared with the simulator */
57 #include "gdb/sim-sh.h"
58
59 static void (*sh_show_regs) (struct frame_info *);
60
61 #define SH_NUM_REGS 67
62
63 struct sh_frame_cache
64 {
65 /* Base address. */
66 CORE_ADDR base;
67 LONGEST sp_offset;
68 CORE_ADDR pc;
69
70 /* Flag showing that a frame has been created in the prologue code. */
71 int uses_fp;
72
73 /* Saved registers. */
74 CORE_ADDR saved_regs[SH_NUM_REGS];
75 CORE_ADDR saved_sp;
76 };
77
78 static const char *
79 sh_sh_register_name (int reg_nr)
80 {
81 static char *register_names[] = {
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "", "",
86 "", "", "", "", "", "", "", "",
87 "", "", "", "", "", "", "", "",
88 "", "",
89 "", "", "", "", "", "", "", "",
90 "", "", "", "", "", "", "", "",
91 "", "", "", "", "", "", "", "",
92 };
93 if (reg_nr < 0)
94 return NULL;
95 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
96 return NULL;
97 return register_names[reg_nr];
98 }
99
100 static const char *
101 sh_sh3_register_name (int reg_nr)
102 {
103 static char *register_names[] = {
104 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "ssr", "spc",
111 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
112 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
113 "", "", "", "", "", "", "", "",
114 };
115 if (reg_nr < 0)
116 return NULL;
117 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
118 return NULL;
119 return register_names[reg_nr];
120 }
121
122 static const char *
123 sh_sh3e_register_name (int reg_nr)
124 {
125 static char *register_names[] = {
126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "fpul", "fpscr",
130 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
131 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
132 "ssr", "spc",
133 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
135 "", "", "", "", "", "", "", "",
136 };
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
140 return NULL;
141 return register_names[reg_nr];
142 }
143
144 static const char *
145 sh_sh2e_register_name (int reg_nr)
146 {
147 static char *register_names[] = {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 "fpul", "fpscr",
152 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 };
159 if (reg_nr < 0)
160 return NULL;
161 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
162 return NULL;
163 return register_names[reg_nr];
164 }
165
166 static const char *
167 sh_sh2a_register_name (int reg_nr)
168 {
169 static char *register_names[] = {
170 /* general registers 0-15 */
171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
172 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
173 /* 16 - 22 */
174 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
175 /* 23, 24 */
176 "fpul", "fpscr",
177 /* floating point registers 25 - 40 */
178 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
179 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
180 /* 41, 42 */
181 "", "",
182 /* 43 - 62. Banked registers. The bank number used is determined by
183 the bank register (63). */
184 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
185 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
186 "machb", "ivnb", "prb", "gbrb", "maclb",
187 /* 63: register bank number, not a real register but used to
188 communicate the register bank currently get/set. This register
189 is hidden to the user, who manipulates it using the pseudo
190 register called "bank" (67). See below. */
191 "",
192 /* 64 - 66 */
193 "ibcr", "ibnr", "tbr",
194 /* 67: register bank number, the user visible pseudo register. */
195 "bank",
196 /* double precision (pseudo) 68 - 75 */
197 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
198 };
199 if (reg_nr < 0)
200 return NULL;
201 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
202 return NULL;
203 return register_names[reg_nr];
204 }
205
206 static const char *
207 sh_sh2a_nofpu_register_name (int reg_nr)
208 {
209 static char *register_names[] = {
210 /* general registers 0-15 */
211 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
212 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 /* 16 - 22 */
214 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
215 /* 23, 24 */
216 "", "",
217 /* floating point registers 25 - 40 */
218 "", "", "", "", "", "", "", "",
219 "", "", "", "", "", "", "", "",
220 /* 41, 42 */
221 "", "",
222 /* 43 - 62. Banked registers. The bank number used is determined by
223 the bank register (63). */
224 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
225 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
226 "machb", "ivnb", "prb", "gbrb", "maclb",
227 /* 63: register bank number, not a real register but used to
228 communicate the register bank currently get/set. This register
229 is hidden to the user, who manipulates it using the pseudo
230 register called "bank" (67). See below. */
231 "",
232 /* 64 - 66 */
233 "ibcr", "ibnr", "tbr",
234 /* 67: register bank number, the user visible pseudo register. */
235 "bank",
236 /* double precision (pseudo) 68 - 75 */
237 "", "", "", "", "", "", "", "",
238 };
239 if (reg_nr < 0)
240 return NULL;
241 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
242 return NULL;
243 return register_names[reg_nr];
244 }
245
246 static const char *
247 sh_sh_dsp_register_name (int reg_nr)
248 {
249 static char *register_names[] = {
250 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
252 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
253 "", "dsr",
254 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
255 "y0", "y1", "", "", "", "", "", "mod",
256 "", "",
257 "rs", "re", "", "", "", "", "", "",
258 "", "", "", "", "", "", "", "",
259 "", "", "", "", "", "", "", "",
260 };
261 if (reg_nr < 0)
262 return NULL;
263 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 return NULL;
265 return register_names[reg_nr];
266 }
267
268 static const char *
269 sh_sh3_dsp_register_name (int reg_nr)
270 {
271 static char *register_names[] = {
272 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
274 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "", "dsr",
276 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
277 "y0", "y1", "", "", "", "", "", "mod",
278 "ssr", "spc",
279 "rs", "re", "", "", "", "", "", "",
280 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
281 "", "", "", "", "", "", "", "",
282 "", "", "", "", "", "", "", "",
283 };
284 if (reg_nr < 0)
285 return NULL;
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
287 return NULL;
288 return register_names[reg_nr];
289 }
290
291 static const char *
292 sh_sh4_register_name (int reg_nr)
293 {
294 static char *register_names[] = {
295 /* general registers 0-15 */
296 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
297 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
298 /* 16 - 22 */
299 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
300 /* 23, 24 */
301 "fpul", "fpscr",
302 /* floating point registers 25 - 40 */
303 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
304 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
305 /* 41, 42 */
306 "ssr", "spc",
307 /* bank 0 43 - 50 */
308 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
309 /* bank 1 51 - 58 */
310 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
311 "", "", "", "", "", "", "", "",
312 /* pseudo bank register. */
313 "",
314 /* double precision (pseudo) 59 - 66 */
315 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
316 /* vectors (pseudo) 67 - 70 */
317 "fv0", "fv4", "fv8", "fv12",
318 /* FIXME: missing XF 71 - 86 */
319 /* FIXME: missing XD 87 - 94 */
320 };
321 if (reg_nr < 0)
322 return NULL;
323 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
324 return NULL;
325 return register_names[reg_nr];
326 }
327
328 static const char *
329 sh_sh4_nofpu_register_name (int reg_nr)
330 {
331 static char *register_names[] = {
332 /* general registers 0-15 */
333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
335 /* 16 - 22 */
336 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
337 /* 23, 24 */
338 "", "",
339 /* floating point registers 25 - 40 -- not for nofpu target */
340 "", "", "", "", "", "", "", "",
341 "", "", "", "", "", "", "", "",
342 /* 41, 42 */
343 "ssr", "spc",
344 /* bank 0 43 - 50 */
345 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
346 /* bank 1 51 - 58 */
347 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
348 "", "", "", "", "", "", "", "",
349 /* pseudo bank register. */
350 "",
351 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
352 "", "", "", "", "", "", "", "",
353 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
354 "", "", "", "",
355 };
356 if (reg_nr < 0)
357 return NULL;
358 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
359 return NULL;
360 return register_names[reg_nr];
361 }
362
363 static const char *
364 sh_sh4al_dsp_register_name (int reg_nr)
365 {
366 static char *register_names[] = {
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
369 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
370 "", "dsr",
371 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
372 "y0", "y1", "", "", "", "", "", "mod",
373 "ssr", "spc",
374 "rs", "re", "", "", "", "", "", "",
375 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
376 "", "", "", "", "", "", "", "",
377 "", "", "", "", "", "", "", "",
378 };
379 if (reg_nr < 0)
380 return NULL;
381 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
382 return NULL;
383 return register_names[reg_nr];
384 }
385
386 static const unsigned char *
387 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
388 {
389 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
390 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
391
392 /* For remote stub targets, trapa #20 is used. */
393 if (strcmp (target_shortname, "remote") == 0)
394 {
395 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
396 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
397
398 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
399 {
400 *lenptr = sizeof (big_remote_breakpoint);
401 return big_remote_breakpoint;
402 }
403 else
404 {
405 *lenptr = sizeof (little_remote_breakpoint);
406 return little_remote_breakpoint;
407 }
408 }
409
410 *lenptr = sizeof (breakpoint);
411 return breakpoint;
412 }
413
414 /* Prologue looks like
415 mov.l r14,@-r15
416 sts.l pr,@-r15
417 mov.l <regs>,@-r15
418 sub <room_for_loca_vars>,r15
419 mov r15,r14
420
421 Actually it can be more complicated than this but that's it, basically.
422 */
423
424 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
425 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
426
427 /* JSR @Rm 0100mmmm00001011 */
428 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
429
430 /* STS.L PR,@-r15 0100111100100010
431 r15-4-->r15, PR-->(r15) */
432 #define IS_STS(x) ((x) == 0x4f22)
433
434 /* STS.L MACL,@-r15 0100111100010010
435 r15-4-->r15, MACL-->(r15) */
436 #define IS_MACL_STS(x) ((x) == 0x4f12)
437
438 /* MOV.L Rm,@-r15 00101111mmmm0110
439 r15-4-->r15, Rm-->(R15) */
440 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
441
442 /* MOV r15,r14 0110111011110011
443 r15-->r14 */
444 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
445
446 /* ADD #imm,r15 01111111iiiiiiii
447 r15+imm-->r15 */
448 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
449
450 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
451 #define IS_SHLL_R3(x) ((x) == 0x4300)
452
453 /* ADD r3,r15 0011111100111100
454 r15+r3-->r15 */
455 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
456
457 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
458 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
459 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
460 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
461 make this entirely clear. */
462 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
463 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
464
465 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
466 #define IS_MOV_ARG_TO_REG(x) \
467 (((x) & 0xf00f) == 0x6003 && \
468 ((x) & 0x00f0) >= 0x0040 && \
469 ((x) & 0x00f0) <= 0x0070)
470 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
471 #define IS_MOV_ARG_TO_IND_R14(x) \
472 (((x) & 0xff0f) == 0x2e02 && \
473 ((x) & 0x00f0) >= 0x0040 && \
474 ((x) & 0x00f0) <= 0x0070)
475 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
476 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
477 (((x) & 0xff00) == 0x1e00 && \
478 ((x) & 0x00f0) >= 0x0040 && \
479 ((x) & 0x00f0) <= 0x0070)
480
481 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
482 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
483 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
484 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
485 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
486 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
487 /* SUB Rn,R15 00111111nnnn1000 */
488 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
489
490 #define FPSCR_SZ (1 << 20)
491
492 /* The following instructions are used for epilogue testing. */
493 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
494 #define IS_RTS(x) ((x) == 0x000b)
495 #define IS_LDS(x) ((x) == 0x4f26)
496 #define IS_MACL_LDS(x) ((x) == 0x4f16)
497 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
498 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
499 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
500
501 /* Disassemble an instruction. */
502 static int
503 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
504 {
505 info->endian = gdbarch_byte_order (current_gdbarch);
506 return print_insn_sh (memaddr, info);
507 }
508
509 static CORE_ADDR
510 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
511 struct sh_frame_cache *cache, ULONGEST fpscr)
512 {
513 ULONGEST inst;
514 CORE_ADDR opc;
515 int offset;
516 int sav_offset = 0;
517 int r3_val = 0;
518 int reg, sav_reg = -1;
519
520 if (pc >= current_pc)
521 return current_pc;
522
523 cache->uses_fp = 0;
524 for (opc = pc + (2 * 28); pc < opc; pc += 2)
525 {
526 inst = read_memory_unsigned_integer (pc, 2);
527 /* See where the registers will be saved to */
528 if (IS_PUSH (inst))
529 {
530 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
531 cache->sp_offset += 4;
532 }
533 else if (IS_STS (inst))
534 {
535 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
536 cache->sp_offset += 4;
537 }
538 else if (IS_MACL_STS (inst))
539 {
540 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
541 cache->sp_offset += 4;
542 }
543 else if (IS_MOV_R3 (inst))
544 {
545 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
546 }
547 else if (IS_SHLL_R3 (inst))
548 {
549 r3_val <<= 1;
550 }
551 else if (IS_ADD_R3SP (inst))
552 {
553 cache->sp_offset += -r3_val;
554 }
555 else if (IS_ADD_IMM_SP (inst))
556 {
557 offset = ((inst & 0xff) ^ 0x80) - 0x80;
558 cache->sp_offset -= offset;
559 }
560 else if (IS_MOVW_PCREL_TO_REG (inst))
561 {
562 if (sav_reg < 0)
563 {
564 reg = GET_TARGET_REG (inst);
565 if (reg < 14)
566 {
567 sav_reg = reg;
568 offset = (inst & 0xff) << 1;
569 sav_offset =
570 read_memory_integer ((pc + 4) + offset, 2);
571 }
572 }
573 }
574 else if (IS_MOVL_PCREL_TO_REG (inst))
575 {
576 if (sav_reg < 0)
577 {
578 reg = GET_TARGET_REG (inst);
579 if (reg < 14)
580 {
581 sav_reg = reg;
582 offset = (inst & 0xff) << 2;
583 sav_offset =
584 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
585 }
586 }
587 }
588 else if (IS_MOVI20 (inst))
589 {
590 if (sav_reg < 0)
591 {
592 reg = GET_TARGET_REG (inst);
593 if (reg < 14)
594 {
595 sav_reg = reg;
596 sav_offset = GET_SOURCE_REG (inst) << 16;
597 /* MOVI20 is a 32 bit instruction! */
598 pc += 2;
599 sav_offset |= read_memory_unsigned_integer (pc, 2);
600 /* Now sav_offset contains an unsigned 20 bit value.
601 It must still get sign extended. */
602 if (sav_offset & 0x00080000)
603 sav_offset |= 0xfff00000;
604 }
605 }
606 }
607 else if (IS_SUB_REG_FROM_SP (inst))
608 {
609 reg = GET_SOURCE_REG (inst);
610 if (sav_reg > 0 && reg == sav_reg)
611 {
612 sav_reg = -1;
613 }
614 cache->sp_offset += sav_offset;
615 }
616 else if (IS_FPUSH (inst))
617 {
618 if (fpscr & FPSCR_SZ)
619 {
620 cache->sp_offset += 8;
621 }
622 else
623 {
624 cache->sp_offset += 4;
625 }
626 }
627 else if (IS_MOV_SP_FP (inst))
628 {
629 cache->uses_fp = 1;
630 /* At this point, only allow argument register moves to other
631 registers or argument register moves to @(X,fp) which are
632 moving the register arguments onto the stack area allocated
633 by a former add somenumber to SP call. Don't allow moving
634 to an fp indirect address above fp + cache->sp_offset. */
635 pc += 2;
636 for (opc = pc + 12; pc < opc; pc += 2)
637 {
638 inst = read_memory_integer (pc, 2);
639 if (IS_MOV_ARG_TO_IND_R14 (inst))
640 {
641 reg = GET_SOURCE_REG (inst);
642 if (cache->sp_offset > 0)
643 cache->saved_regs[reg] = cache->sp_offset;
644 }
645 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
646 {
647 reg = GET_SOURCE_REG (inst);
648 offset = (inst & 0xf) * 4;
649 if (cache->sp_offset > offset)
650 cache->saved_regs[reg] = cache->sp_offset - offset;
651 }
652 else if (IS_MOV_ARG_TO_REG (inst))
653 continue;
654 else
655 break;
656 }
657 break;
658 }
659 else if (IS_JSR (inst))
660 {
661 /* We have found a jsr that has been scheduled into the prologue.
662 If we continue the scan and return a pc someplace after this,
663 then setting a breakpoint on this function will cause it to
664 appear to be called after the function it is calling via the
665 jsr, which will be very confusing. Most likely the next
666 instruction is going to be IS_MOV_SP_FP in the delay slot. If
667 so, note that before returning the current pc. */
668 inst = read_memory_integer (pc + 2, 2);
669 if (IS_MOV_SP_FP (inst))
670 cache->uses_fp = 1;
671 break;
672 }
673 #if 0 /* This used to just stop when it found an instruction that
674 was not considered part of the prologue. Now, we just
675 keep going looking for likely instructions. */
676 else
677 break;
678 #endif
679 }
680
681 return pc;
682 }
683
684 /* Skip any prologue before the guts of a function */
685
686 /* Skip the prologue using the debug information. If this fails we'll
687 fall back on the 'guess' method below. */
688 static CORE_ADDR
689 after_prologue (CORE_ADDR pc)
690 {
691 struct symtab_and_line sal;
692 CORE_ADDR func_addr, func_end;
693
694 /* If we can not find the symbol in the partial symbol table, then
695 there is no hope we can determine the function's start address
696 with this code. */
697 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
698 return 0;
699
700 /* Get the line associated with FUNC_ADDR. */
701 sal = find_pc_line (func_addr, 0);
702
703 /* There are only two cases to consider. First, the end of the source line
704 is within the function bounds. In that case we return the end of the
705 source line. Second is the end of the source line extends beyond the
706 bounds of the current function. We need to use the slow code to
707 examine instructions in that case. */
708 if (sal.end < func_end)
709 return sal.end;
710 else
711 return 0;
712 }
713
714 static CORE_ADDR
715 sh_skip_prologue (CORE_ADDR start_pc)
716 {
717 CORE_ADDR pc;
718 struct sh_frame_cache cache;
719
720 /* See if we can determine the end of the prologue via the symbol table.
721 If so, then return either PC, or the PC after the prologue, whichever
722 is greater. */
723 pc = after_prologue (start_pc);
724
725 /* If after_prologue returned a useful address, then use it. Else
726 fall back on the instruction skipping code. */
727 if (pc)
728 return max (pc, start_pc);
729
730 cache.sp_offset = -4;
731 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
732 if (!cache.uses_fp)
733 return start_pc;
734
735 return pc;
736 }
737
738 /* The ABI says:
739
740 Aggregate types not bigger than 8 bytes that have the same size and
741 alignment as one of the integer scalar types are returned in the
742 same registers as the integer type they match.
743
744 For example, a 2-byte aligned structure with size 2 bytes has the
745 same size and alignment as a short int, and will be returned in R0.
746 A 4-byte aligned structure with size 8 bytes has the same size and
747 alignment as a long long int, and will be returned in R0 and R1.
748
749 When an aggregate type is returned in R0 and R1, R0 contains the
750 first four bytes of the aggregate, and R1 contains the
751 remainder. If the size of the aggregate type is not a multiple of 4
752 bytes, the aggregate is tail-padded up to a multiple of 4
753 bytes. The value of the padding is undefined. For little-endian
754 targets the padding will appear at the most significant end of the
755 last element, for big-endian targets the padding appears at the
756 least significant end of the last element.
757
758 All other aggregate types are returned by address. The caller
759 function passes the address of an area large enough to hold the
760 aggregate value in R2. The called function stores the result in
761 this location.
762
763 To reiterate, structs smaller than 8 bytes could also be returned
764 in memory, if they don't pass the "same size and alignment as an
765 integer type" rule.
766
767 For example, in
768
769 struct s { char c[3]; } wibble;
770 struct s foo(void) { return wibble; }
771
772 the return value from foo() will be in memory, not
773 in R0, because there is no 3-byte integer type.
774
775 Similarly, in
776
777 struct s { char c[2]; } wibble;
778 struct s foo(void) { return wibble; }
779
780 because a struct containing two chars has alignment 1, that matches
781 type char, but size 2, that matches type short. There's no integer
782 type that has alignment 1 and size 2, so the struct is returned in
783 memory.
784
785 */
786
787 static int
788 sh_use_struct_convention (int gcc_p, struct type *type)
789 {
790 int len = TYPE_LENGTH (type);
791 int nelem = TYPE_NFIELDS (type);
792
793 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
794 fit in two registers anyway) use struct convention. */
795 if (len != 1 && len != 2 && len != 4 && len != 8)
796 return 1;
797
798 /* Scalar types and aggregate types with exactly one field are aligned
799 by definition. They are returned in registers. */
800 if (nelem <= 1)
801 return 0;
802
803 /* If the first field in the aggregate has the same length as the entire
804 aggregate type, the type is returned in registers. */
805 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
806 return 0;
807
808 /* If the size of the aggregate is 8 bytes and the first field is
809 of size 4 bytes its alignment is equal to long long's alignment,
810 so it's returned in registers. */
811 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
812 return 0;
813
814 /* Otherwise use struct convention. */
815 return 1;
816 }
817
818 /* Extract from an array REGBUF containing the (raw) register state
819 the address in which a function should return its structure value,
820 as a CORE_ADDR (or an expression that can be used as one). */
821 static CORE_ADDR
822 sh_extract_struct_value_address (struct regcache *regcache)
823 {
824 ULONGEST addr;
825
826 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
827 return addr;
828 }
829
830 static CORE_ADDR
831 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
832 {
833 return sp & ~3;
834 }
835
836 /* Function: push_dummy_call (formerly push_arguments)
837 Setup the function arguments for calling a function in the inferior.
838
839 On the Renesas SH architecture, there are four registers (R4 to R7)
840 which are dedicated for passing function arguments. Up to the first
841 four arguments (depending on size) may go into these registers.
842 The rest go on the stack.
843
844 MVS: Except on SH variants that have floating point registers.
845 In that case, float and double arguments are passed in the same
846 manner, but using FP registers instead of GP registers.
847
848 Arguments that are smaller than 4 bytes will still take up a whole
849 register or a whole 32-bit word on the stack, and will be
850 right-justified in the register or the stack word. This includes
851 chars, shorts, and small aggregate types.
852
853 Arguments that are larger than 4 bytes may be split between two or
854 more registers. If there are not enough registers free, an argument
855 may be passed partly in a register (or registers), and partly on the
856 stack. This includes doubles, long longs, and larger aggregates.
857 As far as I know, there is no upper limit to the size of aggregates
858 that will be passed in this way; in other words, the convention of
859 passing a pointer to a large aggregate instead of a copy is not used.
860
861 MVS: The above appears to be true for the SH variants that do not
862 have an FPU, however those that have an FPU appear to copy the
863 aggregate argument onto the stack (and not place it in registers)
864 if it is larger than 16 bytes (four GP registers).
865
866 An exceptional case exists for struct arguments (and possibly other
867 aggregates such as arrays) if the size is larger than 4 bytes but
868 not a multiple of 4 bytes. In this case the argument is never split
869 between the registers and the stack, but instead is copied in its
870 entirety onto the stack, AND also copied into as many registers as
871 there is room for. In other words, space in registers permitting,
872 two copies of the same argument are passed in. As far as I can tell,
873 only the one on the stack is used, although that may be a function
874 of the level of compiler optimization. I suspect this is a compiler
875 bug. Arguments of these odd sizes are left-justified within the
876 word (as opposed to arguments smaller than 4 bytes, which are
877 right-justified).
878
879 If the function is to return an aggregate type such as a struct, it
880 is either returned in the normal return value register R0 (if its
881 size is no greater than one byte), or else the caller must allocate
882 space into which the callee will copy the return value (if the size
883 is greater than one byte). In this case, a pointer to the return
884 value location is passed into the callee in register R2, which does
885 not displace any of the other arguments passed in via registers R4
886 to R7. */
887
888 /* Helper function to justify value in register according to endianess. */
889 static char *
890 sh_justify_value_in_reg (struct value *val, int len)
891 {
892 static char valbuf[4];
893
894 memset (valbuf, 0, sizeof (valbuf));
895 if (len < 4)
896 {
897 /* value gets right-justified in the register or stack word */
898 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
899 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
900 else
901 memcpy (valbuf, (char *) value_contents (val), len);
902 return valbuf;
903 }
904 return (char *) value_contents (val);
905 }
906
907 /* Helper function to eval number of bytes to allocate on stack. */
908 static CORE_ADDR
909 sh_stack_allocsize (int nargs, struct value **args)
910 {
911 int stack_alloc = 0;
912 while (nargs-- > 0)
913 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
914 return stack_alloc;
915 }
916
917 /* Helper functions for getting the float arguments right. Registers usage
918 depends on the ABI and the endianess. The comments should enlighten how
919 it's intended to work. */
920
921 /* This array stores which of the float arg registers are already in use. */
922 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
923
924 /* This function just resets the above array to "no reg used so far". */
925 static void
926 sh_init_flt_argreg (void)
927 {
928 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
929 }
930
931 /* This function returns the next register to use for float arg passing.
932 It returns either a valid value between FLOAT_ARG0_REGNUM and
933 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
934 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
935
936 Note that register number 0 in flt_argreg_array corresponds with the
937 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
938 29) the parity of the register number is preserved, which is important
939 for the double register passing test (see the "argreg & 1" test below). */
940 static int
941 sh_next_flt_argreg (int len)
942 {
943 int argreg;
944
945 /* First search for the next free register. */
946 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
947 ++argreg)
948 if (!flt_argreg_array[argreg])
949 break;
950
951 /* No register left? */
952 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
953 return FLOAT_ARGLAST_REGNUM + 1;
954
955 if (len == 8)
956 {
957 /* Doubles are always starting in a even register number. */
958 if (argreg & 1)
959 {
960 flt_argreg_array[argreg] = 1;
961
962 ++argreg;
963
964 /* No register left? */
965 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
966 return FLOAT_ARGLAST_REGNUM + 1;
967 }
968 /* Also mark the next register as used. */
969 flt_argreg_array[argreg + 1] = 1;
970 }
971 else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
972 {
973 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
974 if (!flt_argreg_array[argreg + 1])
975 ++argreg;
976 }
977 flt_argreg_array[argreg] = 1;
978 return FLOAT_ARG0_REGNUM + argreg;
979 }
980
981 /* Helper function which figures out, if a type is treated like a float type.
982
983 The FPU ABIs have a special way how to treat types as float types.
984 Structures with exactly one member, which is of type float or double, are
985 treated exactly as the base types float or double:
986
987 struct sf {
988 float f;
989 };
990
991 struct sd {
992 double d;
993 };
994
995 are handled the same way as just
996
997 float f;
998
999 double d;
1000
1001 As a result, arguments of these struct types are pushed into floating point
1002 registers exactly as floats or doubles, using the same decision algorithm.
1003
1004 The same is valid if these types are used as function return types. The
1005 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1006 or even using struct convention as it is for other structs. */
1007
1008 static int
1009 sh_treat_as_flt_p (struct type *type)
1010 {
1011 int len = TYPE_LENGTH (type);
1012
1013 /* Ordinary float types are obviously treated as float. */
1014 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1015 return 1;
1016 /* Otherwise non-struct types are not treated as float. */
1017 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1018 return 0;
1019 /* Otherwise structs with more than one memeber are not treated as float. */
1020 if (TYPE_NFIELDS (type) != 1)
1021 return 0;
1022 /* Otherwise if the type of that member is float, the whole type is
1023 treated as float. */
1024 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1025 return 1;
1026 /* Otherwise it's not treated as float. */
1027 return 0;
1028 }
1029
1030 static CORE_ADDR
1031 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1032 struct value *function,
1033 struct regcache *regcache,
1034 CORE_ADDR bp_addr, int nargs,
1035 struct value **args,
1036 CORE_ADDR sp, int struct_return,
1037 CORE_ADDR struct_addr)
1038 {
1039 int stack_offset = 0;
1040 int argreg = ARG0_REGNUM;
1041 int flt_argreg = 0;
1042 int argnum;
1043 struct type *type;
1044 CORE_ADDR regval;
1045 char *val;
1046 int len, reg_size = 0;
1047 int pass_on_stack = 0;
1048 int treat_as_flt;
1049
1050 /* first force sp to a 4-byte alignment */
1051 sp = sh_frame_align (gdbarch, sp);
1052
1053 if (struct_return)
1054 regcache_cooked_write_unsigned (regcache,
1055 STRUCT_RETURN_REGNUM, struct_addr);
1056
1057 /* make room on stack for args */
1058 sp -= sh_stack_allocsize (nargs, args);
1059
1060 /* Initialize float argument mechanism. */
1061 sh_init_flt_argreg ();
1062
1063 /* Now load as many as possible of the first arguments into
1064 registers, and push the rest onto the stack. There are 16 bytes
1065 in four registers available. Loop thru args from first to last. */
1066 for (argnum = 0; argnum < nargs; argnum++)
1067 {
1068 type = value_type (args[argnum]);
1069 len = TYPE_LENGTH (type);
1070 val = sh_justify_value_in_reg (args[argnum], len);
1071
1072 /* Some decisions have to be made how various types are handled.
1073 This also differs in different ABIs. */
1074 pass_on_stack = 0;
1075
1076 /* Find out the next register to use for a floating point value. */
1077 treat_as_flt = sh_treat_as_flt_p (type);
1078 if (treat_as_flt)
1079 flt_argreg = sh_next_flt_argreg (len);
1080 /* In contrast to non-FPU CPUs, arguments are never split between
1081 registers and stack. If an argument doesn't fit in the remaining
1082 registers it's always pushed entirely on the stack. */
1083 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1084 pass_on_stack = 1;
1085
1086 while (len > 0)
1087 {
1088 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1089 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1090 || pass_on_stack)))
1091 {
1092 /* The data goes entirely on the stack, 4-byte aligned. */
1093 reg_size = (len + 3) & ~3;
1094 write_memory (sp + stack_offset, val, reg_size);
1095 stack_offset += reg_size;
1096 }
1097 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1098 {
1099 /* Argument goes in a float argument register. */
1100 reg_size = register_size (gdbarch, flt_argreg);
1101 regval = extract_unsigned_integer (val, reg_size);
1102 /* In little endian mode, float types taking two registers
1103 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1104 be stored swapped in the argument registers. The below
1105 code first writes the first 32 bits in the next but one
1106 register, increments the val and len values accordingly
1107 and then proceeds as normal by writing the second 32 bits
1108 into the next register. */
1109 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE
1110 && TYPE_LENGTH (type) == 2 * reg_size)
1111 {
1112 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1113 regval);
1114 val += reg_size;
1115 len -= reg_size;
1116 regval = extract_unsigned_integer (val, reg_size);
1117 }
1118 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1119 }
1120 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1121 {
1122 /* there's room in a register */
1123 reg_size = register_size (gdbarch, argreg);
1124 regval = extract_unsigned_integer (val, reg_size);
1125 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1126 }
1127 /* Store the value one register at a time or in one step on stack. */
1128 len -= reg_size;
1129 val += reg_size;
1130 }
1131 }
1132
1133 /* Store return address. */
1134 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1135
1136 /* Update stack pointer. */
1137 regcache_cooked_write_unsigned (regcache,
1138 gdbarch_sp_regnum (current_gdbarch), sp);
1139
1140 return sp;
1141 }
1142
1143 static CORE_ADDR
1144 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1145 struct value *function,
1146 struct regcache *regcache,
1147 CORE_ADDR bp_addr,
1148 int nargs, struct value **args,
1149 CORE_ADDR sp, int struct_return,
1150 CORE_ADDR struct_addr)
1151 {
1152 int stack_offset = 0;
1153 int argreg = ARG0_REGNUM;
1154 int argnum;
1155 struct type *type;
1156 CORE_ADDR regval;
1157 char *val;
1158 int len, reg_size;
1159
1160 /* first force sp to a 4-byte alignment */
1161 sp = sh_frame_align (gdbarch, sp);
1162
1163 if (struct_return)
1164 regcache_cooked_write_unsigned (regcache,
1165 STRUCT_RETURN_REGNUM, struct_addr);
1166
1167 /* make room on stack for args */
1168 sp -= sh_stack_allocsize (nargs, args);
1169
1170 /* Now load as many as possible of the first arguments into
1171 registers, and push the rest onto the stack. There are 16 bytes
1172 in four registers available. Loop thru args from first to last. */
1173 for (argnum = 0; argnum < nargs; argnum++)
1174 {
1175 type = value_type (args[argnum]);
1176 len = TYPE_LENGTH (type);
1177 val = sh_justify_value_in_reg (args[argnum], len);
1178
1179 while (len > 0)
1180 {
1181 if (argreg > ARGLAST_REGNUM)
1182 {
1183 /* The remainder of the data goes entirely on the stack,
1184 4-byte aligned. */
1185 reg_size = (len + 3) & ~3;
1186 write_memory (sp + stack_offset, val, reg_size);
1187 stack_offset += reg_size;
1188 }
1189 else if (argreg <= ARGLAST_REGNUM)
1190 {
1191 /* there's room in a register */
1192 reg_size = register_size (gdbarch, argreg);
1193 regval = extract_unsigned_integer (val, reg_size);
1194 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1195 }
1196 /* Store the value reg_size bytes at a time. This means that things
1197 larger than reg_size bytes may go partly in registers and partly
1198 on the stack. */
1199 len -= reg_size;
1200 val += reg_size;
1201 }
1202 }
1203
1204 /* Store return address. */
1205 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1206
1207 /* Update stack pointer. */
1208 regcache_cooked_write_unsigned (regcache,
1209 gdbarch_sp_regnum (current_gdbarch), sp);
1210
1211 return sp;
1212 }
1213
1214 /* Find a function's return value in the appropriate registers (in
1215 regbuf), and copy it into valbuf. Extract from an array REGBUF
1216 containing the (raw) register state a function return value of type
1217 TYPE, and copy that, in virtual format, into VALBUF. */
1218 static void
1219 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1220 void *valbuf)
1221 {
1222 int len = TYPE_LENGTH (type);
1223 int return_register = R0_REGNUM;
1224 int offset;
1225
1226 if (len <= 4)
1227 {
1228 ULONGEST c;
1229
1230 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1231 store_unsigned_integer (valbuf, len, c);
1232 }
1233 else if (len == 8)
1234 {
1235 int i, regnum = R0_REGNUM;
1236 for (i = 0; i < len; i += 4)
1237 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1238 }
1239 else
1240 error (_("bad size for return value"));
1241 }
1242
1243 static void
1244 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1245 void *valbuf)
1246 {
1247 if (sh_treat_as_flt_p (type))
1248 {
1249 int len = TYPE_LENGTH (type);
1250 int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1251 for (i = 0; i < len; i += 4)
1252 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1253 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1254 else
1255 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1256 }
1257 else
1258 sh_extract_return_value_nofpu (type, regcache, valbuf);
1259 }
1260
1261 /* Write into appropriate registers a function return value
1262 of type TYPE, given in virtual format.
1263 If the architecture is sh4 or sh3e, store a function's return value
1264 in the R0 general register or in the FP0 floating point register,
1265 depending on the type of the return value. In all the other cases
1266 the result is stored in r0, left-justified. */
1267 static void
1268 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1269 const void *valbuf)
1270 {
1271 ULONGEST val;
1272 int len = TYPE_LENGTH (type);
1273
1274 if (len <= 4)
1275 {
1276 val = extract_unsigned_integer (valbuf, len);
1277 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1278 }
1279 else
1280 {
1281 int i, regnum = R0_REGNUM;
1282 for (i = 0; i < len; i += 4)
1283 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1284 }
1285 }
1286
1287 static void
1288 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1289 const void *valbuf)
1290 {
1291 if (sh_treat_as_flt_p (type))
1292 {
1293 int len = TYPE_LENGTH (type);
1294 int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1295 for (i = 0; i < len; i += 4)
1296 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1297 regcache_raw_write (regcache, regnum++,
1298 (char *) valbuf + len - 4 - i);
1299 else
1300 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1301 }
1302 else
1303 sh_store_return_value_nofpu (type, regcache, valbuf);
1304 }
1305
1306 static enum return_value_convention
1307 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1308 struct regcache *regcache,
1309 gdb_byte *readbuf, const gdb_byte *writebuf)
1310 {
1311 if (sh_use_struct_convention (0, type))
1312 return RETURN_VALUE_STRUCT_CONVENTION;
1313 if (writebuf)
1314 sh_store_return_value_nofpu (type, regcache, writebuf);
1315 else if (readbuf)
1316 sh_extract_return_value_nofpu (type, regcache, readbuf);
1317 return RETURN_VALUE_REGISTER_CONVENTION;
1318 }
1319
1320 static enum return_value_convention
1321 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1322 struct regcache *regcache,
1323 gdb_byte *readbuf, const gdb_byte *writebuf)
1324 {
1325 if (sh_use_struct_convention (0, type))
1326 return RETURN_VALUE_STRUCT_CONVENTION;
1327 if (writebuf)
1328 sh_store_return_value_fpu (type, regcache, writebuf);
1329 else if (readbuf)
1330 sh_extract_return_value_fpu (type, regcache, readbuf);
1331 return RETURN_VALUE_REGISTER_CONVENTION;
1332 }
1333
1334 /* Print the registers in a form similar to the E7000 */
1335
1336 static void
1337 sh_generic_show_regs (struct frame_info *frame)
1338 {
1339 printf_filtered
1340 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1341 paddr (get_frame_register_unsigned (frame,
1342 gdbarch_pc_regnum (current_gdbarch))),
1343 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1344 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1345 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1346
1347 printf_filtered
1348 (" GBR %08lx VBR %08lx MACL %08lx\n",
1349 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1350 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1351 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1352
1353 printf_filtered
1354 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1355 (long) get_frame_register_unsigned (frame, 0),
1356 (long) get_frame_register_unsigned (frame, 1),
1357 (long) get_frame_register_unsigned (frame, 2),
1358 (long) get_frame_register_unsigned (frame, 3),
1359 (long) get_frame_register_unsigned (frame, 4),
1360 (long) get_frame_register_unsigned (frame, 5),
1361 (long) get_frame_register_unsigned (frame, 6),
1362 (long) get_frame_register_unsigned (frame, 7));
1363 printf_filtered
1364 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1365 (long) get_frame_register_unsigned (frame, 8),
1366 (long) get_frame_register_unsigned (frame, 9),
1367 (long) get_frame_register_unsigned (frame, 10),
1368 (long) get_frame_register_unsigned (frame, 11),
1369 (long) get_frame_register_unsigned (frame, 12),
1370 (long) get_frame_register_unsigned (frame, 13),
1371 (long) get_frame_register_unsigned (frame, 14),
1372 (long) get_frame_register_unsigned (frame, 15));
1373 }
1374
1375 static void
1376 sh3_show_regs (struct frame_info *frame)
1377 {
1378 printf_filtered
1379 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1380 paddr (get_frame_register_unsigned (frame,
1381 gdbarch_pc_regnum (current_gdbarch))),
1382 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1383 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1384 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1385
1386 printf_filtered
1387 (" GBR %08lx VBR %08lx MACL %08lx\n",
1388 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1389 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1390 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1391 printf_filtered
1392 (" SSR %08lx SPC %08lx\n",
1393 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1394 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1395
1396 printf_filtered
1397 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1398 (long) get_frame_register_unsigned (frame, 0),
1399 (long) get_frame_register_unsigned (frame, 1),
1400 (long) get_frame_register_unsigned (frame, 2),
1401 (long) get_frame_register_unsigned (frame, 3),
1402 (long) get_frame_register_unsigned (frame, 4),
1403 (long) get_frame_register_unsigned (frame, 5),
1404 (long) get_frame_register_unsigned (frame, 6),
1405 (long) get_frame_register_unsigned (frame, 7));
1406 printf_filtered
1407 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1408 (long) get_frame_register_unsigned (frame, 8),
1409 (long) get_frame_register_unsigned (frame, 9),
1410 (long) get_frame_register_unsigned (frame, 10),
1411 (long) get_frame_register_unsigned (frame, 11),
1412 (long) get_frame_register_unsigned (frame, 12),
1413 (long) get_frame_register_unsigned (frame, 13),
1414 (long) get_frame_register_unsigned (frame, 14),
1415 (long) get_frame_register_unsigned (frame, 15));
1416 }
1417
1418 static void
1419 sh2e_show_regs (struct frame_info *frame)
1420 {
1421 printf_filtered
1422 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1423 paddr (get_frame_register_unsigned (frame,
1424 gdbarch_pc_regnum (current_gdbarch))),
1425 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1426 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1427 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1428
1429 printf_filtered
1430 (" GBR %08lx VBR %08lx MACL %08lx\n",
1431 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1432 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1433 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1434 printf_filtered
1435 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1436 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1437 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1438 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1439 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1440
1441 printf_filtered
1442 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1443 (long) get_frame_register_unsigned (frame, 0),
1444 (long) get_frame_register_unsigned (frame, 1),
1445 (long) get_frame_register_unsigned (frame, 2),
1446 (long) get_frame_register_unsigned (frame, 3),
1447 (long) get_frame_register_unsigned (frame, 4),
1448 (long) get_frame_register_unsigned (frame, 5),
1449 (long) get_frame_register_unsigned (frame, 6),
1450 (long) get_frame_register_unsigned (frame, 7));
1451 printf_filtered
1452 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1453 (long) get_frame_register_unsigned (frame, 8),
1454 (long) get_frame_register_unsigned (frame, 9),
1455 (long) get_frame_register_unsigned (frame, 10),
1456 (long) get_frame_register_unsigned (frame, 11),
1457 (long) get_frame_register_unsigned (frame, 12),
1458 (long) get_frame_register_unsigned (frame, 13),
1459 (long) get_frame_register_unsigned (frame, 14),
1460 (long) get_frame_register_unsigned (frame, 15));
1461
1462 printf_filtered
1463 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1464 (long) get_frame_register_unsigned
1465 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1466 (long) get_frame_register_unsigned
1467 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1468 (long) get_frame_register_unsigned
1469 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1470 (long) get_frame_register_unsigned
1471 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1472 (long) get_frame_register_unsigned
1473 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1474 (long) get_frame_register_unsigned
1475 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1476 (long) get_frame_register_unsigned
1477 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1478 (long) get_frame_register_unsigned
1479 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1480 printf_filtered
1481 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1482 (long) get_frame_register_unsigned
1483 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1484 (long) get_frame_register_unsigned
1485 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1486 (long) get_frame_register_unsigned
1487 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1488 (long) get_frame_register_unsigned
1489 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1490 (long) get_frame_register_unsigned
1491 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1492 (long) get_frame_register_unsigned
1493 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1494 (long) get_frame_register_unsigned
1495 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1496 (long) get_frame_register_unsigned
1497 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1498 }
1499
1500 static void
1501 sh2a_show_regs (struct frame_info *frame)
1502 {
1503 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1504
1505 printf_filtered
1506 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1507 paddr (get_frame_register_unsigned (frame,
1508 gdbarch_pc_regnum (current_gdbarch))),
1509 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1510 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1511 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1512
1513 printf_filtered
1514 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1515 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1516 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1517 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1518 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1519 printf_filtered
1520 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1521 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1522 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1523 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1524 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1525
1526 printf_filtered
1527 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1528 (long) get_frame_register_unsigned (frame, 0),
1529 (long) get_frame_register_unsigned (frame, 1),
1530 (long) get_frame_register_unsigned (frame, 2),
1531 (long) get_frame_register_unsigned (frame, 3),
1532 (long) get_frame_register_unsigned (frame, 4),
1533 (long) get_frame_register_unsigned (frame, 5),
1534 (long) get_frame_register_unsigned (frame, 6),
1535 (long) get_frame_register_unsigned (frame, 7));
1536 printf_filtered
1537 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1538 (long) get_frame_register_unsigned (frame, 8),
1539 (long) get_frame_register_unsigned (frame, 9),
1540 (long) get_frame_register_unsigned (frame, 10),
1541 (long) get_frame_register_unsigned (frame, 11),
1542 (long) get_frame_register_unsigned (frame, 12),
1543 (long) get_frame_register_unsigned (frame, 13),
1544 (long) get_frame_register_unsigned (frame, 14),
1545 (long) get_frame_register_unsigned (frame, 15));
1546
1547 printf_filtered
1548 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1549 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1550 (long) get_frame_register_unsigned
1551 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1552 (long) get_frame_register_unsigned
1553 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1554 (long) get_frame_register_unsigned
1555 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1556 (long) get_frame_register_unsigned
1557 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1558 (long) get_frame_register_unsigned
1559 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1560 (long) get_frame_register_unsigned
1561 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1562 (long) get_frame_register_unsigned
1563 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1564 (long) get_frame_register_unsigned
1565 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1566 printf_filtered
1567 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1568 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1569 (long) get_frame_register_unsigned
1570 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1571 (long) get_frame_register_unsigned
1572 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1573 (long) get_frame_register_unsigned
1574 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1575 (long) get_frame_register_unsigned
1576 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1577 (long) get_frame_register_unsigned
1578 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1579 (long) get_frame_register_unsigned
1580 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1581 (long) get_frame_register_unsigned
1582 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1583 (long) get_frame_register_unsigned
1584 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1585 printf_filtered
1586 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1587 printf_filtered
1588 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1589 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1590 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1591 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1592 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1593 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1594 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1595 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1596 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1597 printf_filtered
1598 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1599 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1600 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1601 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1602 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1603 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1604 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1605 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1606 printf_filtered
1607 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1608 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1609 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1610 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1611 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1612 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1613 }
1614
1615 static void
1616 sh2a_nofpu_show_regs (struct frame_info *frame)
1617 {
1618 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1619
1620 printf_filtered
1621 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1622 paddr (get_frame_register_unsigned (frame,
1623 gdbarch_pc_regnum (current_gdbarch))),
1624 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1625 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1626 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1627
1628 printf_filtered
1629 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1630 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1631 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1632 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1633 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1634 printf_filtered
1635 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1636 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1637 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1638 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1639 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1640
1641 printf_filtered
1642 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1643 (long) get_frame_register_unsigned (frame, 0),
1644 (long) get_frame_register_unsigned (frame, 1),
1645 (long) get_frame_register_unsigned (frame, 2),
1646 (long) get_frame_register_unsigned (frame, 3),
1647 (long) get_frame_register_unsigned (frame, 4),
1648 (long) get_frame_register_unsigned (frame, 5),
1649 (long) get_frame_register_unsigned (frame, 6),
1650 (long) get_frame_register_unsigned (frame, 7));
1651 printf_filtered
1652 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1653 (long) get_frame_register_unsigned (frame, 8),
1654 (long) get_frame_register_unsigned (frame, 9),
1655 (long) get_frame_register_unsigned (frame, 10),
1656 (long) get_frame_register_unsigned (frame, 11),
1657 (long) get_frame_register_unsigned (frame, 12),
1658 (long) get_frame_register_unsigned (frame, 13),
1659 (long) get_frame_register_unsigned (frame, 14),
1660 (long) get_frame_register_unsigned (frame, 15));
1661
1662 printf_filtered
1663 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1664 printf_filtered
1665 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1666 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1667 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1668 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1669 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1670 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1671 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1672 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1673 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1674 printf_filtered
1675 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1676 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1677 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1678 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1679 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1680 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1681 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1682 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1683 printf_filtered
1684 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1685 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1686 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1687 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1688 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1689 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1690 }
1691
1692 static void
1693 sh3e_show_regs (struct frame_info *frame)
1694 {
1695 printf_filtered
1696 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1697 paddr (get_frame_register_unsigned (frame,
1698 gdbarch_pc_regnum (current_gdbarch))),
1699 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1700 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1701 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1702
1703 printf_filtered
1704 (" GBR %08lx VBR %08lx MACL %08lx\n",
1705 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1706 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1707 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1708 printf_filtered
1709 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1710 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1711 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1712 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1713 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1714
1715 printf_filtered
1716 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1717 (long) get_frame_register_unsigned (frame, 0),
1718 (long) get_frame_register_unsigned (frame, 1),
1719 (long) get_frame_register_unsigned (frame, 2),
1720 (long) get_frame_register_unsigned (frame, 3),
1721 (long) get_frame_register_unsigned (frame, 4),
1722 (long) get_frame_register_unsigned (frame, 5),
1723 (long) get_frame_register_unsigned (frame, 6),
1724 (long) get_frame_register_unsigned (frame, 7));
1725 printf_filtered
1726 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1727 (long) get_frame_register_unsigned (frame, 8),
1728 (long) get_frame_register_unsigned (frame, 9),
1729 (long) get_frame_register_unsigned (frame, 10),
1730 (long) get_frame_register_unsigned (frame, 11),
1731 (long) get_frame_register_unsigned (frame, 12),
1732 (long) get_frame_register_unsigned (frame, 13),
1733 (long) get_frame_register_unsigned (frame, 14),
1734 (long) get_frame_register_unsigned (frame, 15));
1735
1736 printf_filtered
1737 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1738 (long) get_frame_register_unsigned
1739 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1740 (long) get_frame_register_unsigned
1741 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1742 (long) get_frame_register_unsigned
1743 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1744 (long) get_frame_register_unsigned
1745 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1746 (long) get_frame_register_unsigned
1747 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1748 (long) get_frame_register_unsigned
1749 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1750 (long) get_frame_register_unsigned
1751 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1752 (long) get_frame_register_unsigned
1753 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1754 printf_filtered
1755 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1756 (long) get_frame_register_unsigned
1757 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1758 (long) get_frame_register_unsigned
1759 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1760 (long) get_frame_register_unsigned
1761 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1762 (long) get_frame_register_unsigned
1763 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1764 (long) get_frame_register_unsigned
1765 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1766 (long) get_frame_register_unsigned
1767 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1768 (long) get_frame_register_unsigned
1769 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1770 (long) get_frame_register_unsigned
1771 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1772 }
1773
1774 static void
1775 sh3_dsp_show_regs (struct frame_info *frame)
1776 {
1777 printf_filtered
1778 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1779 paddr (get_frame_register_unsigned (frame,
1780 gdbarch_pc_regnum (current_gdbarch))),
1781 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1782 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1783 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1784
1785 printf_filtered
1786 (" GBR %08lx VBR %08lx MACL %08lx\n",
1787 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1788 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1789 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1790
1791 printf_filtered
1792 (" SSR %08lx SPC %08lx DSR %08lx\n",
1793 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1794 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1795 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1796
1797 printf_filtered
1798 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1799 (long) get_frame_register_unsigned (frame, 0),
1800 (long) get_frame_register_unsigned (frame, 1),
1801 (long) get_frame_register_unsigned (frame, 2),
1802 (long) get_frame_register_unsigned (frame, 3),
1803 (long) get_frame_register_unsigned (frame, 4),
1804 (long) get_frame_register_unsigned (frame, 5),
1805 (long) get_frame_register_unsigned (frame, 6),
1806 (long) get_frame_register_unsigned (frame, 7));
1807 printf_filtered
1808 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1809 (long) get_frame_register_unsigned (frame, 8),
1810 (long) get_frame_register_unsigned (frame, 9),
1811 (long) get_frame_register_unsigned (frame, 10),
1812 (long) get_frame_register_unsigned (frame, 11),
1813 (long) get_frame_register_unsigned (frame, 12),
1814 (long) get_frame_register_unsigned (frame, 13),
1815 (long) get_frame_register_unsigned (frame, 14),
1816 (long) get_frame_register_unsigned (frame, 15));
1817
1818 printf_filtered
1819 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1820 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1821 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1822 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1823 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1824 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1825 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1826 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1827 printf_filtered
1828 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1829 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1830 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1831 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1832 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1833 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1834 (long) get_frame_register_unsigned (frame, RE_REGNUM));
1835 }
1836
1837 static void
1838 sh4_show_regs (struct frame_info *frame)
1839 {
1840 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1841
1842 printf_filtered
1843 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1844 paddr (get_frame_register_unsigned (frame,
1845 gdbarch_pc_regnum (current_gdbarch))),
1846 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1847 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1848 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1849
1850 printf_filtered
1851 (" GBR %08lx VBR %08lx MACL %08lx\n",
1852 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1853 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1854 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1855 printf_filtered
1856 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1857 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1858 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1859 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1860 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1861
1862 printf_filtered
1863 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1864 (long) get_frame_register_unsigned (frame, 0),
1865 (long) get_frame_register_unsigned (frame, 1),
1866 (long) get_frame_register_unsigned (frame, 2),
1867 (long) get_frame_register_unsigned (frame, 3),
1868 (long) get_frame_register_unsigned (frame, 4),
1869 (long) get_frame_register_unsigned (frame, 5),
1870 (long) get_frame_register_unsigned (frame, 6),
1871 (long) get_frame_register_unsigned (frame, 7));
1872 printf_filtered
1873 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1874 (long) get_frame_register_unsigned (frame, 8),
1875 (long) get_frame_register_unsigned (frame, 9),
1876 (long) get_frame_register_unsigned (frame, 10),
1877 (long) get_frame_register_unsigned (frame, 11),
1878 (long) get_frame_register_unsigned (frame, 12),
1879 (long) get_frame_register_unsigned (frame, 13),
1880 (long) get_frame_register_unsigned (frame, 14),
1881 (long) get_frame_register_unsigned (frame, 15));
1882
1883 printf_filtered
1884 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1885 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1886 (long) get_frame_register_unsigned
1887 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1888 (long) get_frame_register_unsigned
1889 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1890 (long) get_frame_register_unsigned
1891 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1892 (long) get_frame_register_unsigned
1893 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1894 (long) get_frame_register_unsigned
1895 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1896 (long) get_frame_register_unsigned
1897 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1898 (long) get_frame_register_unsigned
1899 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1900 (long) get_frame_register_unsigned
1901 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1902 printf_filtered
1903 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1904 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1905 (long) get_frame_register_unsigned
1906 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1907 (long) get_frame_register_unsigned
1908 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1909 (long) get_frame_register_unsigned
1910 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1911 (long) get_frame_register_unsigned
1912 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1913 (long) get_frame_register_unsigned
1914 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1915 (long) get_frame_register_unsigned
1916 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1917 (long) get_frame_register_unsigned
1918 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1919 (long) get_frame_register_unsigned
1920 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1921 }
1922
1923 static void
1924 sh4_nofpu_show_regs (struct frame_info *frame)
1925 {
1926 printf_filtered
1927 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1928 paddr (get_frame_register_unsigned (frame,
1929 gdbarch_pc_regnum (current_gdbarch))),
1930 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1931 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1932 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1933
1934 printf_filtered
1935 (" GBR %08lx VBR %08lx MACL %08lx\n",
1936 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1937 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1938 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1939 printf_filtered
1940 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1941 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1942 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1943 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1944 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1945
1946 printf_filtered
1947 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1948 (long) get_frame_register_unsigned (frame, 0),
1949 (long) get_frame_register_unsigned (frame, 1),
1950 (long) get_frame_register_unsigned (frame, 2),
1951 (long) get_frame_register_unsigned (frame, 3),
1952 (long) get_frame_register_unsigned (frame, 4),
1953 (long) get_frame_register_unsigned (frame, 5),
1954 (long) get_frame_register_unsigned (frame, 6),
1955 (long) get_frame_register_unsigned (frame, 7));
1956 printf_filtered
1957 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1958 (long) get_frame_register_unsigned (frame, 8),
1959 (long) get_frame_register_unsigned (frame, 9),
1960 (long) get_frame_register_unsigned (frame, 10),
1961 (long) get_frame_register_unsigned (frame, 11),
1962 (long) get_frame_register_unsigned (frame, 12),
1963 (long) get_frame_register_unsigned (frame, 13),
1964 (long) get_frame_register_unsigned (frame, 14),
1965 (long) get_frame_register_unsigned (frame, 15));
1966 }
1967
1968 static void
1969 sh_dsp_show_regs (struct frame_info *frame)
1970 {
1971 printf_filtered
1972 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1973 paddr (get_frame_register_unsigned (frame,
1974 gdbarch_pc_regnum (current_gdbarch))),
1975 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1976 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1977 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1978
1979 printf_filtered
1980 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
1981 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1982 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1983 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
1984 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1985
1986 printf_filtered
1987 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1988 (long) get_frame_register_unsigned (frame, 0),
1989 (long) get_frame_register_unsigned (frame, 1),
1990 (long) get_frame_register_unsigned (frame, 2),
1991 (long) get_frame_register_unsigned (frame, 3),
1992 (long) get_frame_register_unsigned (frame, 4),
1993 (long) get_frame_register_unsigned (frame, 5),
1994 (long) get_frame_register_unsigned (frame, 6),
1995 (long) get_frame_register_unsigned (frame, 7));
1996 printf_filtered
1997 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1998 (long) get_frame_register_unsigned (frame, 8),
1999 (long) get_frame_register_unsigned (frame, 9),
2000 (long) get_frame_register_unsigned (frame, 10),
2001 (long) get_frame_register_unsigned (frame, 11),
2002 (long) get_frame_register_unsigned (frame, 12),
2003 (long) get_frame_register_unsigned (frame, 13),
2004 (long) get_frame_register_unsigned (frame, 14),
2005 (long) get_frame_register_unsigned (frame, 15));
2006
2007 printf_filtered
2008 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2009 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2010 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2011 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2012 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2013 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2014 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2015 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2016 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2017 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2018 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2019 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2020 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2021 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2022 (long) get_frame_register_unsigned (frame, RE_REGNUM));
2023 }
2024
2025 static void
2026 sh_show_regs_command (char *args, int from_tty)
2027 {
2028 if (sh_show_regs)
2029 (*sh_show_regs) (get_current_frame ());
2030 }
2031
2032 static struct type *
2033 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2034 {
2035 if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2036 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2037 return builtin_type_float;
2038 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2039 return builtin_type_double;
2040 else
2041 return builtin_type_int;
2042 }
2043
2044 /* Return the GDB type object for the "standard" data type
2045 of data in register N. */
2046 static struct type *
2047 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2048 {
2049 if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2050 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2051 return builtin_type_float;
2052 else
2053 return builtin_type_int;
2054 }
2055
2056 static struct type *
2057 sh_sh4_build_float_register_type (int high)
2058 {
2059 struct type *temp;
2060
2061 temp = create_range_type (NULL, builtin_type_int, 0, high);
2062 return create_array_type (NULL, builtin_type_float, temp);
2063 }
2064
2065 static struct type *
2066 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2067 {
2068 if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2069 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2070 return builtin_type_float;
2071 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2072 return builtin_type_double;
2073 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2074 return sh_sh4_build_float_register_type (3);
2075 else
2076 return builtin_type_int;
2077 }
2078
2079 static struct type *
2080 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2081 {
2082 return builtin_type_int;
2083 }
2084
2085 /* Is a register in a reggroup?
2086 The default code in reggroup.c doesn't identify system registers, some
2087 float registers or any of the vector registers.
2088 TODO: sh2a and dsp registers. */
2089 int
2090 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2091 struct reggroup *reggroup)
2092 {
2093 if (gdbarch_register_name (current_gdbarch, regnum) == NULL
2094 || *gdbarch_register_name (current_gdbarch, regnum) == '\0')
2095 return 0;
2096
2097 if (reggroup == float_reggroup
2098 && (regnum == FPUL_REGNUM
2099 || regnum == FPSCR_REGNUM))
2100 return 1;
2101
2102 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2103 {
2104 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2105 return 1;
2106 if (reggroup == general_reggroup)
2107 return 0;
2108 }
2109
2110 if (regnum == VBR_REGNUM
2111 || regnum == SR_REGNUM
2112 || regnum == FPSCR_REGNUM
2113 || regnum == SSR_REGNUM
2114 || regnum == SPC_REGNUM)
2115 {
2116 if (reggroup == system_reggroup)
2117 return 1;
2118 if (reggroup == general_reggroup)
2119 return 0;
2120 }
2121
2122 /* The default code can cope with any other registers. */
2123 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2124 }
2125
2126 /* On the sh4, the DRi pseudo registers are problematic if the target
2127 is little endian. When the user writes one of those registers, for
2128 instance with 'ser var $dr0=1', we want the double to be stored
2129 like this:
2130 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2131 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2132
2133 This corresponds to little endian byte order & big endian word
2134 order. However if we let gdb write the register w/o conversion, it
2135 will write fr0 and fr1 this way:
2136 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2137 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2138 because it will consider fr0 and fr1 as a single LE stretch of memory.
2139
2140 To achieve what we want we must force gdb to store things in
2141 floatformat_ieee_double_littlebyte_bigword (which is defined in
2142 include/floatformat.h and libiberty/floatformat.c.
2143
2144 In case the target is big endian, there is no problem, the
2145 raw bytes will look like:
2146 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2147 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2148
2149 The other pseudo registers (the FVs) also don't pose a problem
2150 because they are stored as 4 individual FP elements. */
2151
2152 static void
2153 sh_register_convert_to_virtual (int regnum, struct type *type,
2154 char *from, char *to)
2155 {
2156 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2157 {
2158 DOUBLEST val;
2159 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2160 from, &val);
2161 store_typed_floating (to, type, val);
2162 }
2163 else
2164 error
2165 ("sh_register_convert_to_virtual called with non DR register number");
2166 }
2167
2168 static void
2169 sh_register_convert_to_raw (struct type *type, int regnum,
2170 const void *from, void *to)
2171 {
2172 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2173 {
2174 DOUBLEST val = extract_typed_floating (from, type);
2175 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2176 &val, to);
2177 }
2178 else
2179 error (_("sh_register_convert_to_raw called with non DR register number"));
2180 }
2181
2182 /* For vectors of 4 floating point registers. */
2183 static int
2184 fv_reg_base_num (int fv_regnum)
2185 {
2186 int fp_regnum;
2187
2188 fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2189 + (fv_regnum - FV0_REGNUM) * 4;
2190 return fp_regnum;
2191 }
2192
2193 /* For double precision floating point registers, i.e 2 fp regs.*/
2194 static int
2195 dr_reg_base_num (int dr_regnum)
2196 {
2197 int fp_regnum;
2198
2199 fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2200 + (dr_regnum - DR0_REGNUM) * 2;
2201 return fp_regnum;
2202 }
2203
2204 static void
2205 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2206 int reg_nr, gdb_byte *buffer)
2207 {
2208 int base_regnum, portion;
2209 char temp_buffer[MAX_REGISTER_SIZE];
2210
2211 if (reg_nr == PSEUDO_BANK_REGNUM)
2212 regcache_raw_read (regcache, BANK_REGNUM, buffer);
2213 else
2214 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2215 {
2216 base_regnum = dr_reg_base_num (reg_nr);
2217
2218 /* Build the value in the provided buffer. */
2219 /* Read the real regs for which this one is an alias. */
2220 for (portion = 0; portion < 2; portion++)
2221 regcache_raw_read (regcache, base_regnum + portion,
2222 (temp_buffer
2223 + register_size (gdbarch,
2224 base_regnum) * portion));
2225 /* We must pay attention to the endiannes. */
2226 sh_register_convert_to_virtual (reg_nr,
2227 register_type (gdbarch, reg_nr),
2228 temp_buffer, buffer);
2229 }
2230 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2231 {
2232 base_regnum = fv_reg_base_num (reg_nr);
2233
2234 /* Read the real regs for which this one is an alias. */
2235 for (portion = 0; portion < 4; portion++)
2236 regcache_raw_read (regcache, base_regnum + portion,
2237 ((char *) buffer
2238 + register_size (gdbarch,
2239 base_regnum) * portion));
2240 }
2241 }
2242
2243 static void
2244 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2245 int reg_nr, const gdb_byte *buffer)
2246 {
2247 int base_regnum, portion;
2248 char temp_buffer[MAX_REGISTER_SIZE];
2249
2250 if (reg_nr == PSEUDO_BANK_REGNUM)
2251 {
2252 /* When the bank register is written to, the whole register bank
2253 is switched and all values in the bank registers must be read
2254 from the target/sim again. We're just invalidating the regcache
2255 so that a re-read happens next time it's necessary. */
2256 int bregnum;
2257
2258 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2259 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2260 regcache_invalidate (regcache, bregnum);
2261 }
2262 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2263 {
2264 base_regnum = dr_reg_base_num (reg_nr);
2265
2266 /* We must pay attention to the endiannes. */
2267 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2268 reg_nr, buffer, temp_buffer);
2269
2270 /* Write the real regs for which this one is an alias. */
2271 for (portion = 0; portion < 2; portion++)
2272 regcache_raw_write (regcache, base_regnum + portion,
2273 (temp_buffer
2274 + register_size (gdbarch,
2275 base_regnum) * portion));
2276 }
2277 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2278 {
2279 base_regnum = fv_reg_base_num (reg_nr);
2280
2281 /* Write the real regs for which this one is an alias. */
2282 for (portion = 0; portion < 4; portion++)
2283 regcache_raw_write (regcache, base_regnum + portion,
2284 ((char *) buffer
2285 + register_size (gdbarch,
2286 base_regnum) * portion));
2287 }
2288 }
2289
2290 static int
2291 sh_dsp_register_sim_regno (int nr)
2292 {
2293 if (legacy_register_sim_regno (nr) < 0)
2294 return legacy_register_sim_regno (nr);
2295 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2296 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2297 if (nr == MOD_REGNUM)
2298 return SIM_SH_MOD_REGNUM;
2299 if (nr == RS_REGNUM)
2300 return SIM_SH_RS_REGNUM;
2301 if (nr == RE_REGNUM)
2302 return SIM_SH_RE_REGNUM;
2303 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2304 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2305 return nr;
2306 }
2307
2308 static int
2309 sh_sh2a_register_sim_regno (int nr)
2310 {
2311 switch (nr)
2312 {
2313 case TBR_REGNUM:
2314 return SIM_SH_TBR_REGNUM;
2315 case IBNR_REGNUM:
2316 return SIM_SH_IBNR_REGNUM;
2317 case IBCR_REGNUM:
2318 return SIM_SH_IBCR_REGNUM;
2319 case BANK_REGNUM:
2320 return SIM_SH_BANK_REGNUM;
2321 case MACLB_REGNUM:
2322 return SIM_SH_BANK_MACL_REGNUM;
2323 case GBRB_REGNUM:
2324 return SIM_SH_BANK_GBR_REGNUM;
2325 case PRB_REGNUM:
2326 return SIM_SH_BANK_PR_REGNUM;
2327 case IVNB_REGNUM:
2328 return SIM_SH_BANK_IVN_REGNUM;
2329 case MACHB_REGNUM:
2330 return SIM_SH_BANK_MACH_REGNUM;
2331 default:
2332 break;
2333 }
2334 return legacy_register_sim_regno (nr);
2335 }
2336
2337 /* Set up the register unwinding such that call-clobbered registers are
2338 not displayed in frames >0 because the true value is not certain.
2339 The 'undefined' registers will show up as 'not available' unless the
2340 CFI says otherwise.
2341
2342 This function is currently set up for SH4 and compatible only. */
2343
2344 static void
2345 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2346 struct dwarf2_frame_state_reg *reg,
2347 struct frame_info *next_frame)
2348 {
2349 /* Mark the PC as the destination for the return address. */
2350 if (regnum == gdbarch_pc_regnum (current_gdbarch))
2351 reg->how = DWARF2_FRAME_REG_RA;
2352
2353 /* Mark the stack pointer as the call frame address. */
2354 else if (regnum == gdbarch_sp_regnum (current_gdbarch))
2355 reg->how = DWARF2_FRAME_REG_CFA;
2356
2357 /* The above was taken from the default init_reg in dwarf2-frame.c
2358 while the below is SH specific. */
2359
2360 /* Caller save registers. */
2361 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2362 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2363 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2364 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2365 || (regnum == MACH_REGNUM)
2366 || (regnum == MACL_REGNUM)
2367 || (regnum == FPUL_REGNUM)
2368 || (regnum == SR_REGNUM))
2369 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2370
2371 /* Callee save registers. */
2372 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2373 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2374 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2375 || (regnum == FV0_REGNUM+3))
2376 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2377
2378 /* Other registers. These are not in the ABI and may or may not
2379 mean anything in frames >0 so don't show them. */
2380 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2381 || (regnum == GBR_REGNUM)
2382 || (regnum == VBR_REGNUM)
2383 || (regnum == FPSCR_REGNUM)
2384 || (regnum == SSR_REGNUM)
2385 || (regnum == SPC_REGNUM))
2386 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2387 }
2388
2389 static struct sh_frame_cache *
2390 sh_alloc_frame_cache (void)
2391 {
2392 struct sh_frame_cache *cache;
2393 int i;
2394
2395 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2396
2397 /* Base address. */
2398 cache->base = 0;
2399 cache->saved_sp = 0;
2400 cache->sp_offset = 0;
2401 cache->pc = 0;
2402
2403 /* Frameless until proven otherwise. */
2404 cache->uses_fp = 0;
2405
2406 /* Saved registers. We initialize these to -1 since zero is a valid
2407 offset (that's where fp is supposed to be stored). */
2408 for (i = 0; i < SH_NUM_REGS; i++)
2409 {
2410 cache->saved_regs[i] = -1;
2411 }
2412
2413 return cache;
2414 }
2415
2416 static struct sh_frame_cache *
2417 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2418 {
2419 struct sh_frame_cache *cache;
2420 CORE_ADDR current_pc;
2421 int i;
2422
2423 if (*this_cache)
2424 return *this_cache;
2425
2426 cache = sh_alloc_frame_cache ();
2427 *this_cache = cache;
2428
2429 /* In principle, for normal frames, fp holds the frame pointer,
2430 which holds the base address for the current stack frame.
2431 However, for functions that don't need it, the frame pointer is
2432 optional. For these "frameless" functions the frame pointer is
2433 actually the frame pointer of the calling frame. */
2434 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2435 if (cache->base == 0)
2436 return cache;
2437
2438 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
2439 current_pc = frame_pc_unwind (next_frame);
2440 if (cache->pc != 0)
2441 {
2442 ULONGEST fpscr;
2443 fpscr = frame_unwind_register_unsigned (next_frame, FPSCR_REGNUM);
2444 sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
2445 }
2446
2447 if (!cache->uses_fp)
2448 {
2449 /* We didn't find a valid frame, which means that CACHE->base
2450 currently holds the frame pointer for our calling frame. If
2451 we're at the start of a function, or somewhere half-way its
2452 prologue, the function's frame probably hasn't been fully
2453 setup yet. Try to reconstruct the base address for the stack
2454 frame by looking at the stack pointer. For truly "frameless"
2455 functions this might work too. */
2456 cache->base = frame_unwind_register_unsigned
2457 (next_frame, gdbarch_sp_regnum (current_gdbarch));
2458 }
2459
2460 /* Now that we have the base address for the stack frame we can
2461 calculate the value of sp in the calling frame. */
2462 cache->saved_sp = cache->base + cache->sp_offset;
2463
2464 /* Adjust all the saved registers such that they contain addresses
2465 instead of offsets. */
2466 for (i = 0; i < SH_NUM_REGS; i++)
2467 if (cache->saved_regs[i] != -1)
2468 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2469
2470 return cache;
2471 }
2472
2473 static void
2474 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2475 int regnum, int *optimizedp,
2476 enum lval_type *lvalp, CORE_ADDR *addrp,
2477 int *realnump, gdb_byte *valuep)
2478 {
2479 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2480
2481 gdb_assert (regnum >= 0);
2482
2483 if (regnum == gdbarch_sp_regnum (current_gdbarch) && cache->saved_sp)
2484 {
2485 *optimizedp = 0;
2486 *lvalp = not_lval;
2487 *addrp = 0;
2488 *realnump = -1;
2489 if (valuep)
2490 {
2491 /* Store the value. */
2492 store_unsigned_integer (valuep, 4, cache->saved_sp);
2493 }
2494 return;
2495 }
2496
2497 /* The PC of the previous frame is stored in the PR register of
2498 the current frame. Frob regnum so that we pull the value from
2499 the correct place. */
2500 if (regnum == gdbarch_pc_regnum (current_gdbarch))
2501 regnum = PR_REGNUM;
2502
2503 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2504 {
2505 *optimizedp = 0;
2506 *lvalp = lval_memory;
2507 *addrp = cache->saved_regs[regnum];
2508 *realnump = -1;
2509 if (valuep)
2510 {
2511 /* Read the value in from memory. */
2512 read_memory (*addrp, valuep,
2513 register_size (current_gdbarch, regnum));
2514 }
2515 return;
2516 }
2517
2518 *optimizedp = 0;
2519 *lvalp = lval_register;
2520 *addrp = 0;
2521 *realnump = regnum;
2522 if (valuep)
2523 frame_unwind_register (next_frame, (*realnump), valuep);
2524 }
2525
2526 static void
2527 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2528 struct frame_id *this_id)
2529 {
2530 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2531
2532 /* This marks the outermost frame. */
2533 if (cache->base == 0)
2534 return;
2535
2536 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2537 }
2538
2539 static const struct frame_unwind sh_frame_unwind = {
2540 NORMAL_FRAME,
2541 sh_frame_this_id,
2542 sh_frame_prev_register
2543 };
2544
2545 static const struct frame_unwind *
2546 sh_frame_sniffer (struct frame_info *next_frame)
2547 {
2548 return &sh_frame_unwind;
2549 }
2550
2551 static CORE_ADDR
2552 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2553 {
2554 return frame_unwind_register_unsigned (next_frame,
2555 gdbarch_sp_regnum (current_gdbarch));
2556 }
2557
2558 static CORE_ADDR
2559 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2560 {
2561 return frame_unwind_register_unsigned (next_frame,
2562 gdbarch_pc_regnum (current_gdbarch));
2563 }
2564
2565 static struct frame_id
2566 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2567 {
2568 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2569 frame_pc_unwind (next_frame));
2570 }
2571
2572 static CORE_ADDR
2573 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2574 {
2575 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2576
2577 return cache->base;
2578 }
2579
2580 static const struct frame_base sh_frame_base = {
2581 &sh_frame_unwind,
2582 sh_frame_base_address,
2583 sh_frame_base_address,
2584 sh_frame_base_address
2585 };
2586
2587 /* The epilogue is defined here as the area at the end of a function,
2588 either on the `ret' instruction itself or after an instruction which
2589 destroys the function's stack frame. */
2590 static int
2591 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2592 {
2593 CORE_ADDR func_addr = 0, func_end = 0;
2594
2595 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2596 {
2597 ULONGEST inst;
2598 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2599 for a nop and some fixed data (e.g. big offsets) which are
2600 unfortunately also treated as part of the function (which
2601 means, they are below func_end. */
2602 CORE_ADDR addr = func_end - 28;
2603 if (addr < func_addr + 4)
2604 addr = func_addr + 4;
2605 if (pc < addr)
2606 return 0;
2607
2608 /* First search forward until hitting an rts. */
2609 while (addr < func_end
2610 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2611 addr += 2;
2612 if (addr >= func_end)
2613 return 0;
2614
2615 /* At this point we should find a mov.l @r15+,r14 instruction,
2616 either before or after the rts. If not, then the function has
2617 probably no "normal" epilogue and we bail out here. */
2618 inst = read_memory_unsigned_integer (addr - 2, 2);
2619 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2620 addr -= 2;
2621 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2622 return 0;
2623
2624 inst = read_memory_unsigned_integer (addr - 2, 2);
2625
2626 /* Step over possible lds.l @r15+,macl. */
2627 if (IS_MACL_LDS (inst))
2628 {
2629 addr -= 2;
2630 inst = read_memory_unsigned_integer (addr - 2, 2);
2631 }
2632
2633 /* Step over possible lds.l @r15+,pr. */
2634 if (IS_LDS (inst))
2635 {
2636 addr -= 2;
2637 inst = read_memory_unsigned_integer (addr - 2, 2);
2638 }
2639
2640 /* Step over possible mov r14,r15. */
2641 if (IS_MOV_FP_SP (inst))
2642 {
2643 addr -= 2;
2644 inst = read_memory_unsigned_integer (addr - 2, 2);
2645 }
2646
2647 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2648 instructions. */
2649 while (addr > func_addr + 4
2650 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2651 {
2652 addr -= 2;
2653 inst = read_memory_unsigned_integer (addr - 2, 2);
2654 }
2655
2656 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2657 That's allowed for the epilogue. */
2658 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2659 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2660 && addr > func_addr + 6
2661 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2662 addr -= 4;
2663
2664 if (pc >= addr)
2665 return 1;
2666 }
2667 return 0;
2668 }
2669 \f
2670
2671 static struct gdbarch *
2672 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2673 {
2674 struct gdbarch *gdbarch;
2675
2676 sh_show_regs = sh_generic_show_regs;
2677 switch (info.bfd_arch_info->mach)
2678 {
2679 case bfd_mach_sh2e:
2680 sh_show_regs = sh2e_show_regs;
2681 break;
2682 case bfd_mach_sh2a:
2683 sh_show_regs = sh2a_show_regs;
2684 break;
2685 case bfd_mach_sh2a_nofpu:
2686 sh_show_regs = sh2a_nofpu_show_regs;
2687 break;
2688 case bfd_mach_sh_dsp:
2689 sh_show_regs = sh_dsp_show_regs;
2690 break;
2691
2692 case bfd_mach_sh3:
2693 sh_show_regs = sh3_show_regs;
2694 break;
2695
2696 case bfd_mach_sh3e:
2697 sh_show_regs = sh3e_show_regs;
2698 break;
2699
2700 case bfd_mach_sh3_dsp:
2701 case bfd_mach_sh4al_dsp:
2702 sh_show_regs = sh3_dsp_show_regs;
2703 break;
2704
2705 case bfd_mach_sh4:
2706 case bfd_mach_sh4a:
2707 sh_show_regs = sh4_show_regs;
2708 break;
2709
2710 case bfd_mach_sh4_nofpu:
2711 case bfd_mach_sh4a_nofpu:
2712 sh_show_regs = sh4_nofpu_show_regs;
2713 break;
2714
2715 case bfd_mach_sh5:
2716 sh_show_regs = sh64_show_regs;
2717 /* SH5 is handled entirely in sh64-tdep.c */
2718 return sh64_gdbarch_init (info, arches);
2719 }
2720
2721 /* If there is already a candidate, use it. */
2722 arches = gdbarch_list_lookup_by_info (arches, &info);
2723 if (arches != NULL)
2724 return arches->gdbarch;
2725
2726 /* None found, create a new architecture from the information
2727 provided. */
2728 gdbarch = gdbarch_alloc (&info, NULL);
2729
2730 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2731 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2732 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2733 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2734 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2735 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2736 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2737 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2738
2739 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2740 set_gdbarch_sp_regnum (gdbarch, 15);
2741 set_gdbarch_pc_regnum (gdbarch, 16);
2742 set_gdbarch_fp0_regnum (gdbarch, -1);
2743 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2744
2745 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2746 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2747
2748 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2749
2750 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2751 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2752
2753 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2754 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2755 sh_extract_struct_value_address);
2756
2757 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2758 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2759
2760 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2761
2762 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2763
2764 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2765 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2766 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2767 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2768 frame_base_set_default (gdbarch, &sh_frame_base);
2769
2770 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2771
2772 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2773
2774 switch (info.bfd_arch_info->mach)
2775 {
2776 case bfd_mach_sh:
2777 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2778 break;
2779
2780 case bfd_mach_sh2:
2781 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2782 break;
2783
2784 case bfd_mach_sh2e:
2785 /* doubles on sh2e and sh3e are actually 4 byte. */
2786 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2787
2788 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2789 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2790 set_gdbarch_fp0_regnum (gdbarch, 25);
2791 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2792 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2793 break;
2794
2795 case bfd_mach_sh2a:
2796 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2797 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2798 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2799
2800 set_gdbarch_fp0_regnum (gdbarch, 25);
2801 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2802 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2803 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2804 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2805 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2806 break;
2807
2808 case bfd_mach_sh2a_nofpu:
2809 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2810 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2811
2812 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2813 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2814 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2815 break;
2816
2817 case bfd_mach_sh_dsp:
2818 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2819 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2820 break;
2821
2822 case bfd_mach_sh3:
2823 case bfd_mach_sh3_nommu:
2824 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2825 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2826 break;
2827
2828 case bfd_mach_sh3e:
2829 case bfd_mach_sh2a_or_sh3e:
2830 /* doubles on sh2e and sh3e are actually 4 byte. */
2831 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2832
2833 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2834 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2835 set_gdbarch_fp0_regnum (gdbarch, 25);
2836 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2837 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2838 break;
2839
2840 case bfd_mach_sh3_dsp:
2841 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2842 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2843 break;
2844
2845 case bfd_mach_sh4:
2846 case bfd_mach_sh4a:
2847 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2848 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2849 set_gdbarch_fp0_regnum (gdbarch, 25);
2850 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2851 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2852 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2853 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2854 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2855 break;
2856
2857 case bfd_mach_sh4_nofpu:
2858 case bfd_mach_sh4a_nofpu:
2859 case bfd_mach_sh4_nommu_nofpu:
2860 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2861 case bfd_mach_sh2a_or_sh4:
2862 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2863 break;
2864
2865 case bfd_mach_sh4al_dsp:
2866 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2867 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2868 break;
2869
2870 default:
2871 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2872 break;
2873 }
2874
2875 /* Hook in ABI-specific overrides, if they have been registered. */
2876 gdbarch_init_osabi (info, gdbarch);
2877
2878 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2879 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2880
2881 return gdbarch;
2882 }
2883
2884 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2885
2886 void
2887 _initialize_sh_tdep (void)
2888 {
2889 struct cmd_list_element *c;
2890
2891 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2892
2893 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2894 }
A mirror of the official binutils-gdb repository