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* sh-tdep.c (sh_justify_value_in_reg): New function.
[thirdparty/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
32 #include "symtab.h"
33 #include "symfile.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "regcache.h"
45 #include "doublest.h"
46 #include "osabi.h"
47
48 #include "sh-tdep.h"
49
50 #include "elf-bfd.h"
51 #include "solib-svr4.h"
52
53 /* sh flags */
54 #include "elf/sh.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
57
58 static void (*sh_show_regs) (void);
59
60 #define SH_NUM_REGS 59
61
62 struct sh_frame_cache
63 {
64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
75 };
76
77 static const char *
78 sh_generic_register_name (int reg_nr)
79 {
80 static char *register_names[] =
81 {
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fpul", "fpscr",
86 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
87 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "ssr", "spc",
89 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
90 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
91 };
92 if (reg_nr < 0)
93 return NULL;
94 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
95 return NULL;
96 return register_names[reg_nr];
97 }
98
99 static const char *
100 sh_sh_register_name (int reg_nr)
101 {
102 static char *register_names[] =
103 {
104 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "",
111 "", "", "", "", "", "", "", "",
112 "", "", "", "", "", "", "", "",
113 };
114 if (reg_nr < 0)
115 return NULL;
116 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
117 return NULL;
118 return register_names[reg_nr];
119 }
120
121 static const char *
122 sh_sh3_register_name (int reg_nr)
123 {
124 static char *register_names[] =
125 {
126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "ssr", "spc",
133 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 };
136 if (reg_nr < 0)
137 return NULL;
138 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
139 return NULL;
140 return register_names[reg_nr];
141 }
142
143 static const char *
144 sh_sh3e_register_name (int reg_nr)
145 {
146 static char *register_names[] =
147 {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 "fpul", "fpscr",
152 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "ssr", "spc",
155 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
156 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
157 };
158 if (reg_nr < 0)
159 return NULL;
160 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
161 return NULL;
162 return register_names[reg_nr];
163 }
164
165 static const char *
166 sh_sh2e_register_name (int reg_nr)
167 {
168 static char *register_names[] =
169 {
170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 "fpul", "fpscr",
174 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
175 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 };
180 if (reg_nr < 0)
181 return NULL;
182 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
183 return NULL;
184 return register_names[reg_nr];
185 }
186
187 static const char *
188 sh_sh_dsp_register_name (int reg_nr)
189 {
190 static char *register_names[] =
191 {
192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
194 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
195 "", "dsr",
196 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
197 "y0", "y1", "", "", "", "", "", "mod",
198 "", "",
199 "rs", "re", "", "", "", "", "", "",
200 "", "", "", "", "", "", "", "",
201 };
202 if (reg_nr < 0)
203 return NULL;
204 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
205 return NULL;
206 return register_names[reg_nr];
207 }
208
209 static const char *
210 sh_sh3_dsp_register_name (int reg_nr)
211 {
212 static char *register_names[] =
213 {
214 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
215 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
216 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
217 "", "dsr",
218 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
219 "y0", "y1", "", "", "", "", "", "mod",
220 "ssr", "spc",
221 "rs", "re", "", "", "", "", "", "",
222 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
223 "", "", "", "", "", "", "", "",
224 };
225 if (reg_nr < 0)
226 return NULL;
227 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
228 return NULL;
229 return register_names[reg_nr];
230 }
231
232 static const char *
233 sh_sh4_register_name (int reg_nr)
234 {
235 static char *register_names[] =
236 {
237 /* general registers 0-15 */
238 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
239 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
240 /* 16 - 22 */
241 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
242 /* 23, 24 */
243 "fpul", "fpscr",
244 /* floating point registers 25 - 40 */
245 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
246 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
247 /* 41, 42 */
248 "ssr", "spc",
249 /* bank 0 43 - 50 */
250 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
251 /* bank 1 51 - 58 */
252 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
253 /* double precision (pseudo) 59 - 66 */
254 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
255 /* vectors (pseudo) 67 - 70 */
256 "fv0", "fv4", "fv8", "fv12",
257 /* FIXME: missing XF 71 - 86 */
258 /* FIXME: missing XD 87 - 94 */
259 };
260 if (reg_nr < 0)
261 return NULL;
262 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
263 return NULL;
264 return register_names[reg_nr];
265 }
266
267 static const unsigned char *
268 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
269 {
270 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
271 static unsigned char breakpoint[] = {0xc3, 0xc3};
272
273 *lenptr = sizeof (breakpoint);
274 return breakpoint;
275 }
276
277 static CORE_ADDR
278 sh_push_dummy_code (struct gdbarch *gdbarch,
279 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
280 struct value **args, int nargs,
281 struct type *value_type,
282 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
283 {
284 /* Allocate space sufficient for a breakpoint. */
285 sp = (sp - 2) & ~1;
286 /* Store the address of that breakpoint */
287 *bp_addr = sp;
288 /* sh always starts the call at the callee's entry point. */
289 *real_pc = funaddr;
290 return sp;
291 }
292
293 /* Prologue looks like
294 mov.l r14,@-r15
295 sts.l pr,@-r15
296 mov.l <regs>,@-r15
297 sub <room_for_loca_vars>,r15
298 mov r15,r14
299
300 Actually it can be more complicated than this but that's it, basically.
301 */
302
303 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
304 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
305
306 /* STS.L PR,@-r15 0100111100100010
307 r15-4-->r15, PR-->(r15) */
308 #define IS_STS(x) ((x) == 0x4f22)
309
310 /* MOV.L Rm,@-r15 00101111mmmm0110
311 r15-4-->r15, Rm-->(R15) */
312 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
313
314 /* MOV r15,r14 0110111011110011
315 r15-->r14 */
316 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
317
318 /* ADD #imm,r15 01111111iiiiiiii
319 r15+imm-->r15 */
320 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
321
322 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
323 #define IS_SHLL_R3(x) ((x) == 0x4300)
324
325 /* ADD r3,r15 0011111100111100
326 r15+r3-->r15 */
327 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
328
329 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
330 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
331 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
332 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
333 make this entirely clear. */
334 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
335 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
336
337 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
338 #define IS_MOV_ARG_TO_REG(x) \
339 (((x) & 0xf00f) == 0x6003 && \
340 ((x) & 0x00f0) >= 0x0040 && \
341 ((x) & 0x00f0) <= 0x0070)
342 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
343 #define IS_MOV_ARG_TO_IND_R14(x) \
344 (((x) & 0xff0f) == 0x2e02 && \
345 ((x) & 0x00f0) >= 0x0040 && \
346 ((x) & 0x00f0) <= 0x0070)
347 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
348 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
349 (((x) & 0xff00) == 0x1e00 && \
350 ((x) & 0x00f0) >= 0x0040 && \
351 ((x) & 0x00f0) <= 0x0070)
352
353 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
354 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
355 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
356 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
357 /* SUB Rn,R15 00111111nnnn1000 */
358 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
359
360 #define FPSCR_SZ (1 << 20)
361
362 /* The following instructions are used for epilogue testing. */
363 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
364 #define IS_RTS(x) ((x) == 0x000b)
365 #define IS_LDS(x) ((x) == 0x4f26)
366 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
367 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
368 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
369
370 /* Disassemble an instruction. */
371 static int
372 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
373 {
374 info->endian = TARGET_BYTE_ORDER;
375 return print_insn_sh (memaddr, info);
376 }
377
378 static CORE_ADDR
379 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
380 struct sh_frame_cache *cache)
381 {
382 ULONGEST inst;
383 CORE_ADDR opc;
384 int offset;
385 int sav_offset = 0;
386 int r3_val = 0;
387 int reg, sav_reg = -1;
388
389 if (pc >= current_pc)
390 return current_pc;
391
392 cache->uses_fp = 0;
393 for (opc = pc + (2 * 28); pc < opc; pc += 2)
394 {
395 inst = read_memory_unsigned_integer (pc, 2);
396 /* See where the registers will be saved to */
397 if (IS_PUSH (inst))
398 {
399 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
400 cache->sp_offset += 4;
401 }
402 else if (IS_STS (inst))
403 {
404 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
405 cache->sp_offset += 4;
406 }
407 else if (IS_MOV_R3 (inst))
408 {
409 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
410 }
411 else if (IS_SHLL_R3 (inst))
412 {
413 r3_val <<= 1;
414 }
415 else if (IS_ADD_R3SP (inst))
416 {
417 cache->sp_offset += -r3_val;
418 }
419 else if (IS_ADD_IMM_SP (inst))
420 {
421 offset = ((inst & 0xff) ^ 0x80) - 0x80;
422 cache->sp_offset -= offset;
423 }
424 else if (IS_MOVW_PCREL_TO_REG (inst))
425 {
426 if (sav_reg < 0)
427 {
428 reg = GET_TARGET_REG (inst);
429 if (reg < 14)
430 {
431 sav_reg = reg;
432 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
433 sav_offset =
434 read_memory_integer (((pc + 4) & ~3) + offset, 2);
435 }
436 }
437 }
438 else if (IS_MOVL_PCREL_TO_REG (inst))
439 {
440 if (sav_reg < 0)
441 {
442 reg = (inst & 0x0f00) >> 8;
443 if (reg < 14)
444 {
445 sav_reg = reg;
446 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
447 sav_offset =
448 read_memory_integer (((pc + 4) & ~3) + offset, 4);
449 }
450 }
451 }
452 else if (IS_SUB_REG_FROM_SP (inst))
453 {
454 reg = GET_SOURCE_REG (inst);
455 if (sav_reg > 0 && reg == sav_reg)
456 {
457 sav_reg = -1;
458 }
459 cache->sp_offset += sav_offset;
460 }
461 else if (IS_FPUSH (inst))
462 {
463 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
464 {
465 cache->sp_offset += 8;
466 }
467 else
468 {
469 cache->sp_offset += 4;
470 }
471 }
472 else if (IS_MOV_SP_FP (inst))
473 {
474 if (!cache->uses_fp)
475 cache->uses_fp = 1;
476 /* At this point, only allow argument register moves to other
477 registers or argument register moves to @(X,fp) which are
478 moving the register arguments onto the stack area allocated
479 by a former add somenumber to SP call. Don't allow moving
480 to an fp indirect address above fp + cache->sp_offset. */
481 pc += 2;
482 for (opc = pc + 12; pc < opc; pc += 2)
483 {
484 inst = read_memory_integer (pc, 2);
485 if (IS_MOV_ARG_TO_IND_R14 (inst))
486 {
487 reg = GET_SOURCE_REG (inst);
488 if (cache->sp_offset > 0)
489 cache->saved_regs[reg] = cache->sp_offset;
490 }
491 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
492 {
493 reg = GET_SOURCE_REG (inst);
494 offset = (inst & 0xf) * 4;
495 if (cache->sp_offset > offset)
496 cache->saved_regs[reg] = cache->sp_offset - offset;
497 }
498 else if (IS_MOV_ARG_TO_REG (inst))
499 continue;
500 else
501 break;
502 }
503 break;
504 }
505 #if 0 /* This used to just stop when it found an instruction that
506 was not considered part of the prologue. Now, we just
507 keep going looking for likely instructions. */
508 else
509 break;
510 #endif
511 }
512
513 return pc;
514 }
515
516 /* Skip any prologue before the guts of a function */
517
518 /* Skip the prologue using the debug information. If this fails we'll
519 fall back on the 'guess' method below. */
520 static CORE_ADDR
521 after_prologue (CORE_ADDR pc)
522 {
523 struct symtab_and_line sal;
524 CORE_ADDR func_addr, func_end;
525
526 /* If we can not find the symbol in the partial symbol table, then
527 there is no hope we can determine the function's start address
528 with this code. */
529 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
530 return 0;
531
532 /* Get the line associated with FUNC_ADDR. */
533 sal = find_pc_line (func_addr, 0);
534
535 /* There are only two cases to consider. First, the end of the source line
536 is within the function bounds. In that case we return the end of the
537 source line. Second is the end of the source line extends beyond the
538 bounds of the current function. We need to use the slow code to
539 examine instructions in that case. */
540 if (sal.end < func_end)
541 return sal.end;
542 else
543 return 0;
544 }
545
546 static CORE_ADDR
547 sh_skip_prologue (CORE_ADDR start_pc)
548 {
549 CORE_ADDR pc;
550 struct sh_frame_cache cache;
551
552 /* See if we can determine the end of the prologue via the symbol table.
553 If so, then return either PC, or the PC after the prologue, whichever
554 is greater. */
555 pc = after_prologue (start_pc);
556
557 /* If after_prologue returned a useful address, then use it. Else
558 fall back on the instruction skipping code. */
559 if (pc)
560 return max (pc, start_pc);
561
562 cache.sp_offset = -4;
563 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
564 if (!cache.uses_fp)
565 return start_pc;
566
567 return pc;
568 }
569
570 /* Should call_function allocate stack space for a struct return? */
571 static int
572 sh_use_struct_convention (int gcc_p, struct type *type)
573 {
574 int len = TYPE_LENGTH (type);
575 int nelem = TYPE_NFIELDS (type);
576 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
577 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
578 }
579
580 /* Extract from an array REGBUF containing the (raw) register state
581 the address in which a function should return its structure value,
582 as a CORE_ADDR (or an expression that can be used as one). */
583 static CORE_ADDR
584 sh_extract_struct_value_address (struct regcache *regcache)
585 {
586 ULONGEST addr;
587
588 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
589 return addr;
590 }
591
592 static CORE_ADDR
593 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
594 {
595 return sp & ~3;
596 }
597
598 /* Function: push_dummy_call (formerly push_arguments)
599 Setup the function arguments for calling a function in the inferior.
600
601 On the Hitachi SH architecture, there are four registers (R4 to R7)
602 which are dedicated for passing function arguments. Up to the first
603 four arguments (depending on size) may go into these registers.
604 The rest go on the stack.
605
606 MVS: Except on SH variants that have floating point registers.
607 In that case, float and double arguments are passed in the same
608 manner, but using FP registers instead of GP registers.
609
610 Arguments that are smaller than 4 bytes will still take up a whole
611 register or a whole 32-bit word on the stack, and will be
612 right-justified in the register or the stack word. This includes
613 chars, shorts, and small aggregate types.
614
615 Arguments that are larger than 4 bytes may be split between two or
616 more registers. If there are not enough registers free, an argument
617 may be passed partly in a register (or registers), and partly on the
618 stack. This includes doubles, long longs, and larger aggregates.
619 As far as I know, there is no upper limit to the size of aggregates
620 that will be passed in this way; in other words, the convention of
621 passing a pointer to a large aggregate instead of a copy is not used.
622
623 MVS: The above appears to be true for the SH variants that do not
624 have an FPU, however those that have an FPU appear to copy the
625 aggregate argument onto the stack (and not place it in registers)
626 if it is larger than 16 bytes (four GP registers).
627
628 An exceptional case exists for struct arguments (and possibly other
629 aggregates such as arrays) if the size is larger than 4 bytes but
630 not a multiple of 4 bytes. In this case the argument is never split
631 between the registers and the stack, but instead is copied in its
632 entirety onto the stack, AND also copied into as many registers as
633 there is room for. In other words, space in registers permitting,
634 two copies of the same argument are passed in. As far as I can tell,
635 only the one on the stack is used, although that may be a function
636 of the level of compiler optimization. I suspect this is a compiler
637 bug. Arguments of these odd sizes are left-justified within the
638 word (as opposed to arguments smaller than 4 bytes, which are
639 right-justified).
640
641 If the function is to return an aggregate type such as a struct, it
642 is either returned in the normal return value register R0 (if its
643 size is no greater than one byte), or else the caller must allocate
644 space into which the callee will copy the return value (if the size
645 is greater than one byte). In this case, a pointer to the return
646 value location is passed into the callee in register R2, which does
647 not displace any of the other arguments passed in via registers R4
648 to R7. */
649
650 /* Helper function to justify value in register according to endianess. */
651 static char *
652 sh_justify_value_in_reg (struct value *val, int len)
653 {
654 static char valbuf[4];
655
656 memset (valbuf, 0, sizeof (valbuf));
657 if (len < 4)
658 {
659 /* value gets right-justified in the register or stack word */
660 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
661 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
662 else
663 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
664 return valbuf;
665 }
666 return (char *) VALUE_CONTENTS (val);
667 }
668
669 /* Helper function to eval number of bytes to allocate on stack. */
670 static CORE_ADDR
671 sh_stack_allocsize (int nargs, struct value **args)
672 {
673 int stack_alloc = 0;
674 while (nargs-- > 0)
675 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
676 return stack_alloc;
677 }
678
679 /* Helper functions for getting the float arguments right. Registers usage
680 depends on the ABI and the endianess. The comments should enlighten how
681 it's intended to work. */
682
683 /* This array stores which of the float arg registers are already in use. */
684 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
685
686 /* This function just resets the above array to "no reg used so far". */
687 static void
688 sh_init_flt_argreg (void)
689 {
690 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
691 }
692
693 /* This function returns the next register to use for float arg passing.
694 It returns either a valid value between FLOAT_ARG0_REGNUM and
695 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
696 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
697
698 Note that register number 0 in flt_argreg_array corresponds with the
699 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
700 29) the parity of the register number is preserved, which is important
701 for the double register passing test (see the "argreg & 1" test below). */
702 static int
703 sh_next_flt_argreg (int len)
704 {
705 int argreg;
706
707 /* First search for the next free register. */
708 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; ++argreg)
709 if (!flt_argreg_array[argreg])
710 break;
711
712 /* No register left? */
713 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
714 return FLOAT_ARGLAST_REGNUM + 1;
715
716 if (len == 8)
717 {
718 /* Doubles are always starting in a even register number. */
719 if (argreg & 1)
720 {
721 flt_argreg_array[argreg] = 1;
722
723 ++argreg;
724
725 /* No register left? */
726 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
727 return FLOAT_ARGLAST_REGNUM + 1;
728 }
729 /* Also mark the next register as used. */
730 flt_argreg_array[argreg + 1] = 1;
731 }
732 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
733 {
734 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
735 if (!flt_argreg_array[argreg + 1])
736 ++argreg;
737 }
738 flt_argreg_array[argreg] = 1;
739 return FLOAT_ARG0_REGNUM + argreg;
740 }
741
742 static CORE_ADDR
743 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
744 CORE_ADDR func_addr,
745 struct regcache *regcache,
746 CORE_ADDR bp_addr, int nargs,
747 struct value **args,
748 CORE_ADDR sp, int struct_return,
749 CORE_ADDR struct_addr)
750 {
751 int stack_offset = 0;
752 int argreg = ARG0_REGNUM;
753 int flt_argreg;
754 int argnum;
755 struct type *type;
756 CORE_ADDR regval;
757 char *val;
758 int len, reg_size;
759 int pass_on_stack;
760
761 /* first force sp to a 4-byte alignment */
762 sp = sh_frame_align (gdbarch, sp);
763
764 if (struct_return)
765 regcache_cooked_write_unsigned (regcache,
766 STRUCT_RETURN_REGNUM,
767 struct_addr);
768
769 /* make room on stack for args */
770 sp -= sh_stack_allocsize (nargs, args);
771
772 /* Initialize float argument mechanism. */
773 sh_init_flt_argreg ();
774
775 /* Now load as many as possible of the first arguments into
776 registers, and push the rest onto the stack. There are 16 bytes
777 in four registers available. Loop thru args from first to last. */
778 for (argnum = 0; argnum < nargs; argnum++)
779 {
780 type = VALUE_TYPE (args[argnum]);
781 len = TYPE_LENGTH (type);
782 val = sh_justify_value_in_reg (args[argnum], len);
783
784 /* Some decisions have to be made how various types are handled.
785 This also differs in different ABIs. */
786 pass_on_stack = 0;
787 if (len > 16)
788 pass_on_stack = 1; /* Types bigger than 16 bytes are passed on stack. */
789
790 /* Find out the next register to use for a floating point value. */
791 if (TYPE_CODE (type) == TYPE_CODE_FLT)
792 flt_argreg = sh_next_flt_argreg (len);
793
794 while (len > 0)
795 {
796 if ((TYPE_CODE (type) == TYPE_CODE_FLT
797 && flt_argreg > FLOAT_ARGLAST_REGNUM)
798 || argreg > ARGLAST_REGNUM
799 || pass_on_stack)
800 {
801 /* The remainder of the data goes entirely on the stack,
802 4-byte aligned. */
803 reg_size = (len + 3) & ~3;
804 write_memory (sp + stack_offset, val, reg_size);
805 stack_offset += reg_size;
806 }
807 else if (TYPE_CODE (type) == TYPE_CODE_FLT
808 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
809 {
810 /* Argument goes in a float argument register. */
811 reg_size = register_size (gdbarch, flt_argreg);
812 regval = extract_unsigned_integer (val, reg_size);
813 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
814 }
815 else if (argreg <= ARGLAST_REGNUM)
816 {
817 /* there's room in a register */
818 reg_size = register_size (gdbarch, argreg);
819 regval = extract_unsigned_integer (val, reg_size);
820 regcache_cooked_write_unsigned (regcache, argreg++, regval);
821 }
822 /* Store the value reg_size bytes at a time. This means that things
823 larger than reg_size bytes may go partly in registers and partly
824 on the stack. */
825 len -= reg_size;
826 val += reg_size;
827 }
828 }
829
830 /* Store return address. */
831 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
832
833 /* Update stack pointer. */
834 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
835
836 return sp;
837 }
838
839 static CORE_ADDR
840 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
841 CORE_ADDR func_addr,
842 struct regcache *regcache,
843 CORE_ADDR bp_addr,
844 int nargs, struct value **args,
845 CORE_ADDR sp, int struct_return,
846 CORE_ADDR struct_addr)
847 {
848 int stack_offset = 0;
849 int argreg = ARG0_REGNUM;
850 int argnum;
851 struct type *type;
852 CORE_ADDR regval;
853 char *val;
854 int len, reg_size;
855
856 /* first force sp to a 4-byte alignment */
857 sp = sh_frame_align (gdbarch, sp);
858
859 if (struct_return)
860 regcache_cooked_write_unsigned (regcache,
861 STRUCT_RETURN_REGNUM,
862 struct_addr);
863
864 /* make room on stack for args */
865 sp -= sh_stack_allocsize (nargs, args);
866
867 /* Now load as many as possible of the first arguments into
868 registers, and push the rest onto the stack. There are 16 bytes
869 in four registers available. Loop thru args from first to last. */
870 for (argnum = 0; argnum < nargs; argnum++)
871 {
872 type = VALUE_TYPE (args[argnum]);
873 len = TYPE_LENGTH (type);
874 val = sh_justify_value_in_reg (args[argnum], len);
875
876 while (len > 0)
877 {
878 if (argreg > ARGLAST_REGNUM)
879 {
880 /* The remainder of the data goes entirely on the stack,
881 4-byte aligned. */
882 reg_size = (len + 3) & ~3;
883 write_memory (sp + stack_offset, val, reg_size);
884 stack_offset += reg_size;
885 }
886 else if (argreg <= ARGLAST_REGNUM)
887 {
888 /* there's room in a register */
889 reg_size = register_size (gdbarch, argreg);
890 regval = extract_unsigned_integer (val, reg_size);
891 regcache_cooked_write_unsigned (regcache, argreg++, regval);
892 }
893 /* Store the value reg_size bytes at a time. This means that things
894 larger than reg_size bytes may go partly in registers and partly
895 on the stack. */
896 len -= reg_size;
897 val += reg_size;
898 }
899 }
900
901 /* Store return address. */
902 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
903
904 /* Update stack pointer. */
905 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
906
907 return sp;
908 }
909
910 /* Find a function's return value in the appropriate registers (in
911 regbuf), and copy it into valbuf. Extract from an array REGBUF
912 containing the (raw) register state a function return value of type
913 TYPE, and copy that, in virtual format, into VALBUF. */
914 static void
915 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
916 void *valbuf)
917 {
918 int len = TYPE_LENGTH (type);
919 int return_register = R0_REGNUM;
920 int offset;
921
922 if (len <= 4)
923 {
924 ULONGEST c;
925
926 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
927 store_unsigned_integer (valbuf, len, c);
928 }
929 else if (len == 8)
930 {
931 int i, regnum = R0_REGNUM;
932 for (i = 0; i < len; i += 4)
933 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
934 }
935 else
936 error ("bad size for return value");
937 }
938
939 static void
940 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
941 void *valbuf)
942 {
943 if (TYPE_CODE (type) == TYPE_CODE_FLT)
944 {
945 int len = TYPE_LENGTH (type);
946 int i, regnum = FP0_REGNUM;
947 for (i = 0; i < len; i += 4)
948 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
949 }
950 else
951 sh_default_extract_return_value (type, regcache, valbuf);
952 }
953
954 /* Write into appropriate registers a function return value
955 of type TYPE, given in virtual format.
956 If the architecture is sh4 or sh3e, store a function's return value
957 in the R0 general register or in the FP0 floating point register,
958 depending on the type of the return value. In all the other cases
959 the result is stored in r0, left-justified. */
960 static void
961 sh_default_store_return_value (struct type *type, struct regcache *regcache,
962 const void *valbuf)
963 {
964 ULONGEST val;
965 int len = TYPE_LENGTH (type);
966
967 if (len <= 4)
968 {
969 val = extract_unsigned_integer (valbuf, len);
970 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
971 }
972 else
973 {
974 int i, regnum = R0_REGNUM;
975 for (i = 0; i < len; i += 4)
976 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
977 }
978 }
979
980 static void
981 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
982 const void *valbuf)
983 {
984 if (TYPE_CODE (type) == TYPE_CODE_FLT)
985 {
986 int len = TYPE_LENGTH (type);
987 int i, regnum = FP0_REGNUM;
988 for (i = 0; i < len; i += 4)
989 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
990 }
991 else
992 sh_default_store_return_value (type, regcache, valbuf);
993 }
994
995 /* Print the registers in a form similar to the E7000 */
996
997 static void
998 sh_generic_show_regs (void)
999 {
1000 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1001 paddr (read_register (PC_REGNUM)),
1002 (long) read_register (SR_REGNUM),
1003 (long) read_register (PR_REGNUM),
1004 (long) read_register (MACH_REGNUM),
1005 (long) read_register (MACL_REGNUM));
1006
1007 printf_filtered ("GBR=%08lx VBR=%08lx",
1008 (long) read_register (GBR_REGNUM),
1009 (long) read_register (VBR_REGNUM));
1010
1011 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1012 (long) read_register (0),
1013 (long) read_register (1),
1014 (long) read_register (2),
1015 (long) read_register (3),
1016 (long) read_register (4),
1017 (long) read_register (5),
1018 (long) read_register (6),
1019 (long) read_register (7));
1020 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1021 (long) read_register (8),
1022 (long) read_register (9),
1023 (long) read_register (10),
1024 (long) read_register (11),
1025 (long) read_register (12),
1026 (long) read_register (13),
1027 (long) read_register (14),
1028 (long) read_register (15));
1029 }
1030
1031 static void
1032 sh3_show_regs (void)
1033 {
1034 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1035 paddr (read_register (PC_REGNUM)),
1036 (long) read_register (SR_REGNUM),
1037 (long) read_register (PR_REGNUM),
1038 (long) read_register (MACH_REGNUM),
1039 (long) read_register (MACL_REGNUM));
1040
1041 printf_filtered ("GBR=%08lx VBR=%08lx",
1042 (long) read_register (GBR_REGNUM),
1043 (long) read_register (VBR_REGNUM));
1044 printf_filtered (" SSR=%08lx SPC=%08lx",
1045 (long) read_register (SSR_REGNUM),
1046 (long) read_register (SPC_REGNUM));
1047
1048 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1049 (long) read_register (0),
1050 (long) read_register (1),
1051 (long) read_register (2),
1052 (long) read_register (3),
1053 (long) read_register (4),
1054 (long) read_register (5),
1055 (long) read_register (6),
1056 (long) read_register (7));
1057 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1058 (long) read_register (8),
1059 (long) read_register (9),
1060 (long) read_register (10),
1061 (long) read_register (11),
1062 (long) read_register (12),
1063 (long) read_register (13),
1064 (long) read_register (14),
1065 (long) read_register (15));
1066 }
1067
1068
1069 static void
1070 sh2e_show_regs (void)
1071 {
1072 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1073 paddr (read_register (PC_REGNUM)),
1074 (long) read_register (SR_REGNUM),
1075 (long) read_register (PR_REGNUM),
1076 (long) read_register (MACH_REGNUM),
1077 (long) read_register (MACL_REGNUM));
1078
1079 printf_filtered ("GBR=%08lx VBR=%08lx",
1080 (long) read_register (GBR_REGNUM),
1081 (long) read_register (VBR_REGNUM));
1082 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1083 (long) read_register (FPUL_REGNUM),
1084 (long) read_register (FPSCR_REGNUM));
1085
1086 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1087 (long) read_register (0),
1088 (long) read_register (1),
1089 (long) read_register (2),
1090 (long) read_register (3),
1091 (long) read_register (4),
1092 (long) read_register (5),
1093 (long) read_register (6),
1094 (long) read_register (7));
1095 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1096 (long) read_register (8),
1097 (long) read_register (9),
1098 (long) read_register (10),
1099 (long) read_register (11),
1100 (long) read_register (12),
1101 (long) read_register (13),
1102 (long) read_register (14),
1103 (long) read_register (15));
1104
1105 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1106 (long) read_register (FP0_REGNUM + 0),
1107 (long) read_register (FP0_REGNUM + 1),
1108 (long) read_register (FP0_REGNUM + 2),
1109 (long) read_register (FP0_REGNUM + 3),
1110 (long) read_register (FP0_REGNUM + 4),
1111 (long) read_register (FP0_REGNUM + 5),
1112 (long) read_register (FP0_REGNUM + 6),
1113 (long) read_register (FP0_REGNUM + 7));
1114 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1115 (long) read_register (FP0_REGNUM + 8),
1116 (long) read_register (FP0_REGNUM + 9),
1117 (long) read_register (FP0_REGNUM + 10),
1118 (long) read_register (FP0_REGNUM + 11),
1119 (long) read_register (FP0_REGNUM + 12),
1120 (long) read_register (FP0_REGNUM + 13),
1121 (long) read_register (FP0_REGNUM + 14),
1122 (long) read_register (FP0_REGNUM + 15));
1123 }
1124
1125 static void
1126 sh3e_show_regs (void)
1127 {
1128 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1129 paddr (read_register (PC_REGNUM)),
1130 (long) read_register (SR_REGNUM),
1131 (long) read_register (PR_REGNUM),
1132 (long) read_register (MACH_REGNUM),
1133 (long) read_register (MACL_REGNUM));
1134
1135 printf_filtered ("GBR=%08lx VBR=%08lx",
1136 (long) read_register (GBR_REGNUM),
1137 (long) read_register (VBR_REGNUM));
1138 printf_filtered (" SSR=%08lx SPC=%08lx",
1139 (long) read_register (SSR_REGNUM),
1140 (long) read_register (SPC_REGNUM));
1141 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1142 (long) read_register (FPUL_REGNUM),
1143 (long) read_register (FPSCR_REGNUM));
1144
1145 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1146 (long) read_register (0),
1147 (long) read_register (1),
1148 (long) read_register (2),
1149 (long) read_register (3),
1150 (long) read_register (4),
1151 (long) read_register (5),
1152 (long) read_register (6),
1153 (long) read_register (7));
1154 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1155 (long) read_register (8),
1156 (long) read_register (9),
1157 (long) read_register (10),
1158 (long) read_register (11),
1159 (long) read_register (12),
1160 (long) read_register (13),
1161 (long) read_register (14),
1162 (long) read_register (15));
1163
1164 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1165 (long) read_register (FP0_REGNUM + 0),
1166 (long) read_register (FP0_REGNUM + 1),
1167 (long) read_register (FP0_REGNUM + 2),
1168 (long) read_register (FP0_REGNUM + 3),
1169 (long) read_register (FP0_REGNUM + 4),
1170 (long) read_register (FP0_REGNUM + 5),
1171 (long) read_register (FP0_REGNUM + 6),
1172 (long) read_register (FP0_REGNUM + 7));
1173 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1174 (long) read_register (FP0_REGNUM + 8),
1175 (long) read_register (FP0_REGNUM + 9),
1176 (long) read_register (FP0_REGNUM + 10),
1177 (long) read_register (FP0_REGNUM + 11),
1178 (long) read_register (FP0_REGNUM + 12),
1179 (long) read_register (FP0_REGNUM + 13),
1180 (long) read_register (FP0_REGNUM + 14),
1181 (long) read_register (FP0_REGNUM + 15));
1182 }
1183
1184 static void
1185 sh3_dsp_show_regs (void)
1186 {
1187 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1188 paddr (read_register (PC_REGNUM)),
1189 (long) read_register (SR_REGNUM),
1190 (long) read_register (PR_REGNUM),
1191 (long) read_register (MACH_REGNUM),
1192 (long) read_register (MACL_REGNUM));
1193
1194 printf_filtered ("GBR=%08lx VBR=%08lx",
1195 (long) read_register (GBR_REGNUM),
1196 (long) read_register (VBR_REGNUM));
1197
1198 printf_filtered (" SSR=%08lx SPC=%08lx",
1199 (long) read_register (SSR_REGNUM),
1200 (long) read_register (SPC_REGNUM));
1201
1202 printf_filtered (" DSR=%08lx",
1203 (long) read_register (DSR_REGNUM));
1204
1205 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1206 (long) read_register (0),
1207 (long) read_register (1),
1208 (long) read_register (2),
1209 (long) read_register (3),
1210 (long) read_register (4),
1211 (long) read_register (5),
1212 (long) read_register (6),
1213 (long) read_register (7));
1214 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1215 (long) read_register (8),
1216 (long) read_register (9),
1217 (long) read_register (10),
1218 (long) read_register (11),
1219 (long) read_register (12),
1220 (long) read_register (13),
1221 (long) read_register (14),
1222 (long) read_register (15));
1223
1224 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1225 (long) read_register (A0G_REGNUM) & 0xff,
1226 (long) read_register (A0_REGNUM),
1227 (long) read_register (M0_REGNUM),
1228 (long) read_register (X0_REGNUM),
1229 (long) read_register (Y0_REGNUM),
1230 (long) read_register (RS_REGNUM),
1231 (long) read_register (MOD_REGNUM));
1232 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1233 (long) read_register (A1G_REGNUM) & 0xff,
1234 (long) read_register (A1_REGNUM),
1235 (long) read_register (M1_REGNUM),
1236 (long) read_register (X1_REGNUM),
1237 (long) read_register (Y1_REGNUM),
1238 (long) read_register (RE_REGNUM));
1239 }
1240
1241 static void
1242 sh4_show_regs (void)
1243 {
1244 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1245 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1246 paddr (read_register (PC_REGNUM)),
1247 (long) read_register (SR_REGNUM),
1248 (long) read_register (PR_REGNUM),
1249 (long) read_register (MACH_REGNUM),
1250 (long) read_register (MACL_REGNUM));
1251
1252 printf_filtered ("GBR=%08lx VBR=%08lx",
1253 (long) read_register (GBR_REGNUM),
1254 (long) read_register (VBR_REGNUM));
1255 printf_filtered (" SSR=%08lx SPC=%08lx",
1256 (long) read_register (SSR_REGNUM),
1257 (long) read_register (SPC_REGNUM));
1258 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1259 (long) read_register (FPUL_REGNUM),
1260 (long) read_register (FPSCR_REGNUM));
1261
1262 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1263 (long) read_register (0),
1264 (long) read_register (1),
1265 (long) read_register (2),
1266 (long) read_register (3),
1267 (long) read_register (4),
1268 (long) read_register (5),
1269 (long) read_register (6),
1270 (long) read_register (7));
1271 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1272 (long) read_register (8),
1273 (long) read_register (9),
1274 (long) read_register (10),
1275 (long) read_register (11),
1276 (long) read_register (12),
1277 (long) read_register (13),
1278 (long) read_register (14),
1279 (long) read_register (15));
1280
1281 printf_filtered ((pr
1282 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1283 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1284 (long) read_register (FP0_REGNUM + 0),
1285 (long) read_register (FP0_REGNUM + 1),
1286 (long) read_register (FP0_REGNUM + 2),
1287 (long) read_register (FP0_REGNUM + 3),
1288 (long) read_register (FP0_REGNUM + 4),
1289 (long) read_register (FP0_REGNUM + 5),
1290 (long) read_register (FP0_REGNUM + 6),
1291 (long) read_register (FP0_REGNUM + 7));
1292 printf_filtered ((pr
1293 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1294 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1295 (long) read_register (FP0_REGNUM + 8),
1296 (long) read_register (FP0_REGNUM + 9),
1297 (long) read_register (FP0_REGNUM + 10),
1298 (long) read_register (FP0_REGNUM + 11),
1299 (long) read_register (FP0_REGNUM + 12),
1300 (long) read_register (FP0_REGNUM + 13),
1301 (long) read_register (FP0_REGNUM + 14),
1302 (long) read_register (FP0_REGNUM + 15));
1303 }
1304
1305 static void
1306 sh_dsp_show_regs (void)
1307 {
1308 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1309 paddr (read_register (PC_REGNUM)),
1310 (long) read_register (SR_REGNUM),
1311 (long) read_register (PR_REGNUM),
1312 (long) read_register (MACH_REGNUM),
1313 (long) read_register (MACL_REGNUM));
1314
1315 printf_filtered ("GBR=%08lx VBR=%08lx",
1316 (long) read_register (GBR_REGNUM),
1317 (long) read_register (VBR_REGNUM));
1318
1319 printf_filtered (" DSR=%08lx",
1320 (long) read_register (DSR_REGNUM));
1321
1322 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1323 (long) read_register (0),
1324 (long) read_register (1),
1325 (long) read_register (2),
1326 (long) read_register (3),
1327 (long) read_register (4),
1328 (long) read_register (5),
1329 (long) read_register (6),
1330 (long) read_register (7));
1331 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1332 (long) read_register (8),
1333 (long) read_register (9),
1334 (long) read_register (10),
1335 (long) read_register (11),
1336 (long) read_register (12),
1337 (long) read_register (13),
1338 (long) read_register (14),
1339 (long) read_register (15));
1340
1341 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1342 (long) read_register (A0G_REGNUM) & 0xff,
1343 (long) read_register (A0_REGNUM),
1344 (long) read_register (M0_REGNUM),
1345 (long) read_register (X0_REGNUM),
1346 (long) read_register (Y0_REGNUM),
1347 (long) read_register (RS_REGNUM),
1348 (long) read_register (MOD_REGNUM));
1349 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1350 (long) read_register (A1G_REGNUM) & 0xff,
1351 (long) read_register (A1_REGNUM),
1352 (long) read_register (M1_REGNUM),
1353 (long) read_register (X1_REGNUM),
1354 (long) read_register (Y1_REGNUM),
1355 (long) read_register (RE_REGNUM));
1356 }
1357
1358 static void
1359 sh_show_regs_command (char *args, int from_tty)
1360 {
1361 if (sh_show_regs)
1362 (*sh_show_regs)();
1363 }
1364
1365 /* Return the GDB type object for the "standard" data type
1366 of data in register N. */
1367 static struct type *
1368 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1369 {
1370 if ((reg_nr >= FP0_REGNUM
1371 && (reg_nr <= FP_LAST_REGNUM))
1372 || (reg_nr == FPUL_REGNUM))
1373 return builtin_type_float;
1374 else
1375 return builtin_type_int;
1376 }
1377
1378 static struct type *
1379 sh_sh4_build_float_register_type (int high)
1380 {
1381 struct type *temp;
1382
1383 temp = create_range_type (NULL, builtin_type_int, 0, high);
1384 return create_array_type (NULL, builtin_type_float, temp);
1385 }
1386
1387 static struct type *
1388 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1389 {
1390 if ((reg_nr >= FP0_REGNUM
1391 && (reg_nr <= FP_LAST_REGNUM))
1392 || (reg_nr == FPUL_REGNUM))
1393 return builtin_type_float;
1394 else if (reg_nr >= DR0_REGNUM
1395 && reg_nr <= DR_LAST_REGNUM)
1396 return builtin_type_double;
1397 else if (reg_nr >= FV0_REGNUM
1398 && reg_nr <= FV_LAST_REGNUM)
1399 return sh_sh4_build_float_register_type (3);
1400 else
1401 return builtin_type_int;
1402 }
1403
1404 static struct type *
1405 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1406 {
1407 return builtin_type_int;
1408 }
1409
1410 /* On the sh4, the DRi pseudo registers are problematic if the target
1411 is little endian. When the user writes one of those registers, for
1412 instance with 'ser var $dr0=1', we want the double to be stored
1413 like this:
1414 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1415 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1416
1417 This corresponds to little endian byte order & big endian word
1418 order. However if we let gdb write the register w/o conversion, it
1419 will write fr0 and fr1 this way:
1420 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1421 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1422 because it will consider fr0 and fr1 as a single LE stretch of memory.
1423
1424 To achieve what we want we must force gdb to store things in
1425 floatformat_ieee_double_littlebyte_bigword (which is defined in
1426 include/floatformat.h and libiberty/floatformat.c.
1427
1428 In case the target is big endian, there is no problem, the
1429 raw bytes will look like:
1430 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1431 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1432
1433 The other pseudo registers (the FVs) also don't pose a problem
1434 because they are stored as 4 individual FP elements. */
1435
1436 static void
1437 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1438 char *from, char *to)
1439 {
1440 if (regnum >= DR0_REGNUM
1441 && regnum <= DR_LAST_REGNUM)
1442 {
1443 DOUBLEST val;
1444 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1445 store_typed_floating (to, type, val);
1446 }
1447 else
1448 error ("sh_register_convert_to_virtual called with non DR register number");
1449 }
1450
1451 static void
1452 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1453 const void *from, void *to)
1454 {
1455 if (regnum >= DR0_REGNUM
1456 && regnum <= DR_LAST_REGNUM)
1457 {
1458 DOUBLEST val = extract_typed_floating (from, type);
1459 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1460 }
1461 else
1462 error("sh_register_convert_to_raw called with non DR register number");
1463 }
1464
1465 /* For vectors of 4 floating point registers. */
1466 static int
1467 fv_reg_base_num (int fv_regnum)
1468 {
1469 int fp_regnum;
1470
1471 fp_regnum = FP0_REGNUM +
1472 (fv_regnum - FV0_REGNUM) * 4;
1473 return fp_regnum;
1474 }
1475
1476 /* For double precision floating point registers, i.e 2 fp regs.*/
1477 static int
1478 dr_reg_base_num (int dr_regnum)
1479 {
1480 int fp_regnum;
1481
1482 fp_regnum = FP0_REGNUM +
1483 (dr_regnum - DR0_REGNUM) * 2;
1484 return fp_regnum;
1485 }
1486
1487 static void
1488 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1489 int reg_nr, void *buffer)
1490 {
1491 int base_regnum, portion;
1492 char temp_buffer[MAX_REGISTER_SIZE];
1493
1494 if (reg_nr >= DR0_REGNUM
1495 && reg_nr <= DR_LAST_REGNUM)
1496 {
1497 base_regnum = dr_reg_base_num (reg_nr);
1498
1499 /* Build the value in the provided buffer. */
1500 /* Read the real regs for which this one is an alias. */
1501 for (portion = 0; portion < 2; portion++)
1502 regcache_raw_read (regcache, base_regnum + portion,
1503 (temp_buffer
1504 + register_size (gdbarch, base_regnum) * portion));
1505 /* We must pay attention to the endiannes. */
1506 sh_sh4_register_convert_to_virtual (reg_nr,
1507 gdbarch_register_type (gdbarch, reg_nr),
1508 temp_buffer, buffer);
1509 }
1510 else if (reg_nr >= FV0_REGNUM
1511 && reg_nr <= FV_LAST_REGNUM)
1512 {
1513 base_regnum = fv_reg_base_num (reg_nr);
1514
1515 /* Read the real regs for which this one is an alias. */
1516 for (portion = 0; portion < 4; portion++)
1517 regcache_raw_read (regcache, base_regnum + portion,
1518 ((char *) buffer
1519 + register_size (gdbarch, base_regnum) * portion));
1520 }
1521 }
1522
1523 static void
1524 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1525 int reg_nr, const void *buffer)
1526 {
1527 int base_regnum, portion;
1528 char temp_buffer[MAX_REGISTER_SIZE];
1529
1530 if (reg_nr >= DR0_REGNUM
1531 && reg_nr <= DR_LAST_REGNUM)
1532 {
1533 base_regnum = dr_reg_base_num (reg_nr);
1534
1535 /* We must pay attention to the endiannes. */
1536 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr,
1537 buffer, temp_buffer);
1538
1539 /* Write the real regs for which this one is an alias. */
1540 for (portion = 0; portion < 2; portion++)
1541 regcache_raw_write (regcache, base_regnum + portion,
1542 (temp_buffer
1543 + register_size (gdbarch, base_regnum) * portion));
1544 }
1545 else if (reg_nr >= FV0_REGNUM
1546 && reg_nr <= FV_LAST_REGNUM)
1547 {
1548 base_regnum = fv_reg_base_num (reg_nr);
1549
1550 /* Write the real regs for which this one is an alias. */
1551 for (portion = 0; portion < 4; portion++)
1552 regcache_raw_write (regcache, base_regnum + portion,
1553 ((char *) buffer
1554 + register_size (gdbarch, base_regnum) * portion));
1555 }
1556 }
1557
1558 /* Floating point vector of 4 float registers. */
1559 static void
1560 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1561 int fv_regnum)
1562 {
1563 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1564 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1565 fv_regnum - FV0_REGNUM,
1566 (int) read_register (first_fp_reg_num),
1567 (int) read_register (first_fp_reg_num + 1),
1568 (int) read_register (first_fp_reg_num + 2),
1569 (int) read_register (first_fp_reg_num + 3));
1570 }
1571
1572 /* Double precision registers. */
1573 static void
1574 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1575 int dr_regnum)
1576 {
1577 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1578
1579 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1580 dr_regnum - DR0_REGNUM,
1581 (int) read_register (first_fp_reg_num),
1582 (int) read_register (first_fp_reg_num + 1));
1583 }
1584
1585 static void
1586 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1587 int regnum)
1588 {
1589 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1590 internal_error (__FILE__, __LINE__,
1591 "Invalid pseudo register number %d\n", regnum);
1592 else if (regnum >= DR0_REGNUM
1593 && regnum <= DR_LAST_REGNUM)
1594 do_dr_register_info (gdbarch, file, regnum);
1595 else if (regnum >= FV0_REGNUM
1596 && regnum <= FV_LAST_REGNUM)
1597 do_fv_register_info (gdbarch, file, regnum);
1598 }
1599
1600 static void
1601 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1602 { /* do values for FP (float) regs */
1603 char *raw_buffer;
1604 double flt; /* double extracted from raw hex data */
1605 int inv;
1606 int j;
1607
1608 /* Allocate space for the float. */
1609 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1610
1611 /* Get the data in raw format. */
1612 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1613 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1614
1615 /* Get the register as a number */
1616 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1617
1618 /* Print the name and some spaces. */
1619 fputs_filtered (REGISTER_NAME (regnum), file);
1620 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1621
1622 /* Print the value. */
1623 if (inv)
1624 fprintf_filtered (file, "<invalid float>");
1625 else
1626 fprintf_filtered (file, "%-10.9g", flt);
1627
1628 /* Print the fp register as hex. */
1629 fprintf_filtered (file, "\t(raw 0x");
1630 for (j = 0; j < register_size (gdbarch, regnum); j++)
1631 {
1632 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
1633 : register_size (gdbarch, regnum) - 1 - j;
1634 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1635 }
1636 fprintf_filtered (file, ")");
1637 fprintf_filtered (file, "\n");
1638 }
1639
1640 static void
1641 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1642 {
1643 char raw_buffer[MAX_REGISTER_SIZE];
1644
1645 fputs_filtered (REGISTER_NAME (regnum), file);
1646 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1647
1648 /* Get the data in raw format. */
1649 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1650 fprintf_filtered (file, "*value not available*\n");
1651
1652 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1653 file, 'x', 1, 0, Val_pretty_default);
1654 fprintf_filtered (file, "\t");
1655 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1656 file, 0, 1, 0, Val_pretty_default);
1657 fprintf_filtered (file, "\n");
1658 }
1659
1660 static void
1661 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1662 {
1663 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1664 internal_error (__FILE__, __LINE__,
1665 "Invalid register number %d\n", regnum);
1666
1667 else if (regnum >= 0 && regnum < NUM_REGS)
1668 {
1669 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
1670 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1671 else
1672 sh_do_register (gdbarch, file, regnum); /* All other regs */
1673 }
1674
1675 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1676 {
1677 sh_print_pseudo_register (gdbarch, file, regnum);
1678 }
1679 }
1680
1681 static void
1682 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1683 struct frame_info *frame, int regnum, int fpregs)
1684 {
1685 if (regnum != -1) /* do one specified register */
1686 {
1687 if (*(REGISTER_NAME (regnum)) == '\0')
1688 error ("Not a valid register for the current processor type");
1689
1690 sh_print_register (gdbarch, file, regnum);
1691 }
1692 else
1693 /* do all (or most) registers */
1694 {
1695 regnum = 0;
1696 while (regnum < NUM_REGS)
1697 {
1698 /* If the register name is empty, it is undefined for this
1699 processor, so don't display anything. */
1700 if (REGISTER_NAME (regnum) == NULL
1701 || *(REGISTER_NAME (regnum)) == '\0')
1702 {
1703 regnum++;
1704 continue;
1705 }
1706
1707 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
1708 {
1709 if (fpregs)
1710 {
1711 /* true for "INFO ALL-REGISTERS" command */
1712 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1713 regnum ++;
1714 }
1715 else
1716 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1717 }
1718 else
1719 {
1720 sh_do_register (gdbarch, file, regnum); /* All other regs */
1721 regnum++;
1722 }
1723 }
1724
1725 if (fpregs)
1726 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1727 {
1728 sh_print_pseudo_register (gdbarch, file, regnum);
1729 regnum++;
1730 }
1731 }
1732 }
1733
1734 #ifdef SVR4_SHARED_LIBS
1735
1736 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1737 for native i386 linux targets using the struct offsets defined in
1738 link.h (but without actual reference to that file).
1739
1740 This makes it possible to access i386-linux shared libraries from
1741 a gdb that was not built on an i386-linux host (for cross debugging).
1742 */
1743
1744 struct link_map_offsets *
1745 sh_linux_svr4_fetch_link_map_offsets (void)
1746 {
1747 static struct link_map_offsets lmo;
1748 static struct link_map_offsets *lmp = 0;
1749
1750 if (lmp == 0)
1751 {
1752 lmp = &lmo;
1753
1754 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1755
1756 lmo.r_map_offset = 4;
1757 lmo.r_map_size = 4;
1758
1759 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1760
1761 lmo.l_addr_offset = 0;
1762 lmo.l_addr_size = 4;
1763
1764 lmo.l_name_offset = 4;
1765 lmo.l_name_size = 4;
1766
1767 lmo.l_next_offset = 12;
1768 lmo.l_next_size = 4;
1769
1770 lmo.l_prev_offset = 16;
1771 lmo.l_prev_size = 4;
1772 }
1773
1774 return lmp;
1775 }
1776 #endif /* SVR4_SHARED_LIBS */
1777
1778 static int
1779 sh_dsp_register_sim_regno (int nr)
1780 {
1781 if (legacy_register_sim_regno (nr) < 0)
1782 return legacy_register_sim_regno (nr);
1783 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1784 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1785 if (nr == MOD_REGNUM)
1786 return SIM_SH_MOD_REGNUM;
1787 if (nr == RS_REGNUM)
1788 return SIM_SH_RS_REGNUM;
1789 if (nr == RE_REGNUM)
1790 return SIM_SH_RE_REGNUM;
1791 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1792 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1793 return nr;
1794 }
1795
1796 static struct sh_frame_cache *
1797 sh_alloc_frame_cache (void)
1798 {
1799 struct sh_frame_cache *cache;
1800 int i;
1801
1802 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1803
1804 /* Base address. */
1805 cache->base = 0;
1806 cache->saved_sp = 0;
1807 cache->sp_offset = 0;
1808 cache->pc = 0;
1809
1810 /* Frameless until proven otherwise. */
1811 cache->uses_fp = 0;
1812
1813 /* Saved registers. We initialize these to -1 since zero is a valid
1814 offset (that's where fp is supposed to be stored). */
1815 for (i = 0; i < SH_NUM_REGS; i++)
1816 {
1817 cache->saved_regs[i] = -1;
1818 }
1819
1820 return cache;
1821 }
1822
1823 static struct sh_frame_cache *
1824 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1825 {
1826 struct sh_frame_cache *cache;
1827 CORE_ADDR current_pc;
1828 int i;
1829
1830 if (*this_cache)
1831 return *this_cache;
1832
1833 cache = sh_alloc_frame_cache ();
1834 *this_cache = cache;
1835
1836 /* In principle, for normal frames, fp holds the frame pointer,
1837 which holds the base address for the current stack frame.
1838 However, for functions that don't need it, the frame pointer is
1839 optional. For these "frameless" functions the frame pointer is
1840 actually the frame pointer of the calling frame. */
1841 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1842 if (cache->base == 0)
1843 return cache;
1844
1845 cache->pc = frame_func_unwind (next_frame);
1846 current_pc = frame_pc_unwind (next_frame);
1847 if (cache->pc != 0)
1848 sh_analyze_prologue (cache->pc, current_pc, cache);
1849
1850 if (!cache->uses_fp)
1851 {
1852 /* We didn't find a valid frame, which means that CACHE->base
1853 currently holds the frame pointer for our calling frame. If
1854 we're at the start of a function, or somewhere half-way its
1855 prologue, the function's frame probably hasn't been fully
1856 setup yet. Try to reconstruct the base address for the stack
1857 frame by looking at the stack pointer. For truly "frameless"
1858 functions this might work too. */
1859 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1860 }
1861
1862 /* Now that we have the base address for the stack frame we can
1863 calculate the value of sp in the calling frame. */
1864 cache->saved_sp = cache->base + cache->sp_offset;
1865
1866 /* Adjust all the saved registers such that they contain addresses
1867 instead of offsets. */
1868 for (i = 0; i < SH_NUM_REGS; i++)
1869 if (cache->saved_regs[i] != -1)
1870 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1871
1872 return cache;
1873 }
1874
1875 static void
1876 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1877 int regnum, int *optimizedp,
1878 enum lval_type *lvalp, CORE_ADDR *addrp,
1879 int *realnump, void *valuep)
1880 {
1881 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1882
1883 gdb_assert (regnum >= 0);
1884
1885 if (regnum == SP_REGNUM && cache->saved_sp)
1886 {
1887 *optimizedp = 0;
1888 *lvalp = not_lval;
1889 *addrp = 0;
1890 *realnump = -1;
1891 if (valuep)
1892 {
1893 /* Store the value. */
1894 store_unsigned_integer (valuep, 4, cache->saved_sp);
1895 }
1896 return;
1897 }
1898
1899 /* The PC of the previous frame is stored in the PR register of
1900 the current frame. Frob regnum so that we pull the value from
1901 the correct place. */
1902 if (regnum == PC_REGNUM)
1903 regnum = PR_REGNUM;
1904
1905 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1906 {
1907 *optimizedp = 0;
1908 *lvalp = lval_memory;
1909 *addrp = cache->saved_regs[regnum];
1910 *realnump = -1;
1911 if (valuep)
1912 {
1913 /* Read the value in from memory. */
1914 read_memory (*addrp, valuep,
1915 register_size (current_gdbarch, regnum));
1916 }
1917 return;
1918 }
1919
1920 frame_register_unwind (next_frame, regnum,
1921 optimizedp, lvalp, addrp, realnump, valuep);
1922 }
1923
1924 static void
1925 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
1926 struct frame_id *this_id)
1927 {
1928 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1929
1930 /* This marks the outermost frame. */
1931 if (cache->base == 0)
1932 return;
1933
1934 *this_id = frame_id_build (cache->saved_sp, cache->pc);
1935 }
1936
1937 static const struct frame_unwind sh_frame_unwind =
1938 {
1939 NORMAL_FRAME,
1940 sh_frame_this_id,
1941 sh_frame_prev_register
1942 };
1943
1944 static const struct frame_unwind *
1945 sh_frame_sniffer (struct frame_info *next_frame)
1946 {
1947 return &sh_frame_unwind;
1948 }
1949
1950 static CORE_ADDR
1951 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1952 {
1953 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1954 }
1955
1956 static CORE_ADDR
1957 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1958 {
1959 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1960 }
1961
1962 static struct frame_id
1963 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1964 {
1965 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1966 frame_pc_unwind (next_frame));
1967 }
1968
1969 static CORE_ADDR
1970 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
1971 {
1972 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1973
1974 return cache->base;
1975 }
1976
1977 static const struct frame_base sh_frame_base =
1978 {
1979 &sh_frame_unwind,
1980 sh_frame_base_address,
1981 sh_frame_base_address,
1982 sh_frame_base_address
1983 };
1984
1985 /* The epilogue is defined here as the area at the end of a function,
1986 either on the `ret' instruction itself or after an instruction which
1987 destroys the function's stack frame. */
1988 static int
1989 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1990 {
1991 CORE_ADDR func_addr = 0, func_end = 0;
1992
1993 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1994 {
1995 ULONGEST inst;
1996 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
1997 for a nop and some fixed data (e.g. big offsets) which are
1998 unfortunately also treated as part of the function (which
1999 means, they are below func_end. */
2000 CORE_ADDR addr = func_end - 28;
2001 if (addr < func_addr + 4)
2002 addr = func_addr + 4;
2003 if (pc < addr)
2004 return 0;
2005
2006 /* First search forward until hitting an rts. */
2007 while (addr < func_end
2008 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2009 addr += 2;
2010 if (addr >= func_end)
2011 return 0;
2012
2013 /* At this point we should find a mov.l @r15+,r14 instruction,
2014 either before or after the rts. If not, then the function has
2015 probably no "normal" epilogue and we bail out here. */
2016 inst = read_memory_unsigned_integer (addr - 2, 2);
2017 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2018 addr -= 2;
2019 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2020 return 0;
2021
2022 /* Step over possible lds.l @r15+,pr. */
2023 inst = read_memory_unsigned_integer (addr - 2, 2);
2024 if (IS_LDS (inst))
2025 {
2026 addr -= 2;
2027 inst = read_memory_unsigned_integer (addr - 2, 2);
2028 }
2029
2030 /* Step over possible mov r14,r15. */
2031 if (IS_MOV_FP_SP (inst))
2032 {
2033 addr -= 2;
2034 inst = read_memory_unsigned_integer (addr - 2, 2);
2035 }
2036
2037 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2038 instructions. */
2039 while (addr > func_addr + 4
2040 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2041 {
2042 addr -= 2;
2043 inst = read_memory_unsigned_integer (addr - 2, 2);
2044 }
2045
2046 if (pc >= addr)
2047 return 1;
2048 }
2049 return 0;
2050 }
2051
2052 static gdbarch_init_ftype sh_gdbarch_init;
2053
2054 static struct gdbarch *
2055 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2056 {
2057 struct gdbarch *gdbarch;
2058
2059 sh_show_regs = sh_generic_show_regs;
2060 switch (info.bfd_arch_info->mach)
2061 {
2062 case bfd_mach_sh2e:
2063 sh_show_regs = sh2e_show_regs;
2064 break;
2065 case bfd_mach_sh_dsp:
2066 sh_show_regs = sh_dsp_show_regs;
2067 break;
2068
2069 case bfd_mach_sh3:
2070 sh_show_regs = sh3_show_regs;
2071 break;
2072
2073 case bfd_mach_sh3e:
2074 sh_show_regs = sh3e_show_regs;
2075 break;
2076
2077 case bfd_mach_sh3_dsp:
2078 sh_show_regs = sh3_dsp_show_regs;
2079 break;
2080
2081 case bfd_mach_sh4:
2082 sh_show_regs = sh4_show_regs;
2083 break;
2084
2085 case bfd_mach_sh5:
2086 sh_show_regs = sh64_show_regs;
2087 /* SH5 is handled entirely in sh64-tdep.c */
2088 return sh64_gdbarch_init (info, arches);
2089 }
2090
2091 /* If there is already a candidate, use it. */
2092 arches = gdbarch_list_lookup_by_info (arches, &info);
2093 if (arches != NULL)
2094 return arches->gdbarch;
2095
2096 /* None found, create a new architecture from the information
2097 provided. */
2098 gdbarch = gdbarch_alloc (&info, NULL);
2099
2100 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2101 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2102 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2103 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2104 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2105 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2106 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2107 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2108
2109 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2110 set_gdbarch_sp_regnum (gdbarch, 15);
2111 set_gdbarch_pc_regnum (gdbarch, 16);
2112 set_gdbarch_fp0_regnum (gdbarch, -1);
2113 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2114
2115 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2116
2117 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2118
2119 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2120 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2121
2122 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2123 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2124
2125 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2126
2127 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2128 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2129 set_gdbarch_extract_struct_value_address (gdbarch,
2130 sh_extract_struct_value_address);
2131
2132 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2133 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2134 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2135 set_gdbarch_function_start_offset (gdbarch, 0);
2136
2137 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2138 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2139
2140 set_gdbarch_frame_args_skip (gdbarch, 0);
2141 set_gdbarch_frameless_function_invocation (gdbarch,
2142 frameless_look_for_prologue);
2143 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2144
2145 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2146 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2147 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2148 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2149 frame_base_set_default (gdbarch, &sh_frame_base);
2150
2151 set_gdbarch_in_function_epilogue_p (gdbarch,
2152 sh_in_function_epilogue_p);
2153
2154 switch (info.bfd_arch_info->mach)
2155 {
2156 case bfd_mach_sh:
2157 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2158 break;
2159
2160 case bfd_mach_sh2:
2161 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2162 break;
2163
2164 case bfd_mach_sh2e:
2165 /* doubles on sh2e and sh3e are actually 4 byte. */
2166 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2167
2168 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2169 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2170 set_gdbarch_fp0_regnum (gdbarch, 25);
2171 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2172 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2173 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2174 break;
2175
2176 case bfd_mach_sh_dsp:
2177 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2178 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2179 break;
2180
2181 case bfd_mach_sh3:
2182 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2183 break;
2184
2185 case bfd_mach_sh3e:
2186 /* doubles on sh2e and sh3e are actually 4 byte. */
2187 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2188
2189 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2190 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2191 set_gdbarch_fp0_regnum (gdbarch, 25);
2192 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2193 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2194 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2195 break;
2196
2197 case bfd_mach_sh3_dsp:
2198 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2199 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2200 break;
2201
2202 case bfd_mach_sh4:
2203 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2204 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2205 set_gdbarch_fp0_regnum (gdbarch, 25);
2206 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2207 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2208 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2209 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2210 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2211 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2212 break;
2213
2214 default:
2215 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2216 break;
2217 }
2218
2219 /* Hook in ABI-specific overrides, if they have been registered. */
2220 gdbarch_init_osabi (info, gdbarch);
2221
2222 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2223 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2224
2225 return gdbarch;
2226 }
2227
2228 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2229
2230 void
2231 _initialize_sh_tdep (void)
2232 {
2233 struct cmd_list_element *c;
2234
2235 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2236
2237 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2238 }
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