1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
38 #include "target-float.h"
45 /* Register numbers shared with the simulator. */
46 #include "gdb/sim-sh.h"
48 #include "sh64-tdep.h"
51 /* Information that is dependent on the processor variant. */
62 /* ISA-specific data types. */
63 struct type
*sh_littlebyte_bigword_type
;
67 sh64_littlebyte_bigword_type (struct gdbarch
*gdbarch
)
69 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
71 if (tdep
->sh_littlebyte_bigword_type
== NULL
)
72 tdep
->sh_littlebyte_bigword_type
73 = arch_float_type (gdbarch
, -1, "builtin_type_sh_littlebyte_bigword",
74 floatformats_ieee_double_littlebyte_bigword
);
76 return tdep
->sh_littlebyte_bigword_type
;
79 struct sh64_frame_cache
86 /* Flag showing that a frame has been created in the prologue code. */
91 /* Saved registers. */
92 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
96 /* Registers of SH5 */
100 DEFAULT_RETURN_REGNUM
= 2,
101 STRUCT_RETURN_REGNUM
= 2,
104 FLOAT_ARGLAST_REGNUM
= 11,
105 MEDIA_FP_REGNUM
= 14,
109 DR_LAST_REGNUM
= 172,
110 /* FPP stands for Floating Point Pair, to avoid confusion with
111 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
112 point register. Unfortunately on the sh5, the floating point
113 registers are called FR, and the floating point pairs are called FP. */
115 FPP_LAST_REGNUM
= 204,
117 FV_LAST_REGNUM
= 220,
119 R_LAST_C_REGNUM
= 236,
126 FPSCR_C_REGNUM
= 243,
129 FP_LAST_C_REGNUM
= 260,
131 DR_LAST_C_REGNUM
= 268,
133 FV_LAST_C_REGNUM
= 272,
134 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
135 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
136 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
137 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
138 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
142 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
144 static const char *register_names
[] =
146 /* SH MEDIA MODE (ISA 32) */
147 /* general registers (64-bit) 0-63 */
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
151 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
152 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
153 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
154 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
155 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
160 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
163 /* target registers (64-bit) 68-75 */
164 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
166 /* floating point state control register (32-bit) 76 */
169 /* single precision floating point registers (32-bit) 77-140 */
170 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
171 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
172 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
173 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
174 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
175 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
176 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
177 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
179 /* double precision registers (pseudo) 141-172 */
180 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
181 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
182 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
183 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
185 /* floating point pairs (pseudo) 173-204 */
186 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
187 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
188 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
189 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
191 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
192 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
193 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
195 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
196 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
197 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
199 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
201 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
202 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
203 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
204 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
205 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
206 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
207 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
208 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
213 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
215 return register_names
[reg_nr
];
218 #define NUM_PSEUDO_REGS_SH_MEDIA 80
219 #define NUM_PSEUDO_REGS_SH_COMPACT 51
221 /* Macros and functions for setting and testing a bit in a minimal
222 symbol that marks it as 32-bit function. The MSB of the minimal
223 symbol's "info" field is used for this purpose.
225 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
226 i.e. refers to a 32-bit function, and sets a "special" bit in a
227 minimal symbol to mark it as a 32-bit function
228 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
230 #define MSYMBOL_IS_SPECIAL(msym) \
231 MSYMBOL_TARGET_FLAG_1 (msym)
234 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
239 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
241 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
242 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
246 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
247 are some macros to test, set, or clear bit 0 of addresses. */
248 #define IS_ISA32_ADDR(addr) ((addr) & 1)
249 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
250 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
253 pc_is_isa32 (bfd_vma memaddr
)
255 struct bound_minimal_symbol sym
;
257 /* If bit 0 of the address is set, assume this is a
258 ISA32 (shmedia) address. */
259 if (IS_ISA32_ADDR (memaddr
))
262 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
263 the high bit of the info field. Use this to decide if the function is
265 sym
= lookup_minimal_symbol_by_pc (memaddr
);
267 return MSYMBOL_IS_SPECIAL (sym
.minsym
);
273 sh64_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
275 if (pc_is_isa32 (*pcptr
))
277 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
284 static const gdb_byte
*
285 sh64_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
289 /* The BRK instruction for shmedia is
290 01101111 11110101 11111111 11110000
291 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
292 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
294 /* The BRK instruction for shcompact is
296 which translates in big endian mode to 0x0, 0x3b
297 and in little endian mode to 0x3b, 0x0 */
301 static unsigned char big_breakpoint_media
[] = {
302 0x6f, 0xf5, 0xff, 0xf0
304 static unsigned char little_breakpoint_media
[] = {
305 0xf0, 0xff, 0xf5, 0x6f
308 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
309 return big_breakpoint_media
;
311 return little_breakpoint_media
;
315 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
316 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
318 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
319 return big_breakpoint_compact
;
321 return little_breakpoint_compact
;
325 /* Prologue looks like
326 [mov.l <regs>,@-r15]...
331 Actually it can be more complicated than this. For instance, with
349 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
350 with l=1 and n = 18 0110101111110001010010100aaa0000 */
351 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
353 /* STS.L PR,@-r0 0100000000100010
354 r0-4-->r0, PR-->(r0) */
355 #define IS_STS_R0(x) ((x) == 0x4022)
357 /* STS PR, Rm 0000mmmm00101010
359 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
361 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
363 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
365 /* MOV.L R14,@(disp,r15) 000111111110dddd
366 R14-->(dispx4+r15) */
367 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
369 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
370 R18-->(dispx8+R14) */
371 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
373 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
374 R18-->(dispx8+R15) */
375 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
377 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
378 R18-->(dispx4+R15) */
379 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
381 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
382 R14-->(dispx8+R15) */
383 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
385 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
386 R14-->(dispx4+R15) */
387 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
389 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
391 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
393 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
395 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
397 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
399 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
401 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
403 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
405 #define IS_MOV_SP_FP_MEDIA(x) \
406 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
408 /* MOV #imm, R0 1110 0000 ssss ssss
410 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
412 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
413 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
415 /* ADD r15,r0 0011 0000 1111 1100
417 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
419 /* MOV.L R14 @-R0 0010 0000 1110 0110
420 R14-->(R0-4), R0-4-->R0 */
421 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
423 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
424 where Rm is one of r2-r9 which are the argument registers. */
425 /* FIXME: Recognize the float and double register moves too! */
426 #define IS_MEDIA_IND_ARG_MOV(x) \
427 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
428 && (((x) & 0x03f00000) >= 0x00200000 \
429 && ((x) & 0x03f00000) <= 0x00900000))
431 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
432 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
433 where Rm is one of r2-r9 which are the argument registers. */
434 #define IS_MEDIA_ARG_MOV(x) \
435 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
436 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
438 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
439 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
440 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
441 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
442 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
443 #define IS_MEDIA_MOV_TO_R14(x) \
444 ((((x) & 0xfffffc0f) == 0xa0e00000) \
445 || (((x) & 0xfffffc0f) == 0xa4e00000) \
446 || (((x) & 0xfffffc0f) == 0xa8e00000) \
447 || (((x) & 0xfffffc0f) == 0xb4e00000) \
448 || (((x) & 0xfffffc0f) == 0xbce00000))
450 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
452 #define IS_COMPACT_IND_ARG_MOV(x) \
453 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
454 && (((x) & 0x00f0) <= 0x0090))
456 /* compact direct arg move!
457 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
458 #define IS_COMPACT_ARG_MOV(x) \
459 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
460 && ((x) & 0x00f0) <= 0x0090))
462 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
463 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
464 #define IS_COMPACT_MOV_TO_R14(x) \
465 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
467 #define IS_JSR_R0(x) ((x) == 0x400b)
468 #define IS_NOP(x) ((x) == 0x0009)
471 /* MOV r15,r14 0110111011110011
473 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
475 /* ADD #imm,r15 01111111iiiiiiii
477 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
479 /* Skip any prologue before the guts of a function. */
481 /* Skip the prologue using the debug information. If this fails we'll
482 fall back on the 'guess' method below. */
484 after_prologue (CORE_ADDR pc
)
486 struct symtab_and_line sal
;
487 CORE_ADDR func_addr
, func_end
;
489 /* If we can not find the symbol in the partial symbol table, then
490 there is no hope we can determine the function's start address
492 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
496 /* Get the line associated with FUNC_ADDR. */
497 sal
= find_pc_line (func_addr
, 0);
499 /* There are only two cases to consider. First, the end of the source line
500 is within the function bounds. In that case we return the end of the
501 source line. Second is the end of the source line extends beyond the
502 bounds of the current function. We need to use the slow code to
503 examine instructions in that case. */
504 if (sal
.end
< func_end
)
511 look_for_args_moves (struct gdbarch
*gdbarch
,
512 CORE_ADDR start_pc
, int media_mode
)
514 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
517 int insn_size
= (media_mode
? 4 : 2);
519 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
523 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
524 insn_size
, byte_order
);
526 if (IS_MEDIA_IND_ARG_MOV (w
))
528 /* This must be followed by a store to r14, so the argument
529 is where the debug info says it is. This can happen after
530 the SP has been saved, unfortunately. */
532 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
533 insn_size
, byte_order
);
535 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
538 else if (IS_MEDIA_ARG_MOV (w
))
540 /* These instructions store directly the argument in r14. */
548 w
= read_memory_integer (here
, insn_size
, byte_order
);
551 if (IS_COMPACT_IND_ARG_MOV (w
))
553 /* This must be followed by a store to r14, so the argument
554 is where the debug info says it is. This can happen after
555 the SP has been saved, unfortunately. */
557 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
560 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
563 else if (IS_COMPACT_ARG_MOV (w
))
565 /* These instructions store directly the argument in r14. */
568 else if (IS_MOVL_R0 (w
))
570 /* There is a function that gcc calls to get the arguments
571 passed correctly to the function. Only after this
572 function call the arguments will be found at the place
573 where they are supposed to be. This happens in case the
574 argument has to be stored into a 64-bit register (for
575 instance doubles, long longs). SHcompact doesn't have
576 access to the full 64-bits, so we store the register in
577 stack slot and store the address of the stack slot in
578 the register, then do a call through a wrapper that
579 loads the memory value into the register. A SHcompact
580 callee calls an argument decoder
581 (GCC_shcompact_incoming_args) that stores the 64-bit
582 value in a stack slot and stores the address of the
583 stack slot in the register. GCC thinks the argument is
584 just passed by transparent reference, but this is only
585 true after the argument decoder is called. Such a call
586 needs to be considered part of the prologue. */
588 /* This must be followed by a JSR @r0 instruction and by
589 a NOP instruction. After these, the prologue is over! */
591 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
594 if (IS_JSR_R0 (next_insn
))
596 next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
600 if (IS_NOP (next_insn
))
613 sh64_skip_prologue_hard_way (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
615 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
624 if (pc_is_isa32 (start_pc
) == 0)
630 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
635 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
636 insn_size
, byte_order
);
638 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
639 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
640 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
)
641 || IS_PTABSL_R18 (w
))
645 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
653 /* Don't bail out yet, we may have arguments stored in
654 registers here, according to the debug info, so that
655 gdb can print the frames correctly. */
656 start_pc
= look_for_args_moves (gdbarch
,
657 here
- insn_size
, media_mode
);
663 int w
= 0xffff & read_memory_integer (here
, insn_size
, byte_order
);
666 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
667 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
668 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
672 else if (IS_MOV_SP_FP (w
))
680 /* Don't bail out yet, we may have arguments stored in
681 registers here, according to the debug info, so that
682 gdb can print the frames correctly. */
683 start_pc
= look_for_args_moves (gdbarch
,
684 here
- insn_size
, media_mode
);
694 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
696 CORE_ADDR post_prologue_pc
;
698 /* See if we can determine the end of the prologue via the symbol table.
699 If so, then return either PC, or the PC after the prologue, whichever
701 post_prologue_pc
= after_prologue (pc
);
703 /* If after_prologue returned a useful address, then use it. Else
704 fall back on the instruction skipping code. */
705 if (post_prologue_pc
!= 0)
706 return std::max (pc
, post_prologue_pc
);
708 return sh64_skip_prologue_hard_way (gdbarch
, pc
);
711 /* Should call_function allocate stack space for a struct return? */
713 sh64_use_struct_convention (struct type
*type
)
715 return (TYPE_LENGTH (type
) > 8);
718 /* For vectors of 4 floating point registers. */
720 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
724 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
728 /* For double precision floating point registers, i.e 2 fp regs. */
730 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
734 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
738 /* For pairs of floating point registers. */
740 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
744 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
750 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
751 GDB_REGNUM BASE_REGNUM
811 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
813 int base_regnum
= reg_nr
;
815 /* general register N maps to general register N */
816 if (reg_nr
>= R0_C_REGNUM
817 && reg_nr
<= R_LAST_C_REGNUM
)
818 base_regnum
= reg_nr
- R0_C_REGNUM
;
820 /* floating point register N maps to floating point register N */
821 else if (reg_nr
>= FP0_C_REGNUM
822 && reg_nr
<= FP_LAST_C_REGNUM
)
823 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
825 /* double prec register N maps to base regnum for double prec register N */
826 else if (reg_nr
>= DR0_C_REGNUM
827 && reg_nr
<= DR_LAST_C_REGNUM
)
828 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
829 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
831 /* vector N maps to base regnum for vector register N */
832 else if (reg_nr
>= FV0_C_REGNUM
833 && reg_nr
<= FV_LAST_C_REGNUM
)
834 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
835 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
837 else if (reg_nr
== PC_C_REGNUM
)
838 base_regnum
= gdbarch_pc_regnum (gdbarch
);
840 else if (reg_nr
== GBR_C_REGNUM
)
843 else if (reg_nr
== MACH_C_REGNUM
844 || reg_nr
== MACL_C_REGNUM
)
847 else if (reg_nr
== PR_C_REGNUM
)
848 base_regnum
= PR_REGNUM
;
850 else if (reg_nr
== T_C_REGNUM
)
853 else if (reg_nr
== FPSCR_C_REGNUM
)
854 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
856 else if (reg_nr
== FPUL_C_REGNUM
)
857 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
863 sign_extend (int value
, int bits
)
865 value
= value
& ((1 << bits
) - 1);
866 return (value
& (1 << (bits
- 1))
867 ? value
| (~((1 << bits
) - 1))
872 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
873 struct sh64_frame_cache
*cache
,
875 CORE_ADDR current_pc
)
882 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
884 cache
->sp_offset
= 0;
886 /* Loop around examining the prologue insns until we find something
887 that does not appear to be part of the prologue. But give up
888 after 20 of them, since we're getting silly then. */
892 if (cache
->media_mode
)
897 opc
= pc
+ (insn_size
* 28);
898 if (opc
> current_pc
)
900 for ( ; pc
<= opc
; pc
+= insn_size
)
902 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
904 insn_size
, byte_order
);
906 if (!cache
->media_mode
)
908 if (IS_STS_PR (insn
))
910 int next_insn
= read_memory_integer (pc
+ insn_size
,
911 insn_size
, byte_order
);
912 if (IS_MOV_TO_R15 (next_insn
))
914 cache
->saved_regs
[PR_REGNUM
]
915 = cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8)
921 else if (IS_MOV_R14 (insn
))
923 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
924 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
928 else if (IS_MOV_R0 (insn
))
930 /* Put in R0 the offset from SP at which to store some
931 registers. We are interested in this value, because it
932 will tell us where the given registers are stored within
934 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
937 else if (IS_ADD_SP_R0 (insn
))
939 /* This instruction still prepares r0, but we don't care.
940 We already have the offset in r0_val. */
943 else if (IS_STS_R0 (insn
))
945 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
946 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
950 else if (IS_MOV_R14_R0 (insn
))
952 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
953 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
959 else if (IS_ADD_SP (insn
))
960 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
962 else if (IS_MOV_SP_FP (insn
))
967 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
969 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
971 else if (IS_STQ_R18_R15 (insn
))
972 cache
->saved_regs
[PR_REGNUM
]
973 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
976 else if (IS_STL_R18_R15 (insn
))
977 cache
->saved_regs
[PR_REGNUM
]
978 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
981 else if (IS_STQ_R14_R15 (insn
))
983 cache
->saved_regs
[MEDIA_FP_REGNUM
]
984 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
989 else if (IS_STL_R14_R15 (insn
))
991 cache
->saved_regs
[MEDIA_FP_REGNUM
]
992 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
997 else if (IS_MOV_SP_FP_MEDIA (insn
))
1004 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
1009 /* Function: push_dummy_call
1010 Setup the function arguments for calling a function in the inferior.
1012 On the Renesas SH architecture, there are four registers (R4 to R7)
1013 which are dedicated for passing function arguments. Up to the first
1014 four arguments (depending on size) may go into these registers.
1015 The rest go on the stack.
1017 Arguments that are smaller than 4 bytes will still take up a whole
1018 register or a whole 32-bit word on the stack, and will be
1019 right-justified in the register or the stack word. This includes
1020 chars, shorts, and small aggregate types.
1022 Arguments that are larger than 4 bytes may be split between two or
1023 more registers. If there are not enough registers free, an argument
1024 may be passed partly in a register (or registers), and partly on the
1025 stack. This includes doubles, long longs, and larger aggregates.
1026 As far as I know, there is no upper limit to the size of aggregates
1027 that will be passed in this way; in other words, the convention of
1028 passing a pointer to a large aggregate instead of a copy is not used.
1030 An exceptional case exists for struct arguments (and possibly other
1031 aggregates such as arrays) if the size is larger than 4 bytes but
1032 not a multiple of 4 bytes. In this case the argument is never split
1033 between the registers and the stack, but instead is copied in its
1034 entirety onto the stack, AND also copied into as many registers as
1035 there is room for. In other words, space in registers permitting,
1036 two copies of the same argument are passed in. As far as I can tell,
1037 only the one on the stack is used, although that may be a function
1038 of the level of compiler optimization. I suspect this is a compiler
1039 bug. Arguments of these odd sizes are left-justified within the
1040 word (as opposed to arguments smaller than 4 bytes, which are
1043 If the function is to return an aggregate type such as a struct, it
1044 is either returned in the normal return value register R0 (if its
1045 size is no greater than one byte), or else the caller must allocate
1046 space into which the callee will copy the return value (if the size
1047 is greater than one byte). In this case, a pointer to the return
1048 value location is passed into the callee in register R2, which does
1049 not displace any of the other arguments passed in via registers R4
1052 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1053 non-scalar (struct, union) elements (even if the elements are
1055 FR0-FR11 for single precision floating point (float)
1056 DR0-DR10 for double precision floating point (double)
1058 If a float is argument number 3 (for instance) and arguments number
1059 1,2, and 4 are integer, the mapping will be:
1060 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1062 If a float is argument number 10 (for instance) and arguments number
1063 1 through 10 are integer, the mapping will be:
1064 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1065 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1066 arg11->stack(16,SP). I.e. there is hole in the stack.
1068 Different rules apply for variable arguments functions, and for functions
1069 for which the prototype is not known. */
1072 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1073 struct value
*function
,
1074 struct regcache
*regcache
,
1076 int nargs
, struct value
**args
,
1077 CORE_ADDR sp
, int struct_return
,
1078 CORE_ADDR struct_addr
)
1080 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1081 int stack_offset
, stack_alloc
;
1083 int float_arg_index
= 0;
1084 int double_arg_index
= 0;
1088 const gdb_byte
*val
;
1094 memset (fp_args
, 0, sizeof (fp_args
));
1096 /* First force sp to a 8-byte alignment. */
1097 sp
= sh64_frame_align (gdbarch
, sp
);
1099 /* The "struct return pointer" pseudo-argument has its own dedicated
1103 regcache_cooked_write_unsigned (regcache
,
1104 STRUCT_RETURN_REGNUM
, struct_addr
);
1106 /* Now make sure there's space on the stack. */
1107 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1108 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1109 sp
-= stack_alloc
; /* Make room on stack for args. */
1111 /* Now load as many as possible of the first arguments into
1112 registers, and push the rest onto the stack. There are 64 bytes
1113 in eight registers available. Loop thru args from first to last. */
1115 int_argreg
= ARG0_REGNUM
;
1117 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1119 type
= value_type (args
[argnum
]);
1120 len
= TYPE_LENGTH (type
);
1121 memset (valbuf
, 0, sizeof (valbuf
));
1123 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1125 argreg_size
= register_size (gdbarch
, int_argreg
);
1127 if (len
< argreg_size
)
1129 /* value gets right-justified in the register or stack word. */
1130 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1131 memcpy (valbuf
+ argreg_size
- len
,
1132 value_contents (args
[argnum
]), len
);
1134 memcpy (valbuf
, value_contents (args
[argnum
]), len
);
1139 val
= value_contents (args
[argnum
]);
1143 if (int_argreg
> ARGLAST_REGNUM
)
1145 /* Must go on the stack. */
1146 write_memory (sp
+ stack_offset
, val
, argreg_size
);
1147 stack_offset
+= 8;/*argreg_size;*/
1149 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1150 That's because some *&^%$ things get passed on the stack
1151 AND in the registers! */
1152 if (int_argreg
<= ARGLAST_REGNUM
)
1154 /* There's room in a register. */
1155 regval
= extract_unsigned_integer (val
, argreg_size
,
1157 regcache_cooked_write_unsigned (regcache
,
1158 int_argreg
, regval
);
1160 /* Store the value 8 bytes at a time. This means that
1161 things larger than 8 bytes may go partly in registers
1162 and partly on the stack. FIXME: argreg is incremented
1163 before we use its size. */
1171 val
= value_contents (args
[argnum
]);
1174 /* Where is it going to be stored? */
1175 while (fp_args
[float_arg_index
])
1178 /* Now float_argreg points to the register where it
1179 should be stored. Are we still within the allowed
1181 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1183 /* Goes in FR0...FR11 */
1184 regcache_cooked_write (regcache
,
1185 gdbarch_fp0_regnum (gdbarch
)
1188 fp_args
[float_arg_index
] = 1;
1189 /* Skip the corresponding general argument register. */
1194 /* Store it as the integers, 8 bytes at the time, if
1195 necessary spilling on the stack. */
1200 /* Where is it going to be stored? */
1201 while (fp_args
[double_arg_index
])
1202 double_arg_index
+= 2;
1203 /* Now double_argreg points to the register
1204 where it should be stored.
1205 Are we still within the allowed register set? */
1206 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1208 /* Goes in DR0...DR10 */
1209 /* The numbering of the DRi registers is consecutive,
1210 i.e. includes odd numbers. */
1211 int double_register_offset
= double_arg_index
/ 2;
1212 int regnum
= DR0_REGNUM
+ double_register_offset
;
1213 regcache_cooked_write (regcache
, regnum
, val
);
1214 fp_args
[double_arg_index
] = 1;
1215 fp_args
[double_arg_index
+ 1] = 1;
1216 /* Skip the corresponding general argument register. */
1221 /* Store it as the integers, 8 bytes at the time, if
1222 necessary spilling on the stack. */
1227 /* Store return address. */
1228 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1230 /* Update stack pointer. */
1231 regcache_cooked_write_unsigned (regcache
,
1232 gdbarch_sp_regnum (gdbarch
), sp
);
1237 /* Find a function's return value in the appropriate registers (in
1238 regbuf), and copy it into valbuf. Extract from an array REGBUF
1239 containing the (raw) register state a function return value of type
1240 TYPE, and copy that, in virtual format, into VALBUF. */
1242 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1245 struct gdbarch
*gdbarch
= regcache
->arch ();
1246 int len
= TYPE_LENGTH (type
);
1248 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1252 /* Return value stored in gdbarch_fp0_regnum. */
1253 regcache_raw_read (regcache
,
1254 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1258 /* return value stored in DR0_REGNUM. */
1260 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1262 convert_typed_floating (buf
, sh64_littlebyte_bigword_type (gdbarch
),
1272 /* Result is in register 2. If smaller than 8 bytes, it is padded
1273 at the most significant end. */
1274 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1276 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1277 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1281 memcpy (valbuf
, buf
+ offset
, len
);
1284 error (_("bad size for return value"));
1288 /* Write into appropriate registers a function return value
1289 of type TYPE, given in virtual format.
1290 If the architecture is sh4 or sh3e, store a function's return value
1291 in the R0 general register or in the FP0 floating point register,
1292 depending on the type of the return value. In all the other cases
1293 the result is stored in r0, left-justified. */
1296 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1297 const gdb_byte
*valbuf
)
1299 struct gdbarch
*gdbarch
= regcache
->arch ();
1300 gdb_byte buf
[64]; /* more than enough... */
1301 int len
= TYPE_LENGTH (type
);
1303 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1305 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1306 for (i
= 0; i
< len
; i
+= 4)
1307 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1308 regcache_raw_write (regcache
, regnum
++,
1309 valbuf
+ len
- 4 - i
);
1311 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1315 int return_register
= DEFAULT_RETURN_REGNUM
;
1318 if (len
<= register_size (gdbarch
, return_register
))
1320 /* Pad with zeros. */
1321 memset (buf
, 0, register_size (gdbarch
, return_register
));
1322 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1323 offset
= 0; /*register_size (gdbarch,
1324 return_register) - len;*/
1326 offset
= register_size (gdbarch
, return_register
) - len
;
1328 memcpy (buf
+ offset
, valbuf
, len
);
1329 regcache_raw_write (regcache
, return_register
, buf
);
1332 regcache_raw_write (regcache
, return_register
, valbuf
);
1336 static enum return_value_convention
1337 sh64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1338 struct type
*type
, struct regcache
*regcache
,
1339 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1341 if (sh64_use_struct_convention (type
))
1342 return RETURN_VALUE_STRUCT_CONVENTION
;
1344 sh64_store_return_value (type
, regcache
, writebuf
);
1346 sh64_extract_return_value (type
, regcache
, readbuf
);
1347 return RETURN_VALUE_REGISTER_CONVENTION
;
1352 SH MEDIA MODE (ISA 32)
1353 general registers (64-bit) 0-63
1354 0 r0, r1, r2, r3, r4, r5, r6, r7,
1355 64 r8, r9, r10, r11, r12, r13, r14, r15,
1356 128 r16, r17, r18, r19, r20, r21, r22, r23,
1357 192 r24, r25, r26, r27, r28, r29, r30, r31,
1358 256 r32, r33, r34, r35, r36, r37, r38, r39,
1359 320 r40, r41, r42, r43, r44, r45, r46, r47,
1360 384 r48, r49, r50, r51, r52, r53, r54, r55,
1361 448 r56, r57, r58, r59, r60, r61, r62, r63,
1366 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1369 target registers (64-bit) 68-75
1370 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1372 floating point state control register (32-bit) 76
1375 single precision floating point registers (32-bit) 77-140
1376 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1377 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1378 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1379 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1380 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1381 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1382 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1383 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1385 TOTAL SPACE FOR REGISTERS: 868 bytes
1387 From here on they are all pseudo registers: no memory allocated.
1388 REGISTER_BYTE returns the register byte for the base register.
1390 double precision registers (pseudo) 141-172
1391 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1392 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1393 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1394 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1396 floating point pairs (pseudo) 173-204
1397 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1398 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1399 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1400 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1402 floating point vectors (4 floating point regs) (pseudo) 205-220
1403 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1404 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1406 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1407 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1408 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1410 gbr_c, mach_c, macl_c, pr_c, t_c,
1412 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1413 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1414 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1415 fv0_c, fv4_c, fv8_c, fv12_c
1418 static struct type
*
1419 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1421 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1425 /* Return the GDB type object for the "standard" data type
1426 of data in register REG_NR. */
1427 static struct type
*
1428 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1430 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1431 && reg_nr
<= FP_LAST_REGNUM
)
1432 || (reg_nr
>= FP0_C_REGNUM
1433 && reg_nr
<= FP_LAST_C_REGNUM
))
1434 return builtin_type (gdbarch
)->builtin_float
;
1435 else if ((reg_nr
>= DR0_REGNUM
1436 && reg_nr
<= DR_LAST_REGNUM
)
1437 || (reg_nr
>= DR0_C_REGNUM
1438 && reg_nr
<= DR_LAST_C_REGNUM
))
1439 return builtin_type (gdbarch
)->builtin_double
;
1440 else if (reg_nr
>= FPP0_REGNUM
1441 && reg_nr
<= FPP_LAST_REGNUM
)
1442 return sh64_build_float_register_type (gdbarch
, 1);
1443 else if ((reg_nr
>= FV0_REGNUM
1444 && reg_nr
<= FV_LAST_REGNUM
)
1445 ||(reg_nr
>= FV0_C_REGNUM
1446 && reg_nr
<= FV_LAST_C_REGNUM
))
1447 return sh64_build_float_register_type (gdbarch
, 3);
1448 else if (reg_nr
== FPSCR_REGNUM
)
1449 return builtin_type (gdbarch
)->builtin_int
;
1450 else if (reg_nr
>= R0_C_REGNUM
1451 && reg_nr
< FP0_C_REGNUM
)
1452 return builtin_type (gdbarch
)->builtin_int
;
1454 return builtin_type (gdbarch
)->builtin_long_long
;
1458 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1459 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1461 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1463 /* It is a no-op. */
1464 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1468 if ((regnum
>= DR0_REGNUM
1469 && regnum
<= DR_LAST_REGNUM
)
1470 || (regnum
>= DR0_C_REGNUM
1471 && regnum
<= DR_LAST_C_REGNUM
))
1472 convert_typed_floating (from
, sh64_littlebyte_bigword_type (gdbarch
),
1475 error (_("sh64_register_convert_to_virtual "
1476 "called with non DR register number"));
1480 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1481 int regnum
, const void *from
, void *to
)
1483 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1485 /* It is a no-op. */
1486 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1490 if ((regnum
>= DR0_REGNUM
1491 && regnum
<= DR_LAST_REGNUM
)
1492 || (regnum
>= DR0_C_REGNUM
1493 && regnum
<= DR_LAST_C_REGNUM
))
1494 convert_typed_floating (from
, type
,
1495 to
, sh64_littlebyte_bigword_type (gdbarch
));
1497 error (_("sh64_register_convert_to_raw called "
1498 "with non DR register number"));
1501 /* Concatenate PORTIONS contiguous raw registers starting at
1502 BASE_REGNUM into BUFFER. */
1504 static enum register_status
1505 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1506 struct regcache
*regcache
,
1508 int base_regnum
, gdb_byte
*buffer
)
1512 for (portion
= 0; portion
< portions
; portion
++)
1514 enum register_status status
;
1517 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1518 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1519 if (status
!= REG_VALID
)
1526 static enum register_status
1527 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1528 int reg_nr
, gdb_byte
*buffer
)
1530 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1533 enum register_status status
;
1535 if (reg_nr
>= DR0_REGNUM
1536 && reg_nr
<= DR_LAST_REGNUM
)
1538 gdb_byte temp_buffer
[8];
1539 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1541 /* Build the value in the provided buffer. */
1542 /* DR regs are double precision registers obtained by
1543 concatenating 2 single precision floating point registers. */
1544 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1545 2, base_regnum
, temp_buffer
);
1546 if (status
== REG_VALID
)
1548 /* We must pay attention to the endianness. */
1549 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1550 register_type (gdbarch
, reg_nr
),
1551 temp_buffer
, buffer
);
1557 else if (reg_nr
>= FPP0_REGNUM
1558 && reg_nr
<= FPP_LAST_REGNUM
)
1560 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1562 /* Build the value in the provided buffer. */
1563 /* FPP regs are pairs of single precision registers obtained by
1564 concatenating 2 single precision floating point registers. */
1565 return pseudo_register_read_portions (gdbarch
, regcache
,
1566 2, base_regnum
, buffer
);
1569 else if (reg_nr
>= FV0_REGNUM
1570 && reg_nr
<= FV_LAST_REGNUM
)
1572 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1574 /* Build the value in the provided buffer. */
1575 /* FV regs are vectors of single precision registers obtained by
1576 concatenating 4 single precision floating point registers. */
1577 return pseudo_register_read_portions (gdbarch
, regcache
,
1578 4, base_regnum
, buffer
);
1581 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1582 else if (reg_nr
>= R0_C_REGNUM
1583 && reg_nr
<= T_C_REGNUM
)
1585 gdb_byte temp_buffer
[8];
1586 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1588 /* Build the value in the provided buffer. */
1589 status
= regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1590 if (status
!= REG_VALID
)
1592 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1595 temp_buffer
+ offset
, 4); /* get LOWER 32 bits only???? */
1599 else if (reg_nr
>= FP0_C_REGNUM
1600 && reg_nr
<= FP_LAST_C_REGNUM
)
1602 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1604 /* Build the value in the provided buffer. */
1605 /* Floating point registers map 1-1 to the media fp regs,
1606 they have the same size and endianness. */
1607 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1610 else if (reg_nr
>= DR0_C_REGNUM
1611 && reg_nr
<= DR_LAST_C_REGNUM
)
1613 gdb_byte temp_buffer
[8];
1614 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1616 /* DR_C regs are double precision registers obtained by
1617 concatenating 2 single precision floating point registers. */
1618 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1619 2, base_regnum
, temp_buffer
);
1620 if (status
== REG_VALID
)
1622 /* We must pay attention to the endianness. */
1623 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1624 register_type (gdbarch
, reg_nr
),
1625 temp_buffer
, buffer
);
1630 else if (reg_nr
>= FV0_C_REGNUM
1631 && reg_nr
<= FV_LAST_C_REGNUM
)
1633 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1635 /* Build the value in the provided buffer. */
1636 /* FV_C regs are vectors of single precision registers obtained by
1637 concatenating 4 single precision floating point registers. */
1638 return pseudo_register_read_portions (gdbarch
, regcache
,
1639 4, base_regnum
, buffer
);
1642 else if (reg_nr
== FPSCR_C_REGNUM
)
1644 int fpscr_base_regnum
;
1646 ULONGEST fpscr_value
;
1648 unsigned int fpscr_c_value
;
1649 unsigned int fpscr_c_part1_value
;
1650 unsigned int fpscr_c_part2_value
;
1652 fpscr_base_regnum
= FPSCR_REGNUM
;
1653 sr_base_regnum
= SR_REGNUM
;
1655 /* Build the value in the provided buffer. */
1656 /* FPSCR_C is a very weird register that contains sparse bits
1657 from the FPSCR and the SR architectural registers.
1664 2-17 Bit 2-18 of FPSCR
1665 18-20 Bits 12,13,14 of SR
1669 /* Get FPSCR as an int. */
1670 status
= regcache
->raw_read (fpscr_base_regnum
, &fpscr_value
);
1671 if (status
!= REG_VALID
)
1673 /* Get SR as an int. */
1674 status
= regcache
->raw_read (sr_base_regnum
, &sr_value
);
1675 if (status
!= REG_VALID
)
1677 /* Build the new value. */
1678 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1679 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1680 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1681 /* Store that in out buffer!!! */
1682 store_unsigned_integer (buffer
, 4, byte_order
, fpscr_c_value
);
1683 /* FIXME There is surely an endianness gotcha here. */
1688 else if (reg_nr
== FPUL_C_REGNUM
)
1690 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1692 /* FPUL_C register is floating point register 32,
1693 same size, same endianness. */
1694 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1697 gdb_assert_not_reached ("invalid pseudo register number");
1701 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1702 int reg_nr
, const gdb_byte
*buffer
)
1704 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1705 int base_regnum
, portion
;
1708 if (reg_nr
>= DR0_REGNUM
1709 && reg_nr
<= DR_LAST_REGNUM
)
1711 gdb_byte temp_buffer
[8];
1712 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1713 /* We must pay attention to the endianness. */
1714 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1716 buffer
, temp_buffer
);
1718 /* Write the real regs for which this one is an alias. */
1719 for (portion
= 0; portion
< 2; portion
++)
1720 regcache_raw_write (regcache
, base_regnum
+ portion
,
1722 + register_size (gdbarch
,
1723 base_regnum
) * portion
));
1726 else if (reg_nr
>= FPP0_REGNUM
1727 && reg_nr
<= FPP_LAST_REGNUM
)
1729 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1731 /* Write the real regs for which this one is an alias. */
1732 for (portion
= 0; portion
< 2; portion
++)
1733 regcache_raw_write (regcache
, base_regnum
+ portion
,
1734 (buffer
+ register_size (gdbarch
,
1735 base_regnum
) * portion
));
1738 else if (reg_nr
>= FV0_REGNUM
1739 && reg_nr
<= FV_LAST_REGNUM
)
1741 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1743 /* Write the real regs for which this one is an alias. */
1744 for (portion
= 0; portion
< 4; portion
++)
1745 regcache_raw_write (regcache
, base_regnum
+ portion
,
1746 (buffer
+ register_size (gdbarch
,
1747 base_regnum
) * portion
));
1750 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1751 register but only 4 bytes of it. */
1752 else if (reg_nr
>= R0_C_REGNUM
1753 && reg_nr
<= T_C_REGNUM
)
1755 gdb_byte temp_buffer
[8];
1756 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1757 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1758 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1762 /* Let's read the value of the base register into a temporary
1763 buffer, so that overwriting the last four bytes with the new
1764 value of the pseudo will leave the upper 4 bytes unchanged. */
1765 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1766 /* Write as an 8 byte quantity. */
1767 memcpy (temp_buffer
+ offset
, buffer
, 4);
1768 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1771 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1772 registers. Both are 4 bytes. */
1773 else if (reg_nr
>= FP0_C_REGNUM
1774 && reg_nr
<= FP_LAST_C_REGNUM
)
1776 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1777 regcache_raw_write (regcache
, base_regnum
, buffer
);
1780 else if (reg_nr
>= DR0_C_REGNUM
1781 && reg_nr
<= DR_LAST_C_REGNUM
)
1783 gdb_byte temp_buffer
[8];
1784 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1785 for (portion
= 0; portion
< 2; portion
++)
1787 /* We must pay attention to the endianness. */
1788 sh64_register_convert_to_raw (gdbarch
,
1789 register_type (gdbarch
, reg_nr
),
1791 buffer
, temp_buffer
);
1793 regcache_raw_write (regcache
, base_regnum
+ portion
,
1795 + register_size (gdbarch
,
1796 base_regnum
) * portion
));
1800 else if (reg_nr
>= FV0_C_REGNUM
1801 && reg_nr
<= FV_LAST_C_REGNUM
)
1803 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1805 for (portion
= 0; portion
< 4; portion
++)
1807 regcache_raw_write (regcache
, base_regnum
+ portion
,
1809 + register_size (gdbarch
,
1810 base_regnum
) * portion
));
1814 else if (reg_nr
== FPSCR_C_REGNUM
)
1816 int fpscr_base_regnum
;
1818 ULONGEST fpscr_value
;
1820 ULONGEST old_fpscr_value
;
1821 ULONGEST old_sr_value
;
1822 unsigned int fpscr_c_value
;
1823 unsigned int fpscr_mask
;
1824 unsigned int sr_mask
;
1826 fpscr_base_regnum
= FPSCR_REGNUM
;
1827 sr_base_regnum
= SR_REGNUM
;
1829 /* FPSCR_C is a very weird register that contains sparse bits
1830 from the FPSCR and the SR architectural registers.
1837 2-17 Bit 2-18 of FPSCR
1838 18-20 Bits 12,13,14 of SR
1842 /* Get value as an int. */
1843 fpscr_c_value
= extract_unsigned_integer (buffer
, 4, byte_order
);
1845 /* Build the new values. */
1846 fpscr_mask
= 0x0003fffd;
1847 sr_mask
= 0x001c0000;
1849 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1850 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1852 regcache
->raw_read (fpscr_base_regnum
, &old_fpscr_value
);
1853 old_fpscr_value
&= 0xfffc0002;
1854 fpscr_value
|= old_fpscr_value
;
1855 regcache
->raw_write (fpscr_base_regnum
, fpscr_value
);
1857 regcache
->raw_read (sr_base_regnum
, &old_sr_value
);
1858 old_sr_value
&= 0xffff8fff;
1859 sr_value
|= old_sr_value
;
1860 regcache
->raw_write (sr_base_regnum
, sr_value
);
1863 else if (reg_nr
== FPUL_C_REGNUM
)
1865 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1866 regcache_raw_write (regcache
, base_regnum
, buffer
);
1870 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1871 shmedia REGISTERS. */
1872 /* Control registers, compact mode. */
1874 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1877 switch (cr_c_regnum
)
1880 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1881 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1884 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1885 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1888 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1889 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1892 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1893 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1896 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1897 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1900 fprintf_filtered (file
, "t_c\t0x%08x\n",
1901 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1903 case FPSCR_C_REGNUM
:
1904 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1905 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1908 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1909 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1915 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1916 struct frame_info
*frame
, int regnum
)
1917 { /* Do values for FP (float) regs. */
1918 unsigned char *raw_buffer
;
1920 /* Allocate space for the float. */
1921 raw_buffer
= (unsigned char *)
1922 alloca (register_size (gdbarch
, gdbarch_fp0_regnum (gdbarch
)));
1924 /* Get the data in raw format. */
1925 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
1926 error (_("can't read register %d (%s)"),
1927 regnum
, gdbarch_register_name (gdbarch
, regnum
));
1929 /* Print the name and some spaces. */
1930 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
1931 print_spaces_filtered (15 - strlen (gdbarch_register_name
1932 (gdbarch
, regnum
)), file
);
1934 /* Print the value. */
1935 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
1936 std::string str
= target_float_to_string (raw_buffer
, flt_type
, "%-10.9g");
1937 fprintf_filtered (file
, "%s", str
.c_str ());
1939 /* Print the fp register as hex. */
1940 fprintf_filtered (file
, "\t(raw ");
1941 print_hex_chars (file
, raw_buffer
,
1942 register_size (gdbarch
, regnum
),
1943 gdbarch_byte_order (gdbarch
), true);
1944 fprintf_filtered (file
, ")");
1945 fprintf_filtered (file
, "\n");
1949 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1950 struct frame_info
*frame
, int regnum
)
1952 /* All the sh64-compact mode registers are pseudo registers. */
1954 if (regnum
< gdbarch_num_regs (gdbarch
)
1955 || regnum
>= gdbarch_num_regs (gdbarch
)
1956 + NUM_PSEUDO_REGS_SH_MEDIA
1957 + NUM_PSEUDO_REGS_SH_COMPACT
)
1958 internal_error (__FILE__
, __LINE__
,
1959 _("Invalid pseudo register number %d\n"), regnum
);
1961 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
1963 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
1964 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
1965 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1966 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1969 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
1971 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1972 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
1973 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1974 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1977 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
1979 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
1980 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1981 regnum
- FV0_REGNUM
,
1982 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1983 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1984 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1985 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1988 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
1990 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1991 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1992 regnum
- FV0_C_REGNUM
,
1993 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1994 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1995 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1996 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1999 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2001 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2002 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2003 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2004 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2007 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2009 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2010 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2011 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2013 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2014 /* This should work also for pseudoregs. */
2015 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2016 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2017 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2021 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2022 struct frame_info
*frame
, int regnum
)
2024 struct value_print_options opts
;
2027 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2028 print_spaces_filtered (15 - strlen (gdbarch_register_name
2029 (gdbarch
, regnum
)), file
);
2031 /* Get the data in raw format. */
2032 val
= get_frame_register_value (frame
, regnum
);
2033 if (value_optimized_out (val
) || !value_entirely_available (val
))
2035 fprintf_filtered (file
, "*value not available*\n");
2039 get_formatted_print_options (&opts
, 'x');
2041 val_print (register_type (gdbarch
, regnum
),
2043 file
, 0, val
, &opts
, current_language
);
2044 fprintf_filtered (file
, "\t");
2045 get_formatted_print_options (&opts
, 0);
2047 val_print (register_type (gdbarch
, regnum
),
2049 file
, 0, val
, &opts
, current_language
);
2050 fprintf_filtered (file
, "\n");
2054 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2055 struct frame_info
*frame
, int regnum
)
2057 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2058 + gdbarch_num_pseudo_regs (gdbarch
))
2059 internal_error (__FILE__
, __LINE__
,
2060 _("Invalid register number %d\n"), regnum
);
2062 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2064 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2065 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2067 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2070 else if (regnum
< gdbarch_num_regs (gdbarch
)
2071 + gdbarch_num_pseudo_regs (gdbarch
))
2072 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2076 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2077 struct frame_info
*frame
, int regnum
,
2080 if (regnum
!= -1) /* Do one specified register. */
2082 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2083 error (_("Not a valid register for the current processor type"));
2085 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2088 /* Do all (or most) registers. */
2091 while (regnum
< gdbarch_num_regs (gdbarch
))
2093 /* If the register name is empty, it is undefined for this
2094 processor, so don't display anything. */
2095 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2096 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2102 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2107 /* true for "INFO ALL-REGISTERS" command. */
2108 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2112 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2117 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2123 while (regnum
< gdbarch_num_regs (gdbarch
)
2124 + gdbarch_num_pseudo_regs (gdbarch
))
2126 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2133 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2134 struct ui_file
*file
,
2135 struct frame_info
*frame
, int regnum
,
2138 if (regnum
!= -1) /* Do one specified register. */
2140 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2141 error (_("Not a valid register for the current processor type"));
2143 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2144 error (_("Not a valid register for the current processor mode."));
2146 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2149 /* Do all compact registers. */
2151 regnum
= R0_C_REGNUM
;
2152 while (regnum
< gdbarch_num_regs (gdbarch
)
2153 + gdbarch_num_pseudo_regs (gdbarch
))
2155 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2162 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2163 struct frame_info
*frame
, int regnum
, int fpregs
)
2165 if (pc_is_isa32 (get_frame_pc (frame
)))
2166 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2168 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2171 static struct sh64_frame_cache
*
2172 sh64_alloc_frame_cache (void)
2174 struct sh64_frame_cache
*cache
;
2177 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2181 cache
->saved_sp
= 0;
2182 cache
->sp_offset
= 0;
2185 /* Frameless until proven otherwise. */
2188 /* Saved registers. We initialize these to -1 since zero is a valid
2189 offset (that's where fp is supposed to be stored). */
2190 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2192 cache
->saved_regs
[i
] = -1;
2198 static struct sh64_frame_cache
*
2199 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2201 struct gdbarch
*gdbarch
;
2202 struct sh64_frame_cache
*cache
;
2203 CORE_ADDR current_pc
;
2207 return (struct sh64_frame_cache
*) *this_cache
;
2209 gdbarch
= get_frame_arch (this_frame
);
2210 cache
= sh64_alloc_frame_cache ();
2211 *this_cache
= cache
;
2213 current_pc
= get_frame_pc (this_frame
);
2214 cache
->media_mode
= pc_is_isa32 (current_pc
);
2216 /* In principle, for normal frames, fp holds the frame pointer,
2217 which holds the base address for the current stack frame.
2218 However, for functions that don't need it, the frame pointer is
2219 optional. For these "frameless" functions the frame pointer is
2220 actually the frame pointer of the calling frame. */
2221 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2222 if (cache
->base
== 0)
2225 cache
->pc
= get_frame_func (this_frame
);
2227 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2229 if (!cache
->uses_fp
)
2231 /* We didn't find a valid frame, which means that CACHE->base
2232 currently holds the frame pointer for our calling frame. If
2233 we're at the start of a function, or somewhere half-way its
2234 prologue, the function's frame probably hasn't been fully
2235 setup yet. Try to reconstruct the base address for the stack
2236 frame by looking at the stack pointer. For truly "frameless"
2237 functions this might work too. */
2238 cache
->base
= get_frame_register_unsigned
2239 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2242 /* Now that we have the base address for the stack frame we can
2243 calculate the value of sp in the calling frame. */
2244 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2246 /* Adjust all the saved registers such that they contain addresses
2247 instead of offsets. */
2248 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2249 if (cache
->saved_regs
[i
] != -1)
2250 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2255 static struct value
*
2256 sh64_frame_prev_register (struct frame_info
*this_frame
,
2257 void **this_cache
, int regnum
)
2259 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2260 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2261 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2263 gdb_assert (regnum
>= 0);
2265 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2266 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2268 /* The PC of the previous frame is stored in the PR register of
2269 the current frame. Frob regnum so that we pull the value from
2270 the correct place. */
2271 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2274 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2276 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2277 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2280 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
],
2282 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2285 return frame_unwind_got_memory (this_frame
, regnum
,
2286 cache
->saved_regs
[regnum
]);
2289 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2293 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2294 struct frame_id
*this_id
)
2296 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2298 /* This marks the outermost frame. */
2299 if (cache
->base
== 0)
2302 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2305 static const struct frame_unwind sh64_frame_unwind
= {
2307 default_frame_unwind_stop_reason
,
2309 sh64_frame_prev_register
,
2311 default_frame_sniffer
2315 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2317 return frame_unwind_register_unsigned (next_frame
,
2318 gdbarch_sp_regnum (gdbarch
));
2322 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2324 return frame_unwind_register_unsigned (next_frame
,
2325 gdbarch_pc_regnum (gdbarch
));
2328 static struct frame_id
2329 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2331 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2332 gdbarch_sp_regnum (gdbarch
));
2333 return frame_id_build (sp
, get_frame_pc (this_frame
));
2337 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2339 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2344 static const struct frame_base sh64_frame_base
= {
2346 sh64_frame_base_address
,
2347 sh64_frame_base_address
,
2348 sh64_frame_base_address
2353 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2355 struct gdbarch
*gdbarch
;
2356 struct gdbarch_tdep
*tdep
;
2358 /* If there is already a candidate, use it. */
2359 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2361 return arches
->gdbarch
;
2363 /* None found, create a new architecture from the information
2365 tdep
= XCNEW (struct gdbarch_tdep
);
2366 gdbarch
= gdbarch_alloc (&info
, tdep
);
2368 /* Determine the ABI */
2369 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2371 /* If the ABI is the 64-bit one, it can only be sh-media. */
2372 tdep
->sh_abi
= SH_ABI_64
;
2373 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2374 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2378 /* If the ABI is the 32-bit one it could be either media or
2380 tdep
->sh_abi
= SH_ABI_32
;
2381 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2382 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2385 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2386 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2387 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2388 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2389 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2390 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2391 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2393 /* The number of real registers is the same whether we are in
2394 ISA16(compact) or ISA32(media). */
2395 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2396 set_gdbarch_sp_regnum (gdbarch
, 15);
2397 set_gdbarch_pc_regnum (gdbarch
, 64);
2398 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2399 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2400 + NUM_PSEUDO_REGS_SH_COMPACT
);
2402 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2403 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2405 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2406 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2408 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, sh64_breakpoint_kind_from_pc
);
2409 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, sh64_sw_breakpoint_from_kind
);
2410 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2412 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2414 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2415 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2417 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2419 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2421 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2422 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2423 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2424 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2425 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2427 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2429 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2430 sh64_elf_make_msymbol_special
);
2432 /* Hook in ABI-specific overrides, if they have been registered. */
2433 gdbarch_init_osabi (info
, gdbarch
);
2435 dwarf2_append_unwinders (gdbarch
);
2436 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);