1 # Copyright 2021-2024 Free Software Foundation, Inc.
3 # This program is free software; you can redistribute it and/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation; either version 3 of the License, or
6 # (at your option) any later version.
8 # This program is distributed in the hope that it will be useful,
9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with this program. If not, see <http://www.gnu.org/licenses/>.
16 # Test to see if gdb is properly single stepping over the
17 # displaced plxv instruction.
19 require {istarget powerpc*-*} allow_power_isa_3_1_tests
25 if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
30 gdb_test "set radix 0b10000"
31 gdb_test "set debug displaced"
37 gdb_test "set debug displaced on"
39 # Proc to extract the uint128 hex value from the output of
40 # a print vector statement.
41 proc get_vector_hexadecimal_valueof { exp default {test ""} } {
45 set test "get vector_hexadecimal valueof \"${exp}\""
47 gdb_test_multiple "print $${exp}.uint128" $test {
48 -re -wrap "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*" {
49 set val $expect_out(1,string)
52 -re -wrap ".*Illegal instruction.* $" {
53 fail "Illegal instruction on print."
60 # Proc to do a single-step, and ensure we gently handle
61 # an illegal instruction situation.
62 proc stepi_over_instruction { xyz } {
64 gdb_test_multiple "stepi" "${xyz} " {
65 -re -wrap ".*Illegal instruction.*" {
66 fail "Illegal instruction on single step."
75 set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
77 # set some breakpoints on the instructions below main().
78 gdb_test "disas /r main"
80 set bp2 *$check_pc+0d12
81 set bp3 *$check_pc+0d20
82 set bp4 *$check_pc+0d28
88 # single-step through the plxv instructions, and retrieve the
89 # register values as we proceed.
91 stepi_over_instruction "stepi over NOP"
92 stepi_over_instruction "stepi over lnia"
93 stepi_over_instruction "stepi over addi"
95 stepi_over_instruction "stepi over vs4 assignment"
96 set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"]
98 stepi_over_instruction "stepi over vs5 assignment"
99 set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"]
101 stepi_over_instruction "stepi over vs6 assignment"
102 set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"]
104 stepi_over_instruction "stepi over vs7 assignment"
105 set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"]
107 set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2
108 set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4
109 set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6
110 set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8
112 if [expr $check_vs4 != $vs4_expected] {
113 fail "unexpected value vs4; actual:$check_vs4 expected:$vs4_expected"
115 if [expr $check_vs5 != $vs5_expected ] {
116 fail "unexpected value vs5; actual:$check_vs5 expected:$vs5_expected"
118 if [expr $check_vs6 != $vs6_expected ] {
119 fail "unexpected value vs6; actual:$check_vs6 expected:$vs6_expected"
121 if [expr $check_vs7 != $vs7_expected ] {
122 fail "unexpected value vs7; actual:$check_vs7 expected:$vs7_expected"
125 gdb_test "info break"
126 gdb_test "info register vs4 vs5 vs6 vs7 "
127 gdb_test "disas main #2"