1 # Copyright 2015-2024 Free Software Foundation, Inc.
3 # This program is free software; you can redistribute it and/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation; either version 3 of the License, or
6 # (at your option) any later version.
8 # This program is distributed in the hope that it will be useful,
9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with this program. If not, see <http://www.gnu.org/licenses/>.
16 # Test vector register access for s390 platforms.
18 require {is_any_target s390-*-* s390x-*-*}
23 # Create a temporary directory, to take a core dump there later.
24 set coredir [standard_output_file ${testfile}.d]
25 remote_exec build "rm -rf $coredir"
26 remote_exec build "mkdir $coredir"
29 if { [prepare_for_testing "failed to prepare" $testfile $srcfile \
30 [list "additional_flags=-mzarch"]] } {
38 # Run to the first vector instruction and step it. If the inferior
39 # doesn't crash, we have vector support.
41 gdb_breakpoint "check_vx"
42 gdb_continue_to_breakpoint "first vector insn"
44 gdb_test_multiple "x/i \$pc" "get PC at vector insn" {
45 -re "(0x\\S+)\\s+\\S+\\s+vlr\\s+.*$gdb_prompt $" {
46 set before_pc $expect_out(1,string)
50 gdb_test_multiple "stepi" "check for vector support" {
51 -re "Program received signal SIGILL,.*\r\n$gdb_prompt $" {
52 unsupported "no vector support."
55 -re "\[0-9\]+.*\r\n$gdb_prompt $" {
56 pass "vector support available"
59 fail "no vector support (unknown error)"
64 # Has the PC advanced by the expected amount? The kernel may do
65 # something special for the first vector insn in the process.
68 gdb_test_multiple "x/i \$pc" "get PC after vector insn" {
69 -re "(0x\\S+)\\s+.*$gdb_prompt $" {
70 set after_pc $expect_out(1,string)
74 if [expr $before_pc + 6 != $after_pc] {
75 fail "stepping first vector insn"
78 # Lift the core file limit, if possible, and change into the temporary
81 if { $coredir != "" } {
82 gdb_test {print (int) setrlimit (4, &(unsigned long [2]){~0UL, ~0UL})} \
84 gdb_test "print (int) chdir (\"${coredir}\")" " = 0" "chdir"
87 # Initialize all vector registers with GDB "set" commands, using
88 # distinct values. Handle left and right halves separately, in
89 # pseudo-random order.
96 set a [expr ($a_high << 32) | $a_low]
97 set b [expr ($b_high << 32) | $b_low]
99 for {set j 0} {$j < 32} {incr j 1} {
100 set i [expr 17 * $j % 32]
102 "set \$v$i.v2_int64\[0\] = [expr $a * ($i + 1)]" \
104 set i [expr 19 * (31 - $j) % 32]
106 "set \$v$i.v2_int64\[1\] = [expr $b * (32 - $i)]" \
110 # Verify a vector register's union members.
112 gdb_test "info register v0 v31" \
113 "v4_float .* v2_double .* v16_int8 .* v8_int16 .* v4_int32 .* v2_int64 .* uint128\
114 .*v4_float .* v2_double .* v16_int8 .* v8_int16 .* v4_int32 .* v2_int64 .* uint128 .*"
116 # Let the inferior store all vector registers in a buffer, then dump
117 # the buffer and check it.
119 gdb_continue_to_breakpoint "store vrs"
120 set vregs [capture_command_output "x/64xg &save_area" ""]
123 foreach {- left right} [regexp -all -inline -line {^.*:\s+(\w+)\s+(\w+)} $vregs] {
124 if [expr $left != $a * ($i + 1) || $right != $b * (32 - $i)] {
125 fail "verify \$v$i after set"
128 # Check that the FP register was updated accordingly.
129 gdb_test "info register f$i" "raw ${left}.*"
135 fail "dump save area (bad output)"
138 # Let the inferior change all VRs according to a simple algorithm,
139 # then print all VRs and compare their values with our result of the
142 gdb_continue_to_breakpoint "change vrs"
143 set vregs [capture_command_output "info registers vector" ""]
145 # Format a 128-bit value, given individual 4-byte values, as hex.
146 # Suppress leading zeros.
147 proc hex128 {a_high a_low b_high b_low} {
148 set result [format "%x%08x%08x%08x" $a_high $a_low $b_high $b_low]
149 regsub -- "^0*" $result "" result
150 if { $result eq "" } { set result 0 }
155 foreach {- r i val} [regexp -all -inline -line \
156 {^(\D*)(\d+)\s+.*?uint128 = 0x([0-9a-f]+?)} $vregs] {
158 fail "info registers vector: bad line $j"
159 } elseif { $val ne [hex128 \
160 [expr $a_high * ($i + 1) * $a_high ] \
161 [expr $a_low * ($i + 1) * $a_low ] \
162 [expr $b_high * (32 - $i) * $b_high * 32] \
163 [expr $b_low * (32 - $i) * $b_low * 32] ] } {
170 fail "info registers vector"
173 if { $coredir == "" } {
179 gdb_test "signal SIGABRT" "Program terminated with signal SIGABRT, .*"
182 # Find the core file and rename it (avoid accumulating core files).
184 set cores [glob -nocomplain -directory $coredir *core*]
185 if {[llength $cores] != 1} {
186 untested "core file not found"
187 remote_exec build "rm -rf $coredir"
190 set destcore [standard_output_file ${testfile}.core]
191 remote_exec build "mv [file join $coredir [lindex $cores 0]] $destcore"
192 remote_exec build "rm -rf $coredir"
194 # Restart gdb and load the core file. Compare the VRs.
196 clean_restart ${testfile}
198 with_test_prefix "core" {
199 set core_loaded [gdb_core_cmd $destcore "load"]
200 if { $core_loaded != -1 } {
201 set vregs_from_core [capture_command_output "info registers vector" ""]
202 if { $vregs_from_core eq $vregs } {
203 pass "compare vector registers"
205 fail "vector registers mismatch"