1 /* Target-dependent code for the x86-64 for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "x86-64-tdep.h"
41 #include "i387-tdep.h"
43 /* Register information. */
45 struct x86_64_register_info
51 static struct x86_64_register_info x86_64_register_info
[] =
53 { "rax", &builtin_type_int64
},
54 { "rbx", &builtin_type_int64
},
55 { "rcx", &builtin_type_int64
},
56 { "rdx", &builtin_type_int64
},
57 { "rsi", &builtin_type_int64
},
58 { "rdi", &builtin_type_int64
},
59 { "rbp", &builtin_type_void_data_ptr
},
60 { "rsp", &builtin_type_void_data_ptr
},
62 /* %r8 is indeed register number 8. */
63 { "r8", &builtin_type_int64
},
64 { "r9", &builtin_type_int64
},
65 { "r10", &builtin_type_int64
},
66 { "r11", &builtin_type_int64
},
67 { "r12", &builtin_type_int64
},
68 { "r13", &builtin_type_int64
},
69 { "r14", &builtin_type_int64
},
70 { "r15", &builtin_type_int64
},
71 { "rip", &builtin_type_void_func_ptr
},
72 { "eflags", &builtin_type_int32
},
73 { "ds", &builtin_type_int32
},
74 { "es", &builtin_type_int32
},
75 { "fs", &builtin_type_int32
},
76 { "gs", &builtin_type_int32
},
78 /* %st0 is register number 22. */
79 { "st0", &builtin_type_i387_ext
},
80 { "st1", &builtin_type_i387_ext
},
81 { "st2", &builtin_type_i387_ext
},
82 { "st3", &builtin_type_i387_ext
},
83 { "st4", &builtin_type_i387_ext
},
84 { "st5", &builtin_type_i387_ext
},
85 { "st6", &builtin_type_i387_ext
},
86 { "st7", &builtin_type_i387_ext
},
87 { "fctrl", &builtin_type_int32
},
88 { "fstat", &builtin_type_int32
},
89 { "ftag", &builtin_type_int32
},
90 { "fiseg", &builtin_type_int32
},
91 { "fioff", &builtin_type_int32
},
92 { "foseg", &builtin_type_int32
},
93 { "fooff", &builtin_type_int32
},
94 { "fop", &builtin_type_int32
},
96 /* %xmm0 is register number 38. */
97 { "xmm0", &builtin_type_v4sf
},
98 { "xmm1", &builtin_type_v4sf
},
99 { "xmm2", &builtin_type_v4sf
},
100 { "xmm3", &builtin_type_v4sf
},
101 { "xmm4", &builtin_type_v4sf
},
102 { "xmm5", &builtin_type_v4sf
},
103 { "xmm6", &builtin_type_v4sf
},
104 { "xmm7", &builtin_type_v4sf
},
105 { "xmm8", &builtin_type_v4sf
},
106 { "xmm9", &builtin_type_v4sf
},
107 { "xmm10", &builtin_type_v4sf
},
108 { "xmm11", &builtin_type_v4sf
},
109 { "xmm12", &builtin_type_v4sf
},
110 { "xmm13", &builtin_type_v4sf
},
111 { "xmm14", &builtin_type_v4sf
},
112 { "xmm15", &builtin_type_v4sf
},
113 { "mxcsr", &builtin_type_int32
}
116 /* Total number of registers. */
117 #define X86_64_NUM_REGS \
118 (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
120 /* Return the name of register REGNUM. */
123 x86_64_register_name (int regnum
)
125 if (regnum
>= 0 && regnum
< X86_64_NUM_REGS
)
126 return x86_64_register_info
[regnum
].name
;
131 /* Return the GDB type object for the "standard" data type of data in
135 x86_64_register_type (struct gdbarch
*gdbarch
, int regnum
)
137 gdb_assert (regnum
>= 0 && regnum
< X86_64_NUM_REGS
);
139 return *x86_64_register_info
[regnum
].type
;
142 /* DWARF Register Number Mapping as defined in the System V psABI,
145 static int x86_64_dwarf_regmap
[] =
147 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
148 X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
, 2, 1,
149 4, X86_64_RDI_REGNUM
,
151 /* Frame Pointer Register RBP. */
154 /* Stack Pointer Register RSP. */
157 /* Extended Integer Registers 8 - 15. */
158 8, 9, 10, 11, 12, 13, 14, 15,
160 /* Return Address RA. Not mapped. */
163 /* SSE Registers 0 - 7. */
164 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
165 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
166 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
167 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
169 /* Extended SSE Registers 8 - 15. */
170 X86_64_XMM0_REGNUM
+ 8, X86_64_XMM0_REGNUM
+ 9,
171 X86_64_XMM0_REGNUM
+ 10, X86_64_XMM0_REGNUM
+ 11,
172 X86_64_XMM0_REGNUM
+ 12, X86_64_XMM0_REGNUM
+ 13,
173 X86_64_XMM0_REGNUM
+ 14, X86_64_XMM0_REGNUM
+ 15,
175 /* Floating Point Registers 0-7. */
176 X86_64_ST0_REGNUM
+ 0, X86_64_ST0_REGNUM
+ 1,
177 X86_64_ST0_REGNUM
+ 2, X86_64_ST0_REGNUM
+ 3,
178 X86_64_ST0_REGNUM
+ 4, X86_64_ST0_REGNUM
+ 5,
179 X86_64_ST0_REGNUM
+ 6, X86_64_ST0_REGNUM
+ 7
182 static const int x86_64_dwarf_regmap_len
=
183 (sizeof (x86_64_dwarf_regmap
) / sizeof (x86_64_dwarf_regmap
[0]));
185 /* Convert DWARF register number REG to the appropriate register
186 number used by GDB. */
189 x86_64_dwarf_reg_to_regnum (int reg
)
193 if (reg
>= 0 || reg
< x86_64_dwarf_regmap_len
)
194 regnum
= x86_64_dwarf_regmap
[reg
];
197 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
202 /* Return nonzero if a value of type TYPE stored in register REGNUM
203 needs any special handling. */
206 x86_64_convert_register_p (int regnum
, struct type
*type
)
208 return i386_fp_regnum_p (regnum
);
212 /* The returning of values is done according to the special algorithm.
213 Some types are returned in registers an some (big structures) in
214 memory. See the System V psABI for details. */
216 #define MAX_CLASSES 4
218 enum x86_64_reg_class
221 X86_64_INTEGER_CLASS
,
222 X86_64_INTEGERSI_CLASS
,
232 /* Return the union class of CLASS1 and CLASS2.
233 See the System V psABI for details. */
235 static enum x86_64_reg_class
236 merge_classes (enum x86_64_reg_class class1
, enum x86_64_reg_class class2
)
238 /* Rule (a): If both classes are equal, this is the resulting class. */
239 if (class1
== class2
)
242 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
243 is the other class. */
244 if (class1
== X86_64_NO_CLASS
)
246 if (class2
== X86_64_NO_CLASS
)
249 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
250 if (class1
== X86_64_MEMORY_CLASS
|| class2
== X86_64_MEMORY_CLASS
)
251 return X86_64_MEMORY_CLASS
;
253 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
254 if ((class1
== X86_64_INTEGERSI_CLASS
&& class2
== X86_64_SSESF_CLASS
)
255 || (class2
== X86_64_INTEGERSI_CLASS
&& class1
== X86_64_SSESF_CLASS
))
256 return X86_64_INTEGERSI_CLASS
;
257 if (class1
== X86_64_INTEGER_CLASS
|| class1
== X86_64_INTEGERSI_CLASS
258 || class2
== X86_64_INTEGER_CLASS
|| class2
== X86_64_INTEGERSI_CLASS
)
259 return X86_64_INTEGER_CLASS
;
261 /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
263 if (class1
== X86_64_X87_CLASS
|| class1
== X86_64_X87UP_CLASS
264 || class2
== X86_64_X87_CLASS
|| class2
== X86_64_X87UP_CLASS
)
265 return X86_64_MEMORY_CLASS
;
267 /* Rule (f): Otherwise class SSE is used. */
268 return X86_64_SSE_CLASS
;
271 /* Classify the argument type. CLASSES will be filled by the register
272 class used to pass each word of the operand. The number of words
273 is returned. In case the parameter should be passed in memory, 0
274 is returned. As a special case for zero sized containers,
275 classes[0] will be NO_CLASS and 1 is returned.
277 See the System V psABI for details. */
280 classify_argument (struct type
*type
,
281 enum x86_64_reg_class classes
[MAX_CLASSES
], int bit_offset
)
283 int bytes
= TYPE_LENGTH (type
);
284 int words
= (bytes
+ 8 - 1) / 8;
286 switch (TYPE_CODE (type
))
288 case TYPE_CODE_ARRAY
:
289 case TYPE_CODE_STRUCT
:
290 case TYPE_CODE_UNION
:
293 enum x86_64_reg_class subclasses
[MAX_CLASSES
];
295 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
299 for (i
= 0; i
< words
; i
++)
300 classes
[i
] = X86_64_NO_CLASS
;
302 /* Zero sized arrays or structures are NO_CLASS. We return 0
303 to signalize memory class, so handle it as special case. */
306 classes
[0] = X86_64_NO_CLASS
;
309 switch (TYPE_CODE (type
))
311 case TYPE_CODE_STRUCT
:
314 for (j
= 0; j
< TYPE_NFIELDS (type
); ++j
)
316 int num
= classify_argument (TYPE_FIELDS (type
)[j
].type
,
318 (TYPE_FIELDS (type
)[j
].loc
.
319 bitpos
+ bit_offset
) % 256);
322 for (i
= 0; i
< num
; i
++)
325 (TYPE_FIELDS (type
)[j
].loc
.bitpos
+
328 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
333 case TYPE_CODE_ARRAY
:
337 num
= classify_argument (TYPE_TARGET_TYPE (type
),
338 subclasses
, bit_offset
);
342 /* The partial classes are now full classes. */
343 if (subclasses
[0] == X86_64_SSESF_CLASS
&& bytes
!= 4)
344 subclasses
[0] = X86_64_SSE_CLASS
;
345 if (subclasses
[0] == X86_64_INTEGERSI_CLASS
&& bytes
!= 4)
346 subclasses
[0] = X86_64_INTEGER_CLASS
;
348 for (i
= 0; i
< words
; i
++)
349 classes
[i
] = subclasses
[i
% num
];
352 case TYPE_CODE_UNION
:
356 for (j
= 0; j
< TYPE_NFIELDS (type
); ++j
)
359 num
= classify_argument (TYPE_FIELDS (type
)[j
].type
,
360 subclasses
, bit_offset
);
363 for (i
= 0; i
< num
; i
++)
364 classes
[i
] = merge_classes (subclasses
[i
], classes
[i
]);
372 /* Final merger cleanup. */
373 for (i
= 0; i
< words
; i
++)
375 /* If one class is MEMORY, everything should be passed in
377 if (classes
[i
] == X86_64_MEMORY_CLASS
)
380 /* The X86_64_SSEUP_CLASS should be always preceeded by
382 if (classes
[i
] == X86_64_SSEUP_CLASS
383 && (i
== 0 || classes
[i
- 1] != X86_64_SSE_CLASS
))
384 classes
[i
] = X86_64_SSE_CLASS
;
386 /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */
387 if (classes
[i
] == X86_64_X87UP_CLASS
388 && (i
== 0 || classes
[i
- 1] != X86_64_X87_CLASS
))
389 classes
[i
] = X86_64_SSE_CLASS
;
398 if (!(bit_offset
% 64))
399 classes
[0] = X86_64_SSESF_CLASS
;
401 classes
[0] = X86_64_SSE_CLASS
;
404 classes
[0] = X86_64_SSEDF_CLASS
;
407 classes
[0] = X86_64_X87_CLASS
;
408 classes
[1] = X86_64_X87UP_CLASS
;
422 if (bytes
* 8 + bit_offset
<= 32)
423 classes
[0] = X86_64_INTEGERSI_CLASS
;
425 classes
[0] = X86_64_INTEGER_CLASS
;
428 classes
[0] = classes
[1] = X86_64_INTEGER_CLASS
;
435 default: /* Avoid warning. */
438 internal_error (__FILE__
, __LINE__
,
439 "classify_argument: unknown argument type");
442 /* Examine the argument and set *INT_NREGS and *SSE_NREGS to the
443 number of registers required based on the information passed in
444 CLASSES. Return 0 if parameter should be passed in memory. */
447 examine_argument (enum x86_64_reg_class classes
[MAX_CLASSES
],
448 int n
, int *int_nregs
, int *sse_nregs
)
454 for (n
--; n
>= 0; n
--)
457 case X86_64_INTEGER_CLASS
:
458 case X86_64_INTEGERSI_CLASS
:
461 case X86_64_SSE_CLASS
:
462 case X86_64_SSESF_CLASS
:
463 case X86_64_SSEDF_CLASS
:
466 case X86_64_NO_CLASS
:
467 case X86_64_SSEUP_CLASS
:
468 case X86_64_X87_CLASS
:
469 case X86_64_X87UP_CLASS
:
471 case X86_64_MEMORY_CLASS
:
472 internal_error (__FILE__
, __LINE__
,
473 "examine_argument: unexpected memory class");
482 x86_64_push_arguments (struct regcache
*regcache
, int nargs
,
483 struct value
**args
, CORE_ADDR sp
)
487 /* For varargs functions we have to pass the total number of SSE
488 registers used in %rax. So, let's count this number. */
489 int total_sse_args
= 0;
490 /* Once an SSE/int argument is passed on the stack, all subsequent
491 arguments are passed there. */
497 static int int_parameter_registers
[INT_REGS
] =
499 X86_64_RDI_REGNUM
, 4, /* %rdi, %rsi */
500 X86_64_RDX_REGNUM
, 2, /* %rdx, %rcx */
504 static int sse_parameter_registers
[SSE_REGS
] =
506 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
507 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
508 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
509 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
511 int stack_values_count
= 0;
513 stack_values
= alloca (nargs
* sizeof (int));
515 for (i
= 0; i
< nargs
; i
++)
517 enum x86_64_reg_class
class[MAX_CLASSES
];
518 int n
= classify_argument (args
[i
]->type
, class, 0);
523 !examine_argument (class, n
, &needed_intregs
, &needed_sseregs
))
525 stack_values
[stack_values_count
++] = i
;
532 if (intreg
/ 2 + needed_intregs
> INT_REGS
)
534 if (ssereg
/ 2 + needed_sseregs
> SSE_REGS
)
537 total_sse_args
+= needed_sseregs
;
539 for (j
= 0; j
< n
; j
++)
543 case X86_64_NO_CLASS
:
545 case X86_64_INTEGER_CLASS
:
547 stack_values
[stack_values_count
++] = i
;
550 regcache_cooked_write
551 (regcache
, int_parameter_registers
[(intreg
+ 1) / 2],
552 VALUE_CONTENTS_ALL (args
[i
]) + offset
);
557 case X86_64_INTEGERSI_CLASS
:
559 stack_values
[stack_values_count
++] = i
;
562 LONGEST val
= extract_signed_integer
563 (VALUE_CONTENTS_ALL (args
[i
]) + offset
, 4);
564 regcache_cooked_write_signed
565 (regcache
, int_parameter_registers
[intreg
/ 2], val
);
571 case X86_64_SSEDF_CLASS
:
572 case X86_64_SSESF_CLASS
:
573 case X86_64_SSE_CLASS
:
575 stack_values
[stack_values_count
++] = i
;
578 regcache_cooked_write
579 (regcache
, sse_parameter_registers
[(ssereg
+ 1) / 2],
580 VALUE_CONTENTS_ALL (args
[i
]) + offset
);
585 case X86_64_SSEUP_CLASS
:
587 stack_values
[stack_values_count
++] = i
;
590 regcache_cooked_write
591 (regcache
, sse_parameter_registers
[ssereg
/ 2],
592 VALUE_CONTENTS_ALL (args
[i
]) + offset
);
597 case X86_64_X87_CLASS
:
598 case X86_64_MEMORY_CLASS
:
599 stack_values
[stack_values_count
++] = i
;
601 case X86_64_X87UP_CLASS
:
604 internal_error (__FILE__
, __LINE__
,
605 "Unexpected argument class");
607 intreg
+= intreg
% 2;
608 ssereg
+= ssereg
% 2;
613 /* We have to make sure that the stack is 16-byte aligned after the
614 setup. Let's calculate size of arguments first, align stack and
615 then fill in the arguments. */
617 for (i
= 0; i
< stack_values_count
; i
++)
619 struct value
*arg
= args
[stack_values
[i
]];
620 int len
= TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg
));
621 total_sp
+= (len
+ 7) & ~7;
623 /* total_sp is now a multiple of 8, if it is not a multiple of 16,
624 change the stack pointer so that it will be afterwards correctly
629 /* Push any remaining arguments onto the stack. */
630 while (--stack_values_count
>= 0)
632 struct value
*arg
= args
[stack_values
[stack_values_count
]];
633 int len
= TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg
));
635 /* Make sure the stack is 8-byte-aligned. */
636 sp
-= (len
+ 7) & ~7;
637 write_memory (sp
, VALUE_CONTENTS_ALL (arg
), len
);
640 /* Write number of SSE type arguments to RAX to take care of varargs
642 store_unsigned_integer (buf
, 8, total_sse_args
);
643 regcache_cooked_write (regcache
, X86_64_RAX_REGNUM
, buf
);
648 /* Register classes as defined in the psABI. */
662 /* Return the union class of CLASS1 and CLASS2. See the psABI for
665 static enum amd64_reg_class
666 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
668 /* Rule (a): If both classes are equal, this is the resulting class. */
669 if (class1
== class2
)
672 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
673 is the other class. */
674 if (class1
== AMD64_NO_CLASS
)
676 if (class2
== AMD64_NO_CLASS
)
679 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
680 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
683 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
684 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
685 return AMD64_INTEGER
;
687 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
688 MEMORY is used as class. */
689 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
690 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
691 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
694 /* Rule (f): Otherwise class SSE is used. */
698 static void amd64_classify (struct type
*type
, enum amd64_reg_class
class[2]);
700 /* Classify TYPE according to the rules for aggregate (structures and
701 arrays) and union types, and store the result in CLASS. */
704 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
706 int len
= TYPE_LENGTH (type
);
708 /* 1. If the size of an object is larger than two eightbytes, or in
709 C++, is a non-POD structure or union type, or contains
710 unaligned fields, it has class memory. */
713 class[0] = class[1] = AMD64_MEMORY
;
717 /* 2. Both eightbytes get initialized to class NO_CLASS. */
718 class[0] = class[1] = AMD64_NO_CLASS
;
720 /* 3. Each field of an object is classified recursively so that
721 always two fields are considered. The resulting class is
722 calculated according to the classes of the fields in the
725 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
727 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
729 /* All fields in an array have the same type. */
730 amd64_classify (subtype
, class);
731 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
738 /* Structure or union. */
739 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
740 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
742 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
744 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
745 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
746 enum amd64_reg_class subclass
[2];
748 gdb_assert (pos
== 0 || pos
== 1);
750 amd64_classify (subtype
, subclass
);
751 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
753 class[1] = amd64_merge_classes (class[1], subclass
[1]);
757 /* 4. Then a post merger cleanup is done: */
759 /* Rule (a): If one of the classes is MEMORY, the whole argument is
761 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
762 class[0] = class[1] = AMD64_MEMORY
;
764 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
766 if (class[0] == AMD64_SSEUP
)
767 class[0] = AMD64_SSE
;
768 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
769 class[1] = AMD64_SSE
;
772 /* Classify TYPE, and store the result in CLASS. */
775 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
777 enum type_code code
= TYPE_CODE (type
);
778 int len
= TYPE_LENGTH (type
);
780 class[0] = class[1] = AMD64_NO_CLASS
;
782 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
783 long, long long, and pointers are in the INTEGER class. */
784 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
785 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
786 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
787 class[0] = AMD64_INTEGER
;
789 /* Arguments of types float, double and __m64 are in class SSE. */
790 else if (code
== TYPE_CODE_FLT
&& (len
== 4 || len
== 8))
792 class[0] = AMD64_SSE
;
794 /* Arguments of types __float128 and __m128 are split into two
795 halves. The least significant ones belong to class SSE, the most
796 significant one to class SSEUP. */
797 /* FIXME: __float128, __m128. */
799 /* The 64-bit mantissa of arguments of type long double belongs to
800 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
802 else if (code
== TYPE_CODE_FLT
&& len
== 16)
803 /* Class X87 and X87UP. */
804 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
807 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
808 || code
== TYPE_CODE_UNION
)
809 amd64_classify_aggregate (type
, class);
812 static enum return_value_convention
813 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
814 struct regcache
*regcache
,
815 void *readbuf
, const void *writebuf
)
817 enum amd64_reg_class
class[2];
818 int len
= TYPE_LENGTH (type
);
819 static int integer_regnum
[] = { X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
};
820 static int sse_regnum
[] = { X86_64_XMM0_REGNUM
, X86_64_XMM1_REGNUM
};
825 gdb_assert (!(readbuf
&& writebuf
));
827 /* 1. Classify the return type with the classification algorithm. */
828 amd64_classify (type
, class);
830 /* 2. If the type has class MEMORY, then the caller provides space
831 for the return value and passes the address of this storage in
832 %rdi as if it were the first argument to the function. In
833 effect, this address becomes a hidden first argument. */
834 if (class[0] == AMD64_MEMORY
)
835 return RETURN_VALUE_STRUCT_CONVENTION
;
837 gdb_assert (class[1] != AMD64_MEMORY
);
838 gdb_assert (len
<= 16);
840 for (i
= 0; len
> 0; i
++, len
-= 8)
848 /* 3. If the class is INTEGER, the next available register
849 of the sequence %rax, %rdx is used. */
850 regnum
= integer_regnum
[integer_reg
++];
854 /* 4. If the class is SSE, the next available SSE register
855 of the sequence %xmm0, %xmm1 is used. */
856 regnum
= sse_regnum
[sse_reg
++];
860 /* 5. If the class is SSEUP, the eightbyte is passed in the
861 upper half of the last used SSE register. */
862 gdb_assert (sse_reg
> 0);
863 regnum
= sse_regnum
[sse_reg
- 1];
868 /* 6. If the class is X87, the value is returned on the X87
869 stack in %st0 as 80-bit x87 number. */
870 regnum
= X86_64_ST0_REGNUM
;
872 i387_return_value (gdbarch
, regcache
);
876 /* 7. If the class is X87UP, the value is returned together
877 with the previous X87 value in %st0. */
878 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
879 regnum
= X86_64_ST0_REGNUM
;
888 gdb_assert (!"Unexpected register class.");
891 gdb_assert (regnum
!= -1);
894 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
895 (char *) readbuf
+ i
* 8);
897 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
898 (const char *) writebuf
+ i
* 8);
901 return RETURN_VALUE_REGISTER_CONVENTION
;
906 x86_64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
907 struct regcache
*regcache
, CORE_ADDR bp_addr
,
908 int nargs
, struct value
**args
, CORE_ADDR sp
,
909 int struct_return
, CORE_ADDR struct_addr
)
913 /* Pass arguments. */
914 sp
= x86_64_push_arguments (regcache
, nargs
, args
, sp
);
916 /* Pass "hidden" argument". */
919 store_unsigned_integer (buf
, 8, struct_addr
);
920 regcache_cooked_write (regcache
, X86_64_RDI_REGNUM
, buf
);
923 /* Store return address. */
925 store_unsigned_integer (buf
, 8, bp_addr
);
926 write_memory (sp
, buf
, 8);
928 /* Finally, update the stack pointer... */
929 store_unsigned_integer (buf
, 8, sp
);
930 regcache_cooked_write (regcache
, X86_64_RSP_REGNUM
, buf
);
932 /* ...and fake a frame pointer. */
933 regcache_cooked_write (regcache
, X86_64_RBP_REGNUM
, buf
);
939 /* The maximum number of saved registers. This should include %rip. */
940 #define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
942 struct x86_64_frame_cache
949 /* Saved registers. */
950 CORE_ADDR saved_regs
[X86_64_NUM_SAVED_REGS
];
953 /* Do we have a frame? */
957 /* Allocate and initialize a frame cache. */
959 static struct x86_64_frame_cache
*
960 x86_64_alloc_frame_cache (void)
962 struct x86_64_frame_cache
*cache
;
965 cache
= FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache
);
969 cache
->sp_offset
= -8;
972 /* Saved registers. We initialize these to -1 since zero is a valid
973 offset (that's where %rbp is supposed to be stored). */
974 for (i
= 0; i
< X86_64_NUM_SAVED_REGS
; i
++)
975 cache
->saved_regs
[i
] = -1;
978 /* Frameless until proven otherwise. */
979 cache
->frameless_p
= 1;
984 /* Do a limited analysis of the prologue at PC and update CACHE
985 accordingly. Bail out early if CURRENT_PC is reached. Return the
986 address where the analysis stopped.
988 We will handle only functions beginning with:
991 movq %rsp, %rbp 0x48 0x89 0xe5
993 Any function that doesn't start with this sequence will be assumed
994 to have no prologue and thus no valid frame pointer in %rbp. */
997 x86_64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
998 struct x86_64_frame_cache
*cache
)
1000 static unsigned char proto
[3] = { 0x48, 0x89, 0xe5 };
1001 unsigned char buf
[3];
1004 if (current_pc
<= pc
)
1007 op
= read_memory_unsigned_integer (pc
, 1);
1009 if (op
== 0x55) /* pushq %rbp */
1011 /* Take into account that we've executed the `pushq %rbp' that
1012 starts this instruction sequence. */
1013 cache
->saved_regs
[X86_64_RBP_REGNUM
] = 0;
1014 cache
->sp_offset
+= 8;
1016 /* If that's all, return now. */
1017 if (current_pc
<= pc
+ 1)
1020 /* Check for `movq %rsp, %rbp'. */
1021 read_memory (pc
+ 1, buf
, 3);
1022 if (memcmp (buf
, proto
, 3) != 0)
1025 /* OK, we actually have a frame. */
1026 cache
->frameless_p
= 0;
1033 /* Return PC of first real instruction. */
1036 x86_64_skip_prologue (CORE_ADDR start_pc
)
1038 struct x86_64_frame_cache cache
;
1041 pc
= x86_64_analyze_prologue (start_pc
, 0xffffffffffffffff, &cache
);
1042 if (cache
.frameless_p
)
1049 /* Normal frames. */
1051 static struct x86_64_frame_cache
*
1052 x86_64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1054 struct x86_64_frame_cache
*cache
;
1061 cache
= x86_64_alloc_frame_cache ();
1062 *this_cache
= cache
;
1064 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
1065 cache
->base
= extract_unsigned_integer (buf
, 8);
1066 if (cache
->base
== 0)
1069 /* For normal frames, %rip is stored at 8(%rbp). */
1070 cache
->saved_regs
[X86_64_RIP_REGNUM
] = 8;
1072 cache
->pc
= frame_func_unwind (next_frame
);
1074 x86_64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
1076 if (cache
->frameless_p
)
1078 /* We didn't find a valid frame, which means that CACHE->base
1079 currently holds the frame pointer for our calling frame. If
1080 we're at the start of a function, or somewhere half-way its
1081 prologue, the function's frame probably hasn't been fully
1082 setup yet. Try to reconstruct the base address for the stack
1083 frame by looking at the stack pointer. For truly "frameless"
1084 functions this might work too. */
1086 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
1087 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
1090 /* Now that we have the base address for the stack frame we can
1091 calculate the value of %rsp in the calling frame. */
1092 cache
->saved_sp
= cache
->base
+ 16;
1094 /* Adjust all the saved registers such that they contain addresses
1095 instead of offsets. */
1096 for (i
= 0; i
< X86_64_NUM_SAVED_REGS
; i
++)
1097 if (cache
->saved_regs
[i
] != -1)
1098 cache
->saved_regs
[i
] += cache
->base
;
1104 x86_64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1105 struct frame_id
*this_id
)
1107 struct x86_64_frame_cache
*cache
=
1108 x86_64_frame_cache (next_frame
, this_cache
);
1110 /* This marks the outermost frame. */
1111 if (cache
->base
== 0)
1114 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
1118 x86_64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1119 int regnum
, int *optimizedp
,
1120 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1121 int *realnump
, void *valuep
)
1123 struct x86_64_frame_cache
*cache
=
1124 x86_64_frame_cache (next_frame
, this_cache
);
1126 gdb_assert (regnum
>= 0);
1128 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
1136 /* Store the value. */
1137 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
1142 if (regnum
< X86_64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1145 *lvalp
= lval_memory
;
1146 *addrp
= cache
->saved_regs
[regnum
];
1150 /* Read the value in from memory. */
1151 read_memory (*addrp
, valuep
,
1152 register_size (current_gdbarch
, regnum
));
1157 frame_register_unwind (next_frame
, regnum
,
1158 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1161 static const struct frame_unwind x86_64_frame_unwind
=
1164 x86_64_frame_this_id
,
1165 x86_64_frame_prev_register
1168 static const struct frame_unwind
*
1169 x86_64_frame_sniffer (struct frame_info
*next_frame
)
1171 return &x86_64_frame_unwind
;
1175 /* Signal trampolines. */
1177 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1178 64-bit variants. This would require using identical frame caches
1179 on both platforms. */
1181 static struct x86_64_frame_cache
*
1182 x86_64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1184 struct x86_64_frame_cache
*cache
;
1185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1193 cache
= x86_64_alloc_frame_cache ();
1195 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
1196 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
1198 addr
= tdep
->sigcontext_addr (next_frame
);
1199 gdb_assert (tdep
->sc_reg_offset
);
1200 gdb_assert (tdep
->sc_num_regs
<= X86_64_NUM_SAVED_REGS
);
1201 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1202 if (tdep
->sc_reg_offset
[i
] != -1)
1203 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1205 *this_cache
= cache
;
1210 x86_64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
1211 void **this_cache
, struct frame_id
*this_id
)
1213 struct x86_64_frame_cache
*cache
=
1214 x86_64_sigtramp_frame_cache (next_frame
, this_cache
);
1216 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
1220 x86_64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
1222 int regnum
, int *optimizedp
,
1223 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1224 int *realnump
, void *valuep
)
1226 /* Make sure we've initialized the cache. */
1227 x86_64_sigtramp_frame_cache (next_frame
, this_cache
);
1229 x86_64_frame_prev_register (next_frame
, this_cache
, regnum
,
1230 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1233 static const struct frame_unwind x86_64_sigtramp_frame_unwind
=
1236 x86_64_sigtramp_frame_this_id
,
1237 x86_64_sigtramp_frame_prev_register
1240 static const struct frame_unwind
*
1241 x86_64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
1243 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1246 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
1247 if (PC_IN_SIGTRAMP (pc
, name
))
1249 gdb_assert (gdbarch_tdep (current_gdbarch
)->sigcontext_addr
);
1251 return &x86_64_sigtramp_frame_unwind
;
1259 x86_64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1261 struct x86_64_frame_cache
*cache
=
1262 x86_64_frame_cache (next_frame
, this_cache
);
1267 static const struct frame_base x86_64_frame_base
=
1269 &x86_64_frame_unwind
,
1270 x86_64_frame_base_address
,
1271 x86_64_frame_base_address
,
1272 x86_64_frame_base_address
1275 static struct frame_id
1276 x86_64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1281 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
1282 fp
= extract_unsigned_integer (buf
, 8);
1284 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
1287 /* 16 byte align the SP per frame requirements. */
1290 x86_64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1292 return sp
& -(CORE_ADDR
)16;
1296 /* Supply register REGNUM from the floating-point register set REGSET
1297 to register cache REGCACHE. If REGNUM is -1, do this for all
1298 registers in REGSET. */
1301 x86_64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
1302 int regnum
, const void *fpregs
, size_t len
)
1304 const struct gdbarch_tdep
*tdep
= regset
->descr
;
1306 gdb_assert (len
== tdep
->sizeof_fpregset
);
1307 x86_64_supply_fxsave (regcache
, regnum
, fpregs
);
1310 /* Return the appropriate register set for the core section identified
1311 by SECT_NAME and SECT_SIZE. */
1313 static const struct regset
*
1314 x86_64_regset_from_core_section (struct gdbarch
*gdbarch
,
1315 const char *sect_name
, size_t sect_size
)
1317 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1319 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1321 if (tdep
->fpregset
== NULL
)
1323 tdep
->fpregset
= XMALLOC (struct regset
);
1324 tdep
->fpregset
->descr
= tdep
;
1325 tdep
->fpregset
->supply_regset
= x86_64_supply_fpregset
;
1328 return tdep
->fpregset
;
1331 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1336 x86_64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1338 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1340 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1341 floating-point registers. */
1342 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1344 /* AMD64 has an FPU and 16 SSE registers. */
1345 tdep
->st0_regnum
= X86_64_ST0_REGNUM
;
1346 tdep
->num_xmm_regs
= 16;
1348 /* This is what all the fuss is about. */
1349 set_gdbarch_long_bit (gdbarch
, 64);
1350 set_gdbarch_long_long_bit (gdbarch
, 64);
1351 set_gdbarch_ptr_bit (gdbarch
, 64);
1353 /* In contrast to the i386, on the x86-64 a `long double' actually
1354 takes up 128 bits, even though it's still based on the i387
1355 extended floating-point format which has only 80 significant bits. */
1356 set_gdbarch_long_double_bit (gdbarch
, 128);
1358 set_gdbarch_num_regs (gdbarch
, X86_64_NUM_REGS
);
1359 set_gdbarch_register_name (gdbarch
, x86_64_register_name
);
1360 set_gdbarch_register_type (gdbarch
, x86_64_register_type
);
1362 /* Register numbers of various important registers. */
1363 set_gdbarch_sp_regnum (gdbarch
, X86_64_RSP_REGNUM
); /* %rsp */
1364 set_gdbarch_pc_regnum (gdbarch
, X86_64_RIP_REGNUM
); /* %rip */
1365 set_gdbarch_ps_regnum (gdbarch
, X86_64_EFLAGS_REGNUM
); /* %eflags */
1366 set_gdbarch_fp0_regnum (gdbarch
, X86_64_ST0_REGNUM
); /* %st(0) */
1368 /* The "default" register numbering scheme for the x86-64 is
1369 referred to as the "DWARF Register Number Mapping" in the System
1370 V psABI. The preferred debugging format for all known x86-64
1371 targets is actually DWARF2, and GCC doesn't seem to support DWARF
1372 (that is DWARF-1), but we provide the same mapping just in case.
1373 This mapping is also used for stabs, which GCC does support. */
1374 set_gdbarch_stab_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1375 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1376 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1378 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1379 be in use on any of the supported x86-64 targets. */
1381 /* Call dummy code. */
1382 set_gdbarch_push_dummy_call (gdbarch
, x86_64_push_dummy_call
);
1383 set_gdbarch_frame_align (gdbarch
, x86_64_frame_align
);
1384 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1386 set_gdbarch_convert_register_p (gdbarch
, x86_64_convert_register_p
);
1387 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1388 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1390 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
1391 /* Override, since this is handled by x86_64_extract_return_value. */
1392 set_gdbarch_extract_struct_value_address (gdbarch
, NULL
);
1394 set_gdbarch_skip_prologue (gdbarch
, x86_64_skip_prologue
);
1396 /* Avoid wiring in the MMX registers for now. */
1397 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1398 tdep
->mm0_regnum
= -1;
1400 set_gdbarch_unwind_dummy_id (gdbarch
, x86_64_unwind_dummy_id
);
1402 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1403 since all supported x86-64 targets are ELF, but that might change
1405 set_gdbarch_in_solib_call_trampoline (gdbarch
, in_plt_section
);
1407 frame_unwind_append_sniffer (gdbarch
, x86_64_sigtramp_frame_sniffer
);
1408 frame_unwind_append_sniffer (gdbarch
, x86_64_frame_sniffer
);
1409 frame_base_set_default (gdbarch
, &x86_64_frame_base
);
1411 /* If we have a register mapping, enable the generic core file support. */
1412 if (tdep
->gregset_reg_offset
)
1413 set_gdbarch_regset_from_core_section (gdbarch
,
1414 x86_64_regset_from_core_section
);
1418 #define I387_ST0_REGNUM X86_64_ST0_REGNUM
1420 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1421 sense that the instruction pointer and data pointer are simply
1422 64-bit offsets into the code segment and the data segment instead
1423 of a selector offset pair. The functions below store the upper 32
1424 bits of these pointers (instead of just the 16-bits of the segment
1427 /* Fill register REGNUM in REGCACHE with the appropriate
1428 floating-point or SSE register value from *FXSAVE. If REGNUM is
1429 -1, do this for all registers. This function masks off any of the
1430 reserved bits in *FXSAVE. */
1433 x86_64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1436 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1440 const char *regs
= fxsave
;
1442 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1443 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1444 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1445 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1449 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1450 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
1451 this for all registers. This function doesn't touch any of the
1452 reserved bits in *FXSAVE. */
1455 x86_64_fill_fxsave (char *fxsave
, int regnum
)
1457 i387_fill_fxsave (fxsave
, regnum
);
1459 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1460 regcache_collect (I387_FISEG_REGNUM
, fxsave
+ 12);
1461 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1462 regcache_collect (I387_FOSEG_REGNUM
, fxsave
+ 20);