1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
29 #include "reggroups.h"
32 #include "dwarf2/frame.h"
33 #include "frame-base.h"
34 #include "frame-unwind.h"
36 #include "arch-utils.h"
42 #include "xtensa-isa.h"
43 #include "xtensa-tdep.h"
44 #include "xtensa-config.h"
48 static unsigned int xtensa_debug_level
= 0;
50 #define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 gdb_printf (gdb_stdlog, "(warn ) " args)
54 #define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 gdb_printf (gdb_stdlog, "(info ) " args)
58 #define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 gdb_printf (gdb_stdlog, "(trace) " args)
62 #define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 gdb_printf (gdb_stdlog, "(verb ) " args)
67 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
68 #define SP_ALIGNMENT 16
71 /* On Windowed ABI, we use a6 through a11 for passing arguments
72 to a function called by GDB because CALL4 is used. */
73 #define ARGS_NUM_REGS 6
74 #define REGISTER_SIZE 4
77 /* Extract the call size from the return address or PS register. */
78 #define PS_CALLINC_SHIFT 16
79 #define PS_CALLINC_MASK 0x00030000
80 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
83 /* On TX, hardware can be configured without Exception Option.
84 There is no PS register in this case. Inside XT-GDB, let us treat
85 it as a virtual read-only register always holding the same value. */
88 /* ABI-independent macros. */
89 #define ARG_NOF(tdep) \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92 #define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
97 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
98 indicates that the instruction is an ENTRY instruction. */
100 #define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
104 #define XTENSA_ENTRY_LENGTH 3
106 /* windowing_enabled() returns true, if windowing is enabled.
107 WOE must be set to 1; EXCM to 0.
108 Note: We assume that EXCM is always 0 for XEA1. */
110 #define PS_WOE (1<<18)
111 #define PS_EXC (1<<4)
113 /* Big enough to hold the size of the largest register in bytes. */
114 #define XTENSA_MAX_REGISTER_SIZE 64
117 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
119 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
121 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
122 if (tdep
->call_abi
== CallAbiCall0Only
)
125 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
128 /* Convert a live A-register number to the corresponding AR-register
131 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
133 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
136 arreg
= a_regnum
- tdep
->a0_base
;
137 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
138 arreg
&= tdep
->num_aregs
- 1;
140 return arreg
+ tdep
->ar_base
;
143 /* Convert a live AR-register number to the corresponding A-register order
144 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
146 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
148 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
151 areg
= ar_regnum
- tdep
->ar_base
;
152 if (areg
< 0 || areg
>= tdep
->num_aregs
)
154 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
155 return (areg
> 15) ? -1 : areg
;
158 /* Read Xtensa register directly from the hardware. */
160 xtensa_read_register (int regnum
)
164 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
165 return (unsigned long) value
;
168 /* Write Xtensa register directly to the hardware. */
170 xtensa_write_register (int regnum
, ULONGEST value
)
172 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
175 /* Return the window size of the previous call to the function from which we
178 This function is used to extract the return value after a called function
179 has returned to the caller. On Xtensa, the register that holds the return
180 value (from the perspective of the caller) depends on what call
181 instruction was used. For now, we are assuming that the call instruction
182 precedes the current address, so we simply analyze the call instruction.
183 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
184 method to call the inferior function. */
187 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
194 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
196 /* Read the previous instruction (should be a call[x]{4|8|12}. */
197 read_memory (pc
-3, buf
, 3);
198 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
200 /* Decode call instruction:
202 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
203 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
205 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
206 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
208 if (byte_order
== BFD_ENDIAN_LITTLE
)
210 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
211 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
215 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
216 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
222 /* REGISTER INFORMATION */
224 /* Find register by name. */
226 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, const char *name
)
229 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
231 for (i
= 0; i
< gdbarch_num_cooked_regs (gdbarch
); i
++)
232 if (strcasecmp (tdep
->regmap
[i
].name
, name
) == 0)
238 /* Returns the name of a register. */
240 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
242 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
244 /* Return the name stored in the register map. */
245 return tdep
->regmap
[regnum
].name
;
248 /* Return the type of a register. Create a new type, if necessary. */
251 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
253 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
255 /* Return signed integer for ARx and Ax registers. */
256 if ((regnum
>= tdep
->ar_base
257 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
258 || (regnum
>= tdep
->a0_base
259 && regnum
< tdep
->a0_base
+ 16))
260 return builtin_type (gdbarch
)->builtin_int
;
262 if (regnum
== gdbarch_pc_regnum (gdbarch
)
263 || regnum
== tdep
->a0_base
+ 1)
264 return builtin_type (gdbarch
)->builtin_data_ptr
;
266 /* Return the stored type for all other registers. */
267 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
269 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
271 /* Set ctype for this register (only the first time). */
275 struct ctype_cache
*tp
;
276 int size
= reg
->byte_size
;
278 /* We always use the memory representation,
279 even if the register width is smaller. */
283 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
287 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
291 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
295 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
299 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
303 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
304 if (tp
->size
== size
)
309 std::string name
= string_printf ("int%d", size
* 8);
311 tp
= XNEW (struct ctype_cache
);
312 tp
->next
= tdep
->type_entries
;
313 tdep
->type_entries
= tp
;
315 type_allocator
alloc (gdbarch
);
317 = init_integer_type (alloc
, size
* 8, 1, name
.c_str ());
320 reg
->ctype
= tp
->virtual_type
;
326 internal_error (_("invalid register number %d"), regnum
);
331 /* Return the 'local' register number for stubs, dwarf2, etc.
332 The debugging information enumerates registers starting from 0 for A0
333 to n for An. So, we only have to add the base number for A0. */
336 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
339 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
341 if (regnum
>= 0 && regnum
< 16)
342 return tdep
->a0_base
+ regnum
;
344 for (i
= 0; i
< gdbarch_num_cooked_regs (gdbarch
); i
++)
345 if (regnum
== tdep
->regmap
[i
].target_number
)
352 /* Write the bits of a masked register to the various registers.
353 Only the masked areas of these registers are modified; the other
354 fields are untouched. The size of masked registers is always less
355 than or equal to 32 bits. */
358 xtensa_register_write_masked (struct regcache
*regcache
,
359 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
361 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
362 const xtensa_mask_t
*mask
= reg
->mask
;
364 int shift
= 0; /* Shift for next mask (mod 32). */
365 int start
, size
; /* Start bit and size of current mask. */
367 unsigned int *ptr
= value
;
368 unsigned int regval
, m
, mem
= 0;
370 int bytesize
= reg
->byte_size
;
371 int bitsize
= bytesize
* 8;
374 DEBUGTRACE ("xtensa_register_write_masked ()\n");
376 /* Copy the masked register to host byte-order. */
377 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
378 for (i
= 0; i
< bytesize
; i
++)
381 mem
|= (buffer
[bytesize
- i
- 1] << 24);
386 for (i
= 0; i
< bytesize
; i
++)
389 mem
|= (buffer
[i
] << 24);
394 /* We might have to shift the final value:
395 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
396 bytesize & 3 == x -> shift (4-x) * 8. */
398 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
402 /* Write the bits to the masked areas of the other registers. */
403 for (i
= 0; i
< mask
->count
; i
++)
405 start
= mask
->mask
[i
].bit_start
;
406 size
= mask
->mask
[i
].bit_size
;
407 regval
= mem
>> shift
;
409 if ((shift
+= size
) > bitsize
)
410 error (_("size of all masks is larger than the register"));
419 regval
|= mem
<< (size
- shift
);
422 /* Make sure we have a valid register. */
423 r
= mask
->mask
[i
].reg_num
;
424 if (r
>= 0 && size
> 0)
426 /* Don't overwrite the unmasked areas. */
428 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
429 m
= 0xffffffff >> (32 - size
) << start
;
431 regval
= (regval
& m
) | (old_val
& ~m
);
432 regcache_cooked_write_unsigned (regcache
, r
, regval
);
438 /* Read a tie state or mapped registers. Read the masked areas
439 of the registers and assemble them into a single value. */
441 static enum register_status
442 xtensa_register_read_masked (readable_regcache
*regcache
,
443 xtensa_register_t
*reg
, gdb_byte
*buffer
)
445 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
446 const xtensa_mask_t
*mask
= reg
->mask
;
451 unsigned int *ptr
= value
;
452 unsigned int regval
, mem
= 0;
454 int bytesize
= reg
->byte_size
;
455 int bitsize
= bytesize
* 8;
458 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
459 reg
->name
== 0 ? "" : reg
->name
);
461 /* Assemble the register from the masked areas of other registers. */
462 for (i
= 0; i
< mask
->count
; i
++)
464 int r
= mask
->mask
[i
].reg_num
;
467 enum register_status status
;
470 status
= regcache
->cooked_read (r
, &val
);
471 if (status
!= REG_VALID
)
473 regval
= (unsigned int) val
;
478 start
= mask
->mask
[i
].bit_start
;
479 size
= mask
->mask
[i
].bit_size
;
484 regval
&= (0xffffffff >> (32 - size
));
486 mem
|= regval
<< shift
;
488 if ((shift
+= size
) > bitsize
)
489 error (_("size of all masks is larger than the register"));
500 mem
= regval
>> (size
- shift
);
507 /* Copy value to target byte order. */
511 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
512 for (i
= 0; i
< bytesize
; i
++)
516 buffer
[bytesize
- i
- 1] = mem
& 0xff;
520 for (i
= 0; i
< bytesize
; i
++)
524 buffer
[i
] = mem
& 0xff;
532 /* Read pseudo registers. */
534 static enum register_status
535 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
536 readable_regcache
*regcache
,
540 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
541 regnum
, xtensa_register_name (gdbarch
, regnum
));
542 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
544 /* Read aliases a0..a15, if this is a Windowed ABI. */
545 if (tdep
->isa_use_windowed_registers
546 && (regnum
>= tdep
->a0_base
)
547 && (regnum
<= tdep
->a0_base
+ 15))
550 enum register_status status
;
552 status
= regcache
->raw_read (tdep
->wb_regnum
,
554 if (status
!= REG_VALID
)
556 regnum
= arreg_number (gdbarch
, regnum
, value
);
559 /* We can always read non-pseudo registers. */
560 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
561 return regcache
->raw_read (regnum
, buffer
);
563 /* We have to find out how to deal with privileged registers.
564 Let's treat them as pseudo-registers, but we cannot read/write them. */
566 else if (tdep
->call_abi
== CallAbiCall0Only
567 || regnum
< tdep
->a0_base
)
569 buffer
[0] = (gdb_byte
)0;
570 buffer
[1] = (gdb_byte
)0;
571 buffer
[2] = (gdb_byte
)0;
572 buffer
[3] = (gdb_byte
)0;
575 /* Pseudo registers. */
576 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
578 xtensa_register_t
*reg
= &tdep
->regmap
[regnum
];
579 xtensa_register_type_t type
= reg
->type
;
580 int flags
= tdep
->target_flags
;
582 /* We cannot read Unknown or Unmapped registers. */
583 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
585 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
587 warning (_("cannot read register %s"),
588 xtensa_register_name (gdbarch
, regnum
));
593 /* Some targets cannot read TIE register files. */
594 else if (type
== xtRegisterTypeTieRegfile
)
596 /* Use 'fetch' to get register? */
597 if (flags
& xtTargetFlagsUseFetchStore
)
599 warning (_("cannot read register"));
603 /* On some targets (esp. simulators), we can always read the reg. */
604 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
606 warning (_("cannot read register"));
611 /* We can always read mapped registers. */
612 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
613 return xtensa_register_read_masked (regcache
, reg
, buffer
);
615 /* Assume that we can read the register. */
616 return regcache
->raw_read (regnum
, buffer
);
619 internal_error (_("invalid register number %d"), regnum
);
623 /* Write pseudo registers. */
626 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
627 struct regcache
*regcache
,
629 const gdb_byte
*buffer
)
631 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
632 regnum
, xtensa_register_name (gdbarch
, regnum
));
633 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
635 /* Renumber register, if aliases a0..a15 on Windowed ABI. */
636 if (tdep
->isa_use_windowed_registers
637 && (regnum
>= tdep
->a0_base
)
638 && (regnum
<= tdep
->a0_base
+ 15))
641 regcache_raw_read_unsigned (regcache
,
642 tdep
->wb_regnum
, &value
);
643 regnum
= arreg_number (gdbarch
, regnum
, value
);
646 /* We can always write 'core' registers.
647 Note: We might have converted Ax->ARy. */
648 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
649 regcache
->raw_write (regnum
, buffer
);
651 /* We have to find out how to deal with privileged registers.
652 Let's treat them as pseudo-registers, but we cannot read/write them. */
654 else if (regnum
< tdep
->a0_base
)
658 /* Pseudo registers. */
659 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
661 xtensa_register_t
*reg
= &tdep
->regmap
[regnum
];
662 xtensa_register_type_t type
= reg
->type
;
663 int flags
= tdep
->target_flags
;
665 /* On most targets, we cannot write registers
666 of type "Unknown" or "Unmapped". */
667 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
669 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
671 warning (_("cannot write register %s"),
672 xtensa_register_name (gdbarch
, regnum
));
677 /* Some targets cannot read TIE register files. */
678 else if (type
== xtRegisterTypeTieRegfile
)
680 /* Use 'store' to get register? */
681 if (flags
& xtTargetFlagsUseFetchStore
)
683 warning (_("cannot write register"));
687 /* On some targets (esp. simulators), we can always write
689 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
691 warning (_("cannot write register"));
696 /* We can always write mapped registers. */
697 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
699 xtensa_register_write_masked (regcache
, reg
, buffer
);
703 /* Assume that we can write the register. */
704 regcache
->raw_write (regnum
, buffer
);
707 internal_error (_("invalid register number %d"), regnum
);
710 static const reggroup
*xtensa_ar_reggroup
;
711 static const reggroup
*xtensa_user_reggroup
;
712 static const reggroup
*xtensa_vectra_reggroup
;
713 static const reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
716 xtensa_init_reggroups (void)
720 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
721 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
722 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
724 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
725 xtensa_cp
[i
] = reggroup_new (xstrprintf ("cp%d", i
).release (),
730 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
732 /* Xtensa-specific groups. */
733 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
734 reggroup_add (gdbarch
, xtensa_user_reggroup
);
735 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
737 for (int i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
738 reggroup_add (gdbarch
, xtensa_cp
[i
]);
742 xtensa_coprocessor_register_group (const struct reggroup
*group
)
746 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
747 if (group
== xtensa_cp
[i
])
753 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
754 | XTENSA_REGISTER_FLAGS_WRITABLE \
755 | XTENSA_REGISTER_FLAGS_VOLATILE)
757 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
758 | XTENSA_REGISTER_FLAGS_WRITABLE)
761 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
763 const struct reggroup
*group
)
765 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
766 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
767 xtensa_register_type_t type
= reg
->type
;
768 xtensa_register_group_t rg
= reg
->group
;
771 if (group
== save_reggroup
)
772 /* Every single register should be included into the list of registers
773 to be watched for changes while using -data-list-changed-registers. */
776 /* First, skip registers that are not visible to this target
777 (unknown and unmapped registers when not using ISS). */
779 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
781 if (group
== all_reggroup
)
783 if (group
== xtensa_ar_reggroup
)
784 return rg
& xtRegisterGroupAddrReg
;
785 if (group
== xtensa_user_reggroup
)
786 return rg
& xtRegisterGroupUser
;
787 if (group
== float_reggroup
)
788 return rg
& xtRegisterGroupFloat
;
789 if (group
== general_reggroup
)
790 return rg
& xtRegisterGroupGeneral
;
791 if (group
== system_reggroup
)
792 return rg
& xtRegisterGroupState
;
793 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
794 return rg
& xtRegisterGroupVectra
;
795 if (group
== restore_reggroup
)
796 return (regnum
< gdbarch_num_regs (gdbarch
)
797 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
798 cp_number
= xtensa_coprocessor_register_group (group
);
800 return rg
& (xtRegisterGroupCP0
<< cp_number
);
806 /* Supply register REGNUM from the buffer specified by GREGS and LEN
807 in the general-purpose register set REGSET to register cache
808 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
811 xtensa_supply_gregset (const struct regset
*regset
,
817 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
818 struct gdbarch
*gdbarch
= rc
->arch ();
819 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
822 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
824 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
825 rc
->raw_supply (gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
826 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
827 rc
->raw_supply (gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
828 if (regnum
== tdep
->wb_regnum
|| regnum
== -1)
829 rc
->raw_supply (tdep
->wb_regnum
,
830 (char *) ®s
->windowbase
);
831 if (regnum
== tdep
->ws_regnum
|| regnum
== -1)
832 rc
->raw_supply (tdep
->ws_regnum
,
833 (char *) ®s
->windowstart
);
834 if (regnum
== tdep
->lbeg_regnum
|| regnum
== -1)
835 rc
->raw_supply (tdep
->lbeg_regnum
,
836 (char *) ®s
->lbeg
);
837 if (regnum
== tdep
->lend_regnum
|| regnum
== -1)
838 rc
->raw_supply (tdep
->lend_regnum
,
839 (char *) ®s
->lend
);
840 if (regnum
== tdep
->lcount_regnum
|| regnum
== -1)
841 rc
->raw_supply (tdep
->lcount_regnum
,
842 (char *) ®s
->lcount
);
843 if (regnum
== tdep
->sar_regnum
|| regnum
== -1)
844 rc
->raw_supply (tdep
->sar_regnum
,
845 (char *) ®s
->sar
);
846 if (regnum
>=tdep
->ar_base
847 && regnum
< tdep
->ar_base
850 (regnum
, (char *) ®s
->ar
[regnum
- tdep
->ar_base
]);
851 else if (regnum
== -1)
853 for (i
= 0; i
< tdep
->num_aregs
; ++i
)
854 rc
->raw_supply (tdep
->ar_base
+ i
,
855 (char *) ®s
->ar
[i
]);
860 /* Xtensa register set. */
866 xtensa_supply_gregset
870 /* Iterate over supported core file register note sections. */
873 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
874 iterate_over_regset_sections_cb
*cb
,
876 const struct regcache
*regcache
)
878 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
880 cb (".reg", sizeof (xtensa_elf_gregset_t
), sizeof (xtensa_elf_gregset_t
),
881 &xtensa_gregset
, NULL
, cb_data
);
885 /* Handling frames. */
887 /* Number of registers to save in case of Windowed ABI. */
888 #define XTENSA_NUM_SAVED_AREGS 12
890 /* Frame cache part for Windowed ABI. */
891 typedef struct xtensa_windowed_frame_cache
893 int wb
; /* WINDOWBASE of the previous frame. */
894 int callsize
; /* Call size of this frame. */
895 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
896 life windows only. If there is no bit set for the
897 window, that means it had been already spilled
898 because of window overflow. */
900 /* Addresses of spilled A-registers.
901 AREGS[i] == -1, if corresponding AR is alive. */
902 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
903 } xtensa_windowed_frame_cache_t
;
905 /* Call0 ABI Definitions. */
907 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
909 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
910 #define C0_SP 1 /* Register used as SP. */
911 #define C0_FP 15 /* Register used as FP. */
912 #define C0_RA 0 /* Register used as return address. */
913 #define C0_ARGS 2 /* Register used as first arg/retval. */
914 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
916 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
917 A-register where the current content of the reg came from (in terms
918 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
919 mean that the original content of the register was saved to the stack.
920 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
921 know where SP will end up until the entire prologue has been analyzed. */
923 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
924 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
925 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
927 extern xtensa_isa xtensa_default_isa
;
929 typedef struct xtensa_c0reg
931 int fr_reg
; /* original register from which register content
932 is derived, or C0_CONST, or C0_INEXP. */
933 int fr_ofs
; /* constant offset from reg, or immediate value. */
934 int to_stk
; /* offset from original SP to register (4-byte aligned),
935 or C0_NOSTK if register has not been saved. */
938 /* Frame cache part for Call0 ABI. */
939 typedef struct xtensa_call0_frame_cache
941 int c0_frmsz
; /* Stack frame size. */
942 int c0_hasfp
; /* Current frame uses frame pointer. */
943 int fp_regnum
; /* A-register used as FP. */
944 int c0_fp
; /* Actual value of frame pointer. */
945 int c0_fpalign
; /* Dynamic adjustment for the stack
946 pointer. It's an AND mask. Zero,
947 if alignment was not adjusted. */
948 int c0_old_sp
; /* In case of dynamic adjustment, it is
949 a register holding unaligned sp.
950 C0_INEXP, when undefined. */
951 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
952 stack offset. C0_NOSTK otherwise. */
954 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
955 } xtensa_call0_frame_cache_t
;
957 typedef struct xtensa_frame_cache
959 CORE_ADDR base
; /* Stack pointer of this frame. */
960 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
961 CORE_ADDR ra
; /* The raw return address of this frame. */
962 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
963 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
964 int call0
; /* It's a call0 framework (else windowed). */
967 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
968 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
970 } xtensa_frame_cache_t
;
973 static struct xtensa_frame_cache
*
974 xtensa_alloc_frame_cache (int windowed
)
976 xtensa_frame_cache_t
*cache
;
979 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
981 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
988 cache
->call0
= !windowed
;
991 cache
->c0
.c0_frmsz
= -1;
992 cache
->c0
.c0_hasfp
= 0;
993 cache
->c0
.fp_regnum
= -1;
994 cache
->c0
.c0_fp
= -1;
995 cache
->c0
.c0_fpalign
= 0;
996 cache
->c0
.c0_old_sp
= C0_INEXP
;
997 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
999 for (i
= 0; i
< C0_NREGS
; i
++)
1001 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1002 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1003 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1010 cache
->wd
.callsize
= -1;
1012 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1013 cache
->wd
.aregs
[i
] = -1;
1020 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1022 return address
& ~15;
1027 xtensa_unwind_pc (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1032 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1033 host_address_to_string (next_frame
.get ()));
1035 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1036 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1038 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1044 static struct frame_id
1045 xtensa_dummy_id (struct gdbarch
*gdbarch
, frame_info_ptr this_frame
)
1048 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1050 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1052 pc
= get_frame_pc (this_frame
);
1053 fp
= get_frame_register_unsigned
1054 (this_frame
, tdep
->a0_base
+ 1);
1056 /* Make dummy frame ID unique by adding a constant. */
1057 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1060 /* Returns true, if instruction to execute next is unique to Xtensa Window
1061 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1064 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1066 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1067 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1070 if (byte_order
== BFD_ENDIAN_BIG
)
1072 /* Check, if this is L32E or S32E. */
1073 code
= insn
& 0xf000ff00;
1074 if ((code
== 0x00009000) || (code
== 0x00009400))
1076 /* Check, if this is RFWU or RFWO. */
1077 code
= insn
& 0xffffff00;
1078 return ((code
== 0x00430000) || (code
== 0x00530000));
1082 /* Check, if this is L32E or S32E. */
1083 code
= insn
& 0x00ff000f;
1084 if ((code
== 0x090000) || (code
== 0x490000))
1086 /* Check, if this is RFWU or RFWO. */
1087 code
= insn
& 0x00ffffff;
1088 return ((code
== 0x00003400) || (code
== 0x00003500));
1092 /* Returns the best guess about which register is a frame pointer
1093 for the function containing CURRENT_PC. */
1095 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1096 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1099 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1101 #define RETURN_FP goto done
1103 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1104 unsigned int fp_regnum
= tdep
->a0_base
+ 1;
1105 CORE_ADDR start_addr
;
1107 xtensa_insnbuf ins
, slot
;
1108 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1109 CORE_ADDR ia
, bt
, ba
;
1111 int ilen
, islots
, is
;
1113 const char *opcname
;
1115 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1116 if (start_addr
== 0)
1119 isa
= xtensa_default_isa
;
1120 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1121 ins
= xtensa_insnbuf_alloc (isa
);
1122 slot
= xtensa_insnbuf_alloc (isa
);
1125 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1127 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1130 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1131 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1132 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1136 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1137 ifmt
= xtensa_format_decode (isa
, ins
);
1138 if (ifmt
== XTENSA_UNDEFINED
)
1140 ilen
= xtensa_format_length (isa
, ifmt
);
1141 if (ilen
== XTENSA_UNDEFINED
)
1143 islots
= xtensa_format_num_slots (isa
, ifmt
);
1144 if (islots
== XTENSA_UNDEFINED
)
1147 for (is
= 0; is
< islots
; ++is
)
1149 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1152 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1153 if (opc
== XTENSA_UNDEFINED
)
1156 opcname
= xtensa_opcode_name (isa
, opc
);
1158 if (strcasecmp (opcname
, "mov.n") == 0
1159 || strcasecmp (opcname
, "or") == 0)
1161 unsigned int register_operand
;
1163 /* Possible candidate for setting frame pointer
1164 from A1. This is what we are looking for. */
1166 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1167 is
, slot
, ®ister_operand
) != 0)
1169 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1171 if (register_operand
== 1) /* Mov{.n} FP A1. */
1173 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1174 ®ister_operand
) != 0)
1176 if (xtensa_operand_decode (isa
, opc
, 0,
1177 ®ister_operand
) != 0)
1181 = tdep
->a0_base
+ register_operand
;
1187 /* We have problems decoding the memory. */
1189 || strcasecmp (opcname
, "ill") == 0
1190 || strcasecmp (opcname
, "ill.n") == 0
1191 /* Hit planted breakpoint. */
1192 || strcasecmp (opcname
, "break") == 0
1193 || strcasecmp (opcname
, "break.n") == 0
1194 /* Flow control instructions finish prologue. */
1195 || xtensa_opcode_is_branch (isa
, opc
) > 0
1196 || xtensa_opcode_is_jump (isa
, opc
) > 0
1197 || xtensa_opcode_is_loop (isa
, opc
) > 0
1198 || xtensa_opcode_is_call (isa
, opc
) > 0
1199 || strcasecmp (opcname
, "simcall") == 0
1200 || strcasecmp (opcname
, "syscall") == 0)
1201 /* Can not continue analysis. */
1206 xtensa_insnbuf_free(isa
, slot
);
1207 xtensa_insnbuf_free(isa
, ins
);
1211 /* The key values to identify the frame using "cache" are
1213 cache->base = SP (or best guess about FP) of this frame;
1214 cache->pc = entry-PC (entry point of the frame function);
1215 cache->prev_sp = SP of the previous frame. */
1218 call0_frame_cache (frame_info_ptr this_frame
,
1219 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1222 xtensa_window_interrupt_frame_cache (frame_info_ptr this_frame
,
1223 xtensa_frame_cache_t
*cache
,
1226 static struct xtensa_frame_cache
*
1227 xtensa_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
1229 xtensa_frame_cache_t
*cache
;
1230 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1231 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1233 unsigned int fp_regnum
;
1234 int windowed
, ps_regnum
;
1237 return (struct xtensa_frame_cache
*) *this_cache
;
1239 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1240 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1241 ps
= (ps_regnum
>= 0
1242 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1244 windowed
= windowing_enabled (gdbarch
, ps
);
1246 /* Get pristine xtensa-frame. */
1247 cache
= xtensa_alloc_frame_cache (windowed
);
1248 *this_cache
= cache
;
1253 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1255 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1256 wb
= get_frame_register_unsigned (this_frame
,
1258 ws
= get_frame_register_unsigned (this_frame
,
1261 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1262 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1264 int callinc
= CALLINC (ps
);
1265 ra
= get_frame_register_unsigned
1266 (this_frame
, tdep
->a0_base
+ callinc
* 4);
1268 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1269 cache
->wd
.callsize
= 0;
1272 cache
->prev_sp
= get_frame_register_unsigned
1273 (this_frame
, tdep
->a0_base
+ 1);
1275 /* This only can be the outermost frame since we are
1276 just about to execute ENTRY. SP hasn't been set yet.
1277 We can assume any frame size, because it does not
1278 matter, and, let's fake frame base in cache. */
1279 cache
->base
= cache
->prev_sp
- 16;
1282 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1283 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1284 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1290 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1291 ra
= get_frame_register_unsigned (this_frame
,
1293 cache
->wd
.callsize
= WINSIZE (ra
);
1294 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1295 & (tdep
->num_aregs
/ 4 - 1);
1296 cache
->wd
.ws
= ws
& ~(1 << wb
);
1298 cache
->pc
= get_frame_func (this_frame
);
1299 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1300 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1301 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1304 if (cache
->wd
.ws
== 0)
1309 sp
= get_frame_register_unsigned
1310 (this_frame
, tdep
->a0_base
+ 1) - 16;
1312 for (i
= 0; i
< 4; i
++, sp
+= 4)
1314 cache
->wd
.aregs
[i
] = sp
;
1317 if (cache
->wd
.callsize
> 4)
1319 /* Set A4...A7/A11. */
1320 /* Get the SP of the frame previous to the previous one.
1321 To achieve this, we have to dereference SP twice. */
1322 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1323 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1324 sp
-= cache
->wd
.callsize
* 4;
1326 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1328 cache
->wd
.aregs
[i
] = sp
;
1333 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1334 /* If RA is equal to 0 this frame is an outermost frame. Leave
1335 cache->prev_sp unchanged marking the boundary of the frame stack. */
1337 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1339 /* Register window overflow already happened.
1340 We can read caller's SP from the proper spill location. */
1341 sp
= get_frame_register_unsigned
1342 (this_frame
, tdep
->a0_base
+ 1);
1343 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1347 /* Read caller's frame SP directly from the previous window. */
1348 int regnum
= arreg_number
1349 (gdbarch
, tdep
->a0_base
+ 1,
1352 cache
->prev_sp
= xtensa_read_register (regnum
);
1356 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1358 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1360 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1361 /* Everything was set already, including cache->base. */
1364 else /* Call0 framework. */
1366 call0_frame_cache (this_frame
, cache
, pc
);
1367 fp_regnum
= cache
->c0
.fp_regnum
;
1370 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1375 static int xtensa_session_once_reported
= 1;
1377 /* Report a problem with prologue analysis while doing backtracing.
1378 But, do it only once to avoid annoying repeated messages. */
1383 if (xtensa_session_once_reported
== 0)
1385 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1386 This message will not be repeated in this session.\n"));
1388 xtensa_session_once_reported
= 1;
1393 xtensa_frame_this_id (frame_info_ptr this_frame
,
1395 struct frame_id
*this_id
)
1397 struct xtensa_frame_cache
*cache
=
1398 xtensa_frame_cache (this_frame
, this_cache
);
1400 if (cache
->prev_sp
== 0)
1403 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1406 static struct value
*
1407 xtensa_frame_prev_register (frame_info_ptr this_frame
,
1411 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1412 struct xtensa_frame_cache
*cache
;
1413 ULONGEST saved_reg
= 0;
1415 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1417 if (*this_cache
== NULL
)
1418 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1419 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1421 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1422 saved_reg
= cache
->ra
;
1423 else if (regnum
== tdep
->a0_base
+ 1)
1424 saved_reg
= cache
->prev_sp
;
1425 else if (!cache
->call0
)
1427 if (regnum
== tdep
->ws_regnum
)
1428 saved_reg
= cache
->wd
.ws
;
1429 else if (regnum
== tdep
->wb_regnum
)
1430 saved_reg
= cache
->wd
.wb
;
1431 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1432 saved_reg
= cache
->ps
;
1440 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1442 if (!cache
->call0
) /* Windowed ABI. */
1444 /* Convert A-register numbers to AR-register numbers,
1445 if we deal with A-register. */
1446 if (regnum
>= tdep
->a0_base
1447 && regnum
<= tdep
->a0_base
+ 15)
1448 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1450 /* Check, if we deal with AR-register saved on stack. */
1451 if (regnum
>= tdep
->ar_base
1452 && regnum
<= (tdep
->ar_base
1455 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1458 && areg
< XTENSA_NUM_SAVED_AREGS
1459 && cache
->wd
.aregs
[areg
] != -1)
1460 return frame_unwind_got_memory (this_frame
, regnum
,
1461 cache
->wd
.aregs
[areg
]);
1464 else /* Call0 ABI. */
1466 int reg
= (regnum
>= tdep
->ar_base
1467 && regnum
<= (tdep
->ar_base
1469 ? regnum
- tdep
->ar_base
: regnum
;
1476 /* If register was saved in the prologue, retrieve it. */
1477 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1478 if (stkofs
!= C0_NOSTK
)
1480 /* Determine SP on entry based on FP. */
1481 spe
= cache
->c0
.c0_fp
1482 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1484 return frame_unwind_got_memory (this_frame
, regnum
,
1490 /* All other registers have been either saved to
1491 the stack or are still alive in the processor. */
1493 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1497 static const struct frame_unwind
1502 default_frame_unwind_stop_reason
,
1503 xtensa_frame_this_id
,
1504 xtensa_frame_prev_register
,
1506 default_frame_sniffer
1510 xtensa_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
1512 struct xtensa_frame_cache
*cache
=
1513 xtensa_frame_cache (this_frame
, this_cache
);
1518 static const struct frame_base
1522 xtensa_frame_base_address
,
1523 xtensa_frame_base_address
,
1524 xtensa_frame_base_address
1529 xtensa_extract_return_value (struct type
*type
,
1530 struct regcache
*regcache
,
1533 struct gdbarch
*gdbarch
= regcache
->arch ();
1534 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1535 int len
= type
->length ();
1540 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1542 gdb_assert(len
> 0);
1544 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1545 if (tdep
->call_abi
!= CallAbiCall0Only
)
1547 /* First, we have to find the caller window in the register file. */
1548 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1549 callsize
= extract_call_winsize (gdbarch
, pc
);
1551 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1552 if (len
> (callsize
> 8 ? 8 : 16))
1553 internal_error (_("cannot extract return value of %d bytes long"),
1556 /* Get the register offset of the return
1557 register (A2) in the caller window. */
1558 regcache_raw_read_unsigned
1559 (regcache
, tdep
->wb_regnum
, &wb
);
1560 areg
= arreg_number (gdbarch
,
1561 tdep
->a0_base
+ 2 + callsize
, wb
);
1565 /* No windowing hardware - Call0 ABI. */
1566 areg
= tdep
->a0_base
+ C0_ARGS
;
1569 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1571 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1574 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1577 regcache
->raw_read_part (areg
, offset
, len
, valbuf
);
1579 regcache
->raw_read (areg
, valbuf
);
1585 xtensa_store_return_value (struct type
*type
,
1586 struct regcache
*regcache
,
1589 struct gdbarch
*gdbarch
= regcache
->arch ();
1590 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1594 int len
= type
->length ();
1597 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1599 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1600 if (tdep
->call_abi
!= CallAbiCall0Only
)
1602 regcache_raw_read_unsigned
1603 (regcache
, tdep
->wb_regnum
, &wb
);
1604 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1605 callsize
= extract_call_winsize (gdbarch
, pc
);
1607 if (len
> (callsize
> 8 ? 8 : 16))
1608 internal_error (_("unimplemented for this length: %s"),
1609 pulongest (type
->length ()));
1610 areg
= arreg_number (gdbarch
,
1611 tdep
->a0_base
+ 2 + callsize
, wb
);
1613 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1614 callsize
, (int) wb
);
1618 areg
= tdep
->a0_base
+ C0_ARGS
;
1621 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1624 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1627 regcache
->raw_write_part (areg
, offset
, len
, valbuf
);
1629 regcache
->raw_write (areg
, valbuf
);
1634 static enum return_value_convention
1635 xtensa_return_value (struct gdbarch
*gdbarch
,
1636 struct value
*function
,
1637 struct type
*valtype
,
1638 struct regcache
*regcache
,
1640 const gdb_byte
*writebuf
)
1642 /* Structures up to 16 bytes are returned in registers. */
1644 int struct_return
= ((valtype
->code () == TYPE_CODE_STRUCT
1645 || valtype
->code () == TYPE_CODE_UNION
1646 || valtype
->code () == TYPE_CODE_ARRAY
)
1647 && valtype
->length () > 16);
1650 return RETURN_VALUE_STRUCT_CONVENTION
;
1652 DEBUGTRACE ("xtensa_return_value(...)\n");
1654 if (writebuf
!= NULL
)
1656 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1659 if (readbuf
!= NULL
)
1661 gdb_assert (!struct_return
);
1662 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1664 return RETURN_VALUE_REGISTER_CONVENTION
;
1671 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1672 struct value
*function
,
1673 struct regcache
*regcache
,
1676 struct value
**args
,
1678 function_call_return_method return_method
,
1679 CORE_ADDR struct_addr
)
1681 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1682 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1683 int size
, onstack_size
;
1684 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1686 struct argument_info
1688 const bfd_byte
*contents
;
1690 int onstack
; /* onstack == 0 => in reg */
1691 int align
; /* alignment */
1694 int offset
; /* stack offset if on stack. */
1695 int regno
; /* regno if in register. */
1699 struct argument_info
*arg_info
=
1700 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1704 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1706 if (xtensa_debug_level
> 3)
1708 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1709 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1710 "struct_addr=0x%x\n",
1711 (int) sp
, (int) return_method
, (int) struct_addr
);
1713 for (int i
= 0; i
< nargs
; i
++)
1715 struct value
*arg
= args
[i
];
1716 struct type
*arg_type
= check_typedef (arg
->type ());
1717 gdb_printf (gdb_stdlog
, "%2d: %s %3s ", i
,
1718 host_address_to_string (arg
),
1719 pulongest (arg_type
->length ()));
1720 switch (arg_type
->code ())
1723 gdb_printf (gdb_stdlog
, "int");
1725 case TYPE_CODE_STRUCT
:
1726 gdb_printf (gdb_stdlog
, "struct");
1729 gdb_printf (gdb_stdlog
, "%3d", arg_type
->code ());
1732 gdb_printf (gdb_stdlog
, " %s\n",
1733 host_address_to_string (arg
->contents ().data ()));
1737 /* First loop: collect information.
1738 Cast into type_long. (This shouldn't happen often for C because
1739 GDB already does this earlier.) It's possible that GDB could
1740 do it all the time but it's harmless to leave this code here. */
1745 if (return_method
== return_method_struct
)
1746 size
= REGISTER_SIZE
;
1748 for (int i
= 0; i
< nargs
; i
++)
1750 struct argument_info
*info
= &arg_info
[i
];
1751 struct value
*arg
= args
[i
];
1752 struct type
*arg_type
= check_typedef (arg
->type ());
1754 switch (arg_type
->code ())
1757 case TYPE_CODE_BOOL
:
1758 case TYPE_CODE_CHAR
:
1759 case TYPE_CODE_RANGE
:
1760 case TYPE_CODE_ENUM
:
1762 /* Cast argument to long if necessary as the mask does it too. */
1763 if (arg_type
->length ()
1764 < builtin_type (gdbarch
)->builtin_long
->length ())
1766 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1767 arg
= value_cast (arg_type
, arg
);
1769 /* Aligment is equal to the type length for the basic types. */
1770 info
->align
= arg_type
->length ();
1775 /* Align doubles correctly. */
1776 if (arg_type
->length ()
1777 == builtin_type (gdbarch
)->builtin_double
->length ())
1778 info
->align
= builtin_type (gdbarch
)->builtin_double
->length ();
1780 info
->align
= builtin_type (gdbarch
)->builtin_long
->length ();
1783 case TYPE_CODE_STRUCT
:
1785 info
->align
= builtin_type (gdbarch
)->builtin_long
->length ();
1788 info
->length
= arg_type
->length ();
1789 info
->contents
= arg
->contents ().data ();
1791 /* Align size and onstack_size. */
1792 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1793 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1795 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (tdep
))
1798 info
->u
.offset
= onstack_size
;
1799 onstack_size
+= info
->length
;
1804 info
->u
.regno
= ARG_1ST (tdep
) + size
/ REGISTER_SIZE
;
1806 size
+= info
->length
;
1809 /* Adjust the stack pointer and align it. */
1810 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1812 /* Simulate MOVSP, if Windowed ABI. */
1813 if ((tdep
->call_abi
!= CallAbiCall0Only
)
1816 read_memory (osp
- 16, buf
, 16);
1817 write_memory (sp
- 16, buf
, 16);
1820 /* Second Loop: Load arguments. */
1822 if (return_method
== return_method_struct
)
1824 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1825 regcache
->cooked_write (ARG_1ST (tdep
), buf
);
1828 for (int i
= 0; i
< nargs
; i
++)
1830 struct argument_info
*info
= &arg_info
[i
];
1834 int n
= info
->length
;
1835 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1837 /* Odd-sized structs are aligned to the lower side of a memory
1838 word in big-endian mode and require a shift. This only
1839 applies for structures smaller than one word. */
1841 if (n
< REGISTER_SIZE
1842 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1843 offset
+= (REGISTER_SIZE
- n
);
1845 write_memory (offset
, info
->contents
, info
->length
);
1850 int n
= info
->length
;
1851 const bfd_byte
*cp
= info
->contents
;
1852 int r
= info
->u
.regno
;
1854 /* Odd-sized structs are aligned to the lower side of registers in
1855 big-endian mode and require a shift. The odd-sized leftover will
1856 be at the end. Note that this is only true for structures smaller
1857 than REGISTER_SIZE; for larger odd-sized structures the excess
1858 will be left-aligned in the register on both endiannesses. */
1860 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1863 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1864 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1866 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1867 regcache
->cooked_write (r
, buf
);
1869 cp
+= REGISTER_SIZE
;
1876 regcache
->cooked_write (r
, cp
);
1878 cp
+= REGISTER_SIZE
;
1885 /* Set the return address of dummy frame to the dummy address.
1886 The return address for the current function (in A0) is
1887 saved in the dummy frame, so we can safely overwrite A0 here. */
1889 if (tdep
->call_abi
!= CallAbiCall0Only
)
1893 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1894 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1895 ps
= (unsigned long) val
& ~0x00030000;
1896 regcache_cooked_write_unsigned
1897 (regcache
, tdep
->a0_base
+ 4, ra
);
1898 regcache_cooked_write_unsigned (regcache
,
1899 gdbarch_ps_regnum (gdbarch
),
1902 /* All the registers have been saved. After executing
1903 dummy call, they all will be restored. So it's safe
1904 to modify WINDOWSTART register to make it look like there
1905 is only one register window corresponding to WINDOWEBASE. */
1907 regcache
->raw_read (tdep
->wb_regnum
, buf
);
1908 regcache_cooked_write_unsigned
1909 (regcache
, tdep
->ws_regnum
,
1910 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1914 /* Simulate CALL0: write RA into A0 register. */
1915 regcache_cooked_write_unsigned
1916 (regcache
, tdep
->a0_base
, bp_addr
);
1919 /* Set new stack pointer and return it. */
1920 regcache_cooked_write_unsigned (regcache
,
1921 tdep
->a0_base
+ 1, sp
);
1922 /* Make dummy frame ID unique by adding a constant. */
1923 return sp
+ SP_ALIGNMENT
;
1926 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1929 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1931 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
1933 if (tdep
->isa_use_density_instructions
)
1939 /* Return a breakpoint for the current location of PC. We always use
1940 the density version if we have density instructions (regardless of the
1941 current instruction at PC), and use regular instructions otherwise. */
1943 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1944 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1945 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1946 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1948 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1950 static const gdb_byte
*
1951 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1957 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1958 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1960 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1961 return big_breakpoint
;
1963 return little_breakpoint
;
1967 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1968 static unsigned char density_little_breakpoint
[]
1969 = DENSITY_LITTLE_BREAKPOINT
;
1971 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1972 return density_big_breakpoint
;
1974 return density_little_breakpoint
;
1978 /* Call0 ABI support routines. */
1980 /* Return true, if PC points to "ret" or "ret.n". */
1983 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
1985 #define RETURN_RET goto done
1987 xtensa_insnbuf ins
, slot
;
1988 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1989 CORE_ADDR ia
, bt
, ba
;
1991 int ilen
, islots
, is
;
1993 const char *opcname
;
1996 isa
= xtensa_default_isa
;
1997 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1998 ins
= xtensa_insnbuf_alloc (isa
);
1999 slot
= xtensa_insnbuf_alloc (isa
);
2002 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2004 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2007 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2008 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2009 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2013 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2014 ifmt
= xtensa_format_decode (isa
, ins
);
2015 if (ifmt
== XTENSA_UNDEFINED
)
2017 ilen
= xtensa_format_length (isa
, ifmt
);
2018 if (ilen
== XTENSA_UNDEFINED
)
2020 islots
= xtensa_format_num_slots (isa
, ifmt
);
2021 if (islots
== XTENSA_UNDEFINED
)
2024 for (is
= 0; is
< islots
; ++is
)
2026 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2029 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2030 if (opc
== XTENSA_UNDEFINED
)
2033 opcname
= xtensa_opcode_name (isa
, opc
);
2035 if ((strcasecmp (opcname
, "ret.n") == 0)
2036 || (strcasecmp (opcname
, "ret") == 0))
2044 xtensa_insnbuf_free(isa
, slot
);
2045 xtensa_insnbuf_free(isa
, ins
);
2049 /* Call0 opcode class. Opcodes are preclassified according to what they
2050 mean for Call0 prologue analysis, and their number of significant operands.
2051 The purpose of this is to simplify prologue analysis by separating
2052 instruction decoding (libisa) from the semantics of prologue analysis. */
2054 enum xtensa_insn_kind
2056 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2057 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2058 c0opc_flow
, /* Flow control insn. */
2059 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2060 c0opc_break
, /* Debugger software breakpoints. */
2061 c0opc_add
, /* Adding two registers. */
2062 c0opc_addi
, /* Adding a register and an immediate. */
2063 c0opc_and
, /* Bitwise "and"-ing two registers. */
2064 c0opc_sub
, /* Subtracting a register from a register. */
2065 c0opc_mov
, /* Moving a register to a register. */
2066 c0opc_movi
, /* Moving an immediate to a register. */
2067 c0opc_l32r
, /* Loading a literal. */
2068 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2069 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2070 c0opc_l32e
, /* L32E instruction. */
2071 c0opc_s32e
, /* S32E instruction. */
2072 c0opc_rfwo
, /* RFWO instruction. */
2073 c0opc_rfwu
, /* RFWU instruction. */
2074 c0opc_NrOf
/* Number of opcode classifications. */
2077 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2080 rwx_special_register (const char *opcname
)
2082 char ch
= *opcname
++;
2084 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2086 if (*opcname
++ != 's')
2088 if (*opcname
++ != 'r')
2090 if (*opcname
++ != '.')
2096 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2098 static xtensa_insn_kind
2099 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2101 const char *opcname
;
2102 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2104 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2106 /* Get opcode name and handle special classifications. */
2108 opcname
= xtensa_opcode_name (isa
, opc
);
2111 || strcasecmp (opcname
, "ill") == 0
2112 || strcasecmp (opcname
, "ill.n") == 0)
2113 opclass
= c0opc_illegal
;
2114 else if (strcasecmp (opcname
, "break") == 0
2115 || strcasecmp (opcname
, "break.n") == 0)
2116 opclass
= c0opc_break
;
2117 else if (strcasecmp (opcname
, "entry") == 0)
2118 opclass
= c0opc_entry
;
2119 else if (strcasecmp (opcname
, "rfwo") == 0)
2120 opclass
= c0opc_rfwo
;
2121 else if (strcasecmp (opcname
, "rfwu") == 0)
2122 opclass
= c0opc_rfwu
;
2123 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2124 || xtensa_opcode_is_jump (isa
, opc
) > 0
2125 || xtensa_opcode_is_loop (isa
, opc
) > 0
2126 || xtensa_opcode_is_call (isa
, opc
) > 0
2127 || strcasecmp (opcname
, "simcall") == 0
2128 || strcasecmp (opcname
, "syscall") == 0)
2129 opclass
= c0opc_flow
;
2131 /* Also, classify specific opcodes that need to be tracked. */
2132 else if (strcasecmp (opcname
, "add") == 0
2133 || strcasecmp (opcname
, "add.n") == 0)
2134 opclass
= c0opc_add
;
2135 else if (strcasecmp (opcname
, "and") == 0)
2136 opclass
= c0opc_and
;
2137 else if (strcasecmp (opcname
, "addi") == 0
2138 || strcasecmp (opcname
, "addi.n") == 0
2139 || strcasecmp (opcname
, "addmi") == 0)
2140 opclass
= c0opc_addi
;
2141 else if (strcasecmp (opcname
, "sub") == 0)
2142 opclass
= c0opc_sub
;
2143 else if (strcasecmp (opcname
, "mov.n") == 0
2144 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2145 opclass
= c0opc_mov
;
2146 else if (strcasecmp (opcname
, "movi") == 0
2147 || strcasecmp (opcname
, "movi.n") == 0)
2148 opclass
= c0opc_movi
;
2149 else if (strcasecmp (opcname
, "l32r") == 0)
2150 opclass
= c0opc_l32r
;
2151 else if (strcasecmp (opcname
, "s32i") == 0
2152 || strcasecmp (opcname
, "s32i.n") == 0)
2153 opclass
= c0opc_s32i
;
2154 else if (strcasecmp (opcname
, "l32e") == 0)
2155 opclass
= c0opc_l32e
;
2156 else if (strcasecmp (opcname
, "s32e") == 0)
2157 opclass
= c0opc_s32e
;
2158 else if (rwx_special_register (opcname
))
2159 opclass
= c0opc_rwxsr
;
2164 /* Tracks register movement/mutation for a given operation, which may
2165 be within a bundle. Updates the destination register tracking info
2166 accordingly. The pc is needed only for pc-relative load instructions
2167 (eg. l32r). The SP register number is needed to identify stores to
2168 the stack frame. Returns 0, if analysis was successful, non-zero
2172 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2173 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2174 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2176 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2177 unsigned litbase
, litaddr
, litval
;
2178 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
2183 /* 3 operands: dst, src, imm. */
2184 gdb_assert (nods
== 3);
2185 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2186 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2189 /* 3 operands: dst, src1, src2. */
2190 gdb_assert (nods
== 3);
2191 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2193 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2194 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2196 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2198 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2199 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2201 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2204 /* 3 operands: dst, src1, src2. */
2205 gdb_assert (nods
== 3);
2206 if (cache
->c0
.c0_fpalign
== 0)
2208 /* Handle dynamic stack alignment. */
2209 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2211 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2212 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2215 else if ((src
[odv
[0]].fr_reg
== spreg
)
2216 && (src
[odv
[2]].fr_reg
== spreg
))
2218 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2219 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2222 /* else fall through. */
2224 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2226 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2227 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2229 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2231 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2232 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2234 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2237 /* 3 operands: dst, src1, src2. */
2238 gdb_assert (nods
== 3);
2239 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2241 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2242 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2244 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2247 /* 2 operands: dst, src [, src]. */
2248 gdb_assert (nods
== 2);
2249 /* First, check if it's a special case of saving unaligned SP
2250 to a spare register in case of dynamic stack adjustment.
2251 But, only do it one time. The second time could be initializing
2252 frame pointer. We don't want to overwrite the first one. */
2253 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2254 cache
->c0
.c0_old_sp
= odv
[0];
2256 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2257 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2260 /* 2 operands: dst, imm. */
2261 gdb_assert (nods
== 2);
2262 dst
[odv
[0]].fr_reg
= C0_CONST
;
2263 dst
[odv
[0]].fr_ofs
= odv
[1];
2266 /* 2 operands: dst, literal offset. */
2267 gdb_assert (nods
== 2);
2268 /* litbase = xtensa_get_litbase (pc); can be also used. */
2269 litbase
= (tdep
->litbase_regnum
== -1)
2270 ? 0 : xtensa_read_register
2271 (tdep
->litbase_regnum
);
2272 litaddr
= litbase
& 1
2273 ? (litbase
& ~1) + (signed)odv
[1]
2274 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2275 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2276 dst
[odv
[0]].fr_reg
= C0_CONST
;
2277 dst
[odv
[0]].fr_ofs
= litval
;
2280 /* 3 operands: value, base, offset. */
2281 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2282 /* First, check if it's a spill for saved unaligned SP,
2283 when dynamic stack adjustment was applied to this frame. */
2284 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2285 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2286 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2287 cache
->c0
.c0_sp_ofs
= odv
[2];
2289 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2290 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2291 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2292 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2293 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2295 /* ISA encoding guarantees alignment. But, check it anyway. */
2296 gdb_assert ((odv
[2] & 3) == 0);
2297 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2300 /* If we end up inside Window Overflow / Underflow interrupt handler
2301 report an error because these handlers should have been handled
2302 already in a different way. */
2314 /* Analyze prologue of the function at start address to determine if it uses
2315 the Call0 ABI, and if so track register moves and linear modifications
2316 in the prologue up to the PC or just beyond the prologue, whichever is
2317 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2318 prologue. The prologue may overlap non-prologue instructions but is
2319 guaranteed to end by the first flow-control instruction (jump, branch,
2320 call or return). Since an optimized function may move information around
2321 and change the stack frame arbitrarily during the prologue, the information
2322 is guaranteed valid only at the point in the function indicated by the PC.
2323 May be used to skip the prologue or identify the ABI, w/o tracking.
2325 Returns: Address of first instruction after prologue, or PC (whichever
2326 is first), or 0, if decoding failed (in libisa).
2328 start Start address of function/prologue.
2329 pc Program counter to stop at. Use 0 to continue to end of prologue.
2330 If 0, avoids infinite run-on in corrupt code memory by bounding
2331 the scan to the end of the function if that can be determined.
2332 nregs Number of general registers to track.
2334 cache Xtensa frame cache.
2336 Note that these may produce useful results even if decoding fails
2337 because they begin with default assumptions that analysis may change. */
2340 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2341 CORE_ADDR start
, CORE_ADDR pc
,
2342 int nregs
, xtensa_frame_cache_t
*cache
)
2344 CORE_ADDR ia
; /* Current insn address in prologue. */
2345 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2346 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2347 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2348 xtensa_isa isa
; /* libisa ISA handle. */
2349 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2350 xtensa_format ifmt
; /* libisa instruction format. */
2351 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2352 xtensa_opcode opc
; /* Opcode in current slot. */
2353 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2354 int nods
; /* Opcode number of operands. */
2355 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2356 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2357 int j
; /* General loop counter. */
2358 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2359 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2360 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2362 struct symtab_and_line prologue_sal
;
2364 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2365 (int)start
, (int)pc
);
2367 /* Try to limit the scan to the end of the function if a non-zero pc
2368 arg was not supplied to avoid probing beyond the end of valid memory.
2369 If memory is full of garbage that classifies as c0opc_uninteresting.
2370 If this fails (eg. if no symbols) pc ends up 0 as it was.
2371 Initialize the Call0 frame and register tracking info.
2372 Assume it's Call0 until an 'entry' instruction is encountered.
2373 Assume we may be in the prologue until we hit a flow control instr. */
2379 /* Find out, if we have an information about the prologue from DWARF. */
2380 prologue_sal
= find_pc_line (start
, 0);
2381 if (prologue_sal
.line
!= 0) /* Found debug info. */
2382 body_pc
= prologue_sal
.end
;
2384 /* If we are going to analyze the prologue in general without knowing about
2385 the current PC, make the best assumption for the end of the prologue. */
2388 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2389 body_pc
= std::min (end_pc
, body_pc
);
2392 body_pc
= std::min (pc
, body_pc
);
2395 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2397 isa
= xtensa_default_isa
;
2398 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2399 ins
= xtensa_insnbuf_alloc (isa
);
2400 slot
= xtensa_insnbuf_alloc (isa
);
2402 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2404 /* (Re)fill instruction buffer from memory if necessary, but do not
2405 read memory beyond PC to be sure we stay within text section
2406 (this protection only works if a non-zero pc is supplied). */
2408 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2411 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2412 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2413 error (_("Unable to read target memory ..."));
2416 /* Decode format information. */
2418 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2419 ifmt
= xtensa_format_decode (isa
, ins
);
2420 if (ifmt
== XTENSA_UNDEFINED
)
2425 ilen
= xtensa_format_length (isa
, ifmt
);
2426 if (ilen
== XTENSA_UNDEFINED
)
2431 islots
= xtensa_format_num_slots (isa
, ifmt
);
2432 if (islots
== XTENSA_UNDEFINED
)
2438 /* Analyze a bundle or a single instruction, using a snapshot of
2439 the register tracking info as input for the entire bundle so that
2440 register changes do not take effect within this bundle. */
2442 for (j
= 0; j
< nregs
; ++j
)
2443 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2445 for (is
= 0; is
< islots
; ++is
)
2447 /* Decode a slot and classify the opcode. */
2449 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2453 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2454 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2456 if (opc
== XTENSA_UNDEFINED
)
2457 opclass
= c0opc_illegal
;
2459 opclass
= call0_classify_opcode (isa
, opc
);
2461 /* Decide whether to track this opcode, ignore it, or bail out. */
2470 case c0opc_uninteresting
:
2473 case c0opc_flow
: /* Flow control instructions stop analysis. */
2474 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2479 ia
+= ilen
; /* Skip over 'entry' insn. */
2486 /* Only expected opcodes should get this far. */
2488 /* Extract and decode the operands. */
2489 nods
= xtensa_opcode_num_operands (isa
, opc
);
2490 if (nods
== XTENSA_UNDEFINED
)
2496 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2498 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2503 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2508 /* Check operands to verify use of 'mov' assembler macro. */
2509 if (opclass
== c0opc_mov
&& nods
== 3)
2511 if (odv
[2] == odv
[1])
2514 if ((odv
[0] == 1) && (odv
[1] != 1))
2515 /* OR A1, An, An , where n != 1.
2516 This means we are inside epilogue already. */
2521 opclass
= c0opc_uninteresting
;
2526 /* Track register movement and modification for this operation. */
2527 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2528 opclass
, nods
, odv
, ia
, 1, cache
);
2534 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2535 (unsigned)ia
, fail
? "failed" : "succeeded");
2536 xtensa_insnbuf_free(isa
, slot
);
2537 xtensa_insnbuf_free(isa
, ins
);
2538 return fail
? XTENSA_ISA_BADPC
: ia
;
2541 /* Initialize frame cache for the current frame in CALL0 ABI. */
2544 call0_frame_cache (frame_info_ptr this_frame
,
2545 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2547 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2548 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2549 CORE_ADDR start_pc
; /* The beginning of the function. */
2550 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2551 CORE_ADDR sp
, fp
, ra
;
2552 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2553 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
2555 sp
= get_frame_register_unsigned
2556 (this_frame
, tdep
->a0_base
+ 1);
2557 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2559 /* Find the beginning of the prologue of the function containing the PC
2560 and analyze it up to the PC or the end of the prologue. */
2562 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2564 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2566 if (body_pc
== XTENSA_ISA_BADPC
)
2570 goto finish_frame_analysis
;
2574 /* Get the frame information and FP (if used) at the current PC.
2575 If PC is in the prologue, the prologue analysis is more reliable
2576 than DWARF info. We don't not know for sure, if PC is in the prologue,
2577 but we do know no calls have yet taken place, so we can almost
2578 certainly rely on the prologue analysis. */
2582 /* Prologue analysis was successful up to the PC.
2583 It includes the cases when PC == START_PC. */
2584 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2585 /* c0_hasfp == true means there is a frame pointer because
2586 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2587 was derived from SP. Otherwise, it would be C0_FP. */
2588 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2589 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2590 fp_regnum
+= tdep
->a0_base
;
2592 else /* No data from the prologue analysis. */
2595 fp_regnum
= tdep
->a0_base
+ C0_SP
;
2600 if (cache
->c0
.c0_fpalign
)
2602 /* This frame has a special prologue with a dynamic stack adjustment
2603 to force an alignment, which is bigger than standard 16 bytes. */
2605 CORE_ADDR unaligned_sp
;
2607 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2608 /* This can't be. Prologue code should be consistent.
2609 Unaligned stack pointer should be saved in a spare register. */
2613 goto finish_frame_analysis
;
2616 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2617 /* Saved unaligned value of SP is kept in a register. */
2618 unaligned_sp
= get_frame_register_unsigned
2619 (this_frame
, tdep
->a0_base
+ cache
->c0
.c0_old_sp
);
2621 /* Get the value from stack. */
2622 unaligned_sp
= (CORE_ADDR
)
2623 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2625 prev_sp
= unaligned_sp
+ c0_frmsz
;
2628 prev_sp
= fp
+ c0_frmsz
;
2630 /* Frame size from debug info or prologue tracking does not account for
2631 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2634 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2636 /* Update the stack frame size. */
2637 c0_frmsz
+= fp
- sp
;
2640 /* Get the return address (RA) from the stack if saved,
2641 or try to get it from a register. */
2643 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2644 if (to_stk
!= C0_NOSTK
)
2646 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2649 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2650 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2652 /* Special case for terminating backtrace at a function that wants to
2653 be seen as the outermost one. Such a function will clear it's RA (A0)
2654 register to 0 in the prologue instead of saving its original value. */
2659 /* RA was copied to another register or (before any function call) may
2660 still be in the original RA register. This is not always reliable:
2661 even in a leaf function, register tracking stops after prologue, and
2662 even in prologue, non-prologue instructions (not tracked) may overwrite
2663 RA or any register it was copied to. If likely in prologue or before
2664 any call, use retracking info and hope for the best (compiler should
2665 have saved RA in stack if not in a leaf function). If not in prologue,
2671 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2673 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2677 ra
= get_frame_register_unsigned
2679 tdep
->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2684 finish_frame_analysis
:
2685 cache
->pc
= start_pc
;
2687 /* RA == 0 marks the outermost frame. Do not go past it. */
2688 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2689 cache
->c0
.fp_regnum
= fp_regnum
;
2690 cache
->c0
.c0_frmsz
= c0_frmsz
;
2691 cache
->c0
.c0_hasfp
= c0_hasfp
;
2692 cache
->c0
.c0_fp
= fp
;
2695 static CORE_ADDR a0_saved
;
2696 static CORE_ADDR a7_saved
;
2697 static CORE_ADDR a11_saved
;
2698 static int a0_was_saved
;
2699 static int a7_was_saved
;
2700 static int a11_was_saved
;
2702 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2704 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2706 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
2707 int atreg
= arreg_number (gdbarch
, tdep
->a0_base
+ at
, wb
);
2708 int asreg
= arreg_number (gdbarch
, tdep
->a0_base
+ as
, wb
);
2709 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2710 unsigned int spilled_value
2711 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2713 if ((at
== 0) && !a0_was_saved
)
2715 a0_saved
= xtensa_read_register (atreg
);
2718 else if ((at
== 7) && !a7_was_saved
)
2720 a7_saved
= xtensa_read_register (atreg
);
2723 else if ((at
== 11) && !a11_was_saved
)
2725 a11_saved
= xtensa_read_register (atreg
);
2729 xtensa_write_register (atreg
, spilled_value
);
2732 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2734 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2736 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
2737 int atreg
= arreg_number (gdbarch
, tdep
->a0_base
+ at
, wb
);
2738 int asreg
= arreg_number (gdbarch
, tdep
->a0_base
+ as
, wb
);
2739 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2740 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2742 write_memory_unsigned_integer (addr
, 4,
2743 gdbarch_byte_order (gdbarch
),
2747 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2749 enum xtensa_exception_handler_t
2753 xtNoExceptionHandler
2756 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2757 Return type of Xtensa Window Interrupt Handler on success. */
2758 static xtensa_exception_handler_t
2759 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2762 xtensa_insnbuf ins
, slot
;
2763 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2764 CORE_ADDR ia
, bt
, ba
;
2766 int ilen
, islots
, is
;
2769 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2770 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
2772 uint32_t at
, as
, offset
;
2774 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2775 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2777 isa
= xtensa_default_isa
;
2778 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2779 ins
= xtensa_insnbuf_alloc (isa
);
2780 slot
= xtensa_insnbuf_alloc (isa
);
2789 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2791 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2794 bt
= (ba
+ XTENSA_ISA_BSZ
);
2795 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2796 return xtNoExceptionHandler
;
2798 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2799 ifmt
= xtensa_format_decode (isa
, ins
);
2800 if (ifmt
== XTENSA_UNDEFINED
)
2801 return xtNoExceptionHandler
;
2802 ilen
= xtensa_format_length (isa
, ifmt
);
2803 if (ilen
== XTENSA_UNDEFINED
)
2804 return xtNoExceptionHandler
;
2805 islots
= xtensa_format_num_slots (isa
, ifmt
);
2806 if (islots
== XTENSA_UNDEFINED
)
2807 return xtNoExceptionHandler
;
2808 for (is
= 0; is
< islots
; ++is
)
2810 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2811 return xtNoExceptionHandler
;
2812 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2813 if (opc
== XTENSA_UNDEFINED
)
2814 return xtNoExceptionHandler
;
2815 switch (call0_classify_opcode (isa
, opc
))
2821 /* We expect none of them here. */
2822 return xtNoExceptionHandler
;
2824 func
= execute_l32e
;
2827 func
= execute_s32e
;
2829 case c0opc_rfwo
: /* RFWO. */
2830 /* Here, we return from WindowOverflow handler and,
2831 if we stopped at the very beginning, which means
2832 A0 was saved, we have to restore it now. */
2835 int arreg
= arreg_number (gdbarch
,
2838 xtensa_write_register (arreg
, a0_saved
);
2840 return xtWindowOverflow
;
2841 case c0opc_rfwu
: /* RFWU. */
2842 /* Here, we return from WindowUnderflow handler.
2843 Let's see if either A7 or A11 has to be restored. */
2844 if (WindowUnderflow12
)
2848 int arreg
= arreg_number (gdbarch
,
2851 xtensa_write_register (arreg
, a11_saved
);
2854 else if (a7_was_saved
)
2856 int arreg
= arreg_number (gdbarch
,
2859 xtensa_write_register (arreg
, a7_saved
);
2861 return xtWindowUnderflow
;
2862 default: /* Simply skip this insns. */
2866 /* Decode arguments for L32E / S32E and simulate their execution. */
2867 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2868 return xtNoExceptionHandler
;
2869 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2870 return xtNoExceptionHandler
;
2871 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2872 return xtNoExceptionHandler
;
2873 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2874 return xtNoExceptionHandler
;
2875 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2876 return xtNoExceptionHandler
;
2877 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2878 return xtNoExceptionHandler
;
2879 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2880 return xtNoExceptionHandler
;
2882 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2887 return xtNoExceptionHandler
;
2890 /* Handle Window Overflow / Underflow exception frames. */
2893 xtensa_window_interrupt_frame_cache (frame_info_ptr this_frame
,
2894 xtensa_frame_cache_t
*cache
,
2897 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2898 CORE_ADDR ps
, wb
, ws
, ra
;
2899 int epc1_regnum
, i
, regnum
;
2900 xtensa_exception_handler_t eh_type
;
2901 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
2903 /* Read PS, WB, and WS from the hardware. Note that PS register
2904 must be present, if Windowed ABI is supported. */
2905 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2906 wb
= xtensa_read_register (tdep
->wb_regnum
);
2907 ws
= xtensa_read_register (tdep
->ws_regnum
);
2909 /* Execute all the remaining instructions from Window Interrupt Handler
2910 by simulating them on the remote protocol level. On return, set the
2911 type of Xtensa Window Interrupt Handler, or report an error. */
2912 eh_type
= execute_code (gdbarch
, pc
, wb
);
2913 if (eh_type
== xtNoExceptionHandler
)
2915 Unable to decode Xtensa Window Interrupt Handler's code."));
2917 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2918 cache
->call0
= 0; /* It's Windowed ABI. */
2920 /* All registers for the cached frame will be alive. */
2921 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2922 cache
->wd
.aregs
[i
] = -1;
2924 if (eh_type
== xtWindowOverflow
)
2925 cache
->wd
.ws
= ws
^ (1 << wb
);
2926 else /* eh_type == xtWindowUnderflow. */
2927 cache
->wd
.ws
= ws
| (1 << wb
);
2929 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2930 regnum
= arreg_number (gdbarch
, tdep
->a0_base
,
2932 ra
= xtensa_read_register (regnum
);
2933 cache
->wd
.callsize
= WINSIZE (ra
);
2934 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2935 /* Set regnum to a frame pointer of the frame being cached. */
2936 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2937 regnum
= arreg_number (gdbarch
,
2938 tdep
->a0_base
+ regnum
,
2940 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2942 /* Read PC of interrupted function from EPC1 register. */
2943 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2944 if (epc1_regnum
< 0)
2945 error(_("Unable to read Xtensa register EPC1"));
2946 cache
->ra
= xtensa_read_register (epc1_regnum
);
2947 cache
->pc
= get_frame_func (this_frame
);
2951 /* Skip function prologue.
2953 Return the pc of the first instruction after prologue. GDB calls this to
2954 find the address of the first line of the function or (if there is no line
2955 number information) to skip the prologue for planting breakpoints on
2956 function entries. Use debug info (if present) or prologue analysis to skip
2957 the prologue to achieve reliable debugging behavior. For windowed ABI,
2958 only the 'entry' instruction is skipped. It is not strictly necessary to
2959 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2960 backtrace at any point in the prologue, however certain potential hazards
2961 are avoided and a more "normal" debugging experience is ensured by
2962 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2963 For example, if we don't skip the prologue:
2964 - Some args may not yet have been saved to the stack where the debug
2965 info expects to find them (true anyway when only 'entry' is skipped);
2966 - Software breakpoints ('break' instrs) may not have been unplanted
2967 when the prologue analysis is done on initializing the frame cache,
2968 and breaks in the prologue will throw off the analysis.
2970 If we have debug info ( line-number info, in particular ) we simply skip
2971 the code associated with the first function line effectively skipping
2972 the prologue code. It works even in cases like
2975 { int local_var = 1;
2979 because, for this source code, both Xtensa compilers will generate two
2980 separate entries ( with the same line number ) in dwarf line-number
2981 section to make sure there is a boundary between the prologue code and
2982 the rest of the function.
2984 If there is no debug info, we need to analyze the code. */
2986 /* #define DONT_SKIP_PROLOGUE */
2989 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2991 struct symtab_and_line prologue_sal
;
2994 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
2996 #if DONT_SKIP_PROLOGUE
3000 /* Try to find first body line from debug info. */
3002 prologue_sal
= find_pc_line (start_pc
, 0);
3003 if (prologue_sal
.line
!= 0) /* Found debug info. */
3005 /* In Call0, it is possible to have a function with only one instruction
3006 ('ret') resulting from a one-line optimized function that does nothing.
3007 In that case, prologue_sal.end may actually point to the start of the
3008 next function in the text section, causing a breakpoint to be set at
3009 the wrong place. Check, if the end address is within a different
3010 function, and if so return the start PC. We know we have symbol
3015 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
3016 if ((tdep
->call_abi
== CallAbiCall0Only
)
3017 && call0_ret (start_pc
, prologue_sal
.end
))
3020 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3021 if (end_func
!= start_pc
)
3024 return prologue_sal
.end
;
3027 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3028 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3029 xtensa_alloc_frame_cache (0));
3030 return body_pc
!= 0 ? body_pc
: start_pc
;
3033 /* Verify the current configuration. */
3035 xtensa_verify_config (struct gdbarch
*gdbarch
)
3037 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
3040 /* Verify that we got a reasonable number of AREGS. */
3041 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3043 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3046 /* Verify that certain registers exist. */
3048 if (tdep
->pc_regnum
== -1)
3049 log
.printf (_("\n\tpc_regnum: No PC register"));
3050 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3051 log
.printf (_("\n\tps_regnum: No PS register"));
3053 if (tdep
->isa_use_windowed_registers
)
3055 if (tdep
->wb_regnum
== -1)
3056 log
.printf (_("\n\twb_regnum: No WB register"));
3057 if (tdep
->ws_regnum
== -1)
3058 log
.printf (_("\n\tws_regnum: No WS register"));
3059 if (tdep
->ar_base
== -1)
3060 log
.printf (_("\n\tar_base: No AR registers"));
3063 if (tdep
->a0_base
== -1)
3064 log
.printf (_("\n\ta0_base: No Ax registers"));
3067 internal_error (_("the following are invalid: %s"), log
.c_str ());
3071 /* Derive specific register numbers from the array of registers. */
3074 xtensa_derive_tdep (xtensa_gdbarch_tdep
*tdep
)
3076 xtensa_register_t
* rmap
;
3077 int n
, max_size
= 4;
3080 tdep
->num_nopriv_regs
= 0;
3082 /* Special registers 0..255 (core). */
3083 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3084 /* User registers 0..255. */
3085 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3087 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3089 if (rmap
->target_number
== 0x0020)
3090 tdep
->pc_regnum
= n
;
3091 else if (rmap
->target_number
== 0x0100)
3093 else if (rmap
->target_number
== 0x0000)
3095 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3096 tdep
->wb_regnum
= n
;
3097 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3098 tdep
->ws_regnum
= n
;
3099 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3100 tdep
->debugcause_regnum
= n
;
3101 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3102 tdep
->exccause_regnum
= n
;
3103 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3104 tdep
->excvaddr_regnum
= n
;
3105 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3106 tdep
->lbeg_regnum
= n
;
3107 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3108 tdep
->lend_regnum
= n
;
3109 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3110 tdep
->lcount_regnum
= n
;
3111 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3112 tdep
->sar_regnum
= n
;
3113 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3114 tdep
->litbase_regnum
= n
;
3115 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3116 tdep
->ps_regnum
= n
;
3117 else if (rmap
->target_number
== XTENSA_DBREGN_UREG(231))
3118 tdep
->threadptr_regnum
= n
;
3120 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3121 tdep
->interrupt_regnum
= n
;
3122 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3123 tdep
->interrupt2_regnum
= n
;
3124 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3125 tdep
->cpenable_regnum
= n
;
3128 if (rmap
->byte_size
> max_size
)
3129 max_size
= rmap
->byte_size
;
3130 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3132 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3133 && tdep
->num_nopriv_regs
== 0)
3134 tdep
->num_nopriv_regs
= n
;
3136 if (tdep
->num_regs
== 0)
3137 tdep
->num_regs
= tdep
->num_nopriv_regs
;
3139 /* Number of pseudo registers. */
3140 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3142 /* Empirically determined maximum sizes. */
3143 tdep
->max_register_raw_size
= max_size
;
3144 tdep
->max_register_virtual_size
= max_size
;
3147 /* Module "constructor" function. */
3149 extern xtensa_register_t xtensa_rmap
[];
3151 static struct gdbarch
*
3152 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3154 DEBUGTRACE ("gdbarch_init()\n");
3156 if (!xtensa_default_isa
)
3157 xtensa_default_isa
= xtensa_isa_init (0, 0);
3159 /* We have to set the byte order before we call gdbarch_alloc. */
3160 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3163 = gdbarch_alloc (&info
,
3164 gdbarch_tdep_up (new xtensa_gdbarch_tdep (xtensa_rmap
)));
3165 xtensa_gdbarch_tdep
*tdep
= gdbarch_tdep
<xtensa_gdbarch_tdep
> (gdbarch
);
3166 xtensa_derive_tdep (tdep
);
3168 /* Verify our configuration. */
3169 xtensa_verify_config (gdbarch
);
3170 xtensa_session_once_reported
= 0;
3172 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3173 set_gdbarch_wchar_signed (gdbarch
, 0);
3175 /* Pseudo-Register read/write. */
3176 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3177 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3179 /* Set target information. */
3180 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3181 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3182 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3183 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3184 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3186 /* Renumber registers for known formats (stabs and dwarf2). */
3187 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3188 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3190 /* We provide our own function to get register information. */
3191 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3192 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3194 /* To call functions from GDB using dummy frame. */
3195 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3197 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3199 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3201 /* Advance PC across any prologue instructions to reach "real" code. */
3202 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3204 /* Stack grows downward. */
3205 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3207 /* Set breakpoints. */
3208 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3209 xtensa_breakpoint_kind_from_pc
);
3210 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3211 xtensa_sw_breakpoint_from_kind
);
3213 /* After breakpoint instruction or illegal instruction, pc still
3214 points at break instruction, so don't decrement. */
3215 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3217 /* We don't skip args. */
3218 set_gdbarch_frame_args_skip (gdbarch
, 0);
3220 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3222 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3224 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3226 /* Frame handling. */
3227 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3228 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3229 dwarf2_append_unwinders (gdbarch
);
3231 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3233 xtensa_add_reggroups (gdbarch
);
3234 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3236 set_gdbarch_iterate_over_regset_sections
3237 (gdbarch
, xtensa_iterate_over_regset_sections
);
3239 set_solib_svr4_fetch_link_map_offsets
3240 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3242 /* Hook in the ABI-specific overrides, if they have been registered. */
3243 gdbarch_init_osabi (info
, gdbarch
);
3249 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3251 error (_("xtensa_dump_tdep(): not implemented"));
3254 void _initialize_xtensa_tdep ();
3256 _initialize_xtensa_tdep ()
3258 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3259 xtensa_init_reggroups ();
3261 add_setshow_zuinteger_cmd ("xtensa",
3263 &xtensa_debug_level
,
3264 _("Set Xtensa debugging."),
3265 _("Show Xtensa debugging."), _("\
3266 When non-zero, Xtensa-specific debugging is enabled. \
3267 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3270 &setdebuglist
, &showdebuglist
);