1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2023 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
35 #include "nat/gdb_ptrace.h"
36 #include <asm/ptrace.h>
41 #include "gdb_proc_service.h"
42 #include "arch/aarch64.h"
43 #include "arch/aarch64-mte-linux.h"
44 #include "linux-aarch32-tdesc.h"
45 #include "linux-aarch64-tdesc.h"
46 #include "nat/aarch64-mte-linux-ptrace.h"
47 #include "nat/aarch64-sve-linux-ptrace.h"
58 /* Linux target op definitions for the AArch64 architecture. */
60 class aarch64_target
: public linux_process_target
64 const regs_info
*get_regs_info () override
;
66 int breakpoint_kind_from_pc (CORE_ADDR
*pcptr
) override
;
68 int breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
) override
;
70 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
72 bool supports_z_point_type (char z_type
) override
;
74 bool supports_tracepoints () override
;
76 bool supports_fast_tracepoints () override
;
78 int install_fast_tracepoint_jump_pad
79 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
80 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
81 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
82 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
83 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
86 int get_min_fast_tracepoint_insn_len () override
;
88 struct emit_ops
*emit_ops () override
;
90 bool supports_memory_tagging () override
;
92 bool fetch_memtags (CORE_ADDR address
, size_t len
,
93 gdb::byte_vector
&tags
, int type
) override
;
95 bool store_memtags (CORE_ADDR address
, size_t len
,
96 const gdb::byte_vector
&tags
, int type
) override
;
100 void low_arch_setup () override
;
102 bool low_cannot_fetch_register (int regno
) override
;
104 bool low_cannot_store_register (int regno
) override
;
106 bool low_supports_breakpoints () override
;
108 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
110 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
112 bool low_breakpoint_at (CORE_ADDR pc
) override
;
114 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
115 int size
, raw_breakpoint
*bp
) override
;
117 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
118 int size
, raw_breakpoint
*bp
) override
;
120 bool low_stopped_by_watchpoint () override
;
122 CORE_ADDR
low_stopped_data_address () override
;
124 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
125 int direction
) override
;
127 arch_process_info
*low_new_process () override
;
129 void low_delete_process (arch_process_info
*info
) override
;
131 void low_new_thread (lwp_info
*) override
;
133 void low_delete_thread (arch_lwp_info
*) override
;
135 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
137 void low_prepare_to_resume (lwp_info
*lwp
) override
;
139 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
141 bool low_supports_range_stepping () override
;
143 bool low_supports_catch_syscall () override
;
145 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
148 /* The singleton target ops object. */
150 static aarch64_target the_aarch64_target
;
153 aarch64_target::low_cannot_fetch_register (int regno
)
155 gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
156 "is not implemented by the target");
160 aarch64_target::low_cannot_store_register (int regno
)
162 gdb_assert_not_reached ("linux target op low_cannot_store_register "
163 "is not implemented by the target");
167 aarch64_target::low_prepare_to_resume (lwp_info
*lwp
)
169 aarch64_linux_prepare_to_resume (lwp
);
172 /* Per-process arch-specific data we want to keep. */
174 struct arch_process_info
176 /* Hardware breakpoint/watchpoint data.
177 The reason for them to be per-process rather than per-thread is
178 due to the lack of information in the gdbserver environment;
179 gdbserver is not told that whether a requested hardware
180 breakpoint/watchpoint is thread specific or not, so it has to set
181 each hw bp/wp for every thread in the current process. The
182 higher level bp/wp management in gdb will resume a thread if a hw
183 bp/wp trap is not expected for it. Since the hw bp/wp setting is
184 same for each thread, it is reasonable for the data to live here.
186 struct aarch64_debug_reg_state debug_reg_state
;
189 /* Return true if the size of register 0 is 8 byte. */
192 is_64bit_tdesc (void)
194 /* We may not have a current thread at this point, so go straight to
195 the process's target description. */
196 return register_size (current_process ()->tdesc
, 0) == 8;
200 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
202 struct user_pt_regs
*regset
= (struct user_pt_regs
*) buf
;
205 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
206 collect_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
207 collect_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
208 collect_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
209 collect_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
213 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
215 const struct user_pt_regs
*regset
= (const struct user_pt_regs
*) buf
;
218 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
219 supply_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
220 supply_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
221 supply_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
222 supply_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
226 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
228 struct user_fpsimd_state
*regset
= (struct user_fpsimd_state
*) buf
;
231 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
232 collect_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
233 collect_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
234 collect_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
238 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
240 const struct user_fpsimd_state
*regset
241 = (const struct user_fpsimd_state
*) buf
;
244 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
245 supply_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
246 supply_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
247 supply_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
250 /* Store the pauth registers to regcache. */
253 aarch64_store_pauthregset (struct regcache
*regcache
, const void *buf
)
255 uint64_t *pauth_regset
= (uint64_t *) buf
;
256 int pauth_base
= find_regno (regcache
->tdesc
, "pauth_dmask");
261 supply_register (regcache
, AARCH64_PAUTH_DMASK_REGNUM (pauth_base
),
263 supply_register (regcache
, AARCH64_PAUTH_CMASK_REGNUM (pauth_base
),
267 /* Fill BUF with the MTE registers from the regcache. */
270 aarch64_fill_mteregset (struct regcache
*regcache
, void *buf
)
272 uint64_t *mte_regset
= (uint64_t *) buf
;
273 int mte_base
= find_regno (regcache
->tdesc
, "tag_ctl");
275 collect_register (regcache
, mte_base
, mte_regset
);
278 /* Store the MTE registers to regcache. */
281 aarch64_store_mteregset (struct regcache
*regcache
, const void *buf
)
283 uint64_t *mte_regset
= (uint64_t *) buf
;
284 int mte_base
= find_regno (regcache
->tdesc
, "tag_ctl");
286 /* Tag Control register */
287 supply_register (regcache
, mte_base
, mte_regset
);
290 /* Fill BUF with TLS register from the regcache. */
293 aarch64_fill_tlsregset (struct regcache
*regcache
, void *buf
)
295 gdb_byte
*tls_buf
= (gdb_byte
*) buf
;
296 int tls_regnum
= find_regno (regcache
->tdesc
, "tpidr");
298 collect_register (regcache
, tls_regnum
, tls_buf
);
300 /* Read TPIDR2, if it exists. */
301 gdb::optional
<int> regnum
= find_regno_no_throw (regcache
->tdesc
, "tpidr2");
303 if (regnum
.has_value ())
304 collect_register (regcache
, *regnum
, tls_buf
+ sizeof (uint64_t));
307 /* Store TLS register to regcache. */
310 aarch64_store_tlsregset (struct regcache
*regcache
, const void *buf
)
312 gdb_byte
*tls_buf
= (gdb_byte
*) buf
;
313 int tls_regnum
= find_regno (regcache
->tdesc
, "tpidr");
315 supply_register (regcache
, tls_regnum
, tls_buf
);
317 /* Write TPIDR2, if it exists. */
318 gdb::optional
<int> regnum
= find_regno_no_throw (regcache
->tdesc
, "tpidr2");
320 if (regnum
.has_value ())
321 supply_register (regcache
, *regnum
, tls_buf
+ sizeof (uint64_t));
325 aarch64_target::low_supports_breakpoints ()
330 /* Implementation of linux target ops method "low_get_pc". */
333 aarch64_target::low_get_pc (regcache
*regcache
)
335 if (register_size (regcache
->tdesc
, 0) == 8)
336 return linux_get_pc_64bit (regcache
);
338 return linux_get_pc_32bit (regcache
);
341 /* Implementation of linux target ops method "low_set_pc". */
344 aarch64_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
346 if (register_size (regcache
->tdesc
, 0) == 8)
347 linux_set_pc_64bit (regcache
, pc
);
349 linux_set_pc_32bit (regcache
, pc
);
352 #define aarch64_breakpoint_len 4
354 /* AArch64 BRK software debug mode instruction.
355 This instruction needs to match gdb/aarch64-tdep.c
356 (aarch64_default_breakpoint). */
357 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
359 /* Implementation of linux target ops method "low_breakpoint_at". */
362 aarch64_target::low_breakpoint_at (CORE_ADDR where
)
364 if (is_64bit_tdesc ())
366 gdb_byte insn
[aarch64_breakpoint_len
];
368 read_memory (where
, (unsigned char *) &insn
, aarch64_breakpoint_len
);
369 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
375 return arm_breakpoint_at (where
);
379 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
383 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
385 state
->dr_addr_bp
[i
] = 0;
386 state
->dr_ctrl_bp
[i
] = 0;
387 state
->dr_ref_count_bp
[i
] = 0;
390 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
392 state
->dr_addr_wp
[i
] = 0;
393 state
->dr_ctrl_wp
[i
] = 0;
394 state
->dr_ref_count_wp
[i
] = 0;
398 /* Return the pointer to the debug register state structure in the
399 current process' arch-specific data area. */
401 struct aarch64_debug_reg_state
*
402 aarch64_get_debug_reg_state (pid_t pid
)
404 struct process_info
*proc
= find_process_pid (pid
);
406 return &proc
->priv
->arch_private
->debug_reg_state
;
409 /* Implementation of target ops method "supports_z_point_type". */
412 aarch64_target::supports_z_point_type (char z_type
)
418 case Z_PACKET_WRITE_WP
:
419 case Z_PACKET_READ_WP
:
420 case Z_PACKET_ACCESS_WP
:
427 /* Implementation of linux target ops method "low_insert_point".
429 It actually only records the info of the to-be-inserted bp/wp;
430 the actual insertion will happen when threads are resumed. */
433 aarch64_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
434 int len
, raw_breakpoint
*bp
)
437 enum target_hw_bp_type targ_type
;
438 struct aarch64_debug_reg_state
*state
439 = aarch64_get_debug_reg_state (pid_of (current_thread
));
442 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
443 (unsigned long) addr
, len
);
445 /* Determine the type from the raw breakpoint type. */
446 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
448 if (targ_type
!= hw_execute
)
450 if (aarch64_region_ok_for_watchpoint (addr
, len
))
451 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
453 current_lwp_ptid (), state
);
461 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
462 instruction. Set it to 2 to correctly encode length bit
463 mask in hardware/watchpoint control register. */
466 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
467 1 /* is_insert */, current_lwp_ptid (),
472 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
478 /* Implementation of linux target ops method "low_remove_point".
480 It actually only records the info of the to-be-removed bp/wp,
481 the actual removal will be done when threads are resumed. */
484 aarch64_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
485 int len
, raw_breakpoint
*bp
)
488 enum target_hw_bp_type targ_type
;
489 struct aarch64_debug_reg_state
*state
490 = aarch64_get_debug_reg_state (pid_of (current_thread
));
493 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
494 (unsigned long) addr
, len
);
496 /* Determine the type from the raw breakpoint type. */
497 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
499 /* Set up state pointers. */
500 if (targ_type
!= hw_execute
)
502 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
503 current_lwp_ptid (), state
);
508 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
509 instruction. Set it to 2 to correctly encode length bit
510 mask in hardware/watchpoint control register. */
513 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
514 0 /* is_insert */, current_lwp_ptid (),
519 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
526 aarch64_remove_non_address_bits (CORE_ADDR pointer
)
528 /* By default, we assume TBI and discard the top 8 bits plus the
529 VA range select bit (55). */
530 CORE_ADDR mask
= AARCH64_TOP_BITS_MASK
;
532 /* Check if PAC is available for this target. */
533 if (tdesc_contains_feature (current_process ()->tdesc
,
534 "org.gnu.gdb.aarch64.pauth"))
536 /* Fetch the PAC masks. These masks are per-process, so we can just
537 fetch data from whatever thread we have at the moment.
539 Also, we have both a code mask and a data mask. For now they are the
540 same, but this may change in the future. */
542 struct regcache
*regs
= get_thread_regcache (current_thread
, 1);
543 CORE_ADDR dmask
= regcache_raw_get_unsigned_by_name (regs
, "pauth_dmask");
544 CORE_ADDR cmask
= regcache_raw_get_unsigned_by_name (regs
, "pauth_cmask");
545 mask
|= aarch64_mask_from_pac_registers (cmask
, dmask
);
548 return aarch64_remove_top_bits (pointer
, mask
);
551 /* Implementation of linux target ops method "low_stopped_data_address". */
554 aarch64_target::low_stopped_data_address ()
558 struct aarch64_debug_reg_state
*state
;
560 pid
= lwpid_of (current_thread
);
562 /* Get the siginfo. */
563 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
564 return (CORE_ADDR
) 0;
566 /* Need to be a hardware breakpoint/watchpoint trap. */
567 if (siginfo
.si_signo
!= SIGTRAP
568 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
569 return (CORE_ADDR
) 0;
571 /* Make sure to ignore the top byte, otherwise we may not recognize a
572 hardware watchpoint hit. The stopped data addresses coming from the
573 kernel can potentially be tagged addresses. */
574 const CORE_ADDR addr_trap
575 = aarch64_remove_non_address_bits ((CORE_ADDR
) siginfo
.si_addr
);
577 /* Check if the address matches any watched address. */
578 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
579 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
581 const unsigned int offset
582 = aarch64_watchpoint_offset (state
->dr_ctrl_wp
[i
]);
583 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
584 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
] + offset
;
585 const CORE_ADDR addr_watch_aligned
= align_down (state
->dr_addr_wp
[i
], 8);
586 const CORE_ADDR addr_orig
= state
->dr_addr_orig_wp
[i
];
588 if (state
->dr_ref_count_wp
[i
]
589 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
590 && addr_trap
>= addr_watch_aligned
591 && addr_trap
< addr_watch
+ len
)
593 /* ADDR_TRAP reports the first address of the memory range
594 accessed by the CPU, regardless of what was the memory
595 range watched. Thus, a large CPU access that straddles
596 the ADDR_WATCH..ADDR_WATCH+LEN range may result in an
597 ADDR_TRAP that is lower than the
598 ADDR_WATCH..ADDR_WATCH+LEN range. E.g.:
600 addr: | 4 | 5 | 6 | 7 | 8 |
601 |---- range watched ----|
602 |----------- range accessed ------------|
604 In this case, ADDR_TRAP will be 4.
606 To match a watchpoint known to GDB core, we must never
607 report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN
608 range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false
609 positive on kernels older than 4.10. See PR
615 return (CORE_ADDR
) 0;
618 /* Implementation of linux target ops method "low_stopped_by_watchpoint". */
621 aarch64_target::low_stopped_by_watchpoint ()
623 return (low_stopped_data_address () != 0);
626 /* Fetch the thread-local storage pointer for libthread_db. */
629 ps_get_thread_area (struct ps_prochandle
*ph
,
630 lwpid_t lwpid
, int idx
, void **base
)
632 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
636 /* Implementation of linux target ops method "low_siginfo_fixup". */
639 aarch64_target::low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
642 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
643 if (!is_64bit_tdesc ())
646 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
649 aarch64_siginfo_from_compat_siginfo (native
,
650 (struct compat_siginfo
*) inf
);
658 /* Implementation of linux target ops method "low_new_process". */
661 aarch64_target::low_new_process ()
663 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
665 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
670 /* Implementation of linux target ops method "low_delete_process". */
673 aarch64_target::low_delete_process (arch_process_info
*info
)
679 aarch64_target::low_new_thread (lwp_info
*lwp
)
681 aarch64_linux_new_thread (lwp
);
685 aarch64_target::low_delete_thread (arch_lwp_info
*arch_lwp
)
687 aarch64_linux_delete_thread (arch_lwp
);
690 /* Implementation of linux target ops method "low_new_fork". */
693 aarch64_target::low_new_fork (process_info
*parent
,
696 /* These are allocated by linux_add_process. */
697 gdb_assert (parent
->priv
!= NULL
698 && parent
->priv
->arch_private
!= NULL
);
699 gdb_assert (child
->priv
!= NULL
700 && child
->priv
->arch_private
!= NULL
);
702 /* Linux kernel before 2.6.33 commit
703 72f674d203cd230426437cdcf7dd6f681dad8b0d
704 will inherit hardware debug registers from parent
705 on fork/vfork/clone. Newer Linux kernels create such tasks with
706 zeroed debug registers.
708 GDB core assumes the child inherits the watchpoints/hw
709 breakpoints of the parent, and will remove them all from the
710 forked off process. Copy the debug registers mirrors into the
711 new process so that all breakpoints and watchpoints can be
712 removed together. The debug registers mirror will become zeroed
713 in the end before detaching the forked off process, thus making
714 this compatible with older Linux kernels too. */
716 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
719 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
722 aarch64_sve_regs_copy_to_regcache (struct regcache
*regcache
, const void *buf
)
724 return aarch64_sve_regs_copy_to_reg_buf (regcache
, buf
);
727 /* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */
730 aarch64_sve_regs_copy_from_regcache (struct regcache
*regcache
, void *buf
)
732 return aarch64_sve_regs_copy_from_reg_buf (regcache
, buf
);
735 /* Array containing all the possible register sets for AArch64/Linux. During
736 architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
737 validity and enabled/disabled accordingly.
739 Their sizes are set to 0 here, but they will be adjusted later depending
740 on whether each register set is available or not. */
741 static struct regset_info aarch64_regsets
[] =
744 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
746 aarch64_fill_gregset
, aarch64_store_gregset
},
747 /* Floating Point (FPU) registers. */
748 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
750 aarch64_fill_fpregset
, aarch64_store_fpregset
752 /* Scalable Vector Extension (SVE) registers. */
753 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_SVE
,
755 aarch64_sve_regs_copy_from_regcache
, aarch64_sve_regs_copy_to_regcache
758 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_PAC_MASK
,
760 nullptr, aarch64_store_pauthregset
},
761 /* Tagged address control / MTE registers. */
762 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_TAGGED_ADDR_CTRL
,
764 aarch64_fill_mteregset
, aarch64_store_mteregset
},
766 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_TLS
,
768 aarch64_fill_tlsregset
, aarch64_store_tlsregset
},
772 static struct regsets_info aarch64_regsets_info
=
774 aarch64_regsets
, /* regsets */
776 nullptr, /* disabled_regsets */
779 static struct regs_info regs_info_aarch64
=
781 nullptr, /* regset_bitmap */
782 nullptr, /* usrregs */
783 &aarch64_regsets_info
,
786 /* Given FEATURES, adjust the available register sets by setting their
787 sizes. A size of 0 means the register set is disabled and won't be
791 aarch64_adjust_register_sets (const struct aarch64_features
&features
)
793 struct regset_info
*regset
;
795 for (regset
= aarch64_regsets
; regset
->size
>= 0; regset
++)
797 switch (regset
->nt_type
)
800 /* General purpose registers are always present. */
801 regset
->size
= sizeof (struct user_pt_regs
);
804 /* This is unavailable when SVE is present. */
805 if (features
.vq
== 0)
806 regset
->size
= sizeof (struct user_fpsimd_state
);
810 regset
->size
= SVE_PT_SIZE (AARCH64_MAX_SVE_VQ
, SVE_PT_REGS_SVE
);
812 case NT_ARM_PAC_MASK
:
814 regset
->size
= AARCH64_PAUTH_REGS_SIZE
;
816 case NT_ARM_TAGGED_ADDR_CTRL
:
818 regset
->size
= AARCH64_LINUX_SIZEOF_MTE
;
821 if (features
.tls
> 0)
822 regset
->size
= AARCH64_TLS_REGISTER_SIZE
* features
.tls
;
825 gdb_assert_not_reached ("Unknown register set found.");
830 /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
831 #define AARCH64_HWCAP_PACA (1 << 30)
833 /* Implementation of linux target ops method "low_arch_setup". */
836 aarch64_target::low_arch_setup ()
838 unsigned int machine
;
842 tid
= lwpid_of (current_thread
);
844 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
848 struct aarch64_features features
;
850 features
.vq
= aarch64_sve_get_vq (tid
);
851 /* A-profile PAC is 64-bit only. */
852 features
.pauth
= linux_get_hwcap (8) & AARCH64_HWCAP_PACA
;
853 /* A-profile MTE is 64-bit only. */
854 features
.mte
= linux_get_hwcap2 (8) & HWCAP2_MTE
;
855 features
.tls
= aarch64_tls_register_count (tid
);
857 current_process ()->tdesc
= aarch64_linux_read_description (features
);
859 /* Adjust the register sets we should use for this particular set of
861 aarch64_adjust_register_sets (features
);
864 current_process ()->tdesc
= aarch32_linux_read_description ();
866 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
869 /* Implementation of linux target ops method "get_regs_info". */
872 aarch64_target::get_regs_info ()
874 if (!is_64bit_tdesc ())
875 return ®s_info_aarch32
;
877 /* AArch64 64-bit registers. */
878 return ®s_info_aarch64
;
881 /* Implementation of target ops method "supports_tracepoints". */
884 aarch64_target::supports_tracepoints ()
886 if (current_thread
== NULL
)
890 /* We don't support tracepoints on aarch32 now. */
891 return is_64bit_tdesc ();
895 /* Implementation of linux target ops method "low_get_thread_area". */
898 aarch64_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
903 iovec
.iov_base
= ®
;
904 iovec
.iov_len
= sizeof (reg
);
906 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
915 aarch64_target::low_supports_catch_syscall ()
920 /* Implementation of linux target ops method "low_get_syscall_trapinfo". */
923 aarch64_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
925 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
931 collect_register_by_name (regcache
, "x8", &l_sysno
);
932 *sysno
= (int) l_sysno
;
935 collect_register_by_name (regcache
, "r7", sysno
);
938 /* List of condition codes that we need. */
940 enum aarch64_condition_codes
951 enum aarch64_operand_type
957 /* Representation of an operand. At this time, it only supports register
958 and immediate types. */
960 struct aarch64_operand
962 /* Type of the operand. */
963 enum aarch64_operand_type type
;
965 /* Value of the operand according to the type. */
969 struct aarch64_register reg
;
973 /* List of registers that we are currently using, we can add more here as
974 we need to use them. */
976 /* General purpose scratch registers (64 bit). */
977 static const struct aarch64_register x0
= { 0, 1 };
978 static const struct aarch64_register x1
= { 1, 1 };
979 static const struct aarch64_register x2
= { 2, 1 };
980 static const struct aarch64_register x3
= { 3, 1 };
981 static const struct aarch64_register x4
= { 4, 1 };
983 /* General purpose scratch registers (32 bit). */
984 static const struct aarch64_register w0
= { 0, 0 };
985 static const struct aarch64_register w2
= { 2, 0 };
987 /* Intra-procedure scratch registers. */
988 static const struct aarch64_register ip0
= { 16, 1 };
990 /* Special purpose registers. */
991 static const struct aarch64_register fp
= { 29, 1 };
992 static const struct aarch64_register lr
= { 30, 1 };
993 static const struct aarch64_register sp
= { 31, 1 };
994 static const struct aarch64_register xzr
= { 31, 1 };
996 /* Dynamically allocate a new register. If we know the register
997 statically, we should make it a global as above instead of using this
1000 static struct aarch64_register
1001 aarch64_register (unsigned num
, int is64
)
1003 return (struct aarch64_register
) { num
, is64
};
1006 /* Helper function to create a register operand, for instructions with
1007 different types of operands.
1010 p += emit_mov (p, x0, register_operand (x1)); */
1012 static struct aarch64_operand
1013 register_operand (struct aarch64_register reg
)
1015 struct aarch64_operand operand
;
1017 operand
.type
= OPERAND_REGISTER
;
1023 /* Helper function to create an immediate operand, for instructions with
1024 different types of operands.
1027 p += emit_mov (p, x0, immediate_operand (12)); */
1029 static struct aarch64_operand
1030 immediate_operand (uint32_t imm
)
1032 struct aarch64_operand operand
;
1034 operand
.type
= OPERAND_IMMEDIATE
;
1040 /* Helper function to create an offset memory operand.
1043 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
1045 static struct aarch64_memory_operand
1046 offset_memory_operand (int32_t offset
)
1048 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
1051 /* Helper function to create a pre-index memory operand.
1054 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
1056 static struct aarch64_memory_operand
1057 preindex_memory_operand (int32_t index
)
1059 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
1062 /* Helper function to create a post-index memory operand.
1065 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
1067 static struct aarch64_memory_operand
1068 postindex_memory_operand (int32_t index
)
1070 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
1073 /* System control registers. These special registers can be written and
1074 read with the MRS and MSR instructions.
1076 - NZCV: Condition flags. GDB refers to this register under the CPSR
1078 - FPSR: Floating-point status register.
1079 - FPCR: Floating-point control registers.
1080 - TPIDR_EL0: Software thread ID register. */
1082 enum aarch64_system_control_registers
1084 /* op0 op1 crn crm op2 */
1085 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
1086 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
1087 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
1088 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
1091 /* Write a BLR instruction into *BUF.
1095 RN is the register to branch to. */
1098 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
1100 return aarch64_emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
1103 /* Write a RET instruction into *BUF.
1107 RN is the register to branch to. */
1110 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
1112 return aarch64_emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
1116 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
1117 struct aarch64_register rt
,
1118 struct aarch64_register rt2
,
1119 struct aarch64_register rn
,
1120 struct aarch64_memory_operand operand
)
1124 uint32_t write_back
;
1127 opc
= ENCODE (2, 2, 30);
1129 opc
= ENCODE (0, 2, 30);
1131 switch (operand
.type
)
1133 case MEMORY_OPERAND_OFFSET
:
1135 pre_index
= ENCODE (1, 1, 24);
1136 write_back
= ENCODE (0, 1, 23);
1139 case MEMORY_OPERAND_POSTINDEX
:
1141 pre_index
= ENCODE (0, 1, 24);
1142 write_back
= ENCODE (1, 1, 23);
1145 case MEMORY_OPERAND_PREINDEX
:
1147 pre_index
= ENCODE (1, 1, 24);
1148 write_back
= ENCODE (1, 1, 23);
1155 return aarch64_emit_insn (buf
, opcode
| opc
| pre_index
| write_back
1156 | ENCODE (operand
.index
>> 3, 7, 15)
1157 | ENCODE (rt2
.num
, 5, 10)
1158 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1161 /* Write a STP instruction into *BUF.
1163 STP rt, rt2, [rn, #offset]
1164 STP rt, rt2, [rn, #index]!
1165 STP rt, rt2, [rn], #index
1167 RT and RT2 are the registers to store.
1168 RN is the base address register.
1169 OFFSET is the immediate to add to the base address. It is limited to a
1170 -512 .. 504 range (7 bits << 3). */
1173 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
1174 struct aarch64_register rt2
, struct aarch64_register rn
,
1175 struct aarch64_memory_operand operand
)
1177 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
1180 /* Write a LDP instruction into *BUF.
1182 LDP rt, rt2, [rn, #offset]
1183 LDP rt, rt2, [rn, #index]!
1184 LDP rt, rt2, [rn], #index
1186 RT and RT2 are the registers to store.
1187 RN is the base address register.
1188 OFFSET is the immediate to add to the base address. It is limited to a
1189 -512 .. 504 range (7 bits << 3). */
1192 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
1193 struct aarch64_register rt2
, struct aarch64_register rn
,
1194 struct aarch64_memory_operand operand
)
1196 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
1199 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
1201 LDP qt, qt2, [rn, #offset]
1203 RT and RT2 are the Q registers to store.
1204 RN is the base address register.
1205 OFFSET is the immediate to add to the base address. It is limited to
1206 -1024 .. 1008 range (7 bits << 4). */
1209 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1210 struct aarch64_register rn
, int32_t offset
)
1212 uint32_t opc
= ENCODE (2, 2, 30);
1213 uint32_t pre_index
= ENCODE (1, 1, 24);
1215 return aarch64_emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
1216 | ENCODE (offset
>> 4, 7, 15)
1217 | ENCODE (rt2
, 5, 10)
1218 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1221 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
1223 STP qt, qt2, [rn, #offset]
1225 RT and RT2 are the Q registers to store.
1226 RN is the base address register.
1227 OFFSET is the immediate to add to the base address. It is limited to
1228 -1024 .. 1008 range (7 bits << 4). */
1231 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1232 struct aarch64_register rn
, int32_t offset
)
1234 uint32_t opc
= ENCODE (2, 2, 30);
1235 uint32_t pre_index
= ENCODE (1, 1, 24);
1237 return aarch64_emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
1238 | ENCODE (offset
>> 4, 7, 15)
1239 | ENCODE (rt2
, 5, 10)
1240 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1243 /* Write a LDRH instruction into *BUF.
1245 LDRH wt, [xn, #offset]
1246 LDRH wt, [xn, #index]!
1247 LDRH wt, [xn], #index
1249 RT is the register to store.
1250 RN is the base address register.
1251 OFFSET is the immediate to add to the base address. It is limited to
1252 0 .. 32760 range (12 bits << 3). */
1255 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
1256 struct aarch64_register rn
,
1257 struct aarch64_memory_operand operand
)
1259 return aarch64_emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
1262 /* Write a LDRB instruction into *BUF.
1264 LDRB wt, [xn, #offset]
1265 LDRB wt, [xn, #index]!
1266 LDRB wt, [xn], #index
1268 RT is the register to store.
1269 RN is the base address register.
1270 OFFSET is the immediate to add to the base address. It is limited to
1271 0 .. 32760 range (12 bits << 3). */
1274 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
1275 struct aarch64_register rn
,
1276 struct aarch64_memory_operand operand
)
1278 return aarch64_emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
1283 /* Write a STR instruction into *BUF.
1285 STR rt, [rn, #offset]
1286 STR rt, [rn, #index]!
1287 STR rt, [rn], #index
1289 RT is the register to store.
1290 RN is the base address register.
1291 OFFSET is the immediate to add to the base address. It is limited to
1292 0 .. 32760 range (12 bits << 3). */
1295 emit_str (uint32_t *buf
, struct aarch64_register rt
,
1296 struct aarch64_register rn
,
1297 struct aarch64_memory_operand operand
)
1299 return aarch64_emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
1302 /* Helper function emitting an exclusive load or store instruction. */
1305 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
1306 enum aarch64_opcodes opcode
,
1307 struct aarch64_register rs
,
1308 struct aarch64_register rt
,
1309 struct aarch64_register rt2
,
1310 struct aarch64_register rn
)
1312 return aarch64_emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
1313 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
1314 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1317 /* Write a LAXR instruction into *BUF.
1321 RT is the destination register.
1322 RN is the base address register. */
1325 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
1326 struct aarch64_register rn
)
1328 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
1332 /* Write a STXR instruction into *BUF.
1336 RS is the result register, it indicates if the store succeeded or not.
1337 RT is the destination register.
1338 RN is the base address register. */
1341 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1342 struct aarch64_register rt
, struct aarch64_register rn
)
1344 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1348 /* Write a STLR instruction into *BUF.
1352 RT is the register to store.
1353 RN is the base address register. */
1356 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1357 struct aarch64_register rn
)
1359 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1363 /* Helper function for data processing instructions with register sources. */
1366 emit_data_processing_reg (uint32_t *buf
, uint32_t opcode
,
1367 struct aarch64_register rd
,
1368 struct aarch64_register rn
,
1369 struct aarch64_register rm
)
1371 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1373 return aarch64_emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1374 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1377 /* Helper function for data processing instructions taking either a register
1381 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1382 struct aarch64_register rd
,
1383 struct aarch64_register rn
,
1384 struct aarch64_operand operand
)
1386 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1387 /* The opcode is different for register and immediate source operands. */
1388 uint32_t operand_opcode
;
1390 if (operand
.type
== OPERAND_IMMEDIATE
)
1392 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1393 operand_opcode
= ENCODE (8, 4, 25);
1395 return aarch64_emit_insn (buf
, opcode
| operand_opcode
| size
1396 | ENCODE (operand
.imm
, 12, 10)
1397 | ENCODE (rn
.num
, 5, 5)
1398 | ENCODE (rd
.num
, 5, 0));
1402 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1403 operand_opcode
= ENCODE (5, 4, 25);
1405 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1410 /* Write an ADD instruction into *BUF.
1415 This function handles both an immediate and register add.
1417 RD is the destination register.
1418 RN is the input register.
1419 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1420 OPERAND_REGISTER. */
1423 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1424 struct aarch64_register rn
, struct aarch64_operand operand
)
1426 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1429 /* Write a SUB instruction into *BUF.
1434 This function handles both an immediate and register sub.
1436 RD is the destination register.
1437 RN is the input register.
1438 IMM is the immediate to substract to RN. */
1441 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1442 struct aarch64_register rn
, struct aarch64_operand operand
)
1444 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1447 /* Write a MOV instruction into *BUF.
1452 This function handles both a wide immediate move and a register move,
1453 with the condition that the source register is not xzr. xzr and the
1454 stack pointer share the same encoding and this function only supports
1457 RD is the destination register.
1458 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1459 OPERAND_REGISTER. */
1462 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1463 struct aarch64_operand operand
)
1465 if (operand
.type
== OPERAND_IMMEDIATE
)
1467 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1468 /* Do not shift the immediate. */
1469 uint32_t shift
= ENCODE (0, 2, 21);
1471 return aarch64_emit_insn (buf
, MOV
| size
| shift
1472 | ENCODE (operand
.imm
, 16, 5)
1473 | ENCODE (rd
.num
, 5, 0));
1476 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1479 /* Write a MOVK instruction into *BUF.
1481 MOVK rd, #imm, lsl #shift
1483 RD is the destination register.
1484 IMM is the immediate.
1485 SHIFT is the logical shift left to apply to IMM. */
1488 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1491 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1493 return aarch64_emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1494 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1497 /* Write instructions into *BUF in order to move ADDR into a register.
1498 ADDR can be a 64-bit value.
1500 This function will emit a series of MOV and MOVK instructions, such as:
1503 MOVK xd, #(addr >> 16), lsl #16
1504 MOVK xd, #(addr >> 32), lsl #32
1505 MOVK xd, #(addr >> 48), lsl #48 */
1508 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1512 /* The MOV (wide immediate) instruction clears to top bits of the
1514 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1516 if ((addr
>> 16) != 0)
1517 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1521 if ((addr
>> 32) != 0)
1522 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1526 if ((addr
>> 48) != 0)
1527 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1532 /* Write a SUBS instruction into *BUF.
1536 This instruction update the condition flags.
1538 RD is the destination register.
1539 RN and RM are the source registers. */
1542 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1543 struct aarch64_register rn
, struct aarch64_operand operand
)
1545 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1548 /* Write a CMP instruction into *BUF.
1552 This instruction is an alias of SUBS xzr, rn, rm.
1554 RN and RM are the registers to compare. */
1557 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1558 struct aarch64_operand operand
)
1560 return emit_subs (buf
, xzr
, rn
, operand
);
1563 /* Write a AND instruction into *BUF.
1567 RD is the destination register.
1568 RN and RM are the source registers. */
1571 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1572 struct aarch64_register rn
, struct aarch64_register rm
)
1574 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1577 /* Write a ORR instruction into *BUF.
1581 RD is the destination register.
1582 RN and RM are the source registers. */
1585 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1586 struct aarch64_register rn
, struct aarch64_register rm
)
1588 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1591 /* Write a ORN instruction into *BUF.
1595 RD is the destination register.
1596 RN and RM are the source registers. */
1599 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1600 struct aarch64_register rn
, struct aarch64_register rm
)
1602 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1605 /* Write a EOR instruction into *BUF.
1609 RD is the destination register.
1610 RN and RM are the source registers. */
1613 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1614 struct aarch64_register rn
, struct aarch64_register rm
)
1616 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1619 /* Write a MVN instruction into *BUF.
1623 This is an alias for ORN rd, xzr, rm.
1625 RD is the destination register.
1626 RM is the source register. */
1629 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1630 struct aarch64_register rm
)
1632 return emit_orn (buf
, rd
, xzr
, rm
);
1635 /* Write a LSLV instruction into *BUF.
1639 RD is the destination register.
1640 RN and RM are the source registers. */
1643 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1644 struct aarch64_register rn
, struct aarch64_register rm
)
1646 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1649 /* Write a LSRV instruction into *BUF.
1653 RD is the destination register.
1654 RN and RM are the source registers. */
1657 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1658 struct aarch64_register rn
, struct aarch64_register rm
)
1660 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1663 /* Write a ASRV instruction into *BUF.
1667 RD is the destination register.
1668 RN and RM are the source registers. */
1671 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1672 struct aarch64_register rn
, struct aarch64_register rm
)
1674 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1677 /* Write a MUL instruction into *BUF.
1681 RD is the destination register.
1682 RN and RM are the source registers. */
1685 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1686 struct aarch64_register rn
, struct aarch64_register rm
)
1688 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1691 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1695 RT is the destination register.
1696 SYSTEM_REG is special purpose register to read. */
1699 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1700 enum aarch64_system_control_registers system_reg
)
1702 return aarch64_emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1703 | ENCODE (rt
.num
, 5, 0));
1706 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1710 SYSTEM_REG is special purpose register to write.
1711 RT is the input register. */
1714 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1715 struct aarch64_register rt
)
1717 return aarch64_emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1718 | ENCODE (rt
.num
, 5, 0));
1721 /* Write a SEVL instruction into *BUF.
1723 This is a hint instruction telling the hardware to trigger an event. */
1726 emit_sevl (uint32_t *buf
)
1728 return aarch64_emit_insn (buf
, SEVL
);
1731 /* Write a WFE instruction into *BUF.
1733 This is a hint instruction telling the hardware to wait for an event. */
1736 emit_wfe (uint32_t *buf
)
1738 return aarch64_emit_insn (buf
, WFE
);
1741 /* Write a SBFM instruction into *BUF.
1743 SBFM rd, rn, #immr, #imms
1745 This instruction moves the bits from #immr to #imms into the
1746 destination, sign extending the result.
1748 RD is the destination register.
1749 RN is the source register.
1750 IMMR is the bit number to start at (least significant bit).
1751 IMMS is the bit number to stop at (most significant bit). */
1754 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1755 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1757 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1758 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1760 return aarch64_emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1761 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1762 | ENCODE (rd
.num
, 5, 0));
1765 /* Write a SBFX instruction into *BUF.
1767 SBFX rd, rn, #lsb, #width
1769 This instruction moves #width bits from #lsb into the destination, sign
1770 extending the result. This is an alias for:
1772 SBFM rd, rn, #lsb, #(lsb + width - 1)
1774 RD is the destination register.
1775 RN is the source register.
1776 LSB is the bit number to start at (least significant bit).
1777 WIDTH is the number of bits to move. */
1780 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1781 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1783 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1786 /* Write a UBFM instruction into *BUF.
1788 UBFM rd, rn, #immr, #imms
1790 This instruction moves the bits from #immr to #imms into the
1791 destination, extending the result with zeros.
1793 RD is the destination register.
1794 RN is the source register.
1795 IMMR is the bit number to start at (least significant bit).
1796 IMMS is the bit number to stop at (most significant bit). */
1799 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1800 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1802 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1803 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1805 return aarch64_emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1806 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1807 | ENCODE (rd
.num
, 5, 0));
1810 /* Write a UBFX instruction into *BUF.
1812 UBFX rd, rn, #lsb, #width
1814 This instruction moves #width bits from #lsb into the destination,
1815 extending the result with zeros. This is an alias for:
1817 UBFM rd, rn, #lsb, #(lsb + width - 1)
1819 RD is the destination register.
1820 RN is the source register.
1821 LSB is the bit number to start at (least significant bit).
1822 WIDTH is the number of bits to move. */
1825 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1826 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1828 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1831 /* Write a CSINC instruction into *BUF.
1833 CSINC rd, rn, rm, cond
1835 This instruction conditionally increments rn or rm and places the result
1836 in rd. rn is chosen is the condition is true.
1838 RD is the destination register.
1839 RN and RM are the source registers.
1840 COND is the encoded condition. */
1843 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1844 struct aarch64_register rn
, struct aarch64_register rm
,
1847 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1849 return aarch64_emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1850 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1851 | ENCODE (rd
.num
, 5, 0));
1854 /* Write a CSET instruction into *BUF.
1858 This instruction conditionally write 1 or 0 in the destination register.
1859 1 is written if the condition is true. This is an alias for:
1861 CSINC rd, xzr, xzr, !cond
1863 Note that the condition needs to be inverted.
1865 RD is the destination register.
1866 RN and RM are the source registers.
1867 COND is the encoded condition. */
1870 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1872 /* The least significant bit of the condition needs toggling in order to
1874 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1877 /* Write LEN instructions from BUF into the inferior memory at *TO.
1879 Note instructions are always little endian on AArch64, unlike data. */
1882 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1884 size_t byte_len
= len
* sizeof (uint32_t);
1885 #if (__BYTE_ORDER == __BIG_ENDIAN)
1886 uint32_t *le_buf
= (uint32_t *) xmalloc (byte_len
);
1889 for (i
= 0; i
< len
; i
++)
1890 le_buf
[i
] = htole32 (buf
[i
]);
1892 target_write_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1896 target_write_memory (*to
, (const unsigned char *) buf
, byte_len
);
1902 /* Sub-class of struct aarch64_insn_data, store information of
1903 instruction relocation for fast tracepoint. Visitor can
1904 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1905 the relocated instructions in buffer pointed by INSN_PTR. */
1907 struct aarch64_insn_relocation_data
1909 struct aarch64_insn_data base
;
1911 /* The new address the instruction is relocated to. */
1913 /* Pointer to the buffer of relocated instruction(s). */
1917 /* Implementation of aarch64_insn_visitor method "b". */
1920 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1921 struct aarch64_insn_data
*data
)
1923 struct aarch64_insn_relocation_data
*insn_reloc
1924 = (struct aarch64_insn_relocation_data
*) data
;
1926 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1928 if (can_encode_int32 (new_offset
, 28))
1929 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1932 /* Implementation of aarch64_insn_visitor method "b_cond". */
1935 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1936 struct aarch64_insn_data
*data
)
1938 struct aarch64_insn_relocation_data
*insn_reloc
1939 = (struct aarch64_insn_relocation_data
*) data
;
1941 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1943 if (can_encode_int32 (new_offset
, 21))
1945 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1948 else if (can_encode_int32 (new_offset
, 28))
1950 /* The offset is out of range for a conditional branch
1951 instruction but not for a unconditional branch. We can use
1952 the following instructions instead:
1954 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1955 B NOT_TAKEN ; Else jump over TAKEN and continue.
1962 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1963 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1964 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1968 /* Implementation of aarch64_insn_visitor method "cb". */
1971 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1972 const unsigned rn
, int is64
,
1973 struct aarch64_insn_data
*data
)
1975 struct aarch64_insn_relocation_data
*insn_reloc
1976 = (struct aarch64_insn_relocation_data
*) data
;
1978 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1980 if (can_encode_int32 (new_offset
, 21))
1982 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1983 aarch64_register (rn
, is64
), new_offset
);
1985 else if (can_encode_int32 (new_offset
, 28))
1987 /* The offset is out of range for a compare and branch
1988 instruction but not for a unconditional branch. We can use
1989 the following instructions instead:
1991 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1992 B NOT_TAKEN ; Else jump over TAKEN and continue.
1998 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1999 aarch64_register (rn
, is64
), 8);
2000 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
2001 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
2005 /* Implementation of aarch64_insn_visitor method "tb". */
2008 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
2009 const unsigned rt
, unsigned bit
,
2010 struct aarch64_insn_data
*data
)
2012 struct aarch64_insn_relocation_data
*insn_reloc
2013 = (struct aarch64_insn_relocation_data
*) data
;
2015 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
2017 if (can_encode_int32 (new_offset
, 16))
2019 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
2020 aarch64_register (rt
, 1), new_offset
);
2022 else if (can_encode_int32 (new_offset
, 28))
2024 /* The offset is out of range for a test bit and branch
2025 instruction but not for a unconditional branch. We can use
2026 the following instructions instead:
2028 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2029 B NOT_TAKEN ; Else jump over TAKEN and continue.
2035 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
2036 aarch64_register (rt
, 1), 8);
2037 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
2038 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
2043 /* Implementation of aarch64_insn_visitor method "adr". */
2046 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
2048 struct aarch64_insn_data
*data
)
2050 struct aarch64_insn_relocation_data
*insn_reloc
2051 = (struct aarch64_insn_relocation_data
*) data
;
2052 /* We know exactly the address the ADR{P,} instruction will compute.
2053 We can just write it to the destination register. */
2054 CORE_ADDR address
= data
->insn_addr
+ offset
;
2058 /* Clear the lower 12 bits of the offset to get the 4K page. */
2059 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2060 aarch64_register (rd
, 1),
2064 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2065 aarch64_register (rd
, 1), address
);
2068 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2071 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
2072 const unsigned rt
, const int is64
,
2073 struct aarch64_insn_data
*data
)
2075 struct aarch64_insn_relocation_data
*insn_reloc
2076 = (struct aarch64_insn_relocation_data
*) data
;
2077 CORE_ADDR address
= data
->insn_addr
+ offset
;
2079 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2080 aarch64_register (rt
, 1), address
);
2082 /* We know exactly what address to load from, and what register we
2085 MOV xd, #(oldloc + offset)
2086 MOVK xd, #((oldloc + offset) >> 16), lsl #16
2089 LDR xd, [xd] ; or LDRSW xd, [xd]
2094 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
2095 aarch64_register (rt
, 1),
2096 aarch64_register (rt
, 1),
2097 offset_memory_operand (0));
2099 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
2100 aarch64_register (rt
, is64
),
2101 aarch64_register (rt
, 1),
2102 offset_memory_operand (0));
2105 /* Implementation of aarch64_insn_visitor method "others". */
2108 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
2109 struct aarch64_insn_data
*data
)
2111 struct aarch64_insn_relocation_data
*insn_reloc
2112 = (struct aarch64_insn_relocation_data
*) data
;
2114 /* The instruction is not PC relative. Just re-emit it at the new
2116 insn_reloc
->insn_ptr
+= aarch64_emit_insn (insn_reloc
->insn_ptr
, insn
);
2119 static const struct aarch64_insn_visitor visitor
=
2121 aarch64_ftrace_insn_reloc_b
,
2122 aarch64_ftrace_insn_reloc_b_cond
,
2123 aarch64_ftrace_insn_reloc_cb
,
2124 aarch64_ftrace_insn_reloc_tb
,
2125 aarch64_ftrace_insn_reloc_adr
,
2126 aarch64_ftrace_insn_reloc_ldr_literal
,
2127 aarch64_ftrace_insn_reloc_others
,
2131 aarch64_target::supports_fast_tracepoints ()
2136 /* Implementation of target ops method
2137 "install_fast_tracepoint_jump_pad". */
2140 aarch64_target::install_fast_tracepoint_jump_pad
2141 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
2142 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
2143 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
2144 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
2145 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
2153 CORE_ADDR buildaddr
= *jump_entry
;
2154 struct aarch64_insn_relocation_data insn_data
;
2156 /* We need to save the current state on the stack both to restore it
2157 later and to collect register values when the tracepoint is hit.
2159 The saved registers are pushed in a layout that needs to be in sync
2160 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
2161 the supply_fast_tracepoint_registers function will fill in the
2162 register cache from a pointer to saved registers on the stack we build
2165 For simplicity, we set the size of each cell on the stack to 16 bytes.
2166 This way one cell can hold any register type, from system registers
2167 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
2168 has to be 16 bytes aligned anyway.
2170 Note that the CPSR register does not exist on AArch64. Instead we
2171 can access system bits describing the process state with the
2172 MRS/MSR instructions, namely the condition flags. We save them as
2173 if they are part of a CPSR register because that's how GDB
2174 interprets these system bits. At the moment, only the condition
2175 flags are saved in CPSR (NZCV).
2177 Stack layout, each cell is 16 bytes (descending):
2179 High *-------- SIMD&FP registers from 31 down to 0. --------*
2185 *---- General purpose registers from 30 down to 0. ----*
2191 *------------- Special purpose registers. -------------*
2194 | CPSR (NZCV) | 5 cells
2197 *------------- collecting_t object --------------------*
2198 | TPIDR_EL0 | struct tracepoint * |
2199 Low *------------------------------------------------------*
2201 After this stack is set up, we issue a call to the collector, passing
2202 it the saved registers at (SP + 16). */
2204 /* Push SIMD&FP registers on the stack:
2206 SUB sp, sp, #(32 * 16)
2208 STP q30, q31, [sp, #(30 * 16)]
2213 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
2214 for (i
= 30; i
>= 0; i
-= 2)
2215 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2217 /* Push general purpose registers on the stack. Note that we do not need
2218 to push x31 as it represents the xzr register and not the stack
2219 pointer in a STR instruction.
2221 SUB sp, sp, #(31 * 16)
2223 STR x30, [sp, #(30 * 16)]
2228 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
2229 for (i
= 30; i
>= 0; i
-= 1)
2230 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
2231 offset_memory_operand (i
* 16));
2233 /* Make space for 5 more cells.
2235 SUB sp, sp, #(5 * 16)
2238 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
2243 ADD x4, sp, #((32 + 31 + 5) * 16)
2244 STR x4, [sp, #(4 * 16)]
2247 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
2248 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
2250 /* Save PC (tracepoint address):
2255 STR x3, [sp, #(3 * 16)]
2259 p
+= emit_mov_addr (p
, x3
, tpaddr
);
2260 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
2262 /* Save CPSR (NZCV), FPSR and FPCR:
2268 STR x2, [sp, #(2 * 16)]
2269 STR x1, [sp, #(1 * 16)]
2270 STR x0, [sp, #(0 * 16)]
2273 p
+= emit_mrs (p
, x2
, NZCV
);
2274 p
+= emit_mrs (p
, x1
, FPSR
);
2275 p
+= emit_mrs (p
, x0
, FPCR
);
2276 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
2277 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
2278 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2280 /* Push the collecting_t object. It consist of the address of the
2281 tracepoint and an ID for the current thread. We get the latter by
2282 reading the tpidr_el0 system register. It corresponds to the
2283 NT_ARM_TLS register accessible with ptrace.
2290 STP x0, x1, [sp, #-16]!
2294 p
+= emit_mov_addr (p
, x0
, tpoint
);
2295 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
2296 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
2300 The shared memory for the lock is at lockaddr. It will hold zero
2301 if no-one is holding the lock, otherwise it contains the address of
2302 the collecting_t object on the stack of the thread which acquired it.
2304 At this stage, the stack pointer points to this thread's collecting_t
2307 We use the following registers:
2308 - x0: Address of the lock.
2309 - x1: Pointer to collecting_t object.
2310 - x2: Scratch register.
2316 ; Trigger an event local to this core. So the following WFE
2317 ; instruction is ignored.
2320 ; Wait for an event. The event is triggered by either the SEVL
2321 ; or STLR instructions (store release).
2324 ; Atomically read at lockaddr. This marks the memory location as
2325 ; exclusive. This instruction also has memory constraints which
2326 ; make sure all previous data reads and writes are done before
2330 ; Try again if another thread holds the lock.
2333 ; We can lock it! Write the address of the collecting_t object.
2334 ; This instruction will fail if the memory location is not marked
2335 ; as exclusive anymore. If it succeeds, it will remove the
2336 ; exclusive mark on the memory location. This way, if another
2337 ; thread executes this instruction before us, we will fail and try
2344 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2345 p
+= emit_mov (p
, x1
, register_operand (sp
));
2349 p
+= emit_ldaxr (p
, x2
, x0
);
2350 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2351 p
+= emit_stxr (p
, w2
, x1
, x0
);
2352 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2354 /* Call collector (struct tracepoint *, unsigned char *):
2359 ; Saved registers start after the collecting_t object.
2362 ; We use an intra-procedure-call scratch register.
2363 MOV ip0, #(collector)
2366 ; And call back to C!
2371 p
+= emit_mov_addr (p
, x0
, tpoint
);
2372 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2374 p
+= emit_mov_addr (p
, ip0
, collector
);
2375 p
+= emit_blr (p
, ip0
);
2377 /* Release the lock.
2382 ; This instruction is a normal store with memory ordering
2383 ; constraints. Thanks to this we do not have to put a data
2384 ; barrier instruction to make sure all data read and writes are done
2385 ; before this instruction is executed. Furthermore, this instruction
2386 ; will trigger an event, letting other threads know they can grab
2391 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2392 p
+= emit_stlr (p
, xzr
, x0
);
2394 /* Free collecting_t object:
2399 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2401 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2402 registers from the stack.
2404 LDR x2, [sp, #(2 * 16)]
2405 LDR x1, [sp, #(1 * 16)]
2406 LDR x0, [sp, #(0 * 16)]
2412 ADD sp, sp #(5 * 16)
2415 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2416 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2417 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2418 p
+= emit_msr (p
, NZCV
, x2
);
2419 p
+= emit_msr (p
, FPSR
, x1
);
2420 p
+= emit_msr (p
, FPCR
, x0
);
2422 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2424 /* Pop general purpose registers:
2428 LDR x30, [sp, #(30 * 16)]
2430 ADD sp, sp, #(31 * 16)
2433 for (i
= 0; i
<= 30; i
+= 1)
2434 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2435 offset_memory_operand (i
* 16));
2436 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2438 /* Pop SIMD&FP registers:
2442 LDP q30, q31, [sp, #(30 * 16)]
2444 ADD sp, sp, #(32 * 16)
2447 for (i
= 0; i
<= 30; i
+= 2)
2448 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2449 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2451 /* Write the code into the inferior memory. */
2452 append_insns (&buildaddr
, p
- buf
, buf
);
2454 /* Now emit the relocated instruction. */
2455 *adjusted_insn_addr
= buildaddr
;
2456 target_read_uint32 (tpaddr
, &insn
);
2458 insn_data
.base
.insn_addr
= tpaddr
;
2459 insn_data
.new_addr
= buildaddr
;
2460 insn_data
.insn_ptr
= buf
;
2462 aarch64_relocate_instruction (insn
, &visitor
,
2463 (struct aarch64_insn_data
*) &insn_data
);
2465 /* We may not have been able to relocate the instruction. */
2466 if (insn_data
.insn_ptr
== buf
)
2469 "E.Could not relocate instruction from %s to %s.",
2470 core_addr_to_string_nz (tpaddr
),
2471 core_addr_to_string_nz (buildaddr
));
2475 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2476 *adjusted_insn_addr_end
= buildaddr
;
2478 /* Go back to the start of the buffer. */
2481 /* Emit a branch back from the jump pad. */
2482 offset
= (tpaddr
+ orig_size
- buildaddr
);
2483 if (!can_encode_int32 (offset
, 28))
2486 "E.Jump back from jump pad too far from tracepoint "
2487 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2492 p
+= emit_b (p
, 0, offset
);
2493 append_insns (&buildaddr
, p
- buf
, buf
);
2495 /* Give the caller a branch instruction into the jump pad. */
2496 offset
= (*jump_entry
- tpaddr
);
2497 if (!can_encode_int32 (offset
, 28))
2500 "E.Jump pad too far from tracepoint "
2501 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2506 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2507 *jjump_pad_insn_size
= 4;
2509 /* Return the end address of our pad. */
2510 *jump_entry
= buildaddr
;
2515 /* Helper function writing LEN instructions from START into
2516 current_insn_ptr. */
2519 emit_ops_insns (const uint32_t *start
, int len
)
2521 CORE_ADDR buildaddr
= current_insn_ptr
;
2523 threads_debug_printf ("Adding %d instrucions at %s",
2524 len
, paddress (buildaddr
));
2526 append_insns (&buildaddr
, len
, start
);
2527 current_insn_ptr
= buildaddr
;
2530 /* Pop a register from the stack. */
2533 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2535 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2538 /* Push a register on the stack. */
2541 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2543 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2546 /* Implementation of emit_ops method "emit_prologue". */
2549 aarch64_emit_prologue (void)
2554 /* This function emit a prologue for the following function prototype:
2556 enum eval_result_type f (unsigned char *regs,
2559 The first argument is a buffer of raw registers. The second
2560 argument is the result of
2561 evaluating the expression, which will be set to whatever is on top of
2562 the stack at the end.
2564 The stack set up by the prologue is as such:
2566 High *------------------------------------------------------*
2569 | x1 (ULONGEST *value) |
2570 | x0 (unsigned char *regs) |
2571 Low *------------------------------------------------------*
2573 As we are implementing a stack machine, each opcode can expand the
2574 stack so we never know how far we are from the data saved by this
2575 prologue. In order to be able refer to value and regs later, we save
2576 the current stack pointer in the frame pointer. This way, it is not
2577 clobbered when calling C functions.
2579 Finally, throughout every operation, we are using register x0 as the
2580 top of the stack, and x1 as a scratch register. */
2582 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2583 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2584 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2586 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2589 emit_ops_insns (buf
, p
- buf
);
2592 /* Implementation of emit_ops method "emit_epilogue". */
2595 aarch64_emit_epilogue (void)
2600 /* Store the result of the expression (x0) in *value. */
2601 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2602 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2603 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2605 /* Restore the previous state. */
2606 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2607 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2609 /* Return expr_eval_no_error. */
2610 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2611 p
+= emit_ret (p
, lr
);
2613 emit_ops_insns (buf
, p
- buf
);
2616 /* Implementation of emit_ops method "emit_add". */
2619 aarch64_emit_add (void)
2624 p
+= emit_pop (p
, x1
);
2625 p
+= emit_add (p
, x0
, x1
, register_operand (x0
));
2627 emit_ops_insns (buf
, p
- buf
);
2630 /* Implementation of emit_ops method "emit_sub". */
2633 aarch64_emit_sub (void)
2638 p
+= emit_pop (p
, x1
);
2639 p
+= emit_sub (p
, x0
, x1
, register_operand (x0
));
2641 emit_ops_insns (buf
, p
- buf
);
2644 /* Implementation of emit_ops method "emit_mul". */
2647 aarch64_emit_mul (void)
2652 p
+= emit_pop (p
, x1
);
2653 p
+= emit_mul (p
, x0
, x1
, x0
);
2655 emit_ops_insns (buf
, p
- buf
);
2658 /* Implementation of emit_ops method "emit_lsh". */
2661 aarch64_emit_lsh (void)
2666 p
+= emit_pop (p
, x1
);
2667 p
+= emit_lslv (p
, x0
, x1
, x0
);
2669 emit_ops_insns (buf
, p
- buf
);
2672 /* Implementation of emit_ops method "emit_rsh_signed". */
2675 aarch64_emit_rsh_signed (void)
2680 p
+= emit_pop (p
, x1
);
2681 p
+= emit_asrv (p
, x0
, x1
, x0
);
2683 emit_ops_insns (buf
, p
- buf
);
2686 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2689 aarch64_emit_rsh_unsigned (void)
2694 p
+= emit_pop (p
, x1
);
2695 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2697 emit_ops_insns (buf
, p
- buf
);
2700 /* Implementation of emit_ops method "emit_ext". */
2703 aarch64_emit_ext (int arg
)
2708 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2710 emit_ops_insns (buf
, p
- buf
);
2713 /* Implementation of emit_ops method "emit_log_not". */
2716 aarch64_emit_log_not (void)
2721 /* If the top of the stack is 0, replace it with 1. Else replace it with
2724 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2725 p
+= emit_cset (p
, x0
, EQ
);
2727 emit_ops_insns (buf
, p
- buf
);
2730 /* Implementation of emit_ops method "emit_bit_and". */
2733 aarch64_emit_bit_and (void)
2738 p
+= emit_pop (p
, x1
);
2739 p
+= emit_and (p
, x0
, x0
, x1
);
2741 emit_ops_insns (buf
, p
- buf
);
2744 /* Implementation of emit_ops method "emit_bit_or". */
2747 aarch64_emit_bit_or (void)
2752 p
+= emit_pop (p
, x1
);
2753 p
+= emit_orr (p
, x0
, x0
, x1
);
2755 emit_ops_insns (buf
, p
- buf
);
2758 /* Implementation of emit_ops method "emit_bit_xor". */
2761 aarch64_emit_bit_xor (void)
2766 p
+= emit_pop (p
, x1
);
2767 p
+= emit_eor (p
, x0
, x0
, x1
);
2769 emit_ops_insns (buf
, p
- buf
);
2772 /* Implementation of emit_ops method "emit_bit_not". */
2775 aarch64_emit_bit_not (void)
2780 p
+= emit_mvn (p
, x0
, x0
);
2782 emit_ops_insns (buf
, p
- buf
);
2785 /* Implementation of emit_ops method "emit_equal". */
2788 aarch64_emit_equal (void)
2793 p
+= emit_pop (p
, x1
);
2794 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2795 p
+= emit_cset (p
, x0
, EQ
);
2797 emit_ops_insns (buf
, p
- buf
);
2800 /* Implementation of emit_ops method "emit_less_signed". */
2803 aarch64_emit_less_signed (void)
2808 p
+= emit_pop (p
, x1
);
2809 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2810 p
+= emit_cset (p
, x0
, LT
);
2812 emit_ops_insns (buf
, p
- buf
);
2815 /* Implementation of emit_ops method "emit_less_unsigned". */
2818 aarch64_emit_less_unsigned (void)
2823 p
+= emit_pop (p
, x1
);
2824 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2825 p
+= emit_cset (p
, x0
, LO
);
2827 emit_ops_insns (buf
, p
- buf
);
2830 /* Implementation of emit_ops method "emit_ref". */
2833 aarch64_emit_ref (int size
)
2841 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2844 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2847 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2850 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2853 /* Unknown size, bail on compilation. */
2858 emit_ops_insns (buf
, p
- buf
);
2861 /* Implementation of emit_ops method "emit_if_goto". */
2864 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2869 /* The Z flag is set or cleared here. */
2870 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2871 /* This instruction must not change the Z flag. */
2872 p
+= emit_pop (p
, x0
);
2873 /* Branch over the next instruction if x0 == 0. */
2874 p
+= emit_bcond (p
, EQ
, 8);
2876 /* The NOP instruction will be patched with an unconditional branch. */
2878 *offset_p
= (p
- buf
) * 4;
2883 emit_ops_insns (buf
, p
- buf
);
2886 /* Implementation of emit_ops method "emit_goto". */
2889 aarch64_emit_goto (int *offset_p
, int *size_p
)
2894 /* The NOP instruction will be patched with an unconditional branch. */
2901 emit_ops_insns (buf
, p
- buf
);
2904 /* Implementation of emit_ops method "write_goto_address". */
2907 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2911 emit_b (&insn
, 0, to
- from
);
2912 append_insns (&from
, 1, &insn
);
2915 /* Implementation of emit_ops method "emit_const". */
2918 aarch64_emit_const (LONGEST num
)
2923 p
+= emit_mov_addr (p
, x0
, num
);
2925 emit_ops_insns (buf
, p
- buf
);
2928 /* Implementation of emit_ops method "emit_call". */
2931 aarch64_emit_call (CORE_ADDR fn
)
2936 p
+= emit_mov_addr (p
, ip0
, fn
);
2937 p
+= emit_blr (p
, ip0
);
2939 emit_ops_insns (buf
, p
- buf
);
2942 /* Implementation of emit_ops method "emit_reg". */
2945 aarch64_emit_reg (int reg
)
2950 /* Set x0 to unsigned char *regs. */
2951 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2952 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2953 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2955 emit_ops_insns (buf
, p
- buf
);
2957 aarch64_emit_call (get_raw_reg_func_addr ());
2960 /* Implementation of emit_ops method "emit_pop". */
2963 aarch64_emit_pop (void)
2968 p
+= emit_pop (p
, x0
);
2970 emit_ops_insns (buf
, p
- buf
);
2973 /* Implementation of emit_ops method "emit_stack_flush". */
2976 aarch64_emit_stack_flush (void)
2981 p
+= emit_push (p
, x0
);
2983 emit_ops_insns (buf
, p
- buf
);
2986 /* Implementation of emit_ops method "emit_zero_ext". */
2989 aarch64_emit_zero_ext (int arg
)
2994 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2996 emit_ops_insns (buf
, p
- buf
);
2999 /* Implementation of emit_ops method "emit_swap". */
3002 aarch64_emit_swap (void)
3007 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
3008 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
3009 p
+= emit_mov (p
, x0
, register_operand (x1
));
3011 emit_ops_insns (buf
, p
- buf
);
3014 /* Implementation of emit_ops method "emit_stack_adjust". */
3017 aarch64_emit_stack_adjust (int n
)
3019 /* This is not needed with our design. */
3023 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
3025 emit_ops_insns (buf
, p
- buf
);
3028 /* Implementation of emit_ops method "emit_int_call_1". */
3031 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3036 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3038 emit_ops_insns (buf
, p
- buf
);
3040 aarch64_emit_call (fn
);
3043 /* Implementation of emit_ops method "emit_void_call_2". */
3046 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3051 /* Push x0 on the stack. */
3052 aarch64_emit_stack_flush ();
3054 /* Setup arguments for the function call:
3057 x1: top of the stack
3062 p
+= emit_mov (p
, x1
, register_operand (x0
));
3063 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3065 emit_ops_insns (buf
, p
- buf
);
3067 aarch64_emit_call (fn
);
3070 aarch64_emit_pop ();
3073 /* Implementation of emit_ops method "emit_eq_goto". */
3076 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
3081 p
+= emit_pop (p
, x1
);
3082 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3083 /* Branch over the next instruction if x0 != x1. */
3084 p
+= emit_bcond (p
, NE
, 8);
3085 /* The NOP instruction will be patched with an unconditional branch. */
3087 *offset_p
= (p
- buf
) * 4;
3092 emit_ops_insns (buf
, p
- buf
);
3095 /* Implementation of emit_ops method "emit_ne_goto". */
3098 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
3103 p
+= emit_pop (p
, x1
);
3104 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3105 /* Branch over the next instruction if x0 == x1. */
3106 p
+= emit_bcond (p
, EQ
, 8);
3107 /* The NOP instruction will be patched with an unconditional branch. */
3109 *offset_p
= (p
- buf
) * 4;
3114 emit_ops_insns (buf
, p
- buf
);
3117 /* Implementation of emit_ops method "emit_lt_goto". */
3120 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
3125 p
+= emit_pop (p
, x1
);
3126 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3127 /* Branch over the next instruction if x0 >= x1. */
3128 p
+= emit_bcond (p
, GE
, 8);
3129 /* The NOP instruction will be patched with an unconditional branch. */
3131 *offset_p
= (p
- buf
) * 4;
3136 emit_ops_insns (buf
, p
- buf
);
3139 /* Implementation of emit_ops method "emit_le_goto". */
3142 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
3147 p
+= emit_pop (p
, x1
);
3148 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3149 /* Branch over the next instruction if x0 > x1. */
3150 p
+= emit_bcond (p
, GT
, 8);
3151 /* The NOP instruction will be patched with an unconditional branch. */
3153 *offset_p
= (p
- buf
) * 4;
3158 emit_ops_insns (buf
, p
- buf
);
3161 /* Implementation of emit_ops method "emit_gt_goto". */
3164 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
3169 p
+= emit_pop (p
, x1
);
3170 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3171 /* Branch over the next instruction if x0 <= x1. */
3172 p
+= emit_bcond (p
, LE
, 8);
3173 /* The NOP instruction will be patched with an unconditional branch. */
3175 *offset_p
= (p
- buf
) * 4;
3180 emit_ops_insns (buf
, p
- buf
);
3183 /* Implementation of emit_ops method "emit_ge_got". */
3186 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
3191 p
+= emit_pop (p
, x1
);
3192 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3193 /* Branch over the next instruction if x0 <= x1. */
3194 p
+= emit_bcond (p
, LT
, 8);
3195 /* The NOP instruction will be patched with an unconditional branch. */
3197 *offset_p
= (p
- buf
) * 4;
3202 emit_ops_insns (buf
, p
- buf
);
3205 static struct emit_ops aarch64_emit_ops_impl
=
3207 aarch64_emit_prologue
,
3208 aarch64_emit_epilogue
,
3213 aarch64_emit_rsh_signed
,
3214 aarch64_emit_rsh_unsigned
,
3216 aarch64_emit_log_not
,
3217 aarch64_emit_bit_and
,
3218 aarch64_emit_bit_or
,
3219 aarch64_emit_bit_xor
,
3220 aarch64_emit_bit_not
,
3222 aarch64_emit_less_signed
,
3223 aarch64_emit_less_unsigned
,
3225 aarch64_emit_if_goto
,
3227 aarch64_write_goto_address
,
3232 aarch64_emit_stack_flush
,
3233 aarch64_emit_zero_ext
,
3235 aarch64_emit_stack_adjust
,
3236 aarch64_emit_int_call_1
,
3237 aarch64_emit_void_call_2
,
3238 aarch64_emit_eq_goto
,
3239 aarch64_emit_ne_goto
,
3240 aarch64_emit_lt_goto
,
3241 aarch64_emit_le_goto
,
3242 aarch64_emit_gt_goto
,
3243 aarch64_emit_ge_got
,
3246 /* Implementation of target ops method "emit_ops". */
3249 aarch64_target::emit_ops ()
3251 return &aarch64_emit_ops_impl
;
3254 /* Implementation of target ops method
3255 "get_min_fast_tracepoint_insn_len". */
3258 aarch64_target::get_min_fast_tracepoint_insn_len ()
3263 /* Implementation of linux target ops method "low_supports_range_stepping". */
3266 aarch64_target::low_supports_range_stepping ()
3271 /* Implementation of target ops method "sw_breakpoint_from_kind". */
3274 aarch64_target::sw_breakpoint_from_kind (int kind
, int *size
)
3276 if (is_64bit_tdesc ())
3278 *size
= aarch64_breakpoint_len
;
3279 return aarch64_breakpoint
;
3282 return arm_sw_breakpoint_from_kind (kind
, size
);
3285 /* Implementation of target ops method "breakpoint_kind_from_pc". */
3288 aarch64_target::breakpoint_kind_from_pc (CORE_ADDR
*pcptr
)
3290 if (is_64bit_tdesc ())
3291 return aarch64_breakpoint_len
;
3293 return arm_breakpoint_kind_from_pc (pcptr
);
3296 /* Implementation of the target ops method
3297 "breakpoint_kind_from_current_state". */
3300 aarch64_target::breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
)
3302 if (is_64bit_tdesc ())
3303 return aarch64_breakpoint_len
;
3305 return arm_breakpoint_kind_from_current_state (pcptr
);
3308 /* Returns true if memory tagging is supported. */
3310 aarch64_target::supports_memory_tagging ()
3312 if (current_thread
== NULL
)
3314 /* We don't have any processes running, so don't attempt to
3315 use linux_get_hwcap2 as it will try to fetch the current
3316 thread id. Instead, just fetch the auxv from the self
3318 #ifdef HAVE_GETAUXVAL
3319 return (getauxval (AT_HWCAP2
) & HWCAP2_MTE
) != 0;
3325 return (linux_get_hwcap2 (8) & HWCAP2_MTE
) != 0;
3329 aarch64_target::fetch_memtags (CORE_ADDR address
, size_t len
,
3330 gdb::byte_vector
&tags
, int type
)
3332 /* Allocation tags are per-process, so any tid is fine. */
3333 int tid
= lwpid_of (current_thread
);
3335 /* Allocation tag? */
3336 if (type
== static_cast <int> (aarch64_memtag_type::mte_allocation
))
3337 return aarch64_mte_fetch_memtags (tid
, address
, len
, tags
);
3343 aarch64_target::store_memtags (CORE_ADDR address
, size_t len
,
3344 const gdb::byte_vector
&tags
, int type
)
3346 /* Allocation tags are per-process, so any tid is fine. */
3347 int tid
= lwpid_of (current_thread
);
3349 /* Allocation tag? */
3350 if (type
== static_cast <int> (aarch64_memtag_type::mte_allocation
))
3351 return aarch64_mte_store_memtags (tid
, address
, len
, tags
);
3356 /* The linux target ops object. */
3358 linux_process_target
*the_linux_target
= &the_aarch64_target
;
3361 initialize_low_arch (void)
3363 initialize_low_arch_aarch32 ();
3365 initialize_regsets_info (&aarch64_regsets_info
);