gprofng/common/hwc_cpus.h

   1 /* Copyright (C) 2021-2024 Free Software Foundation, Inc.
   2    Contributed by Oracle.
   3
   4    This file is part of GNU Binutils.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 /* Hardware counter profiling: cpu types */
  22
  23 #ifndef __HWC_CPUS_H
  24 #define __HWC_CPUS_H
  25
  26 typedef struct
  27 {
  28   int cpu_cnt;
  29   int cpu_clk_freq;
  30   int cpu_model;
  31   int cpu_family;
  32   int cpu_vendor;
  33   char *cpu_vendorstr;
  34   char *cpu_modelstr;
  35 } cpu_info_t;
  36
  37 extern cpu_info_t *read_cpuinfo();
  38
  39 #define MAX_PICS    20 /* Max # of HW ctrs that can be enabled simultaneously */
  40
  41   /* type for specifying CPU register number */
  42   typedef int regno_t;
  43 #define REGNO_ANY       ((regno_t)-1)
  44 #define REGNO_INVALID   ((regno_t)-2)
  45
  46   /* --- Utilities for use with regno_t and reg_list[] --- */
  47 #define REG_LIST_IS_EMPTY(reg_list) (!(reg_list) || (reg_list)[0] == REGNO_ANY)
  48 #define REG_LIST_EOL(regno)         ((regno)==REGNO_ANY)
  49 #define REG_LIST_SINGLE_VALID_ENTRY(reg_list) \
  50   (((reg_list) && (reg_list)[1] == REGNO_ANY && \
  51       (reg_list)[0] != REGNO_ANY ) ? (reg_list)[0] : REGNO_ANY)
  52
  53   /* enum for specifying unknown or uninitialized CPU */
  54   enum
  55   {
  56     CPUVER_GENERIC = 0,
  57     CPUVER_UNDEFINED = -1
  58   };
  59
  60   // Note: changing an values below may make older HWC experiments unreadable.
  61   // --- Sun/Oracle SPARC ---
  62 #define CPC_ULTRA1              1000
  63 #define CPC_ULTRA2              1001
  64 #define CPC_ULTRA3              1002
  65 #define CPC_ULTRA3_PLUS         1003
  66 #define CPC_ULTRA3_I            1004
  67 #define CPC_ULTRA4_PLUS         1005 /* Panther */
  68 #define CPC_ULTRA4              1017 /* Jaguar */
  69 #define CPC_ULTRA_T1            1100 /* Niagara1 */
  70 #define CPC_ULTRA_T2            1101 /* Niagara2 */
  71 #define CPC_ULTRA_T2P           1102
  72 #define CPC_ULTRA_T3            1103
  73 #define CPC_SPARC_T4            1104
  74 #define CPC_SPARC_T5            1110
  75 #define CPC_SPARC_T6            1120
  76 // #define CPC_SPARC_T7         1130 // use CPC_SPARC_M7
  77 #define CPC_SPARC_M4            1204 /* Obsolete */
  78 #define CPC_SPARC_M5            1210
  79 #define CPC_SPARC_M6            1220
  80 #define CPC_SPARC_M7            1230
  81 #define CPC_SPARC_M8            1240
  82
  83   // --- Intel ---
  84   // Pentium
  85 #define CPC_PENTIUM             2000
  86 #define CPC_PENTIUM_MMX         2001
  87 #define CPC_PENTIUM_PRO         2002
  88 #define CPC_PENTIUM_PRO_MMX     2003
  89 #define CPC_PENTIUM_4           2017
  90 #define CPC_PENTIUM_4_HT        2027
  91
  92   // Core Microarchitecture (Merom/Menryn)
  93 #define CPC_INTEL_CORE2         2028
  94 #define CPC_INTEL_NEHALEM       2040
  95 #define CPC_INTEL_WESTMERE      2042
  96 #define CPC_INTEL_SANDYBRIDGE   2045
  97 #define CPC_INTEL_IVYBRIDGE     2047
  98 #define CPC_INTEL_ATOM          2050 /* Atom*/
  99 #define CPC_INTEL_HASWELL       2060
 100 #define CPC_INTEL_BROADWELL     2070
 101 #define CPC_INTEL_SKYLAKE       2080
 102 #define CPC_INTEL_UNKNOWN       2499
 103 #define CPC_AMD_K8C             2500 /* Opteron, Athlon... */
 104 #define CPC_AMD_FAM_10H         2501 /* Barcelona, Shanghai... */
 105 #define CPC_AMD_FAM_11H         2502 /* Griffin... */
 106 #define CPC_AMD_FAM_15H         2503
 107 #define CPC_AMD_Authentic       2504
 108
 109 #define CPC_KPROF               3003 // OBSOLETE (To support 12.3 and earlier)
 110 #define CPC_FOX                 3004 /* pseudo-chip */
 111
 112   // --- Fujitsu ---
 113 #define CPC_SPARC64_III     3000
 114 #define CPC_SPARC64_V       3002
 115 #define CPC_SPARC64_VI      4003 /* OPL-C */
 116 #define CPC_SPARC64_VII     4004 /* Jupiter */
 117 #define CPC_SPARC64_X       4006 /* Athena */
 118 #define CPC_SPARC64_XII     4010 /* Athena++ */
 119
 120 // aarch64. Constants from tools/arch/arm64/include/asm/cputype.h
 121 // in https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
 122 enum {
 123     ARM_CPU_IMP_ARM     = 0x41,
 124     ARM_CPU_IMP_BRCM    = 0x42,
 125     ARM_CPU_IMP_CAVIUM  = 0x43,
 126     ARM_CPU_IMP_FUJITSU = 0x46,
 127     ARM_CPU_IMP_NVIDIA  = 0x4E,
 128     ARM_CPU_IMP_HISI    = 0x48,
 129     ARM_CPU_IMP_APM     = 0x50,
 130     ARM_CPU_IMP_QCOM    = 0x51,
 131     ARM_CPU_IMP_APPLE   = 0x61,
 132     ARM_CPU_IMP_AMPERE  = 0xC0
 133 };
 134
 135 #define AARCH64_VENDORSTR_ARM   "ARM"
 136
 137   /* strings below must match those returned by cpc_getcpuver() */
 138   typedef struct
 139   {
 140     int cpc2_cpuver;
 141     const char * cpc2_cciname;
 142   } libcpc2_cpu_lookup_t;
 143 #define LIBCPC2_CPU_LOOKUP_LIST \
 144   {CPC_AMD_K8C               , "AMD Opteron & Athlon64"}, \
 145   {CPC_AMD_FAM_10H           , "AMD Family 10h"}, \
 146   {CPC_AMD_FAM_11H           , "AMD Family 11h"}, \
 147   {CPC_AMD_FAM_15H           , "AMD Family 15h Model 01h"}, \
 148   {CPC_AMD_FAM_15H           , "AMD Family 15h Model 02h"},/*future*/ \
 149   {CPC_AMD_FAM_15H           , "AMD Family 15h Model 03h"},/*future*/ \
 150   {CPC_PENTIUM_4_HT          , "Pentium 4 with HyperThreading"}, \
 151   {CPC_PENTIUM_4             , "Pentium 4"}, \
 152   {CPC_PENTIUM_PRO_MMX       , "Pentium Pro with MMX, Pentium II"}, \
 153   {CPC_PENTIUM_PRO           , "Pentium Pro, Pentium II"}, \
 154   {CPC_PENTIUM_MMX           , "Pentium with MMX"}, \
 155   {CPC_PENTIUM               , "Pentium"}, \
 156   {CPC_INTEL_CORE2           , "Core Microarchitecture"}, \
 157     /* Merom:  F6M15: Clovertown, Kentsfield, Conroe, Merom, Woodcrest */ \
 158     /* Merom:  F6M22: Merom Conroe */ \
 159     /* Penryn: F6M23: Yorkfield, Wolfdale, Penryn, Harpertown */ \
 160     /* Penryn: F6M29: Dunnington */ \
 161   {CPC_INTEL_NEHALEM         , "Intel Arch PerfMon v3 on Family 6 Model 26"},/*Bloomfield, Nehalem EP*/ \
 162   {CPC_INTEL_NEHALEM         , "Intel Arch PerfMon v3 on Family 6 Model 30"},/*Clarksfield, Lynnfield, Jasper Forest*/ \
 163   {CPC_INTEL_NEHALEM         , "Intel Arch PerfMon v3 on Family 6 Model 31"},/*(TBD)*/ \
 164   {CPC_INTEL_NEHALEM         , "Intel Arch PerfMon v3 on Family 6 Model 46"},/*Nehalem EX*/ \
 165   {CPC_INTEL_WESTMERE        , "Intel Arch PerfMon v3 on Family 6 Model 37"},/*Arrandale, Clarskdale*/ \
 166   {CPC_INTEL_WESTMERE        , "Intel Arch PerfMon v3 on Family 6 Model 44"},/*Gulftown, Westmere EP*/ \
 167   {CPC_INTEL_WESTMERE        , "Intel Arch PerfMon v3 on Family 6 Model 47"},/*Westmere EX*/ \
 168   {CPC_INTEL_SANDYBRIDGE     , "Intel Arch PerfMon v3 on Family 6 Model 42"},/*Sandy Bridge*/ \
 169   {CPC_INTEL_SANDYBRIDGE     , "Intel Arch PerfMon v3 on Family 6 Model 45"},/*Sandy Bridge E, SandyBridge-EN, SandyBridge EP*/ \
 170   {CPC_INTEL_IVYBRIDGE       , "Intel Arch PerfMon v3 on Family 6 Model 58"},/*Ivy Bridge*/ \
 171   {CPC_INTEL_IVYBRIDGE       , "Intel Arch PerfMon v3 on Family 6 Model 62"},/*(TBD)*/ \
 172   {CPC_INTEL_ATOM            , "Intel Arch PerfMon v3 on Family 6 Model 28"},/*Atom*/ \
 173   {CPC_INTEL_HASWELL         , "Intel Arch PerfMon v3 on Family 6 Model 60"},/*Haswell*/ \
 174   {CPC_INTEL_HASWELL         , "Intel Arch PerfMon v3 on Family 6 Model 63"},/*Haswell*/ \
 175   {CPC_INTEL_HASWELL         , "Intel Arch PerfMon v3 on Family 6 Model 69"},/*Haswell*/ \
 176   {CPC_INTEL_HASWELL         , "Intel Arch PerfMon v3 on Family 6 Model 70"},/*Haswell*/ \
 177   {CPC_INTEL_BROADWELL       , "Intel Arch PerfMon v3 on Family 6 Model 61"},/*Broadwell*/ \
 178   {CPC_INTEL_BROADWELL       , "Intel Arch PerfMon v3 on Family 6 Model 71"},/*Broadwell*/ \
 179   {CPC_INTEL_BROADWELL       , "Intel Arch PerfMon v3 on Family 6 Model 79"},/*Broadwell*/ \
 180   {CPC_INTEL_BROADWELL       , "Intel Arch PerfMon v3 on Family 6 Model 86"},/*Broadwell*/ \
 181   {CPC_INTEL_SKYLAKE         , "Intel Arch PerfMon v4 on Family 6 Model 78"},/*Skylake*/ \
 182   {CPC_INTEL_SKYLAKE         , "Intel Arch PerfMon v4 on Family 6 Model 85"},/*Skylake*/ \
 183   {CPC_INTEL_SKYLAKE         , "Intel Arch PerfMon v4 on Family 6 Model 94"},/*Skylake*/ \
 184   {CPC_INTEL_UNKNOWN         , "Intel Arch PerfMon"},/*Not yet in table*/ \
 185   {CPC_SPARC64_III           , "SPARC64 III"/*?*/}, \
 186   {CPC_SPARC64_V             , "SPARC64 V"/*?*/}, \
 187   {CPC_SPARC64_VI            , "SPARC64 VI"}, \
 188   {CPC_SPARC64_VII           , "SPARC64 VI & VII"}, \
 189   {CPC_SPARC64_X             , "SPARC64 X"}, \
 190   {CPC_SPARC64_XII           , "SPARC64 XII"}, \
 191   {CPC_ULTRA_T1              , "UltraSPARC T1"}, \
 192   {CPC_ULTRA_T2              , "UltraSPARC T2"}, \
 193   {CPC_ULTRA_T2P             , "UltraSPARC T2+"}, \
 194   {CPC_ULTRA_T3              , "SPARC T3"},  \
 195   {CPC_SPARC_T4              , "SPARC T4"},  \
 196   {CPC_SPARC_M4              , "SPARC M4"},  \
 197   {CPC_SPARC_T5              , "SPARC T5"},  \
 198   {CPC_SPARC_M5              , "SPARC M5"},  \
 199   {CPC_SPARC_T6              , "SPARC T6"},  \
 200   {CPC_SPARC_M6              , "SPARC M6"},  \
 201   {CPC_SPARC_M7              , "SPARC T7"},  \
 202   {CPC_SPARC_M7              , "SPARC 3e40"},  \
 203   {CPC_SPARC_M7              , "SPARC M7"},  \
 204   {CPC_SPARC_M8              , "SPARC 3e50"},  \
 205   {CPC_ULTRA4_PLUS           , "UltraSPARC IV+"}, \
 206   {CPC_ULTRA4                , "UltraSPARC IV"}, \
 207   {CPC_ULTRA3_I              , "UltraSPARC IIIi"}, \
 208   {CPC_ULTRA3_I              , "UltraSPARC IIIi & IIIi+"}, \
 209   {CPC_ULTRA3_PLUS           , "UltraSPARC III+"}, \
 210   {CPC_ULTRA3_PLUS           , "UltraSPARC III+ & IV"}, \
 211   {CPC_ULTRA3                , "UltraSPARC III"}, \
 212   {CPC_ULTRA2                , "UltraSPARC I&II"}, \
 213   {CPC_ULTRA1                , "UltraSPARC I&II"}, \
 214   {ARM_CPU_IMP_APM           , AARCH64_VENDORSTR_ARM}, \
 215   {CPC_AMD_Authentic         , "AuthenticAMD"}, \
 216   {0, NULL}
 217   /* init like this:
 218      static libcpc2_cpu_lookup_t cpu_table[]={LIBCPC2_CPU_LOOKUP_LIST};
 219    */
 220 #endif