include/opcode/ChangeLog

   1 2009-09-29  DJ Delorie  <dj@redhat.com>
   2
   3         * rx.h: New file.
   4
   5 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
   6
   7         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
   8
   9 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  10
  11         * ppc.h (PPC_OPCODE_PPCA2): New.
  12
  13 2009-09-05  Martin Thuresson  <martin@mtme.org>
  14
  15         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  16
  17 2009-08-29  Martin Thuresson  <martin@mtme.org>
  18
  19         * tic30.h (template): Rename type template to
  20         insn_template. Updated code to use new name.
  21         * tic54x.h (template): Rename type template to
  22         insn_template.
  23
  24 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  25
  26         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  27
  28 2009-06-11  Anthony Green  <green@moxielogic.com>
  29
  30         * moxie.h (MOXIE_F3_PCREL): Define.
  31         (moxie_form3_opc_info): Grow.
  32
  33 2009-06-06  Anthony Green  <green@moxielogic.com>
  34
  35         * moxie.h (MOXIE_F1_M): Define.
  36
  37 2009-04-15  Anthony Green  <green@moxielogic.com>
  38
  39         * moxie.h: Created.
  40
  41 2009-04-06  DJ Delorie  <dj@redhat.com>
  42
  43         * h8300.h: Add relaxation attributes to MOVA opcodes.
  44
  45 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  46
  47         * ppc.h (ppc_parse_cpu): Declare.
  48
  49 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  50
  51         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  52         and _IMM11 for mbitclr and mbitset.
  53         * score-datadep.h: Update dependency information.
  54
  55 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  56
  57         * ppc.h (PPC_OPCODE_POWER7): New.
  58
  59 2009-02-06  Doug Evans  <dje@google.com>
  60
  61         * i386.h: Add comment regarding sse* insns and prefixes.
  62
  63 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
  64
  65         * mips.h (INSN_XLR): Define.
  66         (INSN_CHIP_MASK): Update.
  67         (CPU_XLR): Define.
  68         (OPCODE_IS_MEMBER): Update.
  69         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  70
  71 2009-01-28  Doug Evans  <dje@google.com>
  72
  73         * opcode/i386.h: Add multiple inclusion protection.
  74         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  75         (EDI_REG_NUM): New macros.
  76         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  77         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  78         (REX_PREFIX_P): New macro.
  79
  80 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  81
  82         * ppc.h (struct powerpc_opcode): New field "deprecated".
  83         (PPC_OPCODE_NOPOWER4): Delete.
  84
  85 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  86
  87         * mips.h: Define CPU_R14000, CPU_R16000.
  88         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  89
  90 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  91
  92         * arm.h (FPU_NEON_FP16): New.
  93         (FPU_ARCH_NEON_FP16): New.
  94
  95 2008-11-06  Chao-ying Fu  <fu@mips.com>
  96
  97         * mips.h: Doucument '1' for 5-bit sync type.
  98
  99 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 102         IA64_RS_CR.
 103
 104 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 105
 106         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 107
 108 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 109
 110         * ppc.h (PPC_OPCODE_405): Define.
 111         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 112
 113 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 114
 115         * ppc.h (ppc_cpu_t): New typedef.
 116         (struct powerpc_opcode <flags>): Use it.
 117         (struct powerpc_operand <insert, extract>): Likewise.
 118         (struct powerpc_macro <flags>): Likewise.
 119
 120 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 121
 122         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 123         Update comment before MIPS16 field descriptors to mention MIPS16.
 124         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 125         BBIT.
 126         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 127         New bit masks and shift counts for cins and exts.
 128
 129         * mips.h: Document new field descriptors +Q.
 130         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 131
 132 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 133
 134         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 135         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 136
 137 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 138
 139         * ppc.h: (PPC_OPCODE_E500MC): New.
 140
 141 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * i386.h (MAX_OPERANDS): Set to 5.
 144         (MAX_MNEM_SIZE): Changed to 20.
 145
 146 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 147
 148         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 149
 150 2008-03-09  Paul Brook  <paul@codesourcery.com>
 151
 152         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 153
 154 2008-03-04  Paul Brook  <paul@codesourcery.com>
 155
 156         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 157         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 158         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 159
 160 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 161             Nick Clifton  <nickc@redhat.com>
 162
 163         PR 3134
 164         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 165         with a 32-bit displacement but without the top bit of the 4th byte
 166         set.
 167
 168 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 169
 170         * cr16.h (cr16_num_optab): Declared.
 171
 172 2008-02-14  Hakan Ardo  <hakan@debian.org>
 173
 174         PR gas/2626
 175         * avr.h (AVR_ISA_2xxe): Define.
 176
 177 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 178
 179         * mips.h: Update copyright.
 180         (INSN_CHIP_MASK): New macro.
 181         (INSN_OCTEON): New macro.
 182         (CPU_OCTEON): New macro.
 183         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 184
 185 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 186
 187         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 188
 189 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 190
 191         * avr.h (AVR_ISA_USB162): Add new opcode set.
 192         (AVR_ISA_AVR3): Likewise.
 193
 194 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 195
 196         * mips.h (INSN_LOONGSON_2E): New.
 197         (INSN_LOONGSON_2F): New.
 198         (CPU_LOONGSON_2E): New.
 199         (CPU_LOONGSON_2F): New.
 200         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 201
 202 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 203
 204         * mips.h (INSN_ISA*): Redefine certain values as an
 205         enumeration.  Update comments.
 206         (mips_isa_table): New.
 207         (ISA_MIPS*): Redefine to match enumeration.
 208         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 209         values.
 210
 211 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 212
 213         * ppc.h (PPC_OPCODE_PPCPS): New.
 214
 215 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 216
 217         * m68k.h: Document j K & E.
 218
 219 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 220
 221         * cr16.h: New file for CR16 target.
 222
 223 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 224
 225         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 226
 227 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 228
 229         * m68k.h (mcfisa_c): New.
 230         (mcfusp, mcf_mask): Adjust.
 231
 232 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 233
 234         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 235         (num_powerpc_operands): Declare.
 236         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 237         (PPC_OPERAND_PLUS1): Define.
 238
 239 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         * i386.h (REX_MODE64): Renamed to ...
 242         (REX_W): This.
 243         (REX_EXTX): Renamed to ...
 244         (REX_R): This.
 245         (REX_EXTY): Renamed to ...
 246         (REX_X): This.
 247         (REX_EXTZ): Renamed to ...
 248         (REX_B): This.
 249
 250 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 251
 252         * i386.h: Add entries from config/tc-i386.h and move tables
 253         to opcodes/i386-opc.h.
 254
 255 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 256
 257         * i386.h (FloatDR): Removed.
 258         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 259
 260 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 261
 262         * spu-insns.h: Add soma double-float insns.
 263
 264 2007-02-20  Thiemo Seufer  <ths@mips.com>
 265             Chao-Ying Fu  <fu@mips.com>
 266
 267         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 268         (INSN_DSPR2): Add flag for DSP R2 instructions.
 269         (M_BALIGN): New macro.
 270
 271 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 272
 273         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 274         and Seg3ShortFrom with Shortform.
 275
 276 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         PR gas/4027
 279         * i386.h (i386_optab): Put the real "test" before the pseudo
 280         one.
 281
 282 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 283
 284         * m68k.h (m68010up): OR fido_a.
 285
 286 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 287
 288         * m68k.h (fido_a): New.
 289
 290 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 291
 292         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 293         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 294         values.
 295
 296 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 299
 300 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 301
 302         * score-inst.h (enum score_insn_type): Add Insn_internal.
 303
 304 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 305             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 306             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 307             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 308             Alan Modra  <amodra@bigpond.net.au>
 309
 310         * spu-insns.h: New file.
 311         * spu.h: New file.
 312
 313 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 314
 315         * ppc.h (PPC_OPCODE_CELL): Define.
 316
 317 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 318
 319         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 320         in amdfam10 architecture.
 321
 322 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         * i386.h: Replace CpuMNI with CpuSSSE3.
 325
 326 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 327             Joseph Myers  <joseph@codesourcery.com>
 328             Ian Lance Taylor  <ian@wasabisystems.com>
 329             Ben Elliston  <bje@wasabisystems.com>
 330
 331         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 332
 333 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 334
 335         * score-datadep.h: New file.
 336         * score-inst.h: New file.
 337
 338 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 341         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 342         movdq2q and movq2dq.
 343
 344 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 345            Michael Meissner             <michael.meissner@amd.com>
 346
 347         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 348
 349 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 350
 351         * i386.h (i386_optab): Add "nop" with memory reference.
 352
 353 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         * i386.h (i386_optab): Update comment for 64bit NOP.
 356
 357 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 358             Anton Blanchard  <anton@samba.org>
 359
 360         * ppc.h (PPC_OPCODE_POWER6): Define.
 361         Adjust whitespace.
 362
 363 2006-06-05  Thiemo Seufer  <ths@mips.com>
 364
 365         * mips.h: Improve description of MT flags.
 366
 367 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 368
 369         * m68k.h (mcf_mask): Define.
 370
 371 2006-05-05  Thiemo Seufer  <ths@mips.com>
 372             David Ung  <davidu@mips.com>
 373
 374         * mips.h (enum): Add macro M_CACHE_AB.
 375
 376 2006-05-04  Thiemo Seufer  <ths@mips.com>
 377             Nigel Stephens  <nigel@mips.com>
 378             David Ung  <davidu@mips.com>
 379
 380         * mips.h: Add INSN_SMARTMIPS define.
 381
 382 2006-04-30  Thiemo Seufer  <ths@mips.com>
 383             David Ung  <davidu@mips.com>
 384
 385         * mips.h: Defines udi bits and masks.  Add description of
 386         characters which may appear in the args field of udi
 387         instructions.
 388
 389 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 390
 391         * mips.h: Improve comments describing the bitfield instruction
 392         fields.
 393
 394 2006-04-26  Julian Brown  <julian@codesourcery.com>
 395
 396         * arm.h (FPU_VFP_EXT_V3): Define constant.
 397         (FPU_NEON_EXT_V1): Likewise.
 398         (FPU_VFP_HARD): Update.
 399         (FPU_VFP_V3): Define macro.
 400         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 401
 402 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 403
 404         * avr.h (AVR_ISA_PWMx): New.
 405
 406 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 407
 408         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 409         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 410         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 411         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 412         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 413
 414 2006-03-10  Paul Brook  <paul@codesourcery.com>
 415
 416         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 417
 418 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 419
 420         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 421         first.  Correct mask of bb "B" opcode.
 422
 423 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 424
 425         * i386.h (i386_optab): Support Intel Merom New Instructions.
 426
 427 2006-02-24  Paul Brook  <paul@codesourcery.com>
 428
 429         * arm.h: Add V7 feature bits.
 430
 431 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 432
 433         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 434
 435 2006-01-31  Paul Brook  <paul@codesourcery.com>
 436         Richard Earnshaw <rearnsha@arm.com>
 437
 438         * arm.h: Use ARM_CPU_FEATURE.
 439         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 440         (arm_feature_set): Change to a structure.
 441         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 442         ARM_FEATURE): New macros.
 443
 444 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 445
 446         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 447         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 448         (ADD_PC_INCR_OPCODE): Don't define.
 449
 450 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         PR gas/1874
 453         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 454
 455 2005-11-14  David Ung  <davidu@mips.com>
 456
 457         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 458         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 459         save/restore encoding of the args field.
 460
 461 2005-10-28  Dave Brolley  <brolley@redhat.com>
 462
 463         Contribute the following changes:
 464         2005-02-16  Dave Brolley  <brolley@redhat.com>
 465
 466         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 467         cgen_isa_mask_* to cgen_bitset_*.
 468         * cgen.h: Likewise.
 469
 470         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 471
 472         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 473         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 474         (CGEN_CPU_TABLE): Make isas a ponter.
 475
 476         2003-09-29  Dave Brolley  <brolley@redhat.com>
 477
 478         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 479         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 480         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 481
 482         2002-12-13  Dave Brolley  <brolley@redhat.com>
 483
 484         * cgen.h (symcat.h): #include it.
 485         (cgen-bitset.h): #include it.
 486         (CGEN_ATTR_VALUE_TYPE): Now a union.
 487         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 488         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 489         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 490         * cgen-bitset.h: New file.
 491
 492 2005-09-30  Catherine Moore  <clm@cm00re.com>
 493
 494         * bfin.h: New file.
 495
 496 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 497
 498         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 499         indirect operands.
 500
 501 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 502
 503         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 504         Add FLAG_STRICT to pa10 ftest opcode.
 505
 506 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 507
 508         * hppa.h (pa_opcodes): Remove lha entries.
 509
 510 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 511
 512         * hppa.h (FLAG_STRICT): Revise comment.
 513         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 514         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 515         entries for "fdc".
 516
 517 2005-09-30  Catherine Moore  <clm@cm00re.com>
 518
 519         * bfin.h: New file.
 520
 521 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 522
 523         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 524
 525 2005-09-06  Chao-ying Fu  <fu@mips.com>
 526
 527         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 528         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 529         define.
 530         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 531         (INSN_ASE_MASK): Update to include INSN_MT.
 532         (INSN_MT): New define for MT ASE.
 533
 534 2005-08-25  Chao-ying Fu  <fu@mips.com>
 535
 536         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 537         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 538         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 539         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 540         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 541         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 542         instructions.
 543         (INSN_DSP): New define for DSP ASE.
 544
 545 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 546
 547         * a29k.h: Delete.
 548
 549 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 550
 551         * ppc.h (PPC_OPCODE_E300): Define.
 552
 553 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 554
 555         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 556
 557 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 558
 559         PR gas/336
 560         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 561         and pitlb.
 562
 563 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 564
 565         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 566         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 567         Add movq-s as 64-bit variants of movd-s.
 568
 569 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 570
 571         * hppa.h: Fix punctuation in comment.
 572
 573         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 574         implicit space-register addressing.  Set space-register bits on opcodes
 575         using implicit space-register addressing.  Add various missing pa20
 576         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 577         space-register addressing.  Use "fE" instead of "fe" in various
 578         fstw opcodes.
 579
 580 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 581
 582         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 583
 584 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 585
 586         * i386.h (i386_optab): Support Intel VMX Instructions.
 587
 588 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 589
 590         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 591
 592 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 593
 594         * i386.h (i386_optab): Add new insns.
 595
 596 2005-07-01  Nick Clifton  <nickc@redhat.com>
 597
 598         * sparc.h: Add typedefs to structure declarations.
 599
 600 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         PR 1013
 603         * i386.h (i386_optab): Update comments for 64bit addressing on
 604         mov. Allow 64bit addressing for mov and movq.
 605
 606 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 607
 608         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 609         respectively, in various floating-point load and store patterns.
 610
 611 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 612
 613         * hppa.h (FLAG_STRICT): Correct comment.
 614         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 615         PA 2.0 mneumonics when equivalent.  Entries with cache control
 616         completers now require PA 1.1.  Adjust whitespace.
 617
 618 2005-05-19  Anton Blanchard  <anton@samba.org>
 619
 620         * ppc.h (PPC_OPCODE_POWER5): Define.
 621
 622 2005-05-10  Nick Clifton  <nickc@redhat.com>
 623
 624         * Update the address and phone number of the FSF organization in
 625         the GPL notices in the following files:
 626         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 627         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 628         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 629         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 630         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 631         tic54x.h, tic80.h, v850.h, vax.h
 632
 633 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 634
 635         * i386.h (i386_optab): Add ht and hnt.
 636
 637 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 638
 639         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 640         Add xcrypt-ctr.  Provide aliases without hyphens.
 641
 642 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         Moved from ../ChangeLog
 645
 646         2005-04-12  Paul Brook  <paul@codesourcery.com>
 647         * m88k.h: Rename psr macros to avoid conflicts.
 648
 649         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 650         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 651         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 652         and ARM_ARCH_V6ZKT2.
 653
 654         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 655         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 656         Remove redundant instruction types.
 657         (struct argument): X_op - new field.
 658         (struct cst4_entry): Remove.
 659         (no_op_insn): Declare.
 660
 661         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 662         * crx.h (enum argtype): Rename types, remove unused types.
 663
 664         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 665         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 666         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 667         (enum operand_type): Rearrange operands, edit comments.
 668         replace us<N> with ui<N> for unsigned immediate.
 669         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 670         displacements (respectively).
 671         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 672         (instruction type): Add NO_TYPE_INS.
 673         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 674         (operand_entry): New field - 'flags'.
 675         (operand flags): New.
 676
 677         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 678         * crx.h (operand_type): Remove redundant types i3, i4,
 679         i5, i8, i12.
 680         Add new unsigned immediate types us3, us4, us5, us16.
 681
 682 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 683
 684         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 685         adjust them accordingly.
 686
 687 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 688
 689         * i386.h (i386_optab): Add rdtscp.
 690
 691 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 692
 693         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 694         between memory and segment register. Allow movq for moving between
 695         general-purpose register and segment register.
 696
 697 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 698
 699         PR gas/707
 700         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 701         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 702         fnstsw.
 703
 704 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 705
 706         * m68k.h (m68008, m68ec030, m68882): Remove.
 707         (m68k_mask): New.
 708         (cpu_m68k, cpu_cf): New.
 709         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 710         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 711
 712 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 713
 714         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 715         * cgen.h (enum cgen_parse_operand_type): Add
 716         CGEN_PARSE_OPERAND_SYMBOLIC.
 717
 718 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 719
 720         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 721         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 722         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 723
 724 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 725
 726         * mips.h (struct mips_opcode): Add new pinfo2 member.
 727         (INSN_ALIAS): New define for opcode table entries that are
 728         specific instances of another entry, such as 'move' for an 'or'
 729         with a zero operand.
 730         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 731         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 732
 733 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 734
 735         * mips.h (CPU_RM9000): Define.
 736         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 737
 738 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 739
 740         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 741         to/from test registers are illegal in 64-bit mode. Add missing
 742         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 743         (previously one had to explicitly encode a rex64 prefix). Re-enable
 744         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 745         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 746
 747 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 748
 749         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 750         available only with SSE2. Change the MMX additions introduced by SSE
 751         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 752         instructions by their now designated identifier (since combining i686
 753         and 3DNow! does not really imply 3DNow!A).
 754
 755 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 756
 757         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 758         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 759
 760 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 761             Vineet Sharma      <vineets@noida.hcltech.com>
 762
 763         * maxq.h: New file: Disassembly information for the maxq port.
 764
 765 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         * i386.h (i386_optab): Put back "movzb".
 768
 769 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 770
 771         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 772         comments.  Remove member cris_ver_sim.  Add members
 773         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 774         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 775         (struct cris_support_reg, struct cris_cond15): New types.
 776         (cris_conds15): Declare.
 777         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 778         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 779         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 780         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 781         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 782         SIZE_FIELD_UNSIGNED.
 783
 784 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 785
 786         * i386.h (sldx_Suf): Remove.
 787         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 788         (q_FP): Define, implying no REX64.
 789         (x_FP, sl_FP): Imply FloatMF.
 790         (i386_optab): Split reg and mem forms of moving from segment registers
 791         so that the memory forms can ignore the 16-/32-bit operand size
 792         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 793         all non-floating-point instructions. Unite 32- and 64-bit forms of
 794         movsx, movzx, and movd. Adjust floating point operations for the above
 795         changes to the *FP macros. Add DefaultSize to floating point control
 796         insns operating on larger memory ranges. Remove left over comments
 797         hinting at certain insns being Intel-syntax ones where the ones
 798         actually meant are already gone.
 799
 800 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 801
 802         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 803         instruction type.
 804
 805 2004-09-30  Paul Brook  <paul@codesourcery.com>
 806
 807         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 808         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 809
 810 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 811
 812         * avr.h: Add support for
 813         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 814
 815 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 816
 817         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 818
 819 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 820
 821         * msp430.h (msp430_opc): Add new instructions.
 822         (msp430_rcodes): Declare new instructions.
 823         (msp430_hcodes): Likewise..
 824
 825 2004-08-13  Nick Clifton  <nickc@redhat.com>
 826
 827         PR/301
 828         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 829         processors.
 830
 831 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 832
 833         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 834
 835 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 838
 839 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 840
 841         * i386.h: Adjust instruction descriptions to better match the
 842         specification.
 843
 844 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 845
 846         * arm.h: Remove all old content.  Replace with architecture defines
 847         from gas/config/tc-arm.c.
 848
 849 2004-07-09  Andreas Schwab  <schwab@suse.de>
 850
 851         * m68k.h: Fix comment.
 852
 853 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 854
 855         * crx.h: New file.
 856
 857 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 858
 859         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 860
 861 2004-05-24  Peter Barada  <peter@the-baradas.com>
 862
 863         * m68k.h: Add 'size' to m68k_opcode.
 864
 865 2004-05-05  Peter Barada  <peter@the-baradas.com>
 866
 867         * m68k.h: Switch from ColdFire chip name to core variant.
 868
 869 2004-04-22  Peter Barada  <peter@the-baradas.com>
 870
 871         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 872         descriptions for new EMAC cases.
 873         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 874         handle Motorola MAC syntax.
 875         Allow disassembly of ColdFire V4e object files.
 876
 877 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 878
 879         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 880
 881 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 882
 883         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 884
 885 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 886
 887         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 888
 889 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 890
 891         * i386.h (i386_optab): Added xstore/xcrypt insns.
 892
 893 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 894
 895         * h8300.h (32bit ldc/stc): Add relaxing support.
 896
 897 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 898
 899         * h8300.h (BITOP): Pass MEMRELAX flag.
 900
 901 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 902
 903         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 904         except for the H8S.
 905
 906 For older changes see ChangeLog-9103
 907 \f
 908 Local Variables:
 909 mode: change-log
 910 left-margin: 8
 911 fill-column: 74
 912 version-control: never
 913 End: