include/opcode/ChangeLog

   1 2010-04-15  Nick Clifton  <nickc@redhat.com>
   2
   3         * alpha.h: Update copyright notice to use GPLv3.
   4         * arc.h: Likewise.
   5         * arm.h: Likewise.
   6         * avr.h: Likewise.
   7         * bfin.h: Likewise.
   8         * cgen.h: Likewise.
   9         * convex.h: Likewise.
  10         * cr16.h: Likewise.
  11         * cris.h: Likewise.
  12         * crx.h: Likewise.
  13         * d10v.h: Likewise.
  14         * d30v.h: Likewise.
  15         * dlx.h: Likewise.
  16         * h8300.h: Likewise.
  17         * hppa.h: Likewise.
  18         * i370.h: Likewise.
  19         * i386.h: Likewise.
  20         * i860.h: Likewise.
  21         * i960.h: Likewise.
  22         * ia64.h: Likewise.
  23         * m68hc11.h: Likewise.
  24         * m68k.h: Likewise.
  25         * m88k.h: Likewise.
  26         * maxq.h: Likewise.
  27         * mips.h: Likewise.
  28         * mmix.h: Likewise.
  29         * mn10200.h: Likewise.
  30         * mn10300.h: Likewise.
  31         * msp430.h: Likewise.
  32         * np1.h: Likewise.
  33         * ns32k.h: Likewise.
  34         * or32.h: Likewise.
  35         * pdp11.h: Likewise.
  36         * pj.h: Likewise.
  37         * pn.h: Likewise.
  38         * ppc.h: Likewise.
  39         * pyr.h: Likewise.
  40         * rx.h: Likewise.
  41         * s390.h: Likewise.
  42         * score-datadep.h: Likewise.
  43         * score-inst.h: Likewise.
  44         * sparc.h: Likewise.
  45         * spu-insns.h: Likewise.
  46         * spu.h: Likewise.
  47         * tic30.h: Likewise.
  48         * tic4x.h: Likewise.
  49         * tic54x.h: Likewise.
  50         * tic80.h: Likewise.
  51         * v850.h: Likewise.
  52         * vax.h: Likewise.
  53
  54 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
  55
  56         * tic6x-control-registers.h, tic6x-insn-formats.h,
  57         tic6x-opcode-table.h, tic6x.h: New.
  58
  59 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
  60
  61         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
  62
  63 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
  64
  65         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
  66
  67 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         * ia64.h (ia64_find_opcode): Remove argument name.
  70         (ia64_find_next_opcode): Likewise.
  71         (ia64_dis_opcode): Likewise.
  72         (ia64_free_opcode): Likewise.
  73         (ia64_find_dependency): Likewise.
  74
  75 2009-11-22  Doug Evans  <dje@sebabeach.org>
  76
  77         * cgen.h: Include bfd_stdint.h.
  78         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
  79
  80 2009-11-18  Paul Brook  <paul@codesourcery.com>
  81
  82         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
  83
  84 2009-11-17  Paul Brook  <paul@codesourcery.com>
  85         Daniel Jacobowitz  <dan@codesourcery.com>
  86
  87         * arm.h (ARM_EXT_V6_DSP): Define.
  88         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
  89         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
  90
  91 2009-11-04  DJ Delorie  <dj@redhat.com>
  92
  93         * rx.h (rx_decode_opcode) (mvtipl): Add.
  94         (mvtcp, mvfcp, opecp): Remove.
  95
  96 2009-11-02  Paul Brook  <paul@codesourcery.com>
  97
  98         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
  99         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 100         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 101         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 102         FPU_ARCH_NEON_VFP_V4): Define.
 103
 104 2009-10-23  Doug Evans  <dje@sebabeach.org>
 105
 106         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 107         * cgen.h: Update.  Improve multi-inclusion macro name.
 108
 109 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 110
 111         * ppc.h (PPC_OPCODE_476): Define.
 112
 113 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 114
 115         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 116
 117 2009-09-29  DJ Delorie  <dj@redhat.com>
 118
 119         * rx.h: New file.
 120
 121 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 122
 123         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 124
 125 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 126
 127         * ppc.h (PPC_OPCODE_PPCA2): New.
 128
 129 2009-09-05  Martin Thuresson  <martin@mtme.org>
 130
 131         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 132
 133 2009-08-29  Martin Thuresson  <martin@mtme.org>
 134
 135         * tic30.h (template): Rename type template to
 136         insn_template. Updated code to use new name.
 137         * tic54x.h (template): Rename type template to
 138         insn_template.
 139
 140 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 141
 142         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 143
 144 2009-06-11  Anthony Green  <green@moxielogic.com>
 145
 146         * moxie.h (MOXIE_F3_PCREL): Define.
 147         (moxie_form3_opc_info): Grow.
 148
 149 2009-06-06  Anthony Green  <green@moxielogic.com>
 150
 151         * moxie.h (MOXIE_F1_M): Define.
 152
 153 2009-04-15  Anthony Green  <green@moxielogic.com>
 154
 155         * moxie.h: Created.
 156
 157 2009-04-06  DJ Delorie  <dj@redhat.com>
 158
 159         * h8300.h: Add relaxation attributes to MOVA opcodes.
 160
 161 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 162
 163         * ppc.h (ppc_parse_cpu): Declare.
 164
 165 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 166
 167         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 168         and _IMM11 for mbitclr and mbitset.
 169         * score-datadep.h: Update dependency information.
 170
 171 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 172
 173         * ppc.h (PPC_OPCODE_POWER7): New.
 174
 175 2009-02-06  Doug Evans  <dje@google.com>
 176
 177         * i386.h: Add comment regarding sse* insns and prefixes.
 178
 179 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 180
 181         * mips.h (INSN_XLR): Define.
 182         (INSN_CHIP_MASK): Update.
 183         (CPU_XLR): Define.
 184         (OPCODE_IS_MEMBER): Update.
 185         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 186
 187 2009-01-28  Doug Evans  <dje@google.com>
 188
 189         * opcode/i386.h: Add multiple inclusion protection.
 190         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 191         (EDI_REG_NUM): New macros.
 192         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 193         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 194         (REX_PREFIX_P): New macro.
 195
 196 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 197
 198         * ppc.h (struct powerpc_opcode): New field "deprecated".
 199         (PPC_OPCODE_NOPOWER4): Delete.
 200
 201 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 202
 203         * mips.h: Define CPU_R14000, CPU_R16000.
 204         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 205
 206 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 207
 208         * arm.h (FPU_NEON_FP16): New.
 209         (FPU_ARCH_NEON_FP16): New.
 210
 211 2008-11-06  Chao-ying Fu  <fu@mips.com>
 212
 213         * mips.h: Doucument '1' for 5-bit sync type.
 214
 215 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 218         IA64_RS_CR.
 219
 220 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 221
 222         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 223
 224 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 225
 226         * ppc.h (PPC_OPCODE_405): Define.
 227         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 228
 229 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 230
 231         * ppc.h (ppc_cpu_t): New typedef.
 232         (struct powerpc_opcode <flags>): Use it.
 233         (struct powerpc_operand <insert, extract>): Likewise.
 234         (struct powerpc_macro <flags>): Likewise.
 235
 236 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 237
 238         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 239         Update comment before MIPS16 field descriptors to mention MIPS16.
 240         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 241         BBIT.
 242         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 243         New bit masks and shift counts for cins and exts.
 244
 245         * mips.h: Document new field descriptors +Q.
 246         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 247
 248 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 249
 250         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 251         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 252
 253 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 254
 255         * ppc.h: (PPC_OPCODE_E500MC): New.
 256
 257 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         * i386.h (MAX_OPERANDS): Set to 5.
 260         (MAX_MNEM_SIZE): Changed to 20.
 261
 262 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 263
 264         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 265
 266 2008-03-09  Paul Brook  <paul@codesourcery.com>
 267
 268         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 269
 270 2008-03-04  Paul Brook  <paul@codesourcery.com>
 271
 272         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 273         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 274         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 275
 276 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 277             Nick Clifton  <nickc@redhat.com>
 278
 279         PR 3134
 280         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 281         with a 32-bit displacement but without the top bit of the 4th byte
 282         set.
 283
 284 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 285
 286         * cr16.h (cr16_num_optab): Declared.
 287
 288 2008-02-14  Hakan Ardo  <hakan@debian.org>
 289
 290         PR gas/2626
 291         * avr.h (AVR_ISA_2xxe): Define.
 292
 293 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 294
 295         * mips.h: Update copyright.
 296         (INSN_CHIP_MASK): New macro.
 297         (INSN_OCTEON): New macro.
 298         (CPU_OCTEON): New macro.
 299         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 300
 301 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 302
 303         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 304
 305 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 306
 307         * avr.h (AVR_ISA_USB162): Add new opcode set.
 308         (AVR_ISA_AVR3): Likewise.
 309
 310 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 311
 312         * mips.h (INSN_LOONGSON_2E): New.
 313         (INSN_LOONGSON_2F): New.
 314         (CPU_LOONGSON_2E): New.
 315         (CPU_LOONGSON_2F): New.
 316         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 317
 318 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 319
 320         * mips.h (INSN_ISA*): Redefine certain values as an
 321         enumeration.  Update comments.
 322         (mips_isa_table): New.
 323         (ISA_MIPS*): Redefine to match enumeration.
 324         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 325         values.
 326
 327 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 328
 329         * ppc.h (PPC_OPCODE_PPCPS): New.
 330
 331 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 332
 333         * m68k.h: Document j K & E.
 334
 335 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 336
 337         * cr16.h: New file for CR16 target.
 338
 339 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 340
 341         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 342
 343 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 344
 345         * m68k.h (mcfisa_c): New.
 346         (mcfusp, mcf_mask): Adjust.
 347
 348 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 349
 350         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 351         (num_powerpc_operands): Declare.
 352         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 353         (PPC_OPERAND_PLUS1): Define.
 354
 355 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 356
 357         * i386.h (REX_MODE64): Renamed to ...
 358         (REX_W): This.
 359         (REX_EXTX): Renamed to ...
 360         (REX_R): This.
 361         (REX_EXTY): Renamed to ...
 362         (REX_X): This.
 363         (REX_EXTZ): Renamed to ...
 364         (REX_B): This.
 365
 366 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         * i386.h: Add entries from config/tc-i386.h and move tables
 369         to opcodes/i386-opc.h.
 370
 371 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 372
 373         * i386.h (FloatDR): Removed.
 374         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 375
 376 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 377
 378         * spu-insns.h: Add soma double-float insns.
 379
 380 2007-02-20  Thiemo Seufer  <ths@mips.com>
 381             Chao-Ying Fu  <fu@mips.com>
 382
 383         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 384         (INSN_DSPR2): Add flag for DSP R2 instructions.
 385         (M_BALIGN): New macro.
 386
 387 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 388
 389         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 390         and Seg3ShortFrom with Shortform.
 391
 392 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         PR gas/4027
 395         * i386.h (i386_optab): Put the real "test" before the pseudo
 396         one.
 397
 398 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 399
 400         * m68k.h (m68010up): OR fido_a.
 401
 402 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 403
 404         * m68k.h (fido_a): New.
 405
 406 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 407
 408         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 409         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 410         values.
 411
 412 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 415
 416 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 417
 418         * score-inst.h (enum score_insn_type): Add Insn_internal.
 419
 420 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 421             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 422             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 423             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 424             Alan Modra  <amodra@bigpond.net.au>
 425
 426         * spu-insns.h: New file.
 427         * spu.h: New file.
 428
 429 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 430
 431         * ppc.h (PPC_OPCODE_CELL): Define.
 432
 433 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 434
 435         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 436         in amdfam10 architecture.
 437
 438 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         * i386.h: Replace CpuMNI with CpuSSSE3.
 441
 442 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 443             Joseph Myers  <joseph@codesourcery.com>
 444             Ian Lance Taylor  <ian@wasabisystems.com>
 445             Ben Elliston  <bje@wasabisystems.com>
 446
 447         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 448
 449 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 450
 451         * score-datadep.h: New file.
 452         * score-inst.h: New file.
 453
 454 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 455
 456         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 457         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 458         movdq2q and movq2dq.
 459
 460 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 461            Michael Meissner             <michael.meissner@amd.com>
 462
 463         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 464
 465 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         * i386.h (i386_optab): Add "nop" with memory reference.
 468
 469 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         * i386.h (i386_optab): Update comment for 64bit NOP.
 472
 473 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 474             Anton Blanchard  <anton@samba.org>
 475
 476         * ppc.h (PPC_OPCODE_POWER6): Define.
 477         Adjust whitespace.
 478
 479 2006-06-05  Thiemo Seufer  <ths@mips.com>
 480
 481         * mips.h: Improve description of MT flags.
 482
 483 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 484
 485         * m68k.h (mcf_mask): Define.
 486
 487 2006-05-05  Thiemo Seufer  <ths@mips.com>
 488             David Ung  <davidu@mips.com>
 489
 490         * mips.h (enum): Add macro M_CACHE_AB.
 491
 492 2006-05-04  Thiemo Seufer  <ths@mips.com>
 493             Nigel Stephens  <nigel@mips.com>
 494             David Ung  <davidu@mips.com>
 495
 496         * mips.h: Add INSN_SMARTMIPS define.
 497
 498 2006-04-30  Thiemo Seufer  <ths@mips.com>
 499             David Ung  <davidu@mips.com>
 500
 501         * mips.h: Defines udi bits and masks.  Add description of
 502         characters which may appear in the args field of udi
 503         instructions.
 504
 505 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 506
 507         * mips.h: Improve comments describing the bitfield instruction
 508         fields.
 509
 510 2006-04-26  Julian Brown  <julian@codesourcery.com>
 511
 512         * arm.h (FPU_VFP_EXT_V3): Define constant.
 513         (FPU_NEON_EXT_V1): Likewise.
 514         (FPU_VFP_HARD): Update.
 515         (FPU_VFP_V3): Define macro.
 516         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 517
 518 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 519
 520         * avr.h (AVR_ISA_PWMx): New.
 521
 522 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 523
 524         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 525         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 526         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 527         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 528         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 529
 530 2006-03-10  Paul Brook  <paul@codesourcery.com>
 531
 532         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 533
 534 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 535
 536         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 537         first.  Correct mask of bb "B" opcode.
 538
 539 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 540
 541         * i386.h (i386_optab): Support Intel Merom New Instructions.
 542
 543 2006-02-24  Paul Brook  <paul@codesourcery.com>
 544
 545         * arm.h: Add V7 feature bits.
 546
 547 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 548
 549         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 550
 551 2006-01-31  Paul Brook  <paul@codesourcery.com>
 552         Richard Earnshaw <rearnsha@arm.com>
 553
 554         * arm.h: Use ARM_CPU_FEATURE.
 555         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 556         (arm_feature_set): Change to a structure.
 557         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 558         ARM_FEATURE): New macros.
 559
 560 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 561
 562         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 563         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 564         (ADD_PC_INCR_OPCODE): Don't define.
 565
 566 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 567
 568         PR gas/1874
 569         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 570
 571 2005-11-14  David Ung  <davidu@mips.com>
 572
 573         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 574         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 575         save/restore encoding of the args field.
 576
 577 2005-10-28  Dave Brolley  <brolley@redhat.com>
 578
 579         Contribute the following changes:
 580         2005-02-16  Dave Brolley  <brolley@redhat.com>
 581
 582         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 583         cgen_isa_mask_* to cgen_bitset_*.
 584         * cgen.h: Likewise.
 585
 586         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 587
 588         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 589         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 590         (CGEN_CPU_TABLE): Make isas a ponter.
 591
 592         2003-09-29  Dave Brolley  <brolley@redhat.com>
 593
 594         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 595         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 596         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 597
 598         2002-12-13  Dave Brolley  <brolley@redhat.com>
 599
 600         * cgen.h (symcat.h): #include it.
 601         (cgen-bitset.h): #include it.
 602         (CGEN_ATTR_VALUE_TYPE): Now a union.
 603         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 604         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 605         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 606         * cgen-bitset.h: New file.
 607
 608 2005-09-30  Catherine Moore  <clm@cm00re.com>
 609
 610         * bfin.h: New file.
 611
 612 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 613
 614         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 615         indirect operands.
 616
 617 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 618
 619         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 620         Add FLAG_STRICT to pa10 ftest opcode.
 621
 622 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 623
 624         * hppa.h (pa_opcodes): Remove lha entries.
 625
 626 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 627
 628         * hppa.h (FLAG_STRICT): Revise comment.
 629         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 630         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 631         entries for "fdc".
 632
 633 2005-09-30  Catherine Moore  <clm@cm00re.com>
 634
 635         * bfin.h: New file.
 636
 637 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 638
 639         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 640
 641 2005-09-06  Chao-ying Fu  <fu@mips.com>
 642
 643         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 644         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 645         define.
 646         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 647         (INSN_ASE_MASK): Update to include INSN_MT.
 648         (INSN_MT): New define for MT ASE.
 649
 650 2005-08-25  Chao-ying Fu  <fu@mips.com>
 651
 652         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 653         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 654         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 655         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 656         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 657         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 658         instructions.
 659         (INSN_DSP): New define for DSP ASE.
 660
 661 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 662
 663         * a29k.h: Delete.
 664
 665 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 666
 667         * ppc.h (PPC_OPCODE_E300): Define.
 668
 669 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 670
 671         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 672
 673 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 674
 675         PR gas/336
 676         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 677         and pitlb.
 678
 679 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 680
 681         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 682         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 683         Add movq-s as 64-bit variants of movd-s.
 684
 685 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 686
 687         * hppa.h: Fix punctuation in comment.
 688
 689         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 690         implicit space-register addressing.  Set space-register bits on opcodes
 691         using implicit space-register addressing.  Add various missing pa20
 692         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 693         space-register addressing.  Use "fE" instead of "fe" in various
 694         fstw opcodes.
 695
 696 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 697
 698         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 699
 700 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 701
 702         * i386.h (i386_optab): Support Intel VMX Instructions.
 703
 704 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 705
 706         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 707
 708 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 709
 710         * i386.h (i386_optab): Add new insns.
 711
 712 2005-07-01  Nick Clifton  <nickc@redhat.com>
 713
 714         * sparc.h: Add typedefs to structure declarations.
 715
 716 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 717
 718         PR 1013
 719         * i386.h (i386_optab): Update comments for 64bit addressing on
 720         mov. Allow 64bit addressing for mov and movq.
 721
 722 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 723
 724         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 725         respectively, in various floating-point load and store patterns.
 726
 727 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 728
 729         * hppa.h (FLAG_STRICT): Correct comment.
 730         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 731         PA 2.0 mneumonics when equivalent.  Entries with cache control
 732         completers now require PA 1.1.  Adjust whitespace.
 733
 734 2005-05-19  Anton Blanchard  <anton@samba.org>
 735
 736         * ppc.h (PPC_OPCODE_POWER5): Define.
 737
 738 2005-05-10  Nick Clifton  <nickc@redhat.com>
 739
 740         * Update the address and phone number of the FSF organization in
 741         the GPL notices in the following files:
 742         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 743         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 744         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 745         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 746         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 747         tic54x.h, tic80.h, v850.h, vax.h
 748
 749 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 750
 751         * i386.h (i386_optab): Add ht and hnt.
 752
 753 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 754
 755         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 756         Add xcrypt-ctr.  Provide aliases without hyphens.
 757
 758 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 759
 760         Moved from ../ChangeLog
 761
 762         2005-04-12  Paul Brook  <paul@codesourcery.com>
 763         * m88k.h: Rename psr macros to avoid conflicts.
 764
 765         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 766         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 767         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 768         and ARM_ARCH_V6ZKT2.
 769
 770         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 771         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 772         Remove redundant instruction types.
 773         (struct argument): X_op - new field.
 774         (struct cst4_entry): Remove.
 775         (no_op_insn): Declare.
 776
 777         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 778         * crx.h (enum argtype): Rename types, remove unused types.
 779
 780         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 781         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 782         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 783         (enum operand_type): Rearrange operands, edit comments.
 784         replace us<N> with ui<N> for unsigned immediate.
 785         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 786         displacements (respectively).
 787         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 788         (instruction type): Add NO_TYPE_INS.
 789         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 790         (operand_entry): New field - 'flags'.
 791         (operand flags): New.
 792
 793         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 794         * crx.h (operand_type): Remove redundant types i3, i4,
 795         i5, i8, i12.
 796         Add new unsigned immediate types us3, us4, us5, us16.
 797
 798 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 799
 800         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 801         adjust them accordingly.
 802
 803 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 804
 805         * i386.h (i386_optab): Add rdtscp.
 806
 807 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 810         between memory and segment register. Allow movq for moving between
 811         general-purpose register and segment register.
 812
 813 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 814
 815         PR gas/707
 816         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 817         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 818         fnstsw.
 819
 820 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 821
 822         * m68k.h (m68008, m68ec030, m68882): Remove.
 823         (m68k_mask): New.
 824         (cpu_m68k, cpu_cf): New.
 825         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 826         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 827
 828 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 829
 830         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 831         * cgen.h (enum cgen_parse_operand_type): Add
 832         CGEN_PARSE_OPERAND_SYMBOLIC.
 833
 834 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 835
 836         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 837         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 838         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 839
 840 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 841
 842         * mips.h (struct mips_opcode): Add new pinfo2 member.
 843         (INSN_ALIAS): New define for opcode table entries that are
 844         specific instances of another entry, such as 'move' for an 'or'
 845         with a zero operand.
 846         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 847         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 848
 849 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 850
 851         * mips.h (CPU_RM9000): Define.
 852         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 853
 854 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 855
 856         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 857         to/from test registers are illegal in 64-bit mode. Add missing
 858         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 859         (previously one had to explicitly encode a rex64 prefix). Re-enable
 860         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 861         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 862
 863 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 864
 865         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 866         available only with SSE2. Change the MMX additions introduced by SSE
 867         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 868         instructions by their now designated identifier (since combining i686
 869         and 3DNow! does not really imply 3DNow!A).
 870
 871 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 872
 873         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 874         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 875
 876 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 877             Vineet Sharma      <vineets@noida.hcltech.com>
 878
 879         * maxq.h: New file: Disassembly information for the maxq port.
 880
 881 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 882
 883         * i386.h (i386_optab): Put back "movzb".
 884
 885 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 886
 887         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 888         comments.  Remove member cris_ver_sim.  Add members
 889         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 890         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 891         (struct cris_support_reg, struct cris_cond15): New types.
 892         (cris_conds15): Declare.
 893         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 894         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 895         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 896         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 897         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 898         SIZE_FIELD_UNSIGNED.
 899
 900 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 901
 902         * i386.h (sldx_Suf): Remove.
 903         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 904         (q_FP): Define, implying no REX64.
 905         (x_FP, sl_FP): Imply FloatMF.
 906         (i386_optab): Split reg and mem forms of moving from segment registers
 907         so that the memory forms can ignore the 16-/32-bit operand size
 908         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 909         all non-floating-point instructions. Unite 32- and 64-bit forms of
 910         movsx, movzx, and movd. Adjust floating point operations for the above
 911         changes to the *FP macros. Add DefaultSize to floating point control
 912         insns operating on larger memory ranges. Remove left over comments
 913         hinting at certain insns being Intel-syntax ones where the ones
 914         actually meant are already gone.
 915
 916 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 917
 918         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 919         instruction type.
 920
 921 2004-09-30  Paul Brook  <paul@codesourcery.com>
 922
 923         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 924         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 925
 926 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 927
 928         * avr.h: Add support for
 929         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 930
 931 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 932
 933         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 934
 935 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 936
 937         * msp430.h (msp430_opc): Add new instructions.
 938         (msp430_rcodes): Declare new instructions.
 939         (msp430_hcodes): Likewise..
 940
 941 2004-08-13  Nick Clifton  <nickc@redhat.com>
 942
 943         PR/301
 944         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 945         processors.
 946
 947 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 948
 949         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 950
 951 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 952
 953         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 954
 955 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 956
 957         * i386.h: Adjust instruction descriptions to better match the
 958         specification.
 959
 960 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 961
 962         * arm.h: Remove all old content.  Replace with architecture defines
 963         from gas/config/tc-arm.c.
 964
 965 2004-07-09  Andreas Schwab  <schwab@suse.de>
 966
 967         * m68k.h: Fix comment.
 968
 969 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 970
 971         * crx.h: New file.
 972
 973 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 974
 975         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 976
 977 2004-05-24  Peter Barada  <peter@the-baradas.com>
 978
 979         * m68k.h: Add 'size' to m68k_opcode.
 980
 981 2004-05-05  Peter Barada  <peter@the-baradas.com>
 982
 983         * m68k.h: Switch from ColdFire chip name to core variant.
 984
 985 2004-04-22  Peter Barada  <peter@the-baradas.com>
 986
 987         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 988         descriptions for new EMAC cases.
 989         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 990         handle Motorola MAC syntax.
 991         Allow disassembly of ColdFire V4e object files.
 992
 993 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 994
 995         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 996
 997 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 998
 999         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1000
1001 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1002
1003         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1004
1005 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1006
1007         * i386.h (i386_optab): Added xstore/xcrypt insns.
1008
1009 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1010
1011         * h8300.h (32bit ldc/stc): Add relaxing support.
1012
1013 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1014
1015         * h8300.h (BITOP): Pass MEMRELAX flag.
1016
1017 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1018
1019         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1020         except for the H8S.
1021
1022 For older changes see ChangeLog-9103
1023 \f
1024 Local Variables:
1025 mode: change-log
1026 left-margin: 8
1027 fill-column: 74
1028 version-control: never
1029 End: