1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn
;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
51 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
52 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
53 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
55 /* Architectures are the sum of the base and extensions. */
56 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
58 | AARCH64_FEATURE_SIMD)
59 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
61 | AARCH64_FEATURE_SIMD \
62 | AARCH64_FEATURE_CRC \
63 | AARCH64_FEATURE_V8_1 \
64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
68 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
69 AARCH64_FEATURE_V8_2 \
70 | AARCH64_FEATURE_F16 \
71 | AARCH64_FEATURE_RAS \
72 | AARCH64_FEATURE_FP \
73 | AARCH64_FEATURE_SIMD \
74 | AARCH64_FEATURE_CRC \
75 | AARCH64_FEATURE_V8_1 \
76 | AARCH64_FEATURE_LSE \
77 | AARCH64_FEATURE_PAN \
78 | AARCH64_FEATURE_LOR \
79 | AARCH64_FEATURE_RDMA)
81 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
82 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
84 /* CPU-specific features. */
85 typedef unsigned long aarch64_feature_set
;
87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
88 ((~(CPU) & (FEAT)) == 0)
90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
91 (((CPU) & (FEAT)) != 0)
93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
94 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
99 (TARG) = (F1) | (F2); \
103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
106 (TARG) = (F1) &~ (F2); \
110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
112 enum aarch64_operand_class
114 AARCH64_OPND_CLASS_NIL
,
115 AARCH64_OPND_CLASS_INT_REG
,
116 AARCH64_OPND_CLASS_MODIFIED_REG
,
117 AARCH64_OPND_CLASS_FP_REG
,
118 AARCH64_OPND_CLASS_SIMD_REG
,
119 AARCH64_OPND_CLASS_SIMD_ELEMENT
,
120 AARCH64_OPND_CLASS_SISD_REG
,
121 AARCH64_OPND_CLASS_SIMD_REGLIST
,
122 AARCH64_OPND_CLASS_CP_REG
,
123 AARCH64_OPND_CLASS_ADDRESS
,
124 AARCH64_OPND_CLASS_IMMEDIATE
,
125 AARCH64_OPND_CLASS_SYSTEM
,
126 AARCH64_OPND_CLASS_COND
,
129 /* Operand code that helps both parsing and coding.
130 Keep AARCH64_OPERANDS synced. */
134 AARCH64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
136 AARCH64_OPND_Rd
, /* Integer register as destination. */
137 AARCH64_OPND_Rn
, /* Integer register as source. */
138 AARCH64_OPND_Rm
, /* Integer register as source. */
139 AARCH64_OPND_Rt
, /* Integer register used in ld/st instructions. */
140 AARCH64_OPND_Rt2
, /* Integer register used in ld/st pair instructions. */
141 AARCH64_OPND_Rs
, /* Integer register used in ld/st exclusive. */
142 AARCH64_OPND_Ra
, /* Integer register used in ddp_3src instructions. */
143 AARCH64_OPND_Rt_SYS
, /* Integer register used in system instructions. */
145 AARCH64_OPND_Rd_SP
, /* Integer Rd or SP. */
146 AARCH64_OPND_Rn_SP
, /* Integer Rn or SP. */
147 AARCH64_OPND_PAIRREG
, /* Paired register operand. */
148 AARCH64_OPND_Rm_EXT
, /* Integer Rm extended. */
149 AARCH64_OPND_Rm_SFT
, /* Integer Rm shifted. */
151 AARCH64_OPND_Fd
, /* Floating-point Fd. */
152 AARCH64_OPND_Fn
, /* Floating-point Fn. */
153 AARCH64_OPND_Fm
, /* Floating-point Fm. */
154 AARCH64_OPND_Fa
, /* Floating-point Fa. */
155 AARCH64_OPND_Ft
, /* Floating-point Ft. */
156 AARCH64_OPND_Ft2
, /* Floating-point Ft2. */
158 AARCH64_OPND_Sd
, /* AdvSIMD Scalar Sd. */
159 AARCH64_OPND_Sn
, /* AdvSIMD Scalar Sn. */
160 AARCH64_OPND_Sm
, /* AdvSIMD Scalar Sm. */
162 AARCH64_OPND_Vd
, /* AdvSIMD Vector Vd. */
163 AARCH64_OPND_Vn
, /* AdvSIMD Vector Vn. */
164 AARCH64_OPND_Vm
, /* AdvSIMD Vector Vm. */
165 AARCH64_OPND_VdD1
, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
166 AARCH64_OPND_VnD1
, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
167 AARCH64_OPND_Ed
, /* AdvSIMD Vector Element Vd. */
168 AARCH64_OPND_En
, /* AdvSIMD Vector Element Vn. */
169 AARCH64_OPND_Em
, /* AdvSIMD Vector Element Vm. */
170 AARCH64_OPND_LVn
, /* AdvSIMD Vector register list used in e.g. TBL. */
171 AARCH64_OPND_LVt
, /* AdvSIMD Vector register list used in ld/st. */
172 AARCH64_OPND_LVt_AL
, /* AdvSIMD Vector register list for loading single
173 structure to all lanes. */
174 AARCH64_OPND_LEt
, /* AdvSIMD Vector Element list. */
176 AARCH64_OPND_Cn
, /* Co-processor register in CRn field. */
177 AARCH64_OPND_Cm
, /* Co-processor register in CRm field. */
179 AARCH64_OPND_IDX
, /* AdvSIMD EXT index operand. */
180 AARCH64_OPND_IMM_VLSL
,/* Immediate for shifting vector registers left. */
181 AARCH64_OPND_IMM_VLSR
,/* Immediate for shifting vector registers right. */
182 AARCH64_OPND_SIMD_IMM
,/* AdvSIMD modified immediate without shift. */
183 AARCH64_OPND_SIMD_IMM_SFT
, /* AdvSIMD modified immediate with shift. */
184 AARCH64_OPND_SIMD_FPIMM
,/* AdvSIMD 8-bit fp immediate. */
185 AARCH64_OPND_SHLL_IMM
,/* Immediate shift for AdvSIMD SHLL instruction
187 AARCH64_OPND_IMM0
, /* Immediate for #0. */
188 AARCH64_OPND_FPIMM0
, /* Immediate for #0.0. */
189 AARCH64_OPND_FPIMM
, /* Floating-point Immediate. */
190 AARCH64_OPND_IMMR
, /* Immediate #<immr> in e.g. BFM. */
191 AARCH64_OPND_IMMS
, /* Immediate #<imms> in e.g. BFM. */
192 AARCH64_OPND_WIDTH
, /* Immediate #<width> in e.g. BFI. */
193 AARCH64_OPND_IMM
, /* Immediate. */
194 AARCH64_OPND_UIMM3_OP1
,/* Unsigned 3-bit immediate in the op1 field. */
195 AARCH64_OPND_UIMM3_OP2
,/* Unsigned 3-bit immediate in the op2 field. */
196 AARCH64_OPND_UIMM4
, /* Unsigned 4-bit immediate in the CRm field. */
197 AARCH64_OPND_UIMM7
, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
198 AARCH64_OPND_BIT_NUM
, /* Immediate. */
199 AARCH64_OPND_EXCEPTION
,/* imm16 operand in exception instructions. */
200 AARCH64_OPND_CCMP_IMM
,/* Immediate in conditional compare instructions. */
201 AARCH64_OPND_NZCV
, /* Flag bit specifier giving an alternative value for
202 each condition flag. */
204 AARCH64_OPND_LIMM
, /* Logical Immediate. */
205 AARCH64_OPND_AIMM
, /* Arithmetic immediate. */
206 AARCH64_OPND_HALF
, /* #<imm16>{, LSL #<shift>} operand in move wide. */
207 AARCH64_OPND_FBITS
, /* FP #<fbits> operand in e.g. SCVTF */
208 AARCH64_OPND_IMM_MOV
, /* Immediate operand for the MOV alias. */
210 AARCH64_OPND_COND
, /* Standard condition as the last operand. */
211 AARCH64_OPND_COND1
, /* Same as the above, but excluding AL and NV. */
213 AARCH64_OPND_ADDR_ADRP
, /* Memory address for ADRP */
214 AARCH64_OPND_ADDR_PCREL14
, /* 14-bit PC-relative address for e.g. TBZ. */
215 AARCH64_OPND_ADDR_PCREL19
, /* 19-bit PC-relative address for e.g. LDR. */
216 AARCH64_OPND_ADDR_PCREL21
, /* 21-bit PC-relative address for e.g. ADR. */
217 AARCH64_OPND_ADDR_PCREL26
, /* 26-bit PC-relative address for e.g. BL. */
219 AARCH64_OPND_ADDR_SIMPLE
, /* Address of ld/st exclusive. */
220 AARCH64_OPND_ADDR_REGOFF
, /* Address of register offset. */
221 AARCH64_OPND_ADDR_SIMM7
, /* Address of signed 7-bit immediate. */
222 AARCH64_OPND_ADDR_SIMM9
, /* Address of signed 9-bit immediate. */
223 AARCH64_OPND_ADDR_SIMM9_2
, /* Same as the above, but the immediate is
224 negative or unaligned and there is
225 no writeback allowed. This operand code
226 is only used to support the programmer-
227 friendly feature of using LDR/STR as the
228 the mnemonic name for LDUR/STUR instructions
229 wherever there is no ambiguity. */
230 AARCH64_OPND_ADDR_UIMM12
, /* Address of unsigned 12-bit immediate. */
231 AARCH64_OPND_SIMD_ADDR_SIMPLE
,/* Address of ld/st multiple structures. */
232 AARCH64_OPND_SIMD_ADDR_POST
, /* Address of ld/st multiple post-indexed. */
234 AARCH64_OPND_SYSREG
, /* System register operand. */
235 AARCH64_OPND_PSTATEFIELD
, /* PSTATE field name operand. */
236 AARCH64_OPND_SYSREG_AT
, /* System register <at_op> operand. */
237 AARCH64_OPND_SYSREG_DC
, /* System register <dc_op> operand. */
238 AARCH64_OPND_SYSREG_IC
, /* System register <ic_op> operand. */
239 AARCH64_OPND_SYSREG_TLBI
, /* System register <tlbi_op> operand. */
240 AARCH64_OPND_BARRIER
, /* Barrier operand. */
241 AARCH64_OPND_BARRIER_ISB
, /* Barrier operand for ISB. */
242 AARCH64_OPND_PRFOP
, /* Prefetch operation. */
243 AARCH64_OPND_BARRIER_PSB
, /* Barrier operand for PSB. */
246 /* Qualifier constrains an operand. It either specifies a variant of an
247 operand type or limits values available to an operand type.
249 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
251 enum aarch64_opnd_qualifier
253 /* Indicating no further qualification on an operand. */
254 AARCH64_OPND_QLF_NIL
,
256 /* Qualifying an operand which is a general purpose (integer) register;
257 indicating the operand data size or a specific register. */
258 AARCH64_OPND_QLF_W
, /* Wn, WZR or WSP. */
259 AARCH64_OPND_QLF_X
, /* Xn, XZR or XSP. */
260 AARCH64_OPND_QLF_WSP
, /* WSP. */
261 AARCH64_OPND_QLF_SP
, /* SP. */
263 /* Qualifying an operand which is a floating-point register, a SIMD
264 vector element or a SIMD vector element list; indicating operand data
265 size or the size of each SIMD vector element in the case of a SIMD
267 These qualifiers are also used to qualify an address operand to
268 indicate the size of data element a load/store instruction is
270 They are also used for the immediate shift operand in e.g. SSHR. Such
271 a use is only for the ease of operand encoding/decoding and qualifier
272 sequence matching; such a use should not be applied widely; use the value
273 constraint qualifiers for immediate operands wherever possible. */
274 AARCH64_OPND_QLF_S_B
,
275 AARCH64_OPND_QLF_S_H
,
276 AARCH64_OPND_QLF_S_S
,
277 AARCH64_OPND_QLF_S_D
,
278 AARCH64_OPND_QLF_S_Q
,
280 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
281 register list; indicating register shape.
282 They are also used for the immediate shift operand in e.g. SSHR. Such
283 a use is only for the ease of operand encoding/decoding and qualifier
284 sequence matching; such a use should not be applied widely; use the value
285 constraint qualifiers for immediate operands wherever possible. */
286 AARCH64_OPND_QLF_V_8B
,
287 AARCH64_OPND_QLF_V_16B
,
288 AARCH64_OPND_QLF_V_2H
,
289 AARCH64_OPND_QLF_V_4H
,
290 AARCH64_OPND_QLF_V_8H
,
291 AARCH64_OPND_QLF_V_2S
,
292 AARCH64_OPND_QLF_V_4S
,
293 AARCH64_OPND_QLF_V_1D
,
294 AARCH64_OPND_QLF_V_2D
,
295 AARCH64_OPND_QLF_V_1Q
,
297 /* Constraint on value. */
298 AARCH64_OPND_QLF_imm_0_7
,
299 AARCH64_OPND_QLF_imm_0_15
,
300 AARCH64_OPND_QLF_imm_0_31
,
301 AARCH64_OPND_QLF_imm_0_63
,
302 AARCH64_OPND_QLF_imm_1_32
,
303 AARCH64_OPND_QLF_imm_1_64
,
305 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
307 AARCH64_OPND_QLF_LSL
,
308 AARCH64_OPND_QLF_MSL
,
310 /* Special qualifier helping retrieve qualifier information during the
311 decoding time (currently not in use). */
312 AARCH64_OPND_QLF_RETRIEVE
,
315 /* Instruction class. */
317 enum aarch64_insn_class
372 ldst_imm9
, /* immpost or immpre */
391 /* Opcode enumerators. */
435 OP_MOV_IMM_LOG
, /* MOV alias for moving bitmask immediate. */
436 OP_MOV_IMM_WIDE
, /* MOV alias for moving wide immediate. */
437 OP_MOV_IMM_WIDEN
, /* MOV alias for moving wide immediate (negated). */
439 OP_MOV_V
, /* MOV alias for moving vector register. */
452 OP_BFC
, /* ARMv8.2. */
469 OP_FCVTXN_S
, /* Scalar version. */
478 OP_TOTAL_NUM
, /* Pseudo. */
481 /* Maximum number of operands an instruction can have. */
482 #define AARCH64_MAX_OPND_NUM 6
483 /* Maximum number of qualifier sequences an instruction can have. */
484 #define AARCH64_MAX_QLF_SEQ_NUM 10
485 /* Operand qualifier typedef; optimized for the size. */
486 typedef unsigned char aarch64_opnd_qualifier_t
;
487 /* Operand qualifier sequence typedef. */
488 typedef aarch64_opnd_qualifier_t \
489 aarch64_opnd_qualifier_seq_t
[AARCH64_MAX_OPND_NUM
];
491 /* FIXME: improve the efficiency. */
492 static inline bfd_boolean
493 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t
*qualifiers
)
496 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
497 if (qualifiers
[i
] != AARCH64_OPND_QLF_NIL
)
502 /* This structure holds information for a particular opcode. */
504 struct aarch64_opcode
506 /* The name of the mnemonic. */
509 /* The opcode itself. Those bits which will be filled in with
510 operands are zeroes. */
513 /* The opcode mask. This is used by the disassembler. This is a
514 mask containing ones indicating those bits which must match the
515 opcode field, and zeroes indicating those bits which need not
516 match (and are presumably filled in by operands). */
519 /* Instruction class. */
520 enum aarch64_insn_class iclass
;
522 /* Enumerator identifier. */
525 /* Which architecture variant provides this instruction. */
526 const aarch64_feature_set
*avariant
;
528 /* An array of operand codes. Each code is an index into the
529 operand table. They appear in the order which the operands must
530 appear in assembly code, and are terminated by a zero. */
531 enum aarch64_opnd operands
[AARCH64_MAX_OPND_NUM
];
533 /* A list of operand qualifier code sequence. Each operand qualifier
534 code qualifies the corresponding operand code. Each operand
535 qualifier sequence specifies a valid opcode variant and related
536 constraint on operands. */
537 aarch64_opnd_qualifier_seq_t qualifiers_list
[AARCH64_MAX_QLF_SEQ_NUM
];
539 /* Flags providing information about this instruction */
542 /* If non-NULL, a function to verify that a given instruction is valid. */
543 bfd_boolean (* verifier
) (const struct aarch64_opcode
*, const aarch64_insn
);
546 typedef struct aarch64_opcode aarch64_opcode
;
548 /* Table describing all the AArch64 opcodes. */
549 extern aarch64_opcode aarch64_opcode_table
[];
552 #define F_ALIAS (1 << 0)
553 #define F_HAS_ALIAS (1 << 1)
554 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
555 is specified, it is the priority 0 by default, i.e. the lowest priority. */
556 #define F_P1 (1 << 2)
557 #define F_P2 (2 << 2)
558 #define F_P3 (3 << 2)
559 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
560 #define F_COND (1 << 4)
561 /* Instruction has the field of 'sf'. */
562 #define F_SF (1 << 5)
563 /* Instruction has the field of 'size:Q'. */
564 #define F_SIZEQ (1 << 6)
565 /* Floating-point instruction has the field of 'type'. */
566 #define F_FPTYPE (1 << 7)
567 /* AdvSIMD scalar instruction has the field of 'size'. */
568 #define F_SSIZE (1 << 8)
569 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
571 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
572 #define F_GPRSIZE_IN_Q (1 << 10)
573 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
574 #define F_LDS_SIZE (1 << 11)
575 /* Optional operand; assume maximum of 1 operand can be optional. */
576 #define F_OPD0_OPT (1 << 12)
577 #define F_OPD1_OPT (2 << 12)
578 #define F_OPD2_OPT (3 << 12)
579 #define F_OPD3_OPT (4 << 12)
580 #define F_OPD4_OPT (5 << 12)
581 /* Default value for the optional operand when omitted from the assembly. */
582 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
583 /* Instruction that is an alias of another instruction needs to be
584 encoded/decoded by converting it to/from the real form, followed by
585 the encoding/decoding according to the rules of the real opcode.
586 This compares to the direct coding using the alias's information.
587 N.B. this flag requires F_ALIAS to be used together. */
588 #define F_CONV (1 << 20)
589 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
590 friendly pseudo instruction available only in the assembly code (thus will
591 not show up in the disassembly). */
592 #define F_PSEUDO (1 << 21)
593 /* Instruction has miscellaneous encoding/decoding rules. */
594 #define F_MISC (1 << 22)
595 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
596 #define F_N (1 << 23)
597 /* Opcode dependent field. */
598 #define F_OD(X) (((X) & 0x7) << 24)
599 /* Instruction has the field of 'sz'. */
600 #define F_LSE_SZ (1 << 27)
601 /* Next bit is 28. */
603 static inline bfd_boolean
604 alias_opcode_p (const aarch64_opcode
*opcode
)
606 return (opcode
->flags
& F_ALIAS
) ? TRUE
: FALSE
;
609 static inline bfd_boolean
610 opcode_has_alias (const aarch64_opcode
*opcode
)
612 return (opcode
->flags
& F_HAS_ALIAS
) ? TRUE
: FALSE
;
615 /* Priority for disassembling preference. */
617 opcode_priority (const aarch64_opcode
*opcode
)
619 return (opcode
->flags
>> 2) & 0x3;
622 static inline bfd_boolean
623 pseudo_opcode_p (const aarch64_opcode
*opcode
)
625 return (opcode
->flags
& F_PSEUDO
) != 0lu ? TRUE
: FALSE
;
628 static inline bfd_boolean
629 optional_operand_p (const aarch64_opcode
*opcode
, unsigned int idx
)
631 return (((opcode
->flags
>> 12) & 0x7) == idx
+ 1)
635 static inline aarch64_insn
636 get_optional_operand_default_value (const aarch64_opcode
*opcode
)
638 return (opcode
->flags
>> 15) & 0x1f;
641 static inline unsigned int
642 get_opcode_dependent_value (const aarch64_opcode
*opcode
)
644 return (opcode
->flags
>> 24) & 0x7;
647 static inline bfd_boolean
648 opcode_has_special_coder (const aarch64_opcode
*opcode
)
650 return (opcode
->flags
& (F_SF
| F_LSE_SZ
| F_SIZEQ
| F_FPTYPE
| F_SSIZE
| F_T
651 | F_GPRSIZE_IN_Q
| F_LDS_SIZE
| F_MISC
| F_N
| F_COND
)) ? TRUE
655 struct aarch64_name_value_pair
661 extern const struct aarch64_name_value_pair aarch64_operand_modifiers
[];
662 extern const struct aarch64_name_value_pair aarch64_barrier_options
[16];
663 extern const struct aarch64_name_value_pair aarch64_prfops
[32];
664 extern const struct aarch64_name_value_pair aarch64_hint_options
[];
673 extern const aarch64_sys_reg aarch64_sys_regs
[];
674 extern const aarch64_sys_reg aarch64_pstatefields
[];
675 extern bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*);
676 extern bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set
,
677 const aarch64_sys_reg
*);
678 extern bfd_boolean
aarch64_pstatefield_supported_p (const aarch64_feature_set
,
679 const aarch64_sys_reg
*);
686 } aarch64_sys_ins_reg
;
688 extern bfd_boolean
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg
*);
690 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set
,
691 const aarch64_sys_ins_reg
*);
693 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic
[];
694 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc
[];
695 extern const aarch64_sys_ins_reg aarch64_sys_regs_at
[];
696 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[];
698 /* Shift/extending operator kinds.
699 N.B. order is important; keep aarch64_operand_modifiers synced. */
700 enum aarch64_modifier_kind
719 aarch64_extend_operator_p (enum aarch64_modifier_kind
);
721 enum aarch64_modifier_kind
722 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*);
727 /* A list of names with the first one as the disassembly preference;
728 terminated by NULL if fewer than 3. */
729 const char *names
[3];
733 extern const aarch64_cond aarch64_conds
[16];
735 const aarch64_cond
* get_cond_from_value (aarch64_insn value
);
736 const aarch64_cond
* get_inverted_cond (const aarch64_cond
*cond
);
738 /* Structure representing an operand. */
740 struct aarch64_opnd_info
742 enum aarch64_opnd type
;
743 aarch64_opnd_qualifier_t qualifier
;
760 unsigned first_regno
: 5;
761 unsigned num_regs
: 3;
762 /* 1 if it is a list of reg element. */
763 unsigned has_index
: 1;
764 /* Lane index; valid only when has_index is 1. */
767 /* e.g. immediate or pc relative address offset. */
773 /* e.g. address in STR (register offset). */
786 unsigned pcrel
: 1; /* PC-relative. */
787 unsigned writeback
: 1;
788 unsigned preind
: 1; /* Pre-indexed. */
789 unsigned postind
: 1; /* Post-indexed. */
791 const aarch64_cond
*cond
;
792 /* The encoding of the system register. */
794 /* The encoding of the PSTATE field. */
795 aarch64_insn pstatefield
;
796 const aarch64_sys_ins_reg
*sysins_op
;
797 const struct aarch64_name_value_pair
*barrier
;
798 const struct aarch64_name_value_pair
*hint_option
;
799 const struct aarch64_name_value_pair
*prfop
;
802 /* Operand shifter; in use when the operand is a register offset address,
803 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
806 enum aarch64_modifier_kind kind
;
808 unsigned operator_present
: 1; /* Only valid during encoding. */
809 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
810 unsigned amount_present
: 1;
813 unsigned skip
:1; /* Operand is not completed if there is a fixup needed
814 to be done on it. In some (but not all) of these
815 cases, we need to tell libopcodes to skip the
816 constraint checking and the encoding for this
817 operand, so that the libopcodes can pick up the
818 right opcode before the operand is fixed-up. This
819 flag should only be used during the
820 assembling/encoding. */
821 unsigned present
:1; /* Whether this operand is present in the assembly
822 line; not used during the disassembly. */
825 typedef struct aarch64_opnd_info aarch64_opnd_info
;
827 /* Structure representing an instruction.
829 It is used during both the assembling and disassembling. The assembler
830 fills an aarch64_inst after a successful parsing and then passes it to the
831 encoding routine to do the encoding. During the disassembling, the
832 disassembler calls the decoding routine to decode a binary instruction; on a
833 successful return, such a structure will be filled with information of the
834 instruction; then the disassembler uses the information to print out the
839 /* The value of the binary instruction. */
842 /* Corresponding opcode entry. */
843 const aarch64_opcode
*opcode
;
845 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
846 const aarch64_cond
*cond
;
848 /* Operands information. */
849 aarch64_opnd_info operands
[AARCH64_MAX_OPND_NUM
];
852 typedef struct aarch64_inst aarch64_inst
;
854 /* Diagnosis related declaration and interface. */
856 /* Operand error kind enumerators.
858 AARCH64_OPDE_RECOVERABLE
859 Less severe error found during the parsing, very possibly because that
860 GAS has picked up a wrong instruction template for the parsing.
862 AARCH64_OPDE_SYNTAX_ERROR
863 General syntax error; it can be either a user error, or simply because
864 that GAS is trying a wrong instruction template.
866 AARCH64_OPDE_FATAL_SYNTAX_ERROR
867 Definitely a user syntax error.
869 AARCH64_OPDE_INVALID_VARIANT
870 No syntax error, but the operands are not a valid combination, e.g.
873 AARCH64_OPDE_OUT_OF_RANGE
874 Error about some immediate value out of a valid range.
876 AARCH64_OPDE_UNALIGNED
877 Error about some immediate value not properly aligned (i.e. not being a
878 multiple times of a certain value).
880 AARCH64_OPDE_REG_LIST
881 Error about the register list operand having unexpected number of
884 AARCH64_OPDE_OTHER_ERROR
885 Error of the highest severity and used for any severe issue that does not
886 fall into any of the above categories.
888 The enumerators are only interesting to GAS. They are declared here (in
889 libopcodes) because that some errors are detected (and then notified to GAS)
890 by libopcodes (rather than by GAS solely).
892 The first three errors are only deteced by GAS while the
893 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
894 only libopcodes has the information about the valid variants of each
897 The enumerators have an increasing severity. This is helpful when there are
898 multiple instruction templates available for a given mnemonic name (e.g.
899 FMOV); this mechanism will help choose the most suitable template from which
900 the generated diagnostics can most closely describe the issues, if any. */
902 enum aarch64_operand_error_kind
905 AARCH64_OPDE_RECOVERABLE
,
906 AARCH64_OPDE_SYNTAX_ERROR
,
907 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
908 AARCH64_OPDE_INVALID_VARIANT
,
909 AARCH64_OPDE_OUT_OF_RANGE
,
910 AARCH64_OPDE_UNALIGNED
,
911 AARCH64_OPDE_REG_LIST
,
912 AARCH64_OPDE_OTHER_ERROR
915 /* N.B. GAS assumes that this structure work well with shallow copy. */
916 struct aarch64_operand_error
918 enum aarch64_operand_error_kind kind
;
921 int data
[3]; /* Some data for extra information. */
924 typedef struct aarch64_operand_error aarch64_operand_error
;
926 /* Encoding entrypoint. */
929 aarch64_opcode_encode (const aarch64_opcode
*, const aarch64_inst
*,
930 aarch64_insn
*, aarch64_opnd_qualifier_t
*,
931 aarch64_operand_error
*);
933 extern const aarch64_opcode
*
934 aarch64_replace_opcode (struct aarch64_inst
*,
935 const aarch64_opcode
*);
937 /* Given the opcode enumerator OP, return the pointer to the corresponding
940 extern const aarch64_opcode
*
941 aarch64_get_opcode (enum aarch64_op
);
943 /* Generate the string representation of an operand. */
945 aarch64_print_operand (char *, size_t, bfd_vma
, const aarch64_opcode
*,
946 const aarch64_opnd_info
*, int, int *, bfd_vma
*);
948 /* Miscellaneous interface. */
951 aarch64_operand_index (const enum aarch64_opnd
*, enum aarch64_opnd
);
953 extern aarch64_opnd_qualifier_t
954 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*, int,
955 const aarch64_opnd_qualifier_t
, int);
958 aarch64_num_of_operands (const aarch64_opcode
*);
961 aarch64_stack_pointer_p (const aarch64_opnd_info
*);
964 aarch64_zero_register_p (const aarch64_opnd_info
*);
967 aarch64_decode_insn (aarch64_insn
, aarch64_inst
*, bfd_boolean
);
969 /* Given an operand qualifier, return the expected data element size
970 of a qualified operand. */
972 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t
);
974 extern enum aarch64_operand_class
975 aarch64_get_operand_class (enum aarch64_opnd
);
978 aarch64_get_operand_name (enum aarch64_opnd
);
981 aarch64_get_operand_desc (enum aarch64_opnd
);
984 extern int debug_dump
;
987 aarch64_verbose (const char *, ...) __attribute__ ((format (printf
, 1, 2)));
989 #define DEBUG_TRACE(M, ...) \
992 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
995 #define DEBUG_TRACE_IF(C, M, ...) \
997 if (debug_dump && (C)) \
998 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1000 #else /* !DEBUG_AARCH64 */
1001 #define DEBUG_TRACE(M, ...) ;
1002 #define DEBUG_TRACE_IF(C, M, ...) ;
1003 #endif /* DEBUG_AARCH64 */
1009 #endif /* OPCODE_AARCH64_H */