include/opcode/riscv.h

   1 /* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   2    Copyright (C) 2011-2024 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    3, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _RISCV_H_
  22 #define _RISCV_H_
  23
  24 #include "riscv-opc.h"
  25 #include <stdlib.h>
  26 #include <stdint.h>
  27
  28 typedef uint64_t insn_t;
  29
  30 static inline unsigned int riscv_insn_length (insn_t insn)
  31 {
  32   if ((insn & 0x3) != 0x3) /* RVC instructions.  */
  33     return 2;
  34   if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
  35     return 4;
  36   if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
  37     return 6;
  38   if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
  39     return 8;
  40   /* 80- ... 176-bit instructions.  */
  41   if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)
  42     return 10 + ((insn >> 11) & 0xe);
  43   /* Maximum value returned by this function.  */
  44 #define RISCV_MAX_INSN_LEN 22
  45   /* Longer instructions not supported at the moment.  */
  46   return 2;
  47 }
  48
  49 #define RVC_JUMP_BITS 11
  50 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  51
  52 #define RVC_BRANCH_BITS 8
  53 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
  54
  55 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
  56 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  57 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
  58 #define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))
  59
  60 #define EXTRACT_ITYPE_IMM(x) \
  61   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
  62 #define EXTRACT_STYPE_IMM(x) \
  63   (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
  64 #define EXTRACT_BTYPE_IMM(x) \
  65   ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
  66 #define EXTRACT_UTYPE_IMM(x) \
  67   ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
  68 #define EXTRACT_JTYPE_IMM(x) \
  69   ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
  70 #define EXTRACT_CITYPE_IMM(x) \
  71   (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
  72 #define EXTRACT_CITYPE_LUI_IMM(x) \
  73   (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
  74 #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
  75   ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
  76 #define EXTRACT_CITYPE_LWSP_IMM(x) \
  77   ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
  78 #define EXTRACT_CITYPE_LDSP_IMM(x) \
  79   ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
  80 #define EXTRACT_CSSTYPE_IMM(x) \
  81   (RV_X(x, 7, 6) << 0)
  82 #define EXTRACT_CSSTYPE_SWSP_IMM(x) \
  83   ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
  84 #define EXTRACT_CSSTYPE_SDSP_IMM(x) \
  85   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
  86 #define EXTRACT_CIWTYPE_IMM(x) \
  87   (RV_X(x, 5, 8))
  88 #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
  89   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
  90 #define EXTRACT_CLTYPE_IMM(x) \
  91   ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
  92 #define EXTRACT_CLTYPE_LW_IMM(x) \
  93   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
  94 #define EXTRACT_CLTYPE_LD_IMM(x) \
  95   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
  96 #define EXTRACT_CBTYPE_IMM(x) \
  97   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
  98 #define EXTRACT_CJTYPE_IMM(x) \
  99   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
 100 #define EXTRACT_RVV_VI_IMM(x) \
 101   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
 102 #define EXTRACT_RVV_VI_UIMM(x) \
 103   (RV_X(x, 15, 5))
 104 #define EXTRACT_RVV_VI_UIMM6(x) \
 105   (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
 106 #define EXTRACT_RVV_OFFSET(x) \
 107   (RV_X(x, 29, 3))
 108 #define EXTRACT_RVV_VB_IMM(x) \
 109   (RV_X(x, 20, 10))
 110 #define EXTRACT_RVV_VC_IMM(x) \
 111   (RV_X(x, 20, 11))
 112 #define EXTRACT_ZCB_BYTE_UIMM(x) \
 113   (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
 114 #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
 115   (RV_X(x, 5, 1) << 1)
 116 #define EXTRACT_ZCMP_SPIMM(x) \
 117   (RV_X(x, 2, 2) << 4)
 118 /* Vendor-specific (CORE-V) extract macros.  */
 119 #define EXTRACT_CV_IS2_UIMM5(x) \
 120   (RV_X(x, 20, 5))
 121 #define EXTRACT_CV_IS3_UIMM5(x) \
 122   (RV_X(x, 25, 5))
 123 #define EXTRACT_CV_BI_IMM5(x) \
 124   (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
 125 #define EXTRACT_CV_BITMANIP_UIMM5(x) \
 126   (RV_X(x, 25, 5))
 127 #define EXTRACT_CV_BITMANIP_UIMM2(x) \
 128   (RV_X(x, 25, 2))
 129 #define EXTRACT_CV_SIMD_IMM6(x) \
 130   ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
 131 #define EXTRACT_CV_SIMD_UIMM6(x) \
 132   ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))
 133
 134 #define ENCODE_ITYPE_IMM(x) \
 135   (RV_X(x, 0, 12) << 20)
 136 #define ENCODE_STYPE_IMM(x) \
 137   ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
 138 #define ENCODE_BTYPE_IMM(x) \
 139   ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
 140 #define ENCODE_UTYPE_IMM(x) \
 141   (RV_X(x, 12, 20) << 12)
 142 #define ENCODE_JTYPE_IMM(x) \
 143   ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 144 #define ENCODE_CITYPE_IMM(x) \
 145   ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
 146 #define ENCODE_CITYPE_LUI_IMM(x) \
 147   ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
 148 #define ENCODE_CITYPE_ADDI16SP_IMM(x) \
 149   ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 150 #define ENCODE_CITYPE_LWSP_IMM(x) \
 151   ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
 152 #define ENCODE_CITYPE_LDSP_IMM(x) \
 153   ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
 154 #define ENCODE_CSSTYPE_IMM(x) \
 155   (RV_X(x, 0, 6) << 7)
 156 #define ENCODE_CSSTYPE_SWSP_IMM(x) \
 157   ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
 158 #define ENCODE_CSSTYPE_SDSP_IMM(x) \
 159   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 160 #define ENCODE_CIWTYPE_IMM(x) \
 161   (RV_X(x, 0, 8) << 5)
 162 #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
 163   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 164 #define ENCODE_CLTYPE_IMM(x) \
 165   ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
 166 #define ENCODE_CLTYPE_LW_IMM(x) \
 167   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 168 #define ENCODE_CLTYPE_LD_IMM(x) \
 169   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
 170 #define ENCODE_CBTYPE_IMM(x) \
 171   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 172 #define ENCODE_CJTYPE_IMM(x) \
 173   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 174 #define ENCODE_RVV_VB_IMM(x) \
 175   (RV_X(x, 0, 10) << 20)
 176 #define ENCODE_RVV_VC_IMM(x) \
 177   (RV_X(x, 0, 11) << 20)
 178 #define ENCODE_RVV_VI_UIMM6(x) \
 179   (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
 180 #define ENCODE_ZCB_BYTE_UIMM(x) \
 181   ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
 182 #define ENCODE_ZCB_HALFWORD_UIMM(x) \
 183   (RV_X(x, 1, 1) << 5)
 184 #define ENCODE_ZCMP_SPIMM(x) \
 185   (RV_X(x, 4, 2) << 2)
 186 /* Vendor-specific (CORE-V) encode macros.  */
 187 #define ENCODE_CV_IS2_UIMM5(x) \
 188   (RV_X(x, 0, 5) << 20)
 189 #define ENCODE_CV_IS3_UIMM5(x) \
 190   (RV_X(x, 0, 5) << 25)
 191 #define ENCODE_CV_BITMANIP_UIMM5(x) \
 192   (RV_X(x, 0, 5) << 25)
 193 #define ENCODE_CV_BITMANIP_UIMM2(x) \
 194   (RV_X(x, 0, 2) << 25)
 195 #define ENCODE_CV_SIMD_IMM6(x) \
 196   ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
 197 #define ENCODE_CV_SIMD_UIMM6(x) \
 198   ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
 199
 200 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 201 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 202 #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
 203 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 204 #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
 205 #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
 206 #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
 207                                  && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
 208 #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
 209                                       && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
 210 #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
 211 #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
 212 #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
 213 #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
 214 #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
 215 #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
 216 #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
 217 #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
 218 #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
 219 #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
 220 #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
 221 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
 222 #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
 223 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
 224 #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
 225 #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
 226 #define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x))
 227
 228 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
 229   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
 230 #define RISCV_ITYPE(insn, rd, rs1, imm) \
 231   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
 232 #define RISCV_STYPE(insn, rs1, rs2, imm) \
 233   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
 234 #define RISCV_BTYPE(insn, rs1, rs2, target) \
 235   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
 236 #define RISCV_UTYPE(insn, rd, bigimm) \
 237   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
 238 #define RISCV_JTYPE(insn, rd, target) \
 239   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
 240
 241 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 242 #define RVC_NOP MATCH_C_ADDI
 243
 244 #define RISCV_CONST_HIGH_PART(VALUE) \
 245   (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 246 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 247 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 248 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 249
 250 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
 251 #define RISCV_JUMP_ALIGN_BITS 1
 252 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 253 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
 254
 255 #define RISCV_IMM_BITS 12
 256 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
 257 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
 258 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
 259 #define RISCV_RVC_IMM_REACH (1LL << 6)
 260 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
 261 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 262 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 263 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
 264
 265 /* RV fields.  */
 266
 267 #define OP_MASK_OP              0x7f
 268 #define OP_SH_OP                0
 269 #define OP_MASK_RS2             0x1f
 270 #define OP_SH_RS2               20
 271 #define OP_MASK_RS1             0x1f
 272 #define OP_SH_RS1               15
 273 #define OP_MASK_RS3             0x1fU
 274 #define OP_SH_RS3               27
 275 #define OP_MASK_RD              0x1f
 276 #define OP_SH_RD                7
 277 #define OP_MASK_SHAMT           0x3f
 278 #define OP_SH_SHAMT             20
 279 #define OP_MASK_SHAMTW          0x1f
 280 #define OP_SH_SHAMTW            20
 281 #define OP_MASK_RM              0x7
 282 #define OP_SH_RM                12
 283 #define OP_MASK_PRED            0xf
 284 #define OP_SH_PRED              24
 285 #define OP_MASK_SUCC            0xf
 286 #define OP_SH_SUCC              20
 287 #define OP_MASK_AQ              0x1
 288 #define OP_SH_AQ                26
 289 #define OP_MASK_RL              0x1
 290 #define OP_SH_RL                25
 291
 292 #define OP_MASK_CSR             0xfffU
 293 #define OP_SH_CSR               20
 294
 295 #define OP_MASK_FUNCT3          0x7
 296 #define OP_SH_FUNCT3            12
 297 #define OP_MASK_FUNCT7          0x7fU
 298 #define OP_SH_FUNCT7            25
 299 #define OP_MASK_FUNCT2          0x3
 300 #define OP_SH_FUNCT2            25
 301
 302 /* RVC fields.  */
 303
 304 #define OP_MASK_OP2             0x3
 305 #define OP_SH_OP2               0
 306
 307 #define OP_MASK_CRS2            0x1f
 308 #define OP_SH_CRS2              2
 309 #define OP_MASK_CRS1S           0x7
 310 #define OP_SH_CRS1S             7
 311 #define OP_MASK_CRS2S           0x7
 312 #define OP_SH_CRS2S             2
 313
 314 #define OP_MASK_CFUNCT6         0x3f
 315 #define OP_SH_CFUNCT6           10
 316 #define OP_MASK_CFUNCT4         0xf
 317 #define OP_SH_CFUNCT4           12
 318 #define OP_MASK_CFUNCT3         0x7
 319 #define OP_SH_CFUNCT3           13
 320 #define OP_MASK_CFUNCT2         0x3
 321 #define OP_SH_CFUNCT2           5
 322
 323 /* Scalar crypto fields. */
 324
 325 #define OP_SH_BS        30
 326 #define OP_MASK_BS      3
 327 #define OP_SH_RNUM      20
 328 #define OP_MASK_RNUM    0xf
 329
 330 /* RVV fields.  */
 331
 332 #define OP_MASK_VD              0x1f
 333 #define OP_SH_VD                7
 334 #define OP_MASK_VS1             0x1f
 335 #define OP_SH_VS1               15
 336 #define OP_MASK_VS2             0x1f
 337 #define OP_SH_VS2               20
 338 #define OP_MASK_VIMM            0x1f
 339 #define OP_SH_VIMM              15
 340 #define OP_MASK_VMASK           0x1
 341 #define OP_SH_VMASK             25
 342 #define OP_MASK_VFUNCT6         0x3f
 343 #define OP_SH_VFUNCT6           26
 344 #define OP_MASK_VLMUL           0x7
 345 #define OP_SH_VLMUL             0
 346 #define OP_MASK_VSEW            0x7
 347 #define OP_SH_VSEW              3
 348 #define OP_MASK_VTA             0x1
 349 #define OP_SH_VTA               6
 350 #define OP_MASK_VMA             0x1
 351 #define OP_SH_VMA               7
 352 #define OP_MASK_VWD             0x1
 353 #define OP_SH_VWD               26
 354
 355 #define OP_MASK_XTHEADVLMUL     0x3
 356 #define OP_SH_XTHEADVLMUL       0
 357 #define OP_MASK_XTHEADVSEW      0x7
 358 #define OP_SH_XTHEADVSEW        2
 359 #define OP_MASK_XTHEADVEDIV     0x3
 360 #define OP_SH_XTHEADVEDIV       5
 361 #define OP_MASK_XTHEADVTYPE_RES 0xf
 362 #define OP_SH_XTHEADVTYPE_RES   7
 363
 364 /* Zc fields.  */
 365 #define OP_MASK_REG_LIST        0xf
 366 #define OP_SH_REG_LIST          4
 367 #define ZCMP_SP_ALIGNMENT       16
 368 #define OP_MASK_SREG1           0x7
 369 #define OP_SH_SREG1             7
 370 #define OP_MASK_SREG2           0x7
 371 #define OP_SH_SREG2             2
 372
 373 #define NVECR 32
 374 #define NVECM 1
 375
 376 /* SiFive fields.  */
 377 #define OP_MASK_XSO2            0x3
 378 #define OP_SH_XSO2              26
 379 #define OP_MASK_XSO1            0x1
 380 #define OP_SH_XSO1              26
 381
 382 /* ABI names for selected x-registers.  */
 383
 384 #define X_RA 1
 385 #define X_SP 2
 386 #define X_GP 3
 387 #define X_TP 4
 388 #define X_T0 5
 389 #define X_T1 6
 390 #define X_T2 7
 391 #define X_S0 8
 392 #define X_S1 9
 393 #define X_A0 10
 394 #define X_A1 11
 395 #define X_S2 18
 396 #define X_S7 23
 397 #define X_S10 26
 398 #define X_S11 27
 399 #define X_T3 28
 400
 401 #define NGPR 32
 402 #define NFPR 32
 403
 404 /* These fake label defines are use by both the assembler, and
 405    libopcodes.  The assembler uses this when it needs to generate a fake
 406    label, and libopcodes uses it to hide the fake labels in its output.  */
 407 #define RISCV_FAKE_LABEL_NAME ".L0 "
 408 #define RISCV_FAKE_LABEL_CHAR ' '
 409
 410 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
 411    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
 412 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
 413   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
 414               | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 415
 416 /* Extract bits MASK << SHIFT from STRUCT and shift them right
 417    SHIFT places.  */
 418 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
 419   (((STRUCT) >> (SHIFT)) & (MASK))
 420
 421 /* Extract the operand given by FIELD from integer INSN.  */
 422 #define EXTRACT_OPERAND(FIELD, INSN) \
 423   ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD))
 424
 425 /* Extract an unsigned immediate operand on position s with n bits.  */
 426 #define EXTRACT_U_IMM(n, s, l) \
 427   RV_X (l, s, n)
 428
 429 /* Extract an signed immediate operand on position s with n bits.  */
 430 #define EXTRACT_S_IMM(n, s, l) \
 431   RV_X_SIGNED (l, s, n)
 432
 433 /* Validate that unsigned n-bit immediate is within bounds.  */
 434 #define VALIDATE_U_IMM(v, n) \
 435   ((unsigned long) v < (1UL << n))
 436
 437 /* Validate that signed n-bit immediate is within bounds.  */
 438 #define VALIDATE_S_IMM(v, n) \
 439   (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1)))
 440
 441 /* The maximal number of subset can be required.  */
 442 #define MAX_SUBSET_NUM 4
 443
 444 /* The range of sregs.  */
 445 #define RISCV_SREG_0_7(REGNO) \
 446         ((REGNO == X_S0 || REGNO == X_S1) \
 447          || (REGNO >= X_S2 && REGNO <= X_S7))
 448
 449 /* All RISC-V instructions belong to at least one of these classes.  */
 450 enum riscv_insn_class
 451 {
 452   INSN_CLASS_NONE,
 453
 454   INSN_CLASS_I,
 455   INSN_CLASS_C,
 456   INSN_CLASS_M,
 457   INSN_CLASS_F,
 458   INSN_CLASS_D,
 459   INSN_CLASS_Q,
 460   INSN_CLASS_F_AND_C,
 461   INSN_CLASS_D_AND_C,
 462   INSN_CLASS_ZICOND,
 463   INSN_CLASS_ZICSR,
 464   INSN_CLASS_ZIFENCEI,
 465   INSN_CLASS_ZIHINTNTL,
 466   INSN_CLASS_ZIHINTNTL_AND_C,
 467   INSN_CLASS_ZIHINTPAUSE,
 468   INSN_CLASS_ZIMOP,
 469   INSN_CLASS_ZMMUL,
 470   INSN_CLASS_ZAAMO,
 471   INSN_CLASS_ZALRSC,
 472   INSN_CLASS_ZAWRS,
 473   INSN_CLASS_F_INX,
 474   INSN_CLASS_D_INX,
 475   INSN_CLASS_Q_INX,
 476   INSN_CLASS_ZFH_INX,
 477   INSN_CLASS_ZFHMIN,
 478   INSN_CLASS_ZFHMIN_INX,
 479   INSN_CLASS_ZFHMIN_AND_D_INX,
 480   INSN_CLASS_ZFHMIN_AND_Q_INX,
 481   INSN_CLASS_ZFBFMIN,
 482   INSN_CLASS_ZFA,
 483   INSN_CLASS_D_AND_ZFA,
 484   INSN_CLASS_Q_AND_ZFA,
 485   INSN_CLASS_ZFH_AND_ZFA,
 486   INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA,
 487   INSN_CLASS_ZBA,
 488   INSN_CLASS_ZBB,
 489   INSN_CLASS_ZBC,
 490   INSN_CLASS_ZBS,
 491   INSN_CLASS_ZBKB,
 492   INSN_CLASS_ZBKC,
 493   INSN_CLASS_ZBKX,
 494   INSN_CLASS_ZKND,
 495   INSN_CLASS_ZKNE,
 496   INSN_CLASS_ZKNH,
 497   INSN_CLASS_ZKSED,
 498   INSN_CLASS_ZKSH,
 499   INSN_CLASS_ZBB_OR_ZBKB,
 500   INSN_CLASS_ZBC_OR_ZBKC,
 501   INSN_CLASS_ZKND_OR_ZKNE,
 502   INSN_CLASS_V,
 503   INSN_CLASS_ZVEF,
 504   INSN_CLASS_ZVBB,
 505   INSN_CLASS_ZVBC,
 506   INSN_CLASS_ZVFBFMIN,
 507   INSN_CLASS_ZVFBFWMA,
 508   INSN_CLASS_ZVKB,
 509   INSN_CLASS_ZVKG,
 510   INSN_CLASS_ZVKNED,
 511   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
 512   INSN_CLASS_ZVKSED,
 513   INSN_CLASS_ZVKSH,
 514   INSN_CLASS_ZCB,
 515   INSN_CLASS_ZCB_AND_ZBA,
 516   INSN_CLASS_ZCB_AND_ZBB,
 517   INSN_CLASS_ZCB_AND_ZMMUL,
 518   INSN_CLASS_ZCMOP,
 519   INSN_CLASS_ZCMP,
 520   INSN_CLASS_SVINVAL,
 521   INSN_CLASS_ZICBOM,
 522   INSN_CLASS_ZICBOP,
 523   INSN_CLASS_ZICBOZ,
 524   INSN_CLASS_ZABHA,
 525   INSN_CLASS_ZACAS,
 526   INSN_CLASS_ZABHA_AND_ZACAS,
 527   INSN_CLASS_H,
 528   INSN_CLASS_XCVALU,
 529   INSN_CLASS_XCVBI,
 530   INSN_CLASS_XCVBITMANIP,
 531   INSN_CLASS_XCVELW,
 532   INSN_CLASS_XCVMAC,
 533   INSN_CLASS_XCVMEM,
 534   INSN_CLASS_XCVSIMD,
 535   INSN_CLASS_XTHEADBA,
 536   INSN_CLASS_XTHEADBB,
 537   INSN_CLASS_XTHEADBS,
 538   INSN_CLASS_XTHEADCMO,
 539   INSN_CLASS_XTHEADCONDMOV,
 540   INSN_CLASS_XTHEADFMEMIDX,
 541   INSN_CLASS_XTHEADFMV,
 542   INSN_CLASS_XTHEADINT,
 543   INSN_CLASS_XTHEADMAC,
 544   INSN_CLASS_XTHEADMEMIDX,
 545   INSN_CLASS_XTHEADMEMPAIR,
 546   INSN_CLASS_XTHEADSYNC,
 547   INSN_CLASS_XTHEADVECTOR,
 548   INSN_CLASS_XTHEADZVAMO,
 549   INSN_CLASS_XVENTANACONDOPS,
 550   INSN_CLASS_XSFVCP,
 551   INSN_CLASS_XSFCEASE,
 552 };
 553
 554 /* This structure holds information for a particular instruction.  */
 555 struct riscv_opcode
 556 {
 557   /* The name of the instruction.  */
 558   const char *name;
 559
 560   /* The requirement of xlen for the instruction, 0 if no requirement.  */
 561   unsigned xlen_requirement;
 562
 563   /* Class to which this instruction belongs.  Used to decide whether or
 564      not this instruction is legal in the current -march context.  */
 565   enum riscv_insn_class insn_class;
 566
 567   /* A string describing the arguments for this instruction.  */
 568   const char *args;
 569
 570   /* The basic opcode for the instruction.  When assembling, this
 571      opcode is modified by the arguments to produce the actual opcode
 572      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 573   insn_t match;
 574
 575   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 576      relevant portions of the opcode when disassembling.  If the
 577      actual opcode anded with the match field equals the opcode field,
 578      then we have found the correct instruction.  If pinfo is
 579      INSN_MACRO, then this field is the macro identifier.  */
 580   insn_t mask;
 581
 582   /* A function to determine if a word corresponds to this instruction.
 583      Usually, this computes ((word & mask) == match).  */
 584   int (*match_func) (const struct riscv_opcode *op, insn_t word);
 585
 586   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 587      of bits describing the instruction, notably any relevant hazard
 588      information.  */
 589   unsigned long pinfo;
 590 };
 591
 592 /* Instruction is a simple alias (e.g. "mv" for "addi").  */
 593 #define INSN_ALIAS              0x00000001
 594
 595 /* These are for setting insn_info fields.
 596
 597    Nonbranch is the default.  Noninsn is used only if there is no match.
 598    There are no condjsr or dref2 instructions.  So that leaves condbranch,
 599    branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
 600 #define INSN_TYPE               0x0000000e
 601
 602 /* Instruction is an unconditional branch.  */
 603 #define INSN_BRANCH             0x00000002
 604 /* Instruction is a conditional branch.  */
 605 #define INSN_CONDBRANCH         0x00000004
 606 /* Instruction is a jump to subroutine.  */
 607 #define INSN_JSR                0x00000006
 608 /* Instruction is a data reference.  */
 609 #define INSN_DREF               0x00000008
 610 /* Instruction is allowed when eew >= 64.  */
 611 #define INSN_V_EEW64            0x10000000
 612
 613 /* We have 5 data reference sizes, which we can encode in 3 bits.  */
 614 #define INSN_DATA_SIZE          0x00000070
 615 #define INSN_DATA_SIZE_SHIFT    4
 616 #define INSN_1_BYTE             0x00000010
 617 #define INSN_2_BYTE             0x00000020
 618 #define INSN_4_BYTE             0x00000030
 619 #define INSN_8_BYTE             0x00000040
 620 #define INSN_16_BYTE            0x00000050
 621
 622 /* Instruction is actually a macro.  It should be ignored by the
 623    disassembler, and requires special treatment by the assembler.  */
 624 #define INSN_MACRO              0xffffffff
 625
 626 /* This is a list of macro expanded instructions.  */
 627 enum
 628 {
 629   M_LA,
 630   M_LLA,
 631   M_LGA,
 632   M_LA_TLS_GD,
 633   M_LA_TLS_IE,
 634   M_Lx,
 635   M_FLx,
 636   M_Sx_FSx,
 637   M_CALL,
 638   M_J,
 639   M_LI,
 640   M_EXTH,
 641   M_ZEXTW,
 642   M_SEXTB,
 643   M_VMSGE,
 644   M_NUM_MACROS
 645 };
 646
 647 /* The mapping symbol states.  */
 648 enum riscv_seg_mstate
 649 {
 650   MAP_NONE = 0,         /* Must be zero, for seginfo in new sections.  */
 651   MAP_DATA,             /* Data.  */
 652   MAP_INSN,             /* Instructions.  */
 653 };
 654
 655 #define NRC (4 + 1)     /* Max characters in register names, incl nul.  */
 656
 657 extern const char riscv_gpr_names_numeric[NGPR][NRC];
 658 extern const char riscv_gpr_names_abi[NGPR][NRC];
 659 extern const char riscv_fpr_names_numeric[NFPR][NRC];
 660 extern const char riscv_fpr_names_abi[NFPR][NRC];
 661 extern const char * const riscv_rm[8];
 662 extern const char * const riscv_pred_succ[16];
 663 extern const char riscv_vecr_names_numeric[NVECR][NRC];
 664 extern const char riscv_vecm_names_numeric[NVECM][NRC];
 665 extern const char * const riscv_vsew[8];
 666 extern const char * const riscv_vlmul[8];
 667 extern const char * const riscv_vta[2];
 668 extern const char * const riscv_vma[2];
 669 extern const char * const riscv_th_vlen[4];
 670 extern const char * const riscv_th_vediv[4];
 671 extern const char * const riscv_fli_symval[32];
 672 extern const float riscv_fli_numval[32];
 673
 674 extern const struct riscv_opcode riscv_opcodes[];
 675 extern const struct riscv_opcode riscv_insn_types[];
 676
 677 extern unsigned int riscv_get_sp_base (insn_t, unsigned int);
 678
 679 #endif /* _RISCV_H_ */