ld/testsuite/ld-powerpc/elfv2exe.d

   1 #source: elfv2.s
   2 #as: -a64
   3 #ld: -melf64ppc --defsym f2=0x1234 --defsym f3=0x10008888 --defsym f4=0x1200000 --defsym _start=f1
   4 #objdump: -dr
   5
   6 .*
   7
   8 Disassembly of section \.text:
   9
  10 0+100000c0 <.*\.plt_branch\.f4>:
  11 .*:     (3d 82 ff ff|ff ff 82 3d)       addis   r12,r2,-1
  12 .*:     (e9 8c 7f 58|58 7f 8c e9)       ld      r12,32600\(r12\)
  13 .*:     (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
  14 .*:     (4e 80 04 20|20 04 80 4e)       bctr
  15
  16 0+100000d0 <.*\.plt_branch\.f2>:
  17 .*:     (3d 82 ff ff|ff ff 82 3d)       addis   r12,r2,-1
  18 .*:     (e9 8c 7f 60|60 7f 8c e9)       ld      r12,32608\(r12\)
  19 .*:     (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
  20 .*:     (4e 80 04 20|20 04 80 4e)       bctr
  21
  22 0+100000e0 <.*\.long_branch\.f5>:
  23 .*:     (f8 41 00 18|18 00 41 f8)       std     r2,24\(r1\)
  24 .*:     (48 00 00 6c|6c 00 00 48)       b       .* <f5>
  25         \.\.\.
  26
  27 0+10000100 <(f1|_start)>:
  28 .*:     (3c 40 10 02|02 10 40 3c)       lis     r2,4098
  29 .*:     (38 42 82 00|00 82 42 38)       addi    r2,r2,-32256
  30 .*:     (7c 08 02 a6|a6 02 08 7c)       mflr    r0
  31 .*:     (f8 21 ff e1|e1 ff 21 f8)       stdu    r1,-32\(r1\)
  32 .*:     (f8 01 00 30|30 00 01 f8)       std     r0,48\(r1\)
  33 .*:     (4b ff ff f5|f5 ff ff 4b)       bl      .* <(f1|_start)\+0x8>
  34 .*:     (e8 62 80 08|08 80 62 e8)       ld      r3,-32760\(r2\)
  35 .*:     (4b .. .. ..|.. .. .. 4b)       bl      .*\.plt_branch\.f2>
  36 .*:     (60 00 00 00|00 00 00 60)       nop
  37 .*:     (38 62 80 18|18 80 62 38)       addi    r3,r2,-32744
  38 .*:     (48 .. .. ..|.. .. .. 48)       bl      10008888 <f3>
  39 .*:     (60 00 00 00|00 00 00 60)       nop
  40 .*:     (4b .. .. ..|.. .. .. 4b)       bl      .*\.plt_branch\.f4>
  41 .*:     (60 00 00 00|00 00 00 60)       nop
  42 .*:     (4b .. .. ..|.. .. .. 4b)       bl      .*\.long_branch\.f5>
  43 .*:     (e8 41 00 18|18 00 41 e8)       ld      r2,24\(r1\)
  44 .*:     (e8 01 00 30|30 00 01 e8)       ld      r0,48\(r1\)
  45 .*:     (38 21 00 20|20 00 21 38)       addi    r1,r1,32
  46 .*:     (7c 08 03 a6|a6 03 08 7c)       mtlr    r0
  47 .*:     (4e 80 00 20|20 00 80 4e)       blr
  48
  49 0+10000150 <f5>:
  50 .*:     (4e 80 00 20|20 00 80 4e)       blr