1 2018-09-20 Jan Beulich <jbeulich@suse.com>
4 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
6 * i386-tbl.h: Re-generate.
8 2019-09-18 Alan Modra <amodra@gmail.com>
10 * arc-ext.c: Update throughout for bfd section macro changes.
12 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
14 * Makefile.in: Re-generate.
15 * configure: Re-generate.
17 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
19 * riscv-opc.c (riscv_opcodes): Change subset field
20 to insn_class field for all instructions.
21 (riscv_insn_types): Likewise.
23 2019-09-16 Phil Blundell <pb@pbcl.net>
25 * configure: Regenerated.
27 2019-09-10 Miod Vallat <miod@online.fr>
30 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
32 2019-09-09 Phil Blundell <pb@pbcl.net>
34 binutils 2.33 branch created.
36 2019-09-03 Nick Clifton <nickc@redhat.com>
39 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
40 greater than zero before indexing via (bufcnt -1).
42 2019-09-03 Nick Clifton <nickc@redhat.com>
45 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
46 (MAX_SPEC_REG_NAME_LEN): Define.
47 (struct mmix_dis_info): Use defined constants for array lengths.
48 (get_reg_name): New function.
49 (get_sprec_reg_name): New function.
50 (print_insn_mmix): Use new functions.
52 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
54 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
55 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
56 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
58 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
60 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
61 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
62 (aarch64_sys_reg_supported_p): Update checks for the above.
64 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
66 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
67 cases MVE_SQRSHRL and MVE_UQRSHLL.
68 (print_insn_mve): Add case for specifier 'k' to check
69 specific bit of the instruction.
71 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
74 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
75 encountering an unknown machine type.
76 (print_insn_arc): Handle arc_insn_length returning 0. In error
77 cases return -1 rather than calling abort.
79 2019-08-07 Jan Beulich <jbeulich@suse.com>
81 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
82 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
84 * i386-tbl.h: Re-generate.
86 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
88 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
91 2019-07-30 Mel Chen <mel.chen@sifive.com>
93 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
94 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
96 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
99 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
101 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
102 and MPY class instructions.
103 (parse_option): Add nps400 option.
104 (print_arc_disassembler_options): Add nps400 info.
106 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
108 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
111 * arc-opc.c (RAD_CHK): Add.
112 * arc-tbl.h: Regenerate.
114 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
116 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
117 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
119 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
121 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
122 instructions as UNPREDICTABLE.
124 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
126 * bpf-desc.c: Regenerated.
128 2019-07-17 Jan Beulich <jbeulich@suse.com>
130 * i386-gen.c (static_assert): Define.
132 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
133 (Opcode_Modifier_Num): ... this.
136 2019-07-16 Jan Beulich <jbeulich@suse.com>
138 * i386-gen.c (operand_types): Move RegMem ...
139 (opcode_modifiers): ... here.
140 * i386-opc.h (RegMem): Move to opcode modifer enum.
141 (union i386_operand_type): Move regmem field ...
142 (struct i386_opcode_modifier): ... here.
143 * i386-opc.tbl (RegMem): Define.
144 (mov, movq): Move RegMem on segment, control, debug, and test
146 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
147 to non-SSE2AVX flavor.
148 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
149 Move RegMem on register only flavors. Drop IgnoreSize from
150 legacy encoding flavors.
151 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
153 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
154 register only flavors.
155 (vmovd): Move RegMem and drop IgnoreSize on register only
156 flavor. Change opcode and operand order to store form.
157 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
159 2019-07-16 Jan Beulich <jbeulich@suse.com>
161 * i386-gen.c (operand_type_init, operand_types): Replace SReg
163 * i386-opc.h (SReg2, SReg3): Replace by ...
165 (union i386_operand_type): Replace sreg fields.
166 * i386-opc.tbl (mov, ): Use SReg.
167 (push, pop): Likewies. Drop i386 and x86-64 specific segment
169 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
170 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
172 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
174 * bpf-desc.c: Regenerate.
175 * bpf-opc.c: Likewise.
176 * bpf-opc.h: Likewise.
178 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
180 * bpf-desc.c: Regenerate.
181 * bpf-opc.c: Likewise.
183 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
185 * arm-dis.c (print_insn_coprocessor): Rename index to
188 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
190 * riscv-opc.c (riscv_insn_types): Add r4 type.
192 * riscv-opc.c (riscv_insn_types): Add b and j type.
194 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
195 format for sb type and correct s type.
197 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
199 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
200 SVE FMOV alias of FCPY.
202 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
204 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
205 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
207 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
209 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
210 registers in an instruction prefixed by MOVPRFX.
212 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
214 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
215 sve_size_13 icode to account for variant behaviour of
217 * aarch64-dis-2.c: Regenerate.
218 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
219 sve_size_13 icode to account for variant behaviour of
221 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
222 (OP_SVE_VVV_Q_D): Add new qualifier.
223 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
224 (struct aarch64_opcode): Split pmull{t,b} into those requiring
227 2019-07-01 Jan Beulich <jbeulich@suse.com>
229 * opcodes/i386-gen.c (operand_type_init): Remove
230 OPERAND_TYPE_VEC_IMM4 entry.
231 (operand_types): Remove Vec_Imm4.
232 * opcodes/i386-opc.h (Vec_Imm4): Delete.
233 (union i386_operand_type): Remove vec_imm4.
234 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
235 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
237 2019-07-01 Jan Beulich <jbeulich@suse.com>
239 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
240 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
241 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
242 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
243 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
244 monitorx, mwaitx): Drop ImmExt from operand-less forms.
245 * i386-tbl.h: Re-generate.
247 2019-07-01 Jan Beulich <jbeulich@suse.com>
249 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
251 * i386-tbl.h: Re-generate.
253 2019-07-01 Jan Beulich <jbeulich@suse.com>
255 * i386-opc.tbl (C): New.
256 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
257 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
258 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
259 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
260 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
261 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
262 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
263 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
264 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
265 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
266 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
267 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
268 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
269 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
270 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
271 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
272 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
273 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
274 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
275 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
276 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
277 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
278 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
279 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
280 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
281 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
283 * i386-tbl.h: Re-generate.
285 2019-07-01 Jan Beulich <jbeulich@suse.com>
287 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
289 * i386-tbl.h: Re-generate.
291 2019-07-01 Jan Beulich <jbeulich@suse.com>
293 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
294 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
295 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
296 * i386-tbl.h: Re-generate.
298 2019-07-01 Jan Beulich <jbeulich@suse.com>
300 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
301 Disp8MemShift from register only templates.
302 * i386-tbl.h: Re-generate.
304 2019-07-01 Jan Beulich <jbeulich@suse.com>
306 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
307 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
308 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
309 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
310 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
311 EVEX_W_0F11_P_3_M_1): Delete.
312 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
313 EVEX_W_0F11_P_3): New.
314 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
315 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
316 MOD_EVEX_0F11_PREFIX_3 table entries.
317 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
318 PREFIX_EVEX_0F11 table entries.
319 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
320 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
321 EVEX_W_0F11_P_3_M_{0,1} table entries.
323 2019-07-01 Jan Beulich <jbeulich@suse.com>
325 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
328 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
331 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
332 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
333 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
334 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
335 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
336 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
337 EVEX_LEN_0F38C7_R_6_P_2_W_1.
338 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
339 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
340 PREFIX_EVEX_0F38C6_REG_6 entries.
341 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
342 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
343 EVEX_W_0F38C7_R_6_P_2 entries.
344 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
345 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
346 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
347 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
348 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
349 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
350 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
352 2019-06-27 Jan Beulich <jbeulich@suse.com>
354 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
355 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
356 VEX_LEN_0F2D_P_3): Delete.
357 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
358 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
359 (prefix_table): ... here.
361 2019-06-27 Jan Beulich <jbeulich@suse.com>
363 * i386-dis.c (Iq): Delete.
365 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
367 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
368 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
369 (OP_E_memory): Also honor needindex when deciding whether an
370 address size prefix needs printing.
371 (OP_I): Remove handling of q_mode. Add handling of d_mode.
373 2019-06-26 Jim Wilson <jimw@sifive.com>
376 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
377 Set info->display_endian to info->endian_code.
379 2019-06-25 Jan Beulich <jbeulich@suse.com>
381 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
382 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
383 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
384 OPERAND_TYPE_ACC64 entries.
385 * i386-init.h: Re-generate.
387 2019-06-25 Jan Beulich <jbeulich@suse.com>
389 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
391 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
393 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
395 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
396 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
398 2019-06-25 Jan Beulich <jbeulich@suse.com>
400 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
403 2019-06-25 Jan Beulich <jbeulich@suse.com>
405 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
406 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
408 * i386-opc.tbl (movnti): Add IgnoreSize.
409 * i386-tbl.h: Re-generate.
411 2019-06-25 Jan Beulich <jbeulich@suse.com>
413 * i386-opc.tbl (and): Mark Imm8S form for optimization.
414 * i386-tbl.h: Re-generate.
416 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
418 * i386-dis-evex.h: Break into ...
419 * i386-dis-evex-len.h: New file.
420 * i386-dis-evex-mod.h: Likewise.
421 * i386-dis-evex-prefix.h: Likewise.
422 * i386-dis-evex-reg.h: Likewise.
423 * i386-dis-evex-w.h: Likewise.
424 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
425 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
428 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
431 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
432 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
434 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
435 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
436 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
437 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
438 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
439 EVEX_LEN_0F385B_P_2_W_1.
440 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
441 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
442 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
443 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
444 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
445 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
446 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
447 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
448 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
449 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
451 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
454 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
455 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
456 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
457 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
458 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
459 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
460 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
461 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
462 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
463 EVEX_LEN_0F3A43_P_2_W_1.
464 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
465 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
466 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
467 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
468 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
469 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
470 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
471 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
472 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
473 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
474 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
475 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
477 2019-06-14 Nick Clifton <nickc@redhat.com>
479 * po/fr.po; Updated French translation.
481 2019-06-13 Stafford Horne <shorne@gmail.com>
483 * or1k-asm.c: Regenerated.
484 * or1k-desc.c: Regenerated.
485 * or1k-desc.h: Regenerated.
486 * or1k-dis.c: Regenerated.
487 * or1k-ibld.c: Regenerated.
488 * or1k-opc.c: Regenerated.
489 * or1k-opc.h: Regenerated.
490 * or1k-opinst.c: Regenerated.
492 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
494 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
496 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
499 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
500 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
501 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
502 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
503 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
504 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
505 EVEX_LEN_0F3A1B_P_2_W_1.
506 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
507 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
508 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
509 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
510 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
511 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
512 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
513 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
515 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
518 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
519 EVEX.vvvv when disassembling VEX and EVEX instructions.
520 (OP_VEX): Set vex.register_specifier to 0 after readding
521 vex.register_specifier.
522 (OP_Vex_2src_1): Likewise.
523 (OP_Vex_2src_2): Likewise.
524 (OP_LWP_E): Likewise.
525 (OP_EX_Vex): Don't check vex.register_specifier.
526 (OP_XMM_Vex): Likewise.
528 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
529 Lili Cui <lili.cui@intel.com>
531 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
532 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
534 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
535 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
536 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
537 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
538 (i386_cpu_flags): Add cpuavx512_vp2intersect.
539 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
540 * i386-init.h: Regenerated.
541 * i386-tbl.h: Likewise.
543 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
544 Lili Cui <lili.cui@intel.com>
546 * doc/c-i386.texi: Document enqcmd.
547 * testsuite/gas/i386/enqcmd-intel.d: New file.
548 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
549 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
550 * testsuite/gas/i386/enqcmd.d: Likewise.
551 * testsuite/gas/i386/enqcmd.s: Likewise.
552 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
553 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
554 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
555 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
556 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
557 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
558 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
561 2019-06-04 Alan Hayward <alan.hayward@arm.com>
563 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
565 2019-06-03 Alan Modra <amodra@gmail.com>
567 * ppc-dis.c (prefix_opcd_indices): Correct size.
569 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
572 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
574 * i386-tbl.h: Regenerated.
576 2019-05-24 Alan Modra <amodra@gmail.com>
578 * po/POTFILES.in: Regenerate.
580 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
581 Alan Modra <amodra@gmail.com>
583 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
584 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
585 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
586 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
587 XTOP>): Define and add entries.
588 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
589 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
590 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
591 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
593 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
594 Alan Modra <amodra@gmail.com>
596 * ppc-dis.c (ppc_opts): Add "future" entry.
597 (PREFIX_OPCD_SEGS): Define.
598 (prefix_opcd_indices): New array.
599 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
600 (lookup_prefix): New function.
601 (print_insn_powerpc): Handle 64-bit prefix instructions.
602 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
603 (PMRR, POWERXX): Define.
604 (prefix_opcodes): New instruction table.
605 (prefix_num_opcodes): New constant.
607 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
609 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
610 * configure: Regenerated.
611 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
613 (HFILES): Add bpf-desc.h and bpf-opc.h.
614 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
615 bpf-ibld.c and bpf-opc.c.
617 * Makefile.in: Regenerated.
618 * disassemble.c (ARCH_bpf): Define.
619 (disassembler): Add case for bfd_arch_bpf.
620 (disassemble_init_for_target): Likewise.
621 (enum epbf_isa_attr): Define.
622 * disassemble.h: extern print_insn_bpf.
623 * bpf-asm.c: Generated.
624 * bpf-opc.h: Likewise.
625 * bpf-opc.c: Likewise.
626 * bpf-ibld.c: Likewise.
627 * bpf-dis.c: Likewise.
628 * bpf-desc.h: Likewise.
629 * bpf-desc.c: Likewise.
631 2019-05-21 Sudakshina Das <sudi.das@arm.com>
633 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
634 and VMSR with the new operands.
636 2019-05-21 Sudakshina Das <sudi.das@arm.com>
638 * arm-dis.c (enum mve_instructions): New enum
639 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
641 (mve_opcodes): New instructions as above.
642 (is_mve_encoding_conflict): Add cases for csinc, csinv,
644 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
646 2019-05-21 Sudakshina Das <sudi.das@arm.com>
648 * arm-dis.c (emun mve_instructions): Updated for new instructions.
649 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
650 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
651 uqshl, urshrl and urshr.
652 (is_mve_okay_in_it): Add new instructions to TRUE list.
653 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
654 (print_insn_mve): Updated to accept new %j,
655 %<bitfield>m and %<bitfield>n patterns.
657 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
659 * mips-opc.c (mips_builtin_opcodes): Change source register
662 2019-05-20 Nick Clifton <nickc@redhat.com>
664 * po/fr.po: Updated French translation.
666 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
667 Michael Collison <michael.collison@arm.com>
669 * arm-dis.c (thumb32_opcodes): Add new instructions.
670 (enum mve_instructions): Likewise.
671 (enum mve_undefined): Add new reasons.
672 (is_mve_encoding_conflict): Handle new instructions.
673 (is_mve_undefined): Likewise.
674 (is_mve_unpredictable): Likewise.
675 (print_mve_undefined): Likewise.
676 (print_mve_size): Likewise.
678 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
679 Michael Collison <michael.collison@arm.com>
681 * arm-dis.c (thumb32_opcodes): Add new instructions.
682 (enum mve_instructions): Likewise.
683 (is_mve_encoding_conflict): Handle new instructions.
684 (is_mve_undefined): Likewise.
685 (is_mve_unpredictable): Likewise.
686 (print_mve_size): Likewise.
688 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
689 Michael Collison <michael.collison@arm.com>
691 * arm-dis.c (thumb32_opcodes): Add new instructions.
692 (enum mve_instructions): Likewise.
693 (is_mve_encoding_conflict): Likewise.
694 (is_mve_unpredictable): Likewise.
695 (print_mve_size): Likewise.
697 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
698 Michael Collison <michael.collison@arm.com>
700 * arm-dis.c (thumb32_opcodes): Add new instructions.
701 (enum mve_instructions): Likewise.
702 (is_mve_encoding_conflict): Handle new instructions.
703 (is_mve_undefined): Likewise.
704 (is_mve_unpredictable): Likewise.
705 (print_mve_size): Likewise.
707 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
708 Michael Collison <michael.collison@arm.com>
710 * arm-dis.c (thumb32_opcodes): Add new instructions.
711 (enum mve_instructions): Likewise.
712 (is_mve_encoding_conflict): Handle new instructions.
713 (is_mve_undefined): Likewise.
714 (is_mve_unpredictable): Likewise.
715 (print_mve_size): Likewise.
716 (print_insn_mve): Likewise.
718 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
719 Michael Collison <michael.collison@arm.com>
721 * arm-dis.c (thumb32_opcodes): Add new instructions.
722 (print_insn_thumb32): Handle new instructions.
724 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
725 Michael Collison <michael.collison@arm.com>
727 * arm-dis.c (enum mve_instructions): Add new instructions.
728 (enum mve_undefined): Add new reasons.
729 (is_mve_encoding_conflict): Handle new instructions.
730 (is_mve_undefined): Likewise.
731 (is_mve_unpredictable): Likewise.
732 (print_mve_undefined): Likewise.
733 (print_mve_size): Likewise.
734 (print_mve_shift_n): Likewise.
735 (print_insn_mve): Likewise.
737 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
738 Michael Collison <michael.collison@arm.com>
740 * arm-dis.c (enum mve_instructions): Add new instructions.
741 (is_mve_encoding_conflict): Handle new instructions.
742 (is_mve_unpredictable): Likewise.
743 (print_mve_rotate): Likewise.
744 (print_mve_size): Likewise.
745 (print_insn_mve): Likewise.
747 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
748 Michael Collison <michael.collison@arm.com>
750 * arm-dis.c (enum mve_instructions): Add new instructions.
751 (is_mve_encoding_conflict): Handle new instructions.
752 (is_mve_unpredictable): Likewise.
753 (print_mve_size): Likewise.
754 (print_insn_mve): Likewise.
756 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
757 Michael Collison <michael.collison@arm.com>
759 * arm-dis.c (enum mve_instructions): Add new instructions.
760 (enum mve_undefined): Add new reasons.
761 (is_mve_encoding_conflict): Handle new instructions.
762 (is_mve_undefined): Likewise.
763 (is_mve_unpredictable): Likewise.
764 (print_mve_undefined): Likewise.
765 (print_mve_size): Likewise.
766 (print_insn_mve): Likewise.
768 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
769 Michael Collison <michael.collison@arm.com>
771 * arm-dis.c (enum mve_instructions): Add new instructions.
772 (is_mve_encoding_conflict): Handle new instructions.
773 (is_mve_undefined): Likewise.
774 (is_mve_unpredictable): Likewise.
775 (print_mve_size): Likewise.
776 (print_insn_mve): Likewise.
778 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
779 Michael Collison <michael.collison@arm.com>
781 * arm-dis.c (enum mve_instructions): Add new instructions.
782 (enum mve_unpredictable): Add new reasons.
783 (enum mve_undefined): Likewise.
784 (is_mve_okay_in_it): Handle new isntructions.
785 (is_mve_encoding_conflict): Likewise.
786 (is_mve_undefined): Likewise.
787 (is_mve_unpredictable): Likewise.
788 (print_mve_vmov_index): Likewise.
789 (print_simd_imm8): Likewise.
790 (print_mve_undefined): Likewise.
791 (print_mve_unpredictable): Likewise.
792 (print_mve_size): Likewise.
793 (print_insn_mve): Likewise.
795 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
796 Michael Collison <michael.collison@arm.com>
798 * arm-dis.c (enum mve_instructions): Add new instructions.
799 (enum mve_unpredictable): Add new reasons.
800 (enum mve_undefined): Likewise.
801 (is_mve_encoding_conflict): Handle new instructions.
802 (is_mve_undefined): Likewise.
803 (is_mve_unpredictable): Likewise.
804 (print_mve_undefined): Likewise.
805 (print_mve_unpredictable): Likewise.
806 (print_mve_rounding_mode): Likewise.
807 (print_mve_vcvt_size): Likewise.
808 (print_mve_size): Likewise.
809 (print_insn_mve): Likewise.
811 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
812 Michael Collison <michael.collison@arm.com>
814 * arm-dis.c (enum mve_instructions): Add new instructions.
815 (enum mve_unpredictable): Add new reasons.
816 (enum mve_undefined): Likewise.
817 (is_mve_undefined): Handle new instructions.
818 (is_mve_unpredictable): Likewise.
819 (print_mve_undefined): Likewise.
820 (print_mve_unpredictable): Likewise.
821 (print_mve_size): Likewise.
822 (print_insn_mve): Likewise.
824 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
825 Michael Collison <michael.collison@arm.com>
827 * arm-dis.c (enum mve_instructions): Add new instructions.
828 (enum mve_undefined): Add new reasons.
829 (insns): Add new instructions.
830 (is_mve_encoding_conflict):
831 (print_mve_vld_str_addr): New print function.
832 (is_mve_undefined): Handle new instructions.
833 (is_mve_unpredictable): Likewise.
834 (print_mve_undefined): Likewise.
835 (print_mve_size): Likewise.
836 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
837 (print_insn_mve): Handle new operands.
839 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
840 Michael Collison <michael.collison@arm.com>
842 * arm-dis.c (enum mve_instructions): Add new instructions.
843 (enum mve_unpredictable): Add new reasons.
844 (is_mve_encoding_conflict): Handle new instructions.
845 (is_mve_unpredictable): Likewise.
846 (mve_opcodes): Add new instructions.
847 (print_mve_unpredictable): Handle new reasons.
848 (print_mve_register_blocks): New print function.
849 (print_mve_size): Handle new instructions.
850 (print_insn_mve): Likewise.
852 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
853 Michael Collison <michael.collison@arm.com>
855 * arm-dis.c (enum mve_instructions): Add new instructions.
856 (enum mve_unpredictable): Add new reasons.
857 (enum mve_undefined): Likewise.
858 (is_mve_encoding_conflict): Handle new instructions.
859 (is_mve_undefined): Likewise.
860 (is_mve_unpredictable): Likewise.
861 (coprocessor_opcodes): Move NEON VDUP from here...
862 (neon_opcodes): ... to here.
863 (mve_opcodes): Add new instructions.
864 (print_mve_undefined): Handle new reasons.
865 (print_mve_unpredictable): Likewise.
866 (print_mve_size): Handle new instructions.
867 (print_insn_neon): Handle vdup.
868 (print_insn_mve): Handle new operands.
870 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
871 Michael Collison <michael.collison@arm.com>
873 * arm-dis.c (enum mve_instructions): Add new instructions.
874 (enum mve_unpredictable): Add new values.
875 (mve_opcodes): Add new instructions.
876 (vec_condnames): New array with vector conditions.
877 (mve_predicatenames): New array with predicate suffixes.
878 (mve_vec_sizename): New array with vector sizes.
879 (enum vpt_pred_state): New enum with vector predication states.
880 (struct vpt_block): New struct type for vpt blocks.
881 (vpt_block_state): Global struct to keep track of state.
882 (mve_extract_pred_mask): New helper function.
883 (num_instructions_vpt_block): Likewise.
884 (mark_outside_vpt_block): Likewise.
885 (mark_inside_vpt_block): Likewise.
886 (invert_next_predicate_state): Likewise.
887 (update_next_predicate_state): Likewise.
888 (update_vpt_block_state): Likewise.
889 (is_vpt_instruction): Likewise.
890 (is_mve_encoding_conflict): Add entries for new instructions.
891 (is_mve_unpredictable): Likewise.
892 (print_mve_unpredictable): Handle new cases.
893 (print_instruction_predicate): Likewise.
894 (print_mve_size): New function.
895 (print_vec_condition): New function.
896 (print_insn_mve): Handle vpt blocks and new print operands.
898 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
900 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
901 8, 14 and 15 for Armv8.1-M Mainline.
903 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
904 Michael Collison <michael.collison@arm.com>
906 * arm-dis.c (enum mve_instructions): New enum.
907 (enum mve_unpredictable): Likewise.
908 (enum mve_undefined): Likewise.
909 (struct mopcode32): New struct.
910 (is_mve_okay_in_it): New function.
911 (is_mve_architecture): Likewise.
912 (arm_decode_field): Likewise.
913 (arm_decode_field_multiple): Likewise.
914 (is_mve_encoding_conflict): Likewise.
915 (is_mve_undefined): Likewise.
916 (is_mve_unpredictable): Likewise.
917 (print_mve_undefined): Likewise.
918 (print_mve_unpredictable): Likewise.
919 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
920 (print_insn_mve): New function.
921 (print_insn_thumb32): Handle MVE architecture.
922 (select_arm_features): Force thumb for Armv8.1-m Mainline.
924 2019-05-10 Nick Clifton <nickc@redhat.com>
927 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
928 end of the table prematurely.
930 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
932 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
935 2019-05-11 Alan Modra <amodra@gmail.com>
937 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
938 when -Mraw is in effect.
940 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
942 * aarch64-dis-2.c: Regenerate.
943 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
944 (OP_SVE_BBB): New variant set.
945 (OP_SVE_DDDD): New variant set.
946 (OP_SVE_HHH): New variant set.
947 (OP_SVE_HHHU): New variant set.
948 (OP_SVE_SSS): New variant set.
949 (OP_SVE_SSSU): New variant set.
950 (OP_SVE_SHH): New variant set.
951 (OP_SVE_SBBU): New variant set.
952 (OP_SVE_DSS): New variant set.
953 (OP_SVE_DHHU): New variant set.
954 (OP_SVE_VMV_HSD_BHS): New variant set.
955 (OP_SVE_VVU_HSD_BHS): New variant set.
956 (OP_SVE_VVVU_SD_BH): New variant set.
957 (OP_SVE_VVVU_BHSD): New variant set.
958 (OP_SVE_VVV_QHD_DBS): New variant set.
959 (OP_SVE_VVV_HSD_BHS): New variant set.
960 (OP_SVE_VVV_HSD_BHS2): New variant set.
961 (OP_SVE_VVV_BHS_HSD): New variant set.
962 (OP_SVE_VV_BHS_HSD): New variant set.
963 (OP_SVE_VVV_SD): New variant set.
964 (OP_SVE_VVU_BHS_HSD): New variant set.
965 (OP_SVE_VZVV_SD): New variant set.
966 (OP_SVE_VZVV_BH): New variant set.
967 (OP_SVE_VZV_SD): New variant set.
968 (aarch64_opcode_table): Add sve2 instructions.
970 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
972 * aarch64-asm-2.c: Regenerated.
973 * aarch64-dis-2.c: Regenerated.
974 * aarch64-opc-2.c: Regenerated.
975 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
976 for SVE_SHLIMM_UNPRED_22.
977 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
978 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
981 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
983 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
984 sve_size_tsz_bhs iclass encode.
985 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
986 sve_size_tsz_bhs iclass decode.
988 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
990 * aarch64-asm-2.c: Regenerated.
991 * aarch64-dis-2.c: Regenerated.
992 * aarch64-opc-2.c: Regenerated.
993 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
994 for SVE_Zm4_11_INDEX.
995 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
996 (fields): Handle SVE_i2h field.
997 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
998 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1000 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1002 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1003 sve_shift_tsz_bhsd iclass encode.
1004 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1005 sve_shift_tsz_bhsd iclass decode.
1007 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1009 * aarch64-asm-2.c: Regenerated.
1010 * aarch64-dis-2.c: Regenerated.
1011 * aarch64-opc-2.c: Regenerated.
1012 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1013 (aarch64_encode_variant_using_iclass): Handle
1014 sve_shift_tsz_hsd iclass encode.
1015 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1016 sve_shift_tsz_hsd iclass decode.
1017 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1018 for SVE_SHRIMM_UNPRED_22.
1019 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1020 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1023 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1025 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1026 sve_size_013 iclass encode.
1027 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1028 sve_size_013 iclass decode.
1030 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1032 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1033 sve_size_bh iclass encode.
1034 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1035 sve_size_bh iclass decode.
1037 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1039 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1040 sve_size_sd2 iclass encode.
1041 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1042 sve_size_sd2 iclass decode.
1043 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1044 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1046 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1048 * aarch64-asm-2.c: Regenerated.
1049 * aarch64-dis-2.c: Regenerated.
1050 * aarch64-opc-2.c: Regenerated.
1051 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1053 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1054 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1056 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1058 * aarch64-asm-2.c: Regenerated.
1059 * aarch64-dis-2.c: Regenerated.
1060 * aarch64-opc-2.c: Regenerated.
1061 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1062 for SVE_Zm3_11_INDEX.
1063 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1064 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1065 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1067 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1069 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1071 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1072 sve_size_hsd2 iclass encode.
1073 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1074 sve_size_hsd2 iclass decode.
1075 * aarch64-opc.c (fields): Handle SVE_size field.
1076 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1078 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1080 * aarch64-asm-2.c: Regenerated.
1081 * aarch64-dis-2.c: Regenerated.
1082 * aarch64-opc-2.c: Regenerated.
1083 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1085 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1086 (fields): Handle SVE_rot3 field.
1087 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1088 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1090 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1092 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1095 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1098 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1099 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1100 aarch64_feature_sve2bitperm): New feature sets.
1101 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1102 for feature set addresses.
1103 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1104 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1106 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1107 Faraz Shahbazker <fshahbazker@wavecomp.com>
1109 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1110 argument and set ASE_EVA_R6 appropriately.
1111 (set_default_mips_dis_options): Pass ISA to above.
1112 (parse_mips_dis_option): Likewise.
1113 * mips-opc.c (EVAR6): New macro.
1114 (mips_builtin_opcodes): Add llwpe, scwpe.
1116 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1118 * aarch64-asm-2.c: Regenerated.
1119 * aarch64-dis-2.c: Regenerated.
1120 * aarch64-opc-2.c: Regenerated.
1121 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1122 AARCH64_OPND_TME_UIMM16.
1123 (aarch64_print_operand): Likewise.
1124 * aarch64-tbl.h (QL_IMM_NIL): New.
1127 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1129 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1131 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1133 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1134 Faraz Shahbazker <fshahbazker@wavecomp.com>
1136 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1138 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1140 * s12z-opc.h: Add extern "C" bracketing to help
1141 users who wish to use this interface in c++ code.
1143 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1145 * s12z-opc.c (bm_decode): Handle bit map operations with the
1148 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1150 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1151 specifier. Add entries for VLDR and VSTR of system registers.
1152 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1153 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1154 of %J and %K format specifier.
1156 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1158 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1159 Add new entries for VSCCLRM instruction.
1160 (print_insn_coprocessor): Handle new %C format control code.
1162 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1164 * arm-dis.c (enum isa): New enum.
1165 (struct sopcode32): New structure.
1166 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1167 set isa field of all current entries to ANY.
1168 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1169 Only match an entry if its isa field allows the current mode.
1171 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1173 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1175 (print_insn_thumb32): Add logic to print %n CLRM register list.
1177 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1179 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1182 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1184 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1185 (print_insn_thumb32): Edit the switch case for %Z.
1187 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1189 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1191 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1193 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1195 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1197 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1199 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1201 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1202 Arm register with r13 and r15 unpredictable.
1203 (thumb32_opcodes): New instructions for bfx and bflx.
1205 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1207 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1209 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1211 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1213 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1215 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1217 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1219 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1221 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1223 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1224 "optr". ("operator" is a reserved word in c++).
1226 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1228 * aarch64-opc.c (aarch64_print_operand): Add case for
1230 (verify_constraints): Likewise.
1231 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1232 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1233 to accept Rt|SP as first operand.
1234 (AARCH64_OPERANDS): Add new Rt_SP.
1235 * aarch64-asm-2.c: Regenerated.
1236 * aarch64-dis-2.c: Regenerated.
1237 * aarch64-opc-2.c: Regenerated.
1239 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1241 * aarch64-asm-2.c: Regenerated.
1242 * aarch64-dis-2.c: Likewise.
1243 * aarch64-opc-2.c: Likewise.
1244 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1246 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1248 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1250 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1252 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1253 * i386-init.h: Regenerated.
1255 2019-04-07 Alan Modra <amodra@gmail.com>
1257 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1258 op_separator to control printing of spaces, comma and parens
1259 rather than need_comma, need_paren and spaces vars.
1261 2019-04-07 Alan Modra <amodra@gmail.com>
1264 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1265 (print_insn_neon, print_insn_arm): Likewise.
1267 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1269 * i386-dis-evex.h (evex_table): Updated to support BF16
1271 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1272 and EVEX_W_0F3872_P_3.
1273 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1274 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1275 * i386-opc.h (enum): Add CpuAVX512_BF16.
1276 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1277 * i386-opc.tbl: Add AVX512 BF16 instructions.
1278 * i386-init.h: Regenerated.
1279 * i386-tbl.h: Likewise.
1281 2019-04-05 Alan Modra <amodra@gmail.com>
1283 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1284 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1285 to favour printing of "-" branch hint when using the "y" bit.
1286 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1288 2019-04-05 Alan Modra <amodra@gmail.com>
1290 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1291 opcode until first operand is output.
1293 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1296 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1297 (valid_bo_post_v2): Add support for 'at' branch hints.
1298 (insert_bo): Only error on branch on ctr.
1299 (get_bo_hint_mask): New function.
1300 (insert_boe): Add new 'branch_taken' formal argument. Add support
1301 for inserting 'at' branch hints.
1302 (extract_boe): Add new 'branch_taken' formal argument. Add support
1303 for extracting 'at' branch hints.
1304 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1305 (BOE): Delete operand.
1306 (BOM, BOP): New operands.
1308 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1309 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1310 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1311 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1312 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1313 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1314 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1315 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1316 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1317 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1318 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1319 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1320 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1321 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1322 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1323 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1324 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1325 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1326 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1327 bttarl+>: New extended mnemonics.
1329 2019-03-28 Alan Modra <amodra@gmail.com>
1332 * ppc-opc.c (BTF): Define.
1333 (powerpc_opcodes): Use for mtfsb*.
1334 * ppc-dis.c (print_insn_powerpc): Print fields with both
1335 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1337 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1339 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1340 (mapping_symbol_for_insn): Implement new algorithm.
1341 (print_insn): Remove duplicate code.
1343 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1345 * aarch64-dis.c (print_insn_aarch64):
1348 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1350 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1353 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1355 * aarch64-dis.c (last_stop_offset): New.
1356 (print_insn_aarch64): Use stop_offset.
1358 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1361 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1363 * i386-init.h: Regenerated.
1365 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1368 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1369 vmovdqu16, vmovdqu32 and vmovdqu64.
1370 * i386-tbl.h: Regenerated.
1372 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1374 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1375 from vstrszb, vstrszh, and vstrszf.
1377 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1379 * s390-opc.txt: Add instruction descriptions.
1381 2019-02-08 Jim Wilson <jimw@sifive.com>
1383 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1386 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1388 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1390 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1393 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1394 * aarch64-opc.c (verify_elem_sd): New.
1395 (fields): Add FLD_sz entr.
1396 * aarch64-tbl.h (_SIMD_INSN): New.
1397 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1398 fmulx scalar and vector by element isns.
1400 2019-02-07 Nick Clifton <nickc@redhat.com>
1402 * po/sv.po: Updated Swedish translation.
1404 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1406 * s390-mkopc.c (main): Accept arch13 as cpu string.
1407 * s390-opc.c: Add new instruction formats and instruction opcode
1409 * s390-opc.txt: Add new arch13 instructions.
1411 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1413 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1414 (aarch64_opcode): Change encoding for stg, stzg
1416 * aarch64-asm-2.c: Regenerated.
1417 * aarch64-dis-2.c: Regenerated.
1418 * aarch64-opc-2.c: Regenerated.
1420 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1422 * aarch64-asm-2.c: Regenerated.
1423 * aarch64-dis-2.c: Likewise.
1424 * aarch64-opc-2.c: Likewise.
1425 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1427 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1428 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1430 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1431 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1432 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1433 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1434 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1435 case for ldstgv_indexed.
1436 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1437 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1438 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1439 * aarch64-asm-2.c: Regenerated.
1440 * aarch64-dis-2.c: Regenerated.
1441 * aarch64-opc-2.c: Regenerated.
1443 2019-01-23 Nick Clifton <nickc@redhat.com>
1445 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1447 2019-01-21 Nick Clifton <nickc@redhat.com>
1449 * po/de.po: Updated German translation.
1450 * po/uk.po: Updated Ukranian translation.
1452 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1453 * mips-dis.c (mips_arch_choices): Fix typo in
1454 gs464, gs464e and gs264e descriptors.
1456 2019-01-19 Nick Clifton <nickc@redhat.com>
1458 * configure: Regenerate.
1459 * po/opcodes.pot: Regenerate.
1461 2018-06-24 Nick Clifton <nickc@redhat.com>
1463 2.32 branch created.
1465 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1467 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1469 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1472 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1474 * configure: Regenerate.
1476 2019-01-07 Alan Modra <amodra@gmail.com>
1478 * configure: Regenerate.
1479 * po/POTFILES.in: Regenerate.
1481 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1483 * s12z-opc.c: New file.
1484 * s12z-opc.h: New file.
1485 * s12z-dis.c: Removed all code not directly related to display
1486 of instructions. Used the interface provided by the new files
1488 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1489 * Makefile.in: Regenerate.
1490 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1491 * configure: Regenerate.
1493 2019-01-01 Alan Modra <amodra@gmail.com>
1495 Update year range in copyright notice of all files.
1497 For older changes see ChangeLog-2018
1499 Copyright (C) 2019 Free Software Foundation, Inc.
1501 Copying and distribution of this file, with or without modification,
1502 are permitted in any medium without royalty provided the copyright
1503 notice and this notice are preserved.
1509 version-control: never